Semiconductor material testing device and testing method

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor material testing device and method, and the device comprises a parameter analyzer, the lower part of the parameter analyzer is provided with a connection assembly, and the right side of the parameter analyzer is provided with a protection storage assembly. The handles at the two ends of the integrated socket in the connecting assembly are pushed into the positioning grooves, so that the integrated socket forms a stable locking state. The test method comprises the following steps: controlling a source measurement unit to inject calibration current into a test loop by using a physical boundary condition with a stable locking state solidified; the static characteristic de-embedding processing module is used for establishing a static linear impedance mathematical model and extracting a static contact impedance constant and a static bias voltage, and in a formal test, the system performs de-embedding compensation calculation on an original response voltage by using the static contact impedance constant and the static bias voltage. The real electrical response voltage of the semiconductor material is restored, and the comprehensive protection performance of the testing device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a semiconductor material testing device and testing method. Background Technology

[0002] Semiconductor material testing equipment is a fundamental testing device in the semiconductor device manufacturing and R&D process. It is mainly used to measure and analyze the electrical properties and physical parameters of semiconductor wafers, chips, and novel thin film materials. This type of testing system typically consists of a parameter analyzer main unit responsible for outputting excitation signals and acquiring response data, a probe station responsible for carrying the sample under test and making probe contact, and a connection interface and cable assembly for establishing a signal transmission path between the two.

[0003] In existing standard testing procedures, technicians place the semiconductor material under test on the probe station's operating platform and adjust the miniature probe to make physical contact with the test electrodes on the semiconductor material's surface. Subsequently, the operator obtains an external coaxial test cable, connecting one end to the signal output of the probe station and the other end directly into the exposed test socket on the front panel of the parameter analyzer, establishing a complete test path. After completing the hardware connection, technicians set the test threshold through the parameter analyzer's control panel, activate the device to apply voltage or current excitation signals to the semiconductor material, and simultaneously record the returned response electrical signals. Finally, the device's built-in universal compensation model performs basic mathematical conversions and outputs graphical charts based on the collected data.

[0004] Existing semiconductor material testing equipment suffers from drawbacks when performing high-precision electrical measurements. Dynamic fluctuations in interface contact impedance cause algorithm compensation failures and limit measurement accuracy. Current parameter analyzer interfaces typically employ conventional plug-and-play structures, lacking robust mechanical restraint designs at the connectors. Throughout the testing cycle, external test cables are highly susceptible to environmental micro-vibrations or stress release within the cables themselves, leading to dynamic contact displacement at the physical contact interface between the plug and the test socket. This dynamic displacement causes the contact impedance at the interface to exhibit unpredictable random fluctuations. Lacking absolutely static physical boundary conditions, existing testing systems cannot accurately establish static characteristic models to extract fixed contact impedance constants. Consequently, the system cannot accurately perform de-embedding compensation calculations during data processing to deduct impedance interference from external wiring. The final electrical response data acquired by the system contains dynamic errors that are difficult to eliminate, failing to accurately reproduce the electrical response voltage of the semiconductor material. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a semiconductor material testing device and method, solving the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The first aspect of this invention provides a semiconductor material testing device, including a parameter analyzer. A connection assembly is disposed at the lower part of the parameter analyzer. A probe station is electrically connected to the right surface of the parameter analyzer via wires. A protective storage assembly is disposed on the right side of the parameter analyzer. The connection assembly includes an integrated socket with multiple integrated ports on its front surface. Handles are slidably connected to the left and right sides of the front surface of the integrated socket. A dustproof plate is rotatably connected to the lower part of the front surface of the parameter analyzer, and a positioning groove is formed on the lower part of the front surface of the parameter analyzer. The protective storage assembly includes a partition plate. The outer surface of the partition plate is fixedly connected to the parameter analyzer. A sponge pad is fixedly connected to the inner side of the partition plate, and a protective plate is slidably connected to the outer side of the partition plate. A magnetic block is fixedly connected to the upper end of the protective plate.

[0007] The lower inner surface of the parameter analyzer has a rectangular groove containing a linear guide structure with ball bearings, which limits the horizontal movement of the integrated socket. The handle is J-shaped, and an elastic damping pad is installed inside the positioning groove. When the bent end of the handle is fully inserted into the positioning groove and forms a tight fit with the elastic damping pad, a stable locking state is achieved between the integrated socket and the parameter analyzer housing. A groove is located on the right side of the parameter analyzer, and a groove for vertically guiding the protective plate is located on the right side of the partition plate. A magnetic metal material is installed at the top of the groove. When the protective plate slides upward to the top closed position, the magnetic block and the magnetic metal material are attracted and fixed. The sponge pad is made of antistatic polyurethane material with a conductive carbon film attached to its surface. The conductive carbon film at the bottom of the sponge pad is connected to the grounding terminal of the parameter analyzer via an internal metal wire. The internal space of the parameter analyzer integrates a central control board for executing logic scheduling, a high-frequency data acquisition module, a source measurement unit, and a static feature de-embedding processing module. The source measurement unit employs a precision numerically controlled constant current source to constant voltage source conversion circuit with four-wire Kelvin terminals. The four-wire Kelvin terminals are electrically connected to the integrated socket via an internal shielded cable. The static feature de-embedding processing module uses a field-programmable gate array chip with an internally configured hardware multiplier-accumulator.

[0008] A second aspect of this invention provides a testing method for a semiconductor material testing apparatus, applied to the semiconductor material testing apparatus provided in the first aspect of this invention. This testing method combines a mechanical locking structure with an internal extraction algorithm. It utilizes the physical boundary solidified by pushing a handle into the positioning groove to eliminate dynamic contact displacement at the interface of the test loop connection, and extracts the constant error characteristics of the interface for de-embedding. The testing method includes the following steps: S100, Curing of Mechanical Boundary Conditions and Hardware Activation Steps: Flip the dust cover, pull out the integrated socket, and push the handle horizontally into the positioning groove to lock the integrated socket in a stable locked state. Slide the protective plate downwards to move the probe station out of the storage groove; adjust the probe station to make the probe contact the semiconductor material, and insert the mating connector at the rear end of the probe station into the integrated socket to complete the physical connection of the test circuit.

[0009] S200, static feature extraction steps based on least squares method: The central control board sends instructions to the source measurement unit, and the source measurement unit injects a step calibration test current into the test circuit; the high-frequency data acquisition module synchronously acquires the transient voltage drop sequence under stable locking state; the static feature de-embedding processing module calculates and extracts the static contact impedance constant between the plug and the integrated socket, and at the same time calculates the static bias voltage of the test circuit.

[0010] In step S200, the static feature de-embedding processing module establishes a static linear impedance mathematical model of the contact interface based on the static constant characteristics of the contact impedance under stable locked state. The module then performs an algebraic solution to the static linear impedance mathematical model, calculating the static contact impedance constant and static bias voltage based on the step calibration test current injected by the source measurement unit and the transient voltage drop sequence acquired by the high-frequency data acquisition module.

[0011] The central control board compares the calculated absolute value of the static bias voltage with the preset safety threshold voltage. If the absolute value of the static bias voltage is greater than the safety threshold voltage, the central control board determines that there is a physical connection abnormality and stops the calibration and test control flow. If the absolute value of the static bias voltage is less than or equal to the safety threshold voltage, the central control board determines that the mechanical locking state is safe and effective, and stores the static contact impedance constant and the static bias voltage in the static feature de-embedding processing module.

[0012] S300, Real-time Signal De-embedding Compensation and Characteristic Analysis Steps: The source measurement unit applies the formal test excitation current to the semiconductor material, and the high-frequency data acquisition module acquires the original response voltage; the static feature de-embedding processing module retrieves the static contact impedance constant and static bias voltage, performs de-embedding compensation calculation, and obtains the true electrical response voltage of the semiconductor material; the central control board plots the current-voltage characteristic curve of the semiconductor material.

[0013] In step S300, the static feature de-embedding processing module calls the de-embedding compensation calculation program to subtract the contact physical voltage drop loss component, which is composed of the product of the formal test excitation current and the static contact impedance constant, from the original response voltage acquired by the high-frequency data acquisition module, and simultaneously subtracts the static bias voltage to calculate the true electrical response voltage of the semiconductor material after stripping the external wiring hardware interference and the underlying system bias interference of the test circuit.

[0014] S400, Physical Reset and Anti-collision Sealed Storage Procedure: Disconnect the plug-in connector and pull the handle out of the positioning slot; push the integrated socket back into the parameter analyzer and close the dust cover. Push the probe station into the groove on the side of the parameter analyzer, so that the probe tip rests against the lower surface of the foam pad; slide the protective plate down to the closed position, and the protective plate will remain closed at the lower end due to its own weight. The probe station has now completed the sealed storage process. Working principle: Before testing semiconductor materials, first unfold and fix the front connection components. The operator flips down the dust cover on the lower part of the front surface of the parameter analyzer and then pulls the integrated socket forward along the slide to the outermost side. In order to ensure the overall structural stability when plugging and unplugging the wires, the operator pulls the J-shaped handles on both sides of the integrated socket outward and pushes the handles into the corresponding positioning slots on the front surface of the parameter analyzer. At this time, the integrated socket is rigidly limited and locked to prevent inward retraction or positional displacement when connecting the test wires. After locking, the test wires can be connected to the integrated socket for relevant parameter testing.

[0015] After testing or when the probe station needs to be stored, use the protective storage component on the right. The operator slides the protective plate upwards to open it. The magnetic block at the top of the protective plate is attracted and fixed to the parameter analyzer. Push the probe station into the groove on the right side of the parameter analyzer. During the pushing and positioning process, the top of the probe station enters the internal cavity constructed by the partition plate and presses it against the lower surface of the sponge pad. The deformation and cushioning effect of the sponge pad provides impact protection for the test probe at the top of the probe station. After proper placement, slide the protective plate downwards to the closed position to complete the dustproof sealing and storage protection of the probe station.

[0016] This invention provides a semiconductor material testing apparatus and method. It has the following beneficial effects: 1. This invention improves the measurement accuracy of material electrical characteristics by using the mechanical locking state of the connecting components as the physical boundary condition for the de-embedding algorithm. The stable locking state created by pushing the handle into the positioning slot eliminates dynamic contact displacement at the interface, solidifying the contact impedance as a constant. Based on this constant characteristic, the system fits the transient voltage drop and extracts the contact impedance constant and bias voltage. During the formal testing phase, the system uses the extracted constant to perform de-embedding compensation calculations on the original response voltage, accurately deducting impedance interference from external wiring and restoring the true electrical response voltage of the semiconductor material.

[0017] 2. This invention achieves closed-loop electrical verification of the mechanical physical connection status by introducing a safety threshold determination mechanism based on static bias voltage. The central control board acquires the static bias voltage calculated through fitting and compares its absolute value with the preset safety threshold voltage. If the absolute value of the bias voltage is greater than the safety threshold voltage, the system determines that the handle has a physical connection abnormality, such as limit failure. After identifying the abnormality, the central control board immediately stops the test process and stops the test excitation current output to avoid arcing and breakdown of semiconductor materials caused by loose interface connections, thus ensuring the safety of the test process.

[0018] 3. This invention improves the overall protection performance of the testing device by configuring a concealed integrated socket and a side-protected storage component with an anti-static sponge pad. When not in use, the integrated socket is retracted into the parameter analyzer to prevent exposure and dust accumulation. After the probe station is pushed into the side groove, the probe tip presses firmly against the anti-static sponge pad. The sponge pad absorbs vibration stress through physical deformation to prevent the fragile probe from breaking. The conductive carbon film on the surface of the sponge pad, together with the grounding terminal, establishes a path for parasitic charge discharge for the probe station, eliminating the risk of static electricity accumulation and ensuring both physical and electrical safety of the device when it is not in operation. Attached Figure Description

[0019] Figure 1 This is an overall schematic diagram of a semiconductor material testing device proposed in this invention; Figure 2 This is a schematic diagram showing the dustproof plate of a semiconductor material testing device proposed in this invention in the open state. Figure 3 This is a right view of a semiconductor material testing device proposed in this invention; Figure 4 This is a schematic diagram of a semiconductor material testing device proposed in this invention with the protective plate removed. Figure 5 This is a schematic diagram of the right-side cross-section of a parameter analyzer for a semiconductor material testing device proposed in this invention; Figure 6 This is a flowchart of the testing method of the present invention.

[0020] Among them, 1. Parameter analyzer; 2. Connection component; 3. Protection and storage component; 4. Probe station; 201. Integrated socket; 202. Handle; 203. Dustproof plate; 204. Integrated socket; 205. Positioning groove; 301. Protective plate; 302. Magnetic block; 303. Sponge pad; 304. Divider plate. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example: Reference Figures 1-2 This invention provides a semiconductor material testing device, including a parameter analyzer 1, a connection component 2 at the lower part of the parameter analyzer 1, a probe station 4 electrically connected to the right surface of the parameter analyzer 1 via wires, and a protective storage component 3 on the right side of the parameter analyzer. The connection component 2 includes an integrated socket 201. The front surface of the integrated socket 201 has multiple integrated sockets 204. The left and right sides of the front surface of the integrated socket 201 are slidably connected to handles 202. The lower part of the front surface of the parameter analyzer 1 is rotatably connected to a dustproof plate 203. The lower part of the front surface of the parameter analyzer 1 is provided with a positioning groove 205.

[0023] The lower inner surface of the parameter analyzer 1 has a rectangular groove, which serves as a guide for the horizontal pulling of internal components, ensuring a smooth and stable process without skewing. A control panel is located on the front surface of the parameter analyzer 1, allowing operators to input test commands and view test data, enabling human-machine interaction. The left and right ends of the integrated socket 201 are slidably connected to the parameter analyzer 1. This sliding connection allows the integrated socket 201 to be hidden or pulled out of the parameter analyzer 1 like a drawer, saving external space and providing dust protection when not in operation. The rear end of the integrated socket 201 is electrically connected to the parameter analyzer 1 via a wire. The internal wire is preferably made of flexible Teflon cable with resistance to bending fatigue to accommodate the integrated socket. The repeated pulling and retracting mechanical action of the socket 201 ensures the stability of internal test signal transmission. The integrated socket 204 is designed as a mating connector, which provides a large physical contact area and mechanical clamping force, reducing contact resistance and making it suitable for the precise transmission of weak electrical signals in semiconductor testing. The handle 202 is designed in a J-shape. The J-shape design not only makes it easy for the operator to hook and pull with their fingers, but its bent end can also serve as the insertion end of the physical latch, participating in subsequent locking. There are two sets of positioning slots 205, and the length and width dimensions of the cross-section of the two sets of positioning slots 205 are the same as those of the handle 202. The matching design of the same size allows the handle 202 to move and insert into the positioning slot 205, forming an inward limit on the integrated socket 201, effectively preventing the integrated socket 201 from shrinking inward or shifting and shaking when inserting or removing external test leads.

[0024] Reference Figures 3-5 The protective storage component 3 includes a partition plate 304. The outer surface of the partition plate 304 is fixedly connected to the parameter analyzer 1. A sponge pad 303 is fixedly connected to the inner side of the partition plate 304. A protective plate 301 is slidably connected to the outer side of the partition plate 304. A magnetic block 302 is fixedly connected to the upper end of the protective plate 301.

[0025] A groove is provided on the right side of the partition plate 304, and a magnetic metal material is provided on the top of the groove. This groove is used to guide the external baffle assembly vertically, ensuring the straightness and smoothness of the opening and closing action. The outer surface of the sponge pad 303 is fixedly connected to the parameter analyzer 1. The sponge pad 303 is preferably made of highly resilient antistatic sponge material, which provides flexible contact and cushioning for the fragile probe at the top of the probe station 4 during storage, preventing physical impact from causing the probe to deform or break, and at the same time avoiding static electricity accumulation that could damage the semiconductor device. The outer surface of the protective plate 301 is slidably connected to the parameter analyzer 1. Through the sliding connection, the protective plate 301 can be opened without occupying additional external rotation space. It can operate flexibly on a narrow test bench and is used to isolate external dust. The front and rear sides of the magnetic block 302 are slidably connected to the parameter analyzer 1. The magnetic block 302 slides synchronously with the protective plate 301. When it reaches the closed position, it is tightly attracted to the magnetic metal material preset at the top of the groove on the right side of the parameter analyzer 1 by magnetic force, providing a reliable closing force and preventing the protective plate 301 from accidentally slipping and opening due to its own weight or environmental vibration. The right side of the parameter analyzer 1 has a groove, which provides an embedded dedicated storage space for the probe station 4. This avoids the probe station 4 from being entangled by cables or damaged by external heavy objects when it is stored externally. It significantly improves the integration and storage safety of the overall test device.

[0026] The semiconductor material testing device mainly consists of a parameter analyzer 1, a connection component 2 located at the front end of the parameter analyzer 1, a protective and storage component 3 located on the side of the parameter analyzer 1, and an external probe station 4. The parameter analyzer 1 integrates a central control board for executing logic scheduling, a high-frequency data acquisition module, a source measurement unit, and a static feature de-embedding processing module. As the underlying hardware support, the source measurement unit uses a precision numerically controlled constant current source to constant voltage source conversion circuit with four-wire Kelvin terminals. The four-wire Kelvin terminals are electrically connected to the integrated socket 201 of the connection component 2 through an internal shielded cable, ensuring stable output of minute excitation signals. The static feature de-embedding processing module uses a digital signal processor or a field-programmable gate array (FPGA) chip. The FPGA chip is equipped with a hardware multiplier-accumulator and has a least squares fitting algorithm program programmed inside, specifically used to process and subtract error voltages generated at the interface. For the selection of the microcontroller for the central control board and the pin wiring of the analog-to-digital converter inside the high-frequency data acquisition module, those skilled in the art can refer to the design manual of standard electronic measuring instruments for conventional assembly and configuration. The basic collaborative logic of the microcontroller and the analog-to-digital converter is a well-known technology in this field and will not be described in detail in the specification.

[0027] The connecting component 2 includes an integrated socket 201 slidably installed inside the parameter analyzer 1, a dustproof plate 203 rotatably connected to the outside of the integrated socket 201, and handles 202 located at both ends of the integrated socket 201. The front surface of the parameter analyzer 1 has a positioning groove 205 that matches the size of the handle 202. The mechanical locking structure formed by pushing the handle 202 into the positioning groove 205 not only prevents the integrated socket 201 from retracting, but also provides an absolutely static mechanical boundary condition input for the static feature de-embedding processing module inside the parameter analyzer 1. The protective and storage component 3 includes a protective plate 301 slidably connected to the side of the parameter analyzer 1, a partition plate 304, a magnet 302, and a sponge pad 303 fixed inside the partition plate 304. The sponge pad 303 is made of antistatic polyurethane material with a conductive carbon film attached to its surface. The conductive carbon film at the bottom of the sponge pad 303 is connected to the grounding terminal of the parameter analyzer 1 via an internal metal wire. The antistatic foam pad 303 not only provides a physical shock-proof buffer for the top probe of the probe station 4, but also, in combination with the grounding structure, provides a physical conductive path for the parameter analyzer 1 to discharge residual parasitic charges on the probe surface.

[0028] Reference Figure 6 The testing method performed by the semiconductor material testing device is compatible with the physical characteristics of the aforementioned hardware architecture. The macroscopic process of the testing method consists of four operational steps: S100, the solidification of mechanical boundary conditions and the hardware conduction steps.

[0029] The tester flips over the dust cover 203, pulls out the integrated socket 201, and pushes the handle 202 horizontally into the positioning groove 205 to lock the integrated socket 201 in place. The tester slides down the protective plate 301 to move the probe station 4 out of the storage groove and place it on the work surface. The tester adjusts the probe station 4 to make the probe contact the semiconductor material, and inserts the mating connector at the rear end of the probe station 4 into the integrated socket 204 of the integrated socket 201 to complete the physical connection of the test circuit.

[0030] S200, a static feature extraction step based on the least squares method.

[0031] The central control board sends commands to the source measurement unit, which injects a step-type calibration test current into the test circuit. The high-frequency data acquisition module simultaneously acquires the transient voltage drop sequence under locked conditions. The static feature de-embedding processing module calls a fitting algorithm program to calculate and extract the static contact impedance constant between the plug and integrated socket 204 based on the acquired calibration test current and transient voltage drop sequence, and simultaneously calculates the static bias voltage of the current test circuit. The static feature extraction step provides the basic parameters for subsequent error subtraction.

[0032] S300, Real-time Signal De-embedding Compensation and Characteristic Analysis Steps.

[0033] The source measurement unit applies the formal test excitation current to the semiconductor material, and the high-frequency data acquisition module acquires the raw response voltage, including interface errors. The static feature de-embedding processing module retrieves the static contact impedance constant and static bias voltage extracted in step S200, performs de-embedding compensation calculations, subtracts error components, and obtains the true electrical response voltage of the semiconductor material. The central control board plots the current-voltage characteristic curve of the semiconductor material based on the correspondence between the formal test excitation current and the true electrical response voltage.

[0034] S400, physical reset and anti-collision closed storage steps.

[0035] The tester disconnects the plug-in connector of the probe station 4, pulls the handle 202 out of the positioning slot 205, and releases the rigid limit of the integrated socket 201. The tester pushes the integrated socket 201 back into the parameter analyzer 1 and closes the dustproof plate 203. The tester pushes the probe station 4 into the groove on the side of the parameter analyzer 1, so that the probe tip of the probe station 4 abuts against the lower surface of the anti-static foam pad 303, and slides the protective plate 301 upward, so that the magnetic block 302 is attracted and closed with the parameter analyzer 1, completing the sealing and protection of the probe station 4.

[0036] Step S100 serves as the preliminary physical foundation of the entire testing method, encompassing the specific mechanical operations that transform dynamic contact into stable physical boundaries, as well as subsequent wiring connections. To ensure that the static feature de-embedding processing module within the parameter analyzer 1 can acquire stable error input parameters, step S100 is specifically broken down into the following execution details: S110, Display operation of interface components.

[0037] The tester flips down the dustproof plate 203 on the lower front surface of the parameter analyzer 1, exposing the integrated socket 201 hidden inside the parameter analyzer 1. Then, along the rectangular groove on the lower inner surface of the parameter analyzer 1, the integrated socket 201 is pulled horizontally outward to the end of its physical travel. The rectangular groove contains a linear guide structure with ball bearings. This linear guide structure restricts the integrated socket 201 to movement only in the horizontal forward-backward direction, limiting its freedom of movement in the vertical and left-right directions.

[0038] S120, based on mechanical boundary curing operation of handle engagement.

[0039] The front surface of the integrated socket 201 has transverse guide grooves on both sides. The handle 202 is slidably connected to the integrated socket 201 through the transverse guide grooves. The tester pulls the J-shaped handles 202 on both sides of the integrated socket 201 laterally outward, aligning the bent end of the handle 202 with the positioning groove 205 on the front surface of the parameter analyzer 1 and pushing it inward, so that the bent end of the handle 202 is fully inserted into the positioning groove 205. An elastic damping pad is provided inside the positioning groove 205. The bent end of the handle 202 forms a tight fit with the elastic damping pad, locking the remaining horizontal front-back freedom of the integrated socket 201, thus creating a stable locked state between the integrated socket 201 and the housing of the parameter analyzer 1. This stable locked state blocks the minor mechanical displacement caused by external environmental vibration or cable pulling, keeping the contraction resistance between the plug and the integrated socket 204 constant. The dynamic contact impedance before the minor mechanical displacement is eliminated and the static contact impedance after the minor mechanical displacement is eliminated obey the following impedance state equation: In the impedance state equation Represents the passage of time The overall contact resistance varies. Represents the volume resistance of the contact element; Represents the film resistance of the contact surface; Represents contact pressure Compared with the actual conductive spot area The varying contraction resistance. When handle 202 is pushed into positioning groove 205 to form a mechanical limit lock, the contact pressure... Compared with the actual conductive spot area This is converted into a constant that does not change with time. Overall contact resistance. The dynamic random variable is fixed into a static contact resistance constant. Static contact resistance constant The formation of these conditions provides the physical boundary conditions that can be accurately extracted for subsequent fitting algorithms.

[0040] S130, Probe station release and test preparation operation.

[0041] The tester slides down the protective plate 301 on the right side of the parameter analyzer 1, causing the magnetic block 302 at the upper end of the protective plate 301 to detach from the parameter analyzer 1. The tester then horizontally moves the probe station 4 out of the groove on the right side of the parameter analyzer 1, causing the tip of the probe station 4 to detach from the physical contact with the sponge pad 303 inside the partition plate 304, and places the probe station 4 on a separate operating table. The tester places the semiconductor material to be tested on the supporting surface of the probe station 4 and adjusts the three-axis micro-motion knob of the probe station 4 to make physical contact between the micro probe of the probe station 4 and the surface test electrode of the semiconductor material to be tested.

[0042] S140, Hardware connection operation for the test circuit.

[0043] The tester obtains the external test lead extending from the rear of the probe station 4. The end of the external test lead is connected to a mating connector with an internal beryllium copper spring. The tester inserts the mating connector into the integrated socket 204, which is in a stable locked state. The beryllium copper spring undergoes elastic deformation inside the integrated socket 204 and adheres to the inner metal layer of the integrated socket 204. During the mating process, the integrated socket 201 relies on the mechanical engagement structure of the handle 202 and the positioning groove 205 to withstand the mating thrust. The mechanical engagement structure prevents the integrated socket 201 from retracting into the parameter analyzer 1, completing the physical connection operation of the test circuit. For the specific threaded drive structure of the three-axis micro-motion knob inside the probe station 4 and the multi-layer coaxial shielding insulation structure of the external test lead, those skilled in the art can refer to the standard mechanical manual of commercial probe stations for configuration and connection. The probe station micro-motion structure and coaxial shielding structure are well-known technologies in the field and will not be described in detail in this specification. After the physical connection of the test loop is completed in step S140, the control logic inside parameter analyzer 1 enters step S200. Step S200 is a static feature extraction step based on the least squares method. To ensure the accuracy of the extraction algorithm and prevent the risk of hardware overload of the test equipment, step S200 is specifically decomposed into four execution details: feature acquisition, mathematical modeling, fitting solution, and safety judgment. S210, calibration signal injection and transient feature acquisition operation.

[0044] The central control board performs a basic level verification of the physical connectivity of the test circuit. Upon successful verification, the central control board sends a calibration start command to the source measurement unit. The source measurement unit receives the calibration start command and injects multiple sets of step-type calibration test currents into the connected test circuit. The step-type calibration test current is set to a microampere-level non-destructive testing signal, and is denoted as [missing information]. .variable This represents the total number of sampling points during the calibration and testing phase. (Variable) Represents the sequence number of a single sample, and The value range is 1 to The high-frequency data acquisition module and the source measurement unit operate synchronously based on a shared clock signal. The high-frequency data acquisition module acquires the transient voltage drop sequence at the test loop endpoints corresponding to each set of step calibration test currents. The transient voltage drop sequence is denoted as... For the trigger synchronization mechanism and clock distribution circuit inside the high-frequency data acquisition module, those skilled in the art can refer to the synchronous sampling architecture of a digital oscilloscope for design. The trigger synchronization mechanism of the high-frequency data acquisition module is a well-known technology in the field and will not be described in detail in the specification.

[0045] S220, the operation for constructing a static linear impedance mathematical model.

[0046] Thanks to the stable locking state formed by the engagement of handle 202 and positioning groove 205 in step S120, the spatial coordinates of the integrated socket 201 are fixed. This fixed spatial coordinates ensure that the microscopic physical contact area between the probe and the semiconductor material surface, and between the mating connector and the integrated socket 204, remains constant. This constant microscopic physical contact area constrains the contact impedance at the contact interface to a static constant that does not fluctuate over time. Based on the static constant characteristic of the contact impedance, the static feature de-embedding processing module establishes a static linear impedance mathematical model of the contact interface. The static linear impedance mathematical model is defined as: In the static linear impedance mathematical model Representing the The transient voltage drop obtained from the second sampling; Representing the The step calibration test current injected next; This represents the static contact impedance constant of the test circuit, including the terminal interface resistance. This represents the static bias voltage of the test circuit when no external excitation is injected. Static bias voltage This includes the zero-point drift voltage of the internal analog circuitry of the system and the thermoelectric error voltage caused by the temperature difference between dissimilar metal materials at the contact terminals.

[0047] S230, Least squares fitting solution operation for characteristic constants.

[0048] The static feature de-embedding module invokes the built-in least squares fitting algorithm to perform an algebraic solution on the constructed static linear impedance mathematical model. The least squares fitting algorithm, with the objective function of minimizing the sum of squared voltage errors, calculates the static contact impedance constant with the highest statistical confidence. and static bias voltage Static contact resistance constant The calculation formula is defined as follows: static bias voltage The calculation formula is defined as follows: The hardware multiply-accumulator configured inside the static feature de-embedding processing module employs a parallel pipelined architecture to perform the accumulation and multiplication operations involved in the fitting formula. This parallel pipelined architecture ensures the data throughput and real-time performance of the parameter analyzer 1 during the impedance feature extraction stage.

[0049] S240, Safety threshold verification and early warning operation for mechanical limit status.

[0050] After the characteristic constants are calculated, the central control board uses the calculated static bias voltage. A closed-loop verification of the mechanical locking state in step S120 is performed. A safety threshold voltage is preset and stored in the non-volatile memory of the central control board. The safety threshold voltage is denoted as... The central control board obtains the static bias voltage. and static bias voltage The absolute value and the safety threshold voltage Perform numerical comparison. If the static bias voltage The absolute value is greater than the safety threshold voltage. Or the static contact resistance constant calculated in step S230. Exhibiting nonlinear divergent characteristics, the central control board determines that the current test system has a physical connection abnormality. This abnormality corresponds to mechanical limit failure caused by the handle 202 not being pushed to the deepest point of the positioning slot 205, or to physical contamination particles inside the integrated socket 204 causing leakage. Upon determining a physical connection abnormality, the central control board immediately halts the calibration and test control flow of the parameter analyzer 1. The central control board drives the buzzer and LEDs on the front control panel of the parameter analyzer 1 to output audible and visual alarm signals, instructing the test personnel to re-check the mechanical connection components. If the static bias voltage... The absolute value is less than or equal to the safety threshold voltage. And static contact resistance constant To ensure stable convergence values, the central control board determines that the mechanical locking state is safe and effective, and sets the static contact resistance constant. and static bias voltage The error parameters are written into the high-speed random access memory of the static feature de-embedding processing module to solidify them for use in subsequent formal test signal de-embedding steps.

[0051] After step S240 determines that the mechanical locking state is safe and effective and completes the error parameter solidification, the underlying logic of parameter analyzer 1 enters step S300. Step S300 is the real-time signal de-embedding compensation and characteristic analysis step. Step S300 aims to eliminate interference components introduced by the physical connection interface between the integrated socket 204 and the probe station wire connector, as well as the underlying analog circuitry of parameter analyzer 1, to restore the true electrical response of the semiconductor material unaffected by the external measurement system. Step S300 is specifically broken down into three execution details: parameter configuration and data acquisition, hardware de-embedding calculation, and characteristic model construction. S310, formal test stimulus application and raw data synchronous acquisition operation.

[0052] The tester inputs the formal test threshold and step parameter commands for the semiconductor material through the control panel located on the front surface of the parameter analyzer 1. The control panel converts the formal test threshold and step parameter commands into digital control signals and sends them to the central control board. The central control board parses the digital control signals and drives the high-precision digital-to-analog converter circuit inside the source measurement unit. Based on the digital control signals, the source measurement unit outputs a stepped formal test excitation current to the completed test loop. The formal test excitation current is denoted as... In the formal test of the excitation current During the synchronous cycle flowing through the semiconductor material, the analog-to-digital converter inside the high-frequency data acquisition module performs high-frequency sampling of the voltage signal at the test circuit endpoints. The high-frequency data acquisition module quantizes the acquired analog voltage signal into a raw response voltage sequence composed of discrete sampling points. The raw response voltage is denoted as... Original response voltage It is the sum of the intrinsic physical voltage drop of the semiconductor material, the contact voltage drop when the handle 202 and the positioning groove 205 are engaged and locked, and the bias voltage of the underlying system of the test circuit.

[0053] S320 is a real-time digital de-embedding operation based on a hardware multiply-accumulator.

[0054] The high-frequency data acquisition module quantizes the raw response voltage. The sequence is transmitted to the static feature de-embedding processing module via the internal high-speed data bus. The static feature de-embedding processing module retrieves the static contact impedance constant calculated and fixed in step S230 from the internal high-speed random access memory. With static bias voltage Because the handle 202 and the positioning groove 205 form a mechanically stable locked state, the static contact resistance is constant. No numerical drift occurs during the formal testing cycle. The field-programmable gate array (FPGA) chip inside the static feature de-embedding processing module executes the digital de-embedding compensation operation program driven by the internal clock signal. The FPGA chip calls the hardware multiplier, utilizing the formal test excitation current. Multiply by the static contact resistance constant The voltage loss component at the mechanical locking interface is calculated. The field-programmable gate array (FPGA) chip calls the hardware accumulator to process the raw response voltage read by the high-frequency data acquisition module. Subtract the calculated voltage loss component and static bias voltage After subtracting the hardware impedance interference and zero-point drift interference from the parameter analyzer 1 itself, the electrical response voltage, representing the true physical properties of the semiconductor material, is calculated. The true electrical response voltage is denoted as... The de-embedding compensation formula is defined as follows: In the de-embedding compensation formula This represents the true electrical response voltage after removing external wiring and internal system errors of the parameter analyzer 1; This represents the raw response voltage directly read by the high-frequency data acquisition module; The current value represents the formal test excitation current output by the source measurement unit at the current moment. This represents the static contact resistance constant extracted when the handle 202 and the positioning groove 205 are mechanically and stably locked. This represents the system static bias voltage constant when there is no excitation injection in the test circuit.

[0055] S330, Electrical Parameter Evaluation and Characteristic Curve Construction Operation.

[0056] The static feature de-embedding module calculates the actual electrical response voltage. The sequence is transmitted back to the central control board. The central control board then transmits the formal test excitation current output from the source measurement unit. Sequence and Real Electrical Response Voltage The sequence undergoes time-domain alignment and one-dimensional array mapping. The central control board constructs a current-voltage characteristic curve data model of the semiconductor material based on the one-dimensional array mapping relationship. For the calculation of the semiconductor material breakdown voltage threshold, the extraction of leakage current characteristic parameters, and the rendering algorithms for related charts, those skilled in the art can refer to the conventional analysis models in the fundamental theory of semiconductor device testing for programming implementation. The breakdown voltage threshold calculation and chart rendering algorithms are well-known technologies in this field and will not be elaborated further in this specification. The central control board outputs the constructed current-voltage characteristic curve data model to the control panel display screen for visualization. Simultaneously, the central control board displays the actual electrical response voltage of the semiconductor material. The sequence is stored in the internal non-volatile memory to complete the measurement, analysis and de-intercalation process of the core electrical parameters of the semiconductor material.

[0057] The S400 physical reset and anti-collision enclosure operation is as follows: After data storage and visualization are completed in step S330, the electrical test process of the test circuit ends. The tester disconnects the plug-in connector inside the integrated socket 204. The tester pulls the handle 202 outward laterally out of the positioning slot 205, releasing the stable locking state between the integrated socket 201 and the parameter analyzer 1. The tester pushes the integrated socket 201 into the parameter analyzer 1 along the rectangular slide to the physical limit end point, and flips the dustproof plate 203 upward to close it. In the probe station storage stage, the tester pushes the probe station 4 into the groove on the right side of the parameter analyzer 1. The tester adjusts the position of the probe station 4 so that the probe tip of the probe station 4 enters the internal cavity constructed by the partition plate 304. The probe tip of the probe station 4 presses against the lower surface of the sponge pad 303, and the sponge pad 303 absorbs residual stress through physical deformation. The tester slides the protective plate 301 downward to the closed position. The magnetic block 302 at the upper end of the protective plate 301 detaches from the parameter analyzer 1 and remains in a fixed state. The protective plate 301 is held in a closed state at the lower end by its own gravity. The probe station 4 completes the physical impact protection and dustproof sealing and storage process, and the parameter analyzer 1 returns to its initial standby open circuit state.

[0058] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A semiconductor material testing device, comprising a parameter analyzer (1), characterized in that: The lower part of the parameter analyzer (1) is provided with a connecting component (2), the right surface of the parameter analyzer (1) is electrically connected to a probe station (4) via a wire, and the right side of the parameter analyzer is provided with a protective storage component (3). The connection component (2) includes an integrated socket (201), the front surface of which has multiple integrated sockets (204), handles (202) are slidably connected to the left and right sides of the front surface of the integrated socket (201), a dustproof plate (203) is rotatably connected to the lower part of the front surface of the parameter analyzer (1), and a positioning groove (205) is provided on the lower part of the front surface of the parameter analyzer (1).

2. The semiconductor material testing device according to claim 1, characterized in that: The protective storage component (3) includes a partition plate (304), the outer surface of which is fixedly connected to the parameter analyzer (1), a sponge pad (303) is fixedly connected to the inner side of the partition plate (304), a protective plate (301) is slidably connected to the outer side of the partition plate (304), and a magnetic block (302) is fixedly connected to the upper end of the protective plate (301).

3. The semiconductor material testing device according to claim 1, characterized in that: The lower part of the inner surface of the parameter analyzer (1) is provided with a rectangular sliding groove, and the front surface of the parameter analyzer (1) is provided with a control panel.

4. The semiconductor material testing device according to claim 1, characterized in that: The left and right ends of the integrated socket (201) are slidably connected to the parameter analyzer (1), and the rear end of the integrated socket (201) is electrically connected to the parameter analyzer (1) through a wire.

5. The semiconductor material testing device according to claim 1, characterized in that: The integrated socket (204) is configured as a plug-in connector, the handle (202) is configured as a J-shape, and the positioning groove (205) is provided in two sets, and the length and width dimensions of the two sets of positioning grooves (205) at the cross-section are the same as those of the handle (202).

6. The semiconductor material testing device according to claim 2, characterized in that: The partition plate (304) has a sliding groove on its right side, the outer surface of the sponge pad (303) is fixedly connected to the parameter analyzer (1), the outer surface of the protective plate (301) is slidably connected to the parameter analyzer (1), the front and rear sides of the magnetic block (302) are slidably connected to the parameter analyzer (1), and a groove is provided on the right side of the parameter analyzer (1).

7. A semiconductor material testing device according to claim 2, characterized in that, The sponge pad (303) is made of antistatic polyurethane material with a conductive carbon film attached to its surface. The conductive carbon film at the bottom of the sponge pad (303) is connected to the grounding terminal of the parameter analyzer (1) through an internal metal wire. The internal space of the parameter analyzer (1) integrates a central control board for executing logic scheduling, a high-frequency data acquisition module, a source measurement unit, and a static feature de-embedding processing module.

8. A semiconductor material testing device according to claim 7, characterized in that, The source measurement unit adopts a precision numerical control constant current source and constant voltage source conversion circuit with a four-wire Kelvin terminal block. The four-wire Kelvin terminal block is electrically connected to the integrated socket (201) through an internal shielded ribbon cable. The static feature de-embedding processing module uses a field-programmable gate array chip with an internally configured hardware multiplier-accumulator.

9. A testing method for a semiconductor material testing device, characterized in that, The test method is applied to the semiconductor material testing apparatus as described in any one of claims 1 to 8, and the test method includes the following steps: S100, Mechanical boundary condition solidification and hardware connection steps: flip the dust cover (203), pull out the integrated socket (201), push the handle (202) horizontally into the positioning groove (205) to limit and lock the integrated socket (201) to form a stable locking state; slide the protective plate (301) down to move the probe station (4) out of the storage groove; adjust the probe station (4) to make the probe contact the semiconductor material, insert the plug-in type connector at the rear end of the probe station (4) into the integrated socket (204) of the integrated socket (201) to complete the physical connection of the test circuit; S200, static feature extraction steps based on least squares method: the central control board sends instructions to the source measurement unit, the source measurement unit injects a step calibration test current into the test circuit; the high-frequency data acquisition module synchronously acquires the transient voltage drop sequence under stable locking state; the static feature de-embedding processing module calculates and extracts the static contact impedance constant between the plug and the integrated socket (204), and at the same time calculates the static bias voltage of the test circuit; S300, Real-time Signal De-embedding Compensation and Characteristic Analysis Steps: The source measurement unit applies the formal test excitation current to the semiconductor material, and the high-frequency data acquisition module acquires the original response voltage; the static feature de-embedding processing module retrieves the static contact impedance constant and static bias voltage, performs de-embedding compensation calculation, and obtains the true electrical response voltage of the semiconductor material; the central control board plots the current-voltage characteristic curve of the semiconductor material. S400, Physical Reset and Anti-collision Enclosure Storage Steps: Unplug the plug-in connector and pull the handle (202) out of the positioning slot (205); push the integrated socket (201) back into the parameter analyzer (1) and close the dustproof plate (203); push the probe station (4) into the groove on the side of the parameter analyzer (1) so that the probe tip of the probe station (4) abuts against the lower surface of the sponge pad (303); slide the protective plate (301) down to the closed position, and the protective plate (301) is kept closed at the lower end by its own weight.

10. The semiconductor material testing apparatus and method according to claim 9, characterized in that, In step S200, the specific execution logic of the static feature extraction step is as follows: The static feature de-embedding processing module establishes a static linear impedance mathematical model of the contact interface based on the static constant characteristics of the contact impedance. The static feature de-embedding processing module performs algebraic solution on the static linear impedance mathematical model to calculate the static contact impedance constant and static bias voltage. The central control board compares the absolute value of the static bias voltage with the preset safety threshold voltage. If the absolute value of the static bias voltage is greater than the safety threshold voltage, the central control board determines that there is an abnormal physical connection and stops the calibration and test control flow. If the absolute value of the static bias voltage is less than or equal to the safety threshold voltage, the central control board determines that the mechanical locking state is safe and effective and solidifies the static contact impedance constant and the static bias voltage.

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