Abnormality detection method and system of servo driver, servo driver and medium

Abstract

The invention relates to an anomaly detection method and system of a servo driver, the servo driver and a medium. The method is applied to a servo driver, and comprises the following steps: when a target interrupt period arrives, performing zero clearing on a count value of a target timer through a target kernel; wherein the target timer is used for generating a counting overflow event when the counting value of the target timer reaches the counting period of the target timer; the counting period of the target timer is not less than the target interruption period; and under the condition that the counting overflow event occurs in the target timer, reporting the timeout abnormity of the target kernel to the controller, and stopping outputting the pulse width modulation signal. By adopting the method, the overtime abnormity of the target kernel can be detected in time, and the pulse width modulation signal can be blocked, so that the safety of servo control is ensured.

Description

Technical Field

[0001] This application relates to the field of servo control technology, and in particular to a method, system, servo driver, and medium for detecting anomalies in a servo driver. Background Technology

[0002] In a servo control system, the servo driver is the key hub between the upper-level controller and the servo motor. It can convert the control signals from the upper-level controller into pulse width modulation signals that the servo motor can execute, so as to drive the servo motor to complete the required mechanical motion.

[0003] In traditional technology, the upper-level controller periodically checks the status of the servo drive for abnormalities. However, this method has limitations, as it is difficult to capture kernel timeout exceptions occurring within the servo drive in a timely manner, thus failing to guarantee the safety of servo control. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, system, servo driver, and medium for detecting anomalies in a servo driver that can ensure the safety of servo control, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides an anomaly detection method for a servo driver, applied to a servo driver; the method includes: Whenever the target interrupt cycle arrives, the target kernel resets the count value of the target timer to zero; wherein, the target timer is used to trigger a count overflow event when its count value reaches its own count cycle; the count cycle of the target timer is not less than the target interrupt cycle; In the event of the target timer overflowing, the timeout exception of the target kernel is reported to the controller, and the output of the pulse width modulation signal is stopped.

[0006] Secondly, this application also provides an anomaly detection system for a servo driver, comprising: The system includes a target kernel, a target timer, and a pulse width modulation module; The target kernel is used to clear the count value of the target timer whenever the target interrupt cycle arrives; The target timer is used to trigger a count overflow event when its count value reaches its own count cycle; the count cycle of the target timer is not less than the target interrupt cycle; The target kernel is also configured to report a timeout exception of the target kernel to the controller in the event that the target timer causes the count overflow event; The pulse width modulation module is used to stop outputting the pulse width modulation signal when the target timer experiences the count overflow event.

[0007] Thirdly, this application also provides a servo driver, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the method described above.

[0008] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-described method.

[0009] The aforementioned servo driver anomaly detection method, system, servo driver, and medium, whenever the target interrupt cycle arrives, reset the target timer's count value to zero via the target kernel. The target timer is used to trigger a count overflow event when its count value reaches its own count cycle. The target timer's count cycle is not less than the target interrupt cycle. By setting a target timer whose count value is reset by the target kernel, under normal target kernel operation, the target timer's count value can be reset promptly, preventing a count overflow event. Conversely, in the event of a timeout anomaly in the target kernel, the target timer's count value cannot be reset promptly, leading to a count overflow event. Therefore, the target timer's count overflow event reflects the target kernel's timeout anomaly. Furthermore, in the event of a target timer count overflow event, the timeout anomaly of the target kernel is reported to the controller, and the output of the pulse width modulation signal is stopped. This timely reporting of the target kernel's timeout anomaly and blocking of the pulse width modulation signal prevents inaccurate pulse width modulation signals from causing abnormal motor movement, thereby ensuring the safety of servo control. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is an application environment diagram of a servo driver anomaly detection method provided in an embodiment of this application.

[0012] Figure 2 This is a flowchart illustrating a method for detecting anomalies in a servo driver, as provided in an embodiment of this application.

[0013] Figure 3 This is a schematic diagram illustrating a target timer overflow event provided in an embodiment of this application.

[0014] Figure 4A This is a flowchart illustrating the steps executed by the first kernel when a first interrupt cycle arrives, as provided in an embodiment of this application.

[0015] Figure 4B This is a flowchart illustrating the steps executed by the second kernel when a second interrupt cycle arrives, as provided in an embodiment of this application.

[0016] Figure 5 This is a schematic diagram illustrating the routing of a count overflow event to a pulse width modulation module, as provided in an embodiment of this application.

[0017] Figure 6A This is a structural block diagram of a servo driver anomaly detection system provided in an embodiment of this application.

[0018] Figure 6B This is a structural block diagram of another servo driver anomaly detection system provided in an embodiment of this application.

[0019] Figure 6C This is a structural block diagram of another servo driver anomaly detection system provided in an embodiment of this application.

[0020] Figure 7 This is an internal structure diagram of a servo driver provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] The servo driver anomaly detection method provided in this application embodiment can be applied to, for example... Figure 1 The application environment shown is illustrated. The servo driver includes a target kernel, a target timer, and a pulse width modulation module. Each servo driver 102 communicates with the controller 104 via an industrial fieldbus.

[0023] The servo driver 102 can clear the count value of the target timer through the target kernel whenever the target interrupt cycle arrives. The target timer is used to trigger a count overflow event when its count value reaches its own count cycle. The count cycle of the target timer is not less than the target interrupt cycle. In the event of a count overflow event of the target timer, a timeout exception of the target kernel is reported to the controller 104, and the output of the pulse width modulation signal is stopped.

[0024] The controller 104 can display the corresponding prompt information for the timeout exception of the target kernel on the screen. The controller 104 can also, for each downstream servo driver, control each servo driver to stop running or stop outputting pulse width modulation signals when a timeout exception occurs in the target kernel of the servo driver. The controller can be, but is not limited to, at least one of electronic devices or programmable logic controllers. Electronic devices can include at least one of terminals or servers.

[0025] In one exemplary embodiment, such as Figure 2 The diagram shows a flowchart of a method for detecting anomalies in a servo driver, which is applied to... Figure 1 The following steps are used as an example of the servo driver in the process of illustration, including steps 202 to 204.

[0026] Step 202: Whenever the target interrupt cycle arrives, the target kernel resets the count value of the target timer to zero; the target timer is used to trigger a count overflow event when its count value reaches its own count cycle; the count cycle of the target timer is not less than the target interrupt cycle.

[0027] The target interrupt period is the interval between periodic interrupts that trigger the target kernel to execute the corresponding interrupt service routine. For example, if the target interrupt period is 1ms, then the target kernel will execute the code in the corresponding interrupt service routine once every 1ms. Normally, the target kernel executes code sequentially. When a periodic interrupt occurs, the target kernel pauses the currently executing code and executes the corresponding interrupt service routine. This means that the code in the interrupt service routine has a higher execution priority than non-interrupt service routine code. Furthermore, if multiple periodic interrupts occur simultaneously, the interrupt service routine corresponding to the highest priority interrupt has the highest execution priority.

[0028] For example, the servo driver can enable the target timer after setting its counting period based on the target interrupt cycle via the target kernel. The target timer, once enabled, continuously counts, resuming counting from zero whenever the count value is reset, and triggering a count overflow event when the count value reaches its own counting cycle. Whenever the target interrupt cycle arrives, the target kernel executes the corresponding interrupt service routine to reset the target timer's count value to zero.

[0029] In some embodiments, the servo driver is controlled by a microcontroller unit (MCU). The MCU has a target kernel. Specifically, the MCU can handle the servo driver's control functions for the servo motor, as well as the information interaction functions with the upper-level controller. It is understood that the MCU may experience excessively long interrupt calculation times due to malfunctions in the target kernel, resulting in the inability to timely interact with the controller and update the pulse width modulation (PWM) signal used for motor control, thus affecting the safety of servo motor operation. Whenever a target interrupt cycle arrives, the target kernel resets the target timer's count value. This ensures that when the target kernel is not malfunctioning, the target timer's count value is reset promptly; when a target kernel malfunction causes excessively long interrupt calculation times, the target timer overflows due to not being reset in time. Therefore, the target timer's overflow event can promptly reflect the problem of excessively long interrupt calculation times caused by target kernel malfunctions. In the event of a target timer overflow event, the MCU reports the target kernel's timeout malfunction to the controller and stops outputting the PWM signal, ensuring the safety of servo motor operation.

[0030] In some embodiments, such as Figure 3 The diagram illustrates a scenario where a target timer experiences a count overflow event. If the target kernel resets the target timer's count to zero, the count overflow event will not be triggered if the target timer's count value does not reach the counting period. However, if the target timer's count value is not reset to zero, a count overflow event will occur if the count value reaches the counting period.

[0031] Step 204: In the event of a count overflow event of the target timer, report the timeout exception of the target kernel to the controller and stop outputting the pulse width modulation signal.

[0032] The overflow event refers to the event where the count value of the target timer reaches the count period. An event can be understood as a hardware signal triggered by an on-chip peripheral, used directly through the hardware link to trigger the operation of other peripherals without the need for target kernel intervention. The overflow event is triggered by the target timer and directly through the hardware link to stop the Pulse-Width Modulation (PWM) module from outputting the PWM signal.

[0033] For example, the servo driver can report a timeout exception of the target kernel to the controller via the target kernel in the event of a target timer overflow. Upon detecting a count overflow event, the pulse width modulation module stops outputting the pulse width modulation signal.

[0034] In some implementations, the servo driver can route a count overflow event to the pulse width modulation module via a hardware link, triggering the pulse width modulation module to stop outputting the pulse width modulation signal.

[0035] In some embodiments, the servo driver can send target exception data to the controller when a target timer overflows, thereby reporting timeout exceptions of the target kernel. The servo driver can periodically send heartbeat messages to the controller via the target kernel. The controller can determine the status of the servo driver based on the heartbeat messages. It is understood that once the target kernel freezes, the servo driver will be unable to send either target exception data or heartbeat messages. The controller can determine that the servo driver is in an abnormal state upon receiving target exception data or failing to receive a heartbeat message after a timeout, and control the servo driver to stop running or stop outputting pulse width modulation signals.

[0036] In some embodiments, the servo driver can route a count overflow event to the pulse width modulation module based on a crossbar or a block interconnect network to trigger the pulse width modulation module to stop outputting the pulse width modulation signal.

[0037] In some embodiments, the target timer can trigger a count overflow event by issuing an overflow event signal or setting the overflow flag in its status register to valid when its count value reaches its own counting period. The servo driver can route the overflow event signal to the pulse width modulation module via a hardware link to trigger the pulse width modulation module to stop outputting the pulse width modulation signal.

[0038] In some embodiments, the servo driver can generate a fault blocking signal by the pulse width modulation module when a count overflow event is detected, so as to control the local end to stop sending pulse width modulation signals.

[0039] In some embodiments, there are at least two target kernels. Each target kernel corresponds to a different target timer. The target interrupt cycle refers to the interrupt cycle of the target interrupt of the target kernel. The target interrupt can be, but is not limited to, the highest priority interrupt. Each target kernel can correspond to a different target interrupt cycle. For each target kernel, the servo driver can, whenever the target interrupt cycle corresponding to that target kernel arrives, clear the count value of the corresponding target timer through that target kernel, and if a count overflow event is detected for the target timer corresponding to another kernel, report the timeout exception of the other kernel to the controller. Other kernels refer to target kernels other than the target kernel mentioned above.

[0040] In the above-described servo driver anomaly detection method, the target kernel resets the target timer's count value to zero whenever the target interrupt cycle arrives. The target timer is used to trigger a count overflow event when its count value reaches its own count cycle. The target timer's count cycle is not less than the target interrupt cycle. By setting a target timer whose count value is reset by the target kernel, under normal target kernel operation, the target timer's count value can be reset promptly, preventing a count overflow event. Conversely, in the event of a timeout anomaly in the target kernel, the target timer's count value cannot be reset promptly, leading to a count overflow event. Therefore, the target timer's count overflow event reflects the target kernel's timeout anomaly. Furthermore, in the event of a target timer count overflow event, the timeout anomaly of the target kernel is reported to the controller, and the output of the pulse width modulation signal is stopped. This timely reporting of the target kernel's timeout anomaly and blocking of the pulse width modulation signal prevents inaccurate pulse width modulation signals from causing abnormal motor movement, thereby ensuring the safety of servo control.

[0041] In some embodiments, the target kernel includes at least one of a first kernel or a second kernel; the target interrupt cycle includes at least one of a first interrupt cycle or a second interrupt cycle; the target timer includes at least one of a first timer or a second timer; the counting period of the first timer is not less than the first interrupt cycle; the counting period of the second timer is not less than the second interrupt cycle; whenever the target interrupt cycle arrives, the count value of the target timer is cleared by the target kernel, including: whenever the first interrupt cycle arrives, the count value of the first timer is cleared by the first kernel, and a count overflow event of the second timer is detected; whenever the second interrupt cycle arrives, the count value of the second timer is cleared by the second kernel, and a count overflow event of the first timer is detected.

[0042] The first interrupt cycle is the periodic interrupt interval that triggers the execution of the corresponding interrupt service routine by the first kernel. The second interrupt cycle is the periodic interrupt interval that triggers the execution of the corresponding interrupt service routine by the second kernel.

[0043] For example, the servo driver can configure the counting period of a first timer based on a first interrupt cycle and the counting period of a second timer based on a second interrupt cycle via a first kernel or a second kernel. After configuration, the first and second timers are started to trigger the first timer and the second timer to begin counting. It can be understood that both the first and second timers will trigger their own count overflow events when their count values ​​reach their own counting periods.

[0044] The servo driver can, upon the arrival of the first interrupt cycle, execute the corresponding interrupt service routine through the first kernel to clear the count value of the first timer and detect whether the second timer has overflowed. Similarly, upon the arrival of the second interrupt cycle, the second kernel can execute the corresponding interrupt service routine to clear the count value of the second timer and detect whether the first timer has overflowed.

[0045] In some embodiments, the servo driver can report a timeout exception of the first timer to the controller via the second kernel when a count overflow event of the first timer is detected. Similarly, the first kernel can report a timeout exception of the second timer to the controller when a count overflow event of the second timer is detected. The count overflow event of either the first or second timer is routed to the pulse width modulation module to trigger the pulse width modulation module to stop outputting the pulse width modulation signal.

[0046] In this embodiment, whenever the first interrupt cycle arrives, the first kernel clears the count value of the first timer and checks whether the second timer has experienced a count overflow event; whenever the second interrupt cycle arrives, the second kernel clears the count value of the second timer and checks whether the first timer has experienced a count overflow event. If either target kernel experiences a timeout exception and fails to clear the corresponding target timer in time, the other target kernel will detect that the corresponding target timer has experienced a count overflow event. This implements a dual-core cross-monitoring mechanism, which can detect timeout exceptions of the first and second kernels in a timely manner.

[0047] In some embodiments, when a count overflow event occurs in the target timer, reporting a timeout exception of the target kernel to the controller includes: the first kernel reporting a timeout exception of the second kernel to the controller when a count overflow event of the second timer is detected; and the second kernel interacting with the first kernel when a count overflow event of the first timer is detected, causing the first kernel to report a timeout exception of the first kernel to the controller.

[0048] For example, the servo driver has a dual-core microcontroller unit (MCU). In the dual-core MCU, the first core mainly handles communication and application functions, while the second core mainly handles motor control functions. The first and second cores can periodically execute their respective code at their fixed execution frequencies. Target exception data may include first exception data and second exception data. Since the first core mainly handles communication and application functions, communication between the servo driver and the upper-level controller is mainly implemented based on the first core. Therefore, the servo driver can directly send the second exception data to the controller when the first core detects a count overflow event of the second timer, thereby reporting a timeout exception of the second core. Conversely, the second core can interact with the first core when it detects a count overflow event of the first timer, causing the first core to send the first exception data to the controller, thereby reporting a timeout exception of the first core.

[0049] In this embodiment, when the first kernel detects a count overflow event of the second timer, it reports the timeout exception of the second kernel to the controller; when the second kernel detects a count overflow event of the first timer, it interacts with the first kernel, causing the first kernel to report the timeout exception of the first kernel to the controller. The first kernel is responsible for reporting the timeout exceptions of the first and second timers to the controller, which can avoid communication resource conflicts between the two cores and ensure communication reliability.

[0050] In some embodiments, the method further includes: configuring the counting period of a first timer according to a preset weighting parameter and a first interrupt period via a first kernel or a second kernel, configuring the counting period of a second timer according to the weighting parameter and a second interrupt period, and triggering the first timer and the first timer to start counting after the configuration is completed.

[0051] For example, the servo driver can use a first kernel or a second kernel to weight the first interrupt cycle according to preset weighting parameters to obtain a first weighted cycle, set the first weighted cycle as the counting cycle of the first timer, weight the second interrupt cycle according to preset weighting parameters to obtain a second weighted cycle, set the second weighted cycle as the counting cycle of the second timer, and after both the first timer and the second timer are set, the first timer and the first timer start counting synchronously.

[0052] It is understandable that, in order to ensure that the counting period of the first timer is not less than the first interrupt period, and the counting period of the second timer is not less than the second interrupt period, the weighting parameter can be no less than 1. Since the target kernel also needs time to enter the interrupt, the weighting parameter can be set adaptively based on engineering experience. For example, the weighting parameter can be any value in the range of 1.1 to 1.5.

[0053] In some embodiments, the weighting parameters may include a first parameter and a second parameter. The servo driver can calculate the product of the first parameter and the first interrupt cycle to obtain a first weighted cycle, and calculate the product of the second parameter and the second interrupt cycle to obtain a second weighted cycle.

[0054] In this embodiment, the counting period of the first timer is configured according to the preset weighting parameters and the first interrupt period by the first kernel or the second kernel, and the counting period of the second timer is configured according to the weighting parameters and the second interrupt period. After the configuration is completed, the first timer is triggered and the first timer starts counting. The first timer and the second timer are configured and triggered centrally by a target kernel, so as to avoid the monitoring vulnerability caused by the asynchronous initialization of the first timer and the second timer and ensure the reliability of the dual-core cross-monitoring mechanism.

[0055] In some embodiments, the target timer is configured to set the overflow flag of its status register to be valid when its count value reaches its own count cycle, so as to indicate that a count overflow event has occurred; in the event that the target timer has a count overflow event, the target timer reports a timeout exception of the target kernel to the controller, including: reporting a timeout exception of the target kernel to the controller when the overflow flag of the target timer's status register is valid.

[0056] For example, the status registers of both the first and second timers can be accessed by both the first and second kernels. The servo driver can access the status register of the second timer through the first kernel whenever the first interrupt cycle arrives. If the overflow flag of the second timer's status register is detected to be valid, it reports a timeout exception of the second kernel to the controller. Conversely, if the second interrupt cycle arrives, the driver can access the status register of the first timer through the second kernel. If the overflow flag of the first timer's status register is detected to be valid, the driver interacts with the first kernel, causing the first kernel to report a timeout exception of the first kernel to the controller.

[0057] In some embodiments, such as Figure 4A The diagram illustrates the steps executed by the first kernel when the first interrupt cycle arrives. Upon arrival of the first interrupt cycle, the first kernel clears the first timer, resetting its count to zero. It then accesses the status register of the second timer. If the overflow flag in the second timer's status register is valid, a timeout exception is reported to the second kernel. If the overflow flag in the second timer's status register is invalid, execution returns to the steps performed when the first interrupt cycle arrived, where the first kernel cleared the first timer.

[0058] In some embodiments, such as Figure 4BThe diagram illustrates the steps executed by the second kernel when the second interrupt cycle arrives. Upon arrival of the second interrupt cycle, the second kernel clears the second timer, resetting its count to zero. It then accesses the status register of the first timer. If the overflow flag of the first timer's status register is valid, the first kernel reports a timeout exception. If the overflow flag of the first timer's status register is invalid, the process returns to the step of clearing the second timer via the second kernel upon arrival of the second interrupt cycle.

[0059] In this embodiment, the target timer sets the overflow flag of its status register to be valid when its count value reaches its own counting cycle, so as to indicate that a count overflow event has occurred. The count overflow event of the target timer can reflect the timeout exception of the target kernel. When the overflow flag of the target timer's status register is valid, the timeout exception of the target kernel is reported to the controller, which can report the timeout exception of the target kernel in a timely manner and ensure the safety of servo control.

[0060] In some embodiments, stopping the output of the pulse width modulation signal includes: routing a count overflow event to a fault input of the pulse width modulation module via an event linking module to trigger the pulse width modulation module to stop outputting the pulse width modulation signal.

[0061] For example, the target timer and pulse width modulation module are respectively connected to the event link module. The event link module may be, but is not limited to, a crossbar, a block interconnect network, or an event link controller (ELC).

[0062] The servo driver can route the count overflow event of the first timer or the count overflow event of the second timer to the fault input of the pulse width modulation module through the event linking module, so as to trigger the pulse width modulation module to stop outputting the pulse width modulation signal when the count overflow event of the first timer or the count overflow event of the second timer occurs.

[0063] In some embodiments, such as Figure 5 The diagram illustrates the routing of a count overflow event to the pulse width modulation (PWM) module. The servo driver can route both the count overflow events of the first and second timers to the fault input of the PWM module, triggering the PWM module to generate a fault blocking signal, thus stopping the PWM module from transmitting pulse width modulation signals.

[0064] In this embodiment, the count overflow event is routed to the fault input of the pulse width modulation module to trigger the pulse width modulation module to stop outputting the pulse width modulation signal. This can avoid the problem of abnormal waveform generation by the pulse width modulation module when a timeout exception occurs in the target kernel, thus ensuring the safety of servo control.

[0065] In some embodiments, the target interrupt cycle is the interrupt cycle of the highest priority interrupt in the target kernel.

[0066] For example, the first interrupt cycle is the interrupt cycle of the highest priority interrupt of the first kernel. Whenever the first interrupt cycle arrives, the first kernel pauses the currently executing code, executes the interrupt service routine corresponding to its highest priority interrupt, clears the count value of the first timer, and detects the overflow event of the second timer. It can be understood that using the interrupt cycle of the highest priority interrupt of the first kernel as the first interrupt cycle ensures that the first kernel prioritizes clearing the first timer and detecting the overflow event of the second timer, thereby ensuring the timeliness and reliability of anomaly detection.

[0067] The second interrupt cycle is the interrupt cycle of the highest priority interrupt in the second kernel. Whenever the second interrupt cycle arrives, the second kernel pauses the currently executing code, executes the interrupt service routine corresponding to its highest priority interrupt, clears the second timer's counter value, and checks for the first timer's overflow event. It can be understood that using the interrupt cycle of the second kernel's highest priority interrupt as the second interrupt cycle ensures that the second kernel prioritizes clearing the second timer and detecting the first timer's overflow event, thereby guaranteeing the timeliness and reliability of anomaly detection.

[0068] In this embodiment, the target interrupt cycle is the interrupt cycle of the highest priority interrupt of the target kernel. The interrupt service routine corresponding to the highest priority interrupt has the highest priority execution right, which makes the target kernel operate the target timer first, ensuring that the count value of the target timer can be cleared in time and that no count overflow event will occur. This avoids misjudging the timeout exception of the target kernel and ensures the accuracy of servo control.

[0069] In some embodiments, the servo driver includes a dual-core microcontroller unit, an event linking module, a pulse width modulation module, a first timer, and a second timer. The dual-core microcontroller unit includes a first core and a second core. The first core mainly handles communication and application functions, while the second core mainly handles motor control functions. The second core can interact with the first core and communicate with the controller through the first core.

[0070] After power-on, the first or second kernel can weight the first interrupt cycle according to preset weighting parameters to obtain the first weighted cycle, and set the first weighted cycle as the counting cycle of the first timer. It can also weight the second interrupt cycle according to preset weighting parameters to obtain the second weighted cycle, and set the second weighted cycle as the counting cycle of the second timer. After both the first and second timers are set, the first timer and the second timer are synchronously triggered to start counting.

[0071] The first kernel can clear the count value of the first timer by executing the interrupt service routine corresponding to its highest priority interrupt whenever the first interrupt cycle arrives, and access the status register of the second timer. If the overflow flag bit of the status register of the second timer is detected to be valid, the kernel can report the timeout exception of the second kernel to the controller.

[0072] The second kernel can clear the count value of the second timer by executing the corresponding interrupt service routine whenever the second interrupt cycle arrives, and access the status register of the first timer. If the overflow flag of the first timer's status register is detected to be valid, it interacts with the first kernel, causing the first kernel to report a timeout exception to the controller. The controller can stop the operation of each downstream servo driver if a timeout exception occurs in either the first or second kernel.

[0073] The first kernel can also periodically send heartbeat messages to the controller. If the target kernel freezes, fails to report timeout exceptions, and is unable to send heartbeat messages, the controller can determine that the servo drive is in an abnormal state and control the servo drive to stop running if no heartbeat message is received after the timeout.

[0074] The first and second timers can continuously count, starting from zero whenever the count value is cleared, and issuing an overflow event signal and setting the overflow flag bit of their own status register to be valid when the count value reaches its own counting cycle, thereby triggering a count overflow event.

[0075] The event linking module can route the overflow event signals of the first timer and the second timer to the fault input of the pulse width modulation module.

[0076] The pulse width modulation module can generate a fault blocking signal when an overflow event signal is detected at the fault input, so as to control itself to stop transmitting pulse width modulation signals.

[0077] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0078] Based on the same inventive concept, this application also provides a servo drive anomaly detection system for implementing the above-described servo drive anomaly detection method. The solution provided by this system is similar to the implementation described in the above method; therefore, the specific limitations of one or more servo drive anomaly detection system embodiments provided below can be found in the limitations of the servo drive anomaly detection method described above, and will not be repeated here.

[0079] In one exemplary embodiment, such as Figure 6A As shown, a servo driver anomaly detection system 600 is provided, including: a target kernel 602, a target timer 604, and a pulse width modulation module 606, wherein: The target kernel 602 is used to clear the count value of the target timer 604 whenever the target interrupt cycle arrives.

[0080] The target timer 604 is used to trigger a count overflow event when its count value reaches its own count cycle; the count cycle of the target timer 604 is not less than the target interrupt cycle.

[0081] The target kernel 602 is used to report a timeout exception of the target kernel 602 to the controller in the event of a count overflow event in the target timer 604.

[0082] The pulse width modulation module 606 is used to stop outputting the pulse width modulation signal when a count overflow event occurs in the target timer 604.

[0083] In some embodiments, such as Figure 6BAs shown, another servo driver anomaly detection system 600 is provided. The target kernel 602 includes at least one of a first kernel 608 or a second kernel 610; the target interrupt cycle includes at least one of a first interrupt cycle or a second interrupt cycle; the target timer 604 includes at least one of a first timer 612 or a second timer 614; the counting period of the first timer 612 is not less than the first interrupt cycle; the counting period of the second timer 614 is not less than the second interrupt cycle; the first kernel 608 is used to clear the count value of the first timer 612 to zero whenever the first interrupt cycle arrives, and to detect whether a count overflow event has occurred in the second timer 614; the second kernel 610 is used to clear the count value of the second timer 614 to zero whenever the second interrupt cycle arrives, and to detect whether a count overflow event has occurred in the first timer 612.

[0084] In some embodiments, the first kernel 608 is configured to report a timeout exception of the second kernel 610 to the controller when a count overflow event is detected in the second timer 614; the second kernel 610 is configured to interact with the first kernel 608 when a count overflow event is detected in the first timer 612, so that the first kernel 608 reports a timeout exception of the first kernel 608 to the controller.

[0085] In some embodiments, the first kernel 608 or the second kernel 610 is configured to configure the counting period of the first timer 612 according to a preset weighting parameter and a first interrupt period, and configure the counting period of the second timer 614 according to the weighting parameter and the second interrupt period, and after the configuration is completed, trigger the first timer 612 and the first timer 614 to start counting.

[0086] In some embodiments, the target timer 604 is configured to set the overflow flag of its own status register to be valid when its own count value reaches its own count cycle, so as to indicate that a count overflow event has occurred; the target kernel 602 is configured to report the timeout exception of the target kernel 602 to the controller when the overflow flag of the status register of the target timer 604 is valid.

[0087] In some embodiments, such as Figure 6C As shown, another servo driver anomaly detection system 600 is provided. The target timer 604 and the pulse width modulation module 606 are respectively connected to the event linking module 616; the event linking module 616 is used to route the count overflow event to the fault input of the pulse width modulation module 606 to trigger the pulse width modulation module 606 to stop outputting the pulse width modulation signal.

[0088] The modules in the aforementioned servo drive anomaly detection system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor within the servo drive in hardware form or independent of it, or stored in the servo drive's memory in software form, so that the processor can call and execute the corresponding operations of each module.

[0089] In one exemplary embodiment, a servo driver is provided, the internal structure of which can be shown in the diagram below. Figure 7 As shown, the servo drive includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores computer programs. The internal memory provides an environment for the execution of the computer programs in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for detecting servo drive anomalies.

[0090] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the solution of this application and does not constitute a limitation on the servo driver to which the solution of this application is applied. A specific servo driver may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0091] In one embodiment, a servo driver is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0092] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0093] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0094] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for detecting anomalies in a servo driver, characterized in that, Applied to servo drives; The method includes: Whenever the target interrupt cycle arrives, the target kernel resets the count value of the target timer to zero; wherein, the target timer is used to trigger a count overflow event when its count value reaches its own count cycle; the count cycle of the target timer is not less than the target interrupt cycle; In the event of the target timer overflowing, the timeout exception of the target kernel is reported to the controller, and the output of the pulse width modulation signal is stopped.

2. The method according to claim 1, characterized in that, The target kernel includes at least one of a first kernel or a second kernel; the target interrupt cycle includes at least one of a first interrupt cycle or a second interrupt cycle; the target timer includes at least one of a first timer or a second timer; the counting period of the first timer is not less than the first interrupt cycle; the counting period of the second timer is not less than the second interrupt cycle; the step of clearing the count value of the target timer by the target kernel whenever the target interrupt cycle arrives includes: Whenever the first interrupt cycle arrives, the first kernel clears the count value of the first timer and checks whether the second timer has experienced a count overflow event. Whenever the second interrupt cycle arrives, the second kernel clears the count value of the second timer and checks whether the first timer has experienced a count overflow event.

3. The method according to claim 2, characterized in that, In the event that the target timer experiences a count overflow event, the method of reporting a timeout exception of the target kernel to the controller includes: When the first kernel detects that the second timer has overflowed, it reports a timeout exception to the controller. When the second kernel detects that the first timer has overflowed, it interacts with the first kernel, causing the first kernel to report a timeout exception to the controller.

4. The method according to claim 2, characterized in that, The method further includes: The counting period of the first timer is configured according to the preset weighting parameters and the first interrupt period by the first kernel or the second kernel, and the counting period of the second timer is configured according to the weighting parameters and the second interrupt period. After the configuration is completed, the first timer is triggered and the first timer starts counting.

5. The method according to claim 1, characterized in that, The target timer is used to set the overflow flag of its status register to be valid when its count value reaches its own count cycle, so as to indicate that the count overflow event has occurred. In the event that the target timer experiences a count overflow event, the method of reporting a timeout exception of the target kernel to the controller includes: If the overflow flag in the status register of the target timer is valid, report the timeout exception of the target kernel to the controller.

6. The method according to claim 1, characterized in that, The stopping of output pulse width modulation signal includes: The count overflow event is routed to the fault input of the pulse width modulation module to trigger the pulse width modulation module to stop outputting the pulse width modulation signal.

7. The method according to any one of claims 1 to 6, characterized in that, The target interrupt cycle is the interrupt cycle of the highest priority interrupt in the target kernel.

8. A fault detection system for a servo driver, characterized in that, The system includes a target kernel, a target timer, and a pulse width modulation module; The target kernel is used to clear the count value of the target timer whenever the target interrupt cycle arrives; The target timer is used to trigger a count overflow event when its count value reaches its own count cycle; the count cycle of the target timer is not less than the target interrupt cycle; The target kernel is also configured to report a timeout exception of the target kernel to the controller in the event that the target timer causes the count overflow event; The pulse width modulation module is used to stop outputting the pulse width modulation signal when the target timer experiences the count overflow event.

9. A servo driver, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

Images