Low-temperature-drift high-PSRR band-gap reference circuit

Abstract

A low-temperature-drift high-PSRR band-gap reference circuit belongs to the field of analog integrated circuits and comprises a positive temperature current generation circuit, a negative temperature current generation circuit, a segmented curvature temperature compensation circuit, a power supply rejection ratio (PSRR) enhancement circuit and a current-voltage conversion circuit. The positive temperature current generating circuit generates current positively correlated with absolute temperature; the negative temperature current generating circuit generates current which is negatively correlated with absolute temperature; the segmented curvature temperature compensation circuit generates CTAT current in a low-temperature interval and generates PTAT current in a high-temperature interval; the PSRR enhancement circuit increases the suppression of the output reference voltage on the power supply fluctuation; the voltage conversion circuit converts a superimposed current of the positive temperature coefficient current, the negative temperature coefficient current and the segmented compensation current into a target voltage. The low-impedance loop is additionally arranged and connected with the band-gap reference in parallel, so that low impedance to ground is achieved, and it is guaranteed that the influence of power fluctuation on output reference voltage is small; the segmented curvature compensation circuit is simple in structure.

Description

Technical Field

[0001] This invention relates to a low-temperature drift, high PSRR bandgap reference circuit, belonging to the field of analog integrated circuit design. Background Technology

[0002] In most analog and mixed-signal circuit systems, bandgap reference circuits used to generate constant voltage references are a crucial component. Since these circuit systems need to operate in various environments, and the voltage output accuracy of the bandgap reference circuit determines the maximum achievable accuracy of the overall circuit system, a low temperature coefficient of the reference voltage and effective suppression of power supply fluctuations are essential.

[0003] The bandgap reference circuit, as a power supply unit in a chip, is a fundamental module in integrated circuits. An ideal bandgap reference circuit can provide a stable reference voltage unaffected by external factors such as process technology, power supply voltage, and temperature, thereby powering various circuit modules of the chip. Traditional bandgap reference circuits typically superimpose the CTAT current generated by the base-emitter voltage of a BJT and the PTAT current generated by the base-emitter voltage difference between two BJTs operating at different current densities, and then replicate this superposition to the output path where resistor R3 is located, thus forming a temperature-insensitive reference voltage. However, when a high-precision reference source is required, many factors affect the accuracy of the reference voltage, such as process parameter fluctuations, nonlinearity, changes in bipolar transistor current gain, and offsets and noise from the power supply and amplifier. Among these, the presence of nonlinear high-order temperature terms and power supply fluctuations are the most significant factors limiting the accuracy of the reference. Simply relying on the linear superposition of the PTAT and CTAT currents cannot cancel out the nonlinear high-order temperature terms, and without adding power supply measures to suppress power supply fluctuations, this leads to significant systematic output deviations. To address the temperature drift and power supply fluctuation issues of traditional bandgap reference circuits and obtain a more accurate reference voltage, this invention proposes a bandgap reference circuit with low temperature drift and high PSRR. Summary of the Invention

[0004] The purpose of this invention is to provide a high-precision output bandgap reference circuit with a simple structure, low temperature drift, and high power supply rejection ratio (PSRR), achieving an extremely low temperature coefficient while reducing the impact of power supply fluctuations on the output reference voltage. The main innovation of this invention lies in compensating for the overall current through piecewise curvature compensation current temperature curvature adjustment, resulting in a low temperature coefficient characteristic for the final reference output voltage. Furthermore, a low-impedance loop is proposed to reduce the impedance of the VREG to ground, improving the suppression of power supply fluctuations by the reference voltage. The proposed low-temperature drift, high PSRR bandgap reference circuit has a simple structure with fewer branches, reducing the overall circuit power consumption.

[0005] A segmented curvature temperature-compensated bandgap reference circuit. It includes a positive temperature current generation circuit, a negative temperature current generation circuit, a zero temperature coefficient current generation circuit, a segmented curvature compensation circuit, a PSRR enhancement circuit, and a current-to-voltage conversion circuit. The PSRR enhancement circuit adds a... (gmp3 is the transconductance of PMOS transistor MP3, ro3 is the impedance of PMOS transistor MP3, and gmn3 is the transconductance of NMOS transistor MN3) A low-impedance loop is connected in parallel with the bandgap reference circuit (i.e., the negative temperature coefficient current generation circuit, the zero temperature coefficient current generation circuit, the current-to-voltage conversion circuit, and the piecewise curvature compensation circuit, which form a whole) to improve the power supply rejection ratio of the reference voltage; the positive temperature current generation circuit is used to generate a current I that is positively correlated with the absolute temperature. PTAT The negative temperature current generating circuit is used to generate a current I that is negatively correlated with absolute temperature. CTAT The zero-temperature current generating circuit is used to generate a current I that is independent of absolute temperature. ZTAT The high-order temperature compensation circuit generates I. COMP It is used to compensate for the higher-order temperature-dependent components in the current and to improve stability through a feedback loop; the voltage conversion circuit is used to convert the superimposed current of positive temperature coefficient current, negative temperature coefficient current and piecewise curvature compensation current into the target voltage VREF.

[0006] Compared with the prior art, the present invention has the following advantages:

[0007] (1) The PSRR enhancement circuit designed in this invention has a simple structure and adds one A low-impedance loop to ground is connected in parallel with the bandgap reference circuit to improve the suppression of power supply fluctuations by the output voltage; the segmented curvature-compensated bandgap reference circuit employs a positive temperature current generation circuit, a negative temperature current generation circuit, a high-order temperature compensation circuit, and a current-to-voltage conversion circuit. The positive temperature current generation circuit first generates I... PTAT Then, I is generated by the negative temperature current generating circuit. CTAT Finally, an I is generated through a high-order temperature compensation circuit. COMP Used for compensating for high and low temperature ranges in the current; with a power supply voltage of 3.3V and a temperature range of -40℃ to 125℃, the output voltage temperature drift coefficient can reach 1.195ppm / ℃, which is 20 times lower than the bandgap reference temperature drift of first-order temperature compensation.

[0008] (2) The present invention effectively solves the problems of high output voltage temperature coefficient and low power supply rejection ratio of traditional bandgap reference circuits. It reduces temperature drift and improves the stability of the circuit system by adding a segmented curvature compensation circuit. Moreover, the structure of the present invention is simple, and the added compensation circuits are all in the nA range. Compared with the traditional high-order compensation bandgap reference circuit scheme, the power consumption is low. Attached Figure Description

[0009] Figure 1 This is a circuit structure diagram of a low-temperature drift high PSRR bandgap reference circuit according to a specific embodiment of the present invention.

[0010] Figure 2 This is a simulation diagram of the power supply rejection ratio of the output voltage VREF in a specific embodiment of the present invention.

[0011] Figure 3 This is a graph showing the output voltage VREF changing with temperature in a specific embodiment of the present invention. Detailed Implementation

[0012] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0013] like Figure 1 As shown, the low-temperature drift, high PSRR bandgap reference circuit designed in this invention includes a positive temperature current generation circuit, a negative temperature current generation circuit, a zero temperature coefficient current generation circuit, a PSRR enhancement circuit, a segmented curvature compensation circuit, and a current-to-voltage conversion circuit. The positive temperature current generation circuit is used to generate a current I that is positively correlated with absolute temperature. PTAT The negative temperature current generating circuit is used to generate a current I that is negatively correlated with absolute temperature. CTAT and I CTAT1 The PSRR enhancement circuit is used to improve the suppression of power supply fluctuations by the output voltage VREF; the zero-temperature current generation circuit is used to generate a current I that is independent of absolute temperature. ZTAT The segmented curvature compensation circuit is used to generate a compensation current I. COMP The voltage conversion circuit is used to compensate for the current in the high and low temperature ranges; the voltage conversion circuit is used to convert the superimposed current of positive temperature coefficient current, negative temperature coefficient current and piecewise curvature compensation current into the target voltage VREF.

[0014] Reference Figure 1 In practical applications, this type of low-temperature drift, high PSRR bandgap reference circuit is used in positive temperature coefficient current generation circuits (positive temperature coefficient current is included in the circuit). Figure 1The design includes a zero temperature coefficient current generation circuit, a negative temperature current generation circuit, a PSRR enhancement circuit, a segmented curvature compensation circuit, and a current-to-voltage conversion circuit. Specific components include amplifier A1, amplifier A2, resistors R1, R2, R3, R4, R5, R6, bipolar PNP transistors Q1 and Q2, P-type field-effect transistors MP1, MP2, and MP3, power supply VDD, ground GND, and P-type field-effect transistors MP4, MP5, MP6, and MP7. P-type field-effect transistor MP8, P-type field-effect transistor MP9, P-type field-effect transistor MP10, P-type field-effect transistor MP11, P-type field-effect transistor MP12, P-type field-effect transistor MP13, P-type field-effect transistor MP14, P-type field-effect transistor MP15, P-type field-effect transistor MP16, N-type field-effect transistor MN1, N-type field-effect transistor MN2, N-type field-effect transistor MN3, N-type field-effect transistor MN4, N-type field-effect transistor MN5, N-type field-effect transistor MN6, N-type field-effect transistor MN7, N-type field-effect transistor MN8, N-type field-effect transistor MN9.

[0015] The inverting input of amplifier A1 is connected to the emitter of bipolar PNP transistor Q2, one end of resistor R4, and the drain of P-type field-effect transistor MP7. The non-inverting input of amplifier A1 is connected to one end of resistor R1, the negative input of amplifier A2, one end of resistor R2, and the drain of P-type field-effect transistor MP6. The output of amplifier A1 is connected to the gate of P-type field-effect transistors MP3, MP4, MP6, MP7, MP8, MP11, and MP16.

[0016] The inverting input terminal of amplifier A2 is connected to one end of resistor R1, one end of resistor R2, the non-inverting input terminal of amplifier A1, and the drain of P-type field-effect transistor MP6. The non-inverting input terminal of amplifier A2 is connected to one end of resistor R3 and the drain of P-type field-effect transistor MP5. The output terminal of amplifier A2 is connected to the gate of P-type field-effect transistors MP5, MP12, and MP15.

[0017] The base of the bipolar PNP transistor Q1 is connected to ground (GND), the emitter is connected to the other end of amplifier R1, and the collector is connected to ground (GND).

[0018] The base of the bipolar PNP transistor Q2 is connected to ground (GND). The emitter is connected to one end of resistor R4, and the collector is connected to ground (GND).

[0019] One end of resistor R1 is connected to the emitter of bipolar PNP transistor Q1, and the other end is connected to the positive input terminal of amplifier A1, one end of resistor R2, the negative input terminal of amplifier A2, and the drain of P-type field-effect transistor MP6.

[0020] One end of resistor R2 is connected to one end of R1, the positive input terminal of amplifier A1, the negative input terminal of amplifier A2, and the drain of P-type field-effect transistor MP6, while the other end is connected to ground GND.

[0021] One end of resistor R3 is connected to the positive input terminal of amplifier A2 and the drain of P-type field-effect transistor MP5, and the other end is connected to ground GND.

[0022] One end of resistor R4 is connected to the emitter of bipolar PNP transistor Q2, the negative input terminal of amplifier A1, and the drain of P-type field-effect transistor MP7.

[0023] One end of resistor R5 is connected to the drain of P-type field-effect transistor MP8 and also to the output port VREF. The other end is connected to the drain of P-type field-effect transistor MP9, one end of resistor R6, and the drain of P-type field-effect transistor MP13.

[0024] One end of resistor R6 is connected to ground (GND), and the other end is connected to the drain of P-type field-effect transistor MP9, one end of resistor R5, and the drain of P-type field-effect transistor MP13.

[0025] The gate of P-type field-effect transistor MP1 is connected to the drain of P-type field-effect transistor MP1 and the gate of P-type field-effect transistor MP2. The source is connected to the power supply VDD. The drain is connected to the gate of P-type field-effect transistor MP1, the gate of P-type field-effect transistor MP2, and the drain of N-type field-effect transistor MN1.

[0026] The gate of P-type field-effect transistor MP2 is connected to the gate and drain of P-type field-effect transistor MP1 and the drain of N-type field-effect transistor MN1. The source is connected to the power supply VDD. The drain is connected to the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP11, the source of P-type field-effect transistor MP12, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, and the source of P-type field-effect transistor MP16.

[0027] The gate of P-type field-effect transistor MP3 is connected to the output terminal of amplifier A1, the gate of P-type field-effect transistor MP4, the gate of P-type field-effect transistor MP6, the gate of P-type field-effect transistor MP7, the gate of P-type field-effect transistor MP8, the gate of P-type field-effect transistor MP11, and the gate of P-type field-effect transistor MP16. The source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP4, and the source of P-type field-effect transistor MP5. The source of transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP11, the source of P-type field-effect transistor MP12, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, and the source of P-type field-effect transistor MP16 are connected, and the drain is connected to the gate of N-type field-effect transistor MN3 and the drain of N-type field-effect transistor MN4.

[0028] The gate of P-type field-effect transistor MP4 is connected to the output terminal of amplifier A1, the gate of P-type field-effect transistor MP3, the gate of P-type field-effect transistor MP6, the gate of P-type field-effect transistor MP7, the gate of P-type field-effect transistor MP8, the gate of P-type field-effect transistor MP11, and the gate of P-type field-effect transistor MP16. The source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP5, and the P-type field-effect transistor... The source of transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP11, the source of P-type field-effect transistor MP12, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, and the source of P-type field-effect transistor MP16 are connected, and the drain is connected to the gate of N-type field-effect transistor MN5 and the drain of N-type field-effect transistor MN5.

[0029] The gate of P-type field-effect transistor MP5 is connected to the output terminal of amplifier A2, the gate of P-type field-effect transistor MP12, and the gate of P-type field-effect transistor MP15. The source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, the source of P-type field-effect transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP12, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, and the source of P-type field-effect transistor MP11. The drain is connected to the positive input terminal of amplifier A2 and one end of resistor R3.

[0030] The gate of P-type field-effect transistor MP6 is connected to the output terminal of amplifier A1, the gate of P-type field-effect transistor MP3, the gate of P-type field-effect transistor MP4, the gate of P-type field-effect transistor MP7, the gate of P-type field-effect transistor MP8, the gate of P-type field-effect transistor MP11, and the gate of P-type field-effect transistor MP16. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, and the gate of P-type field-effect transistor MP5. The source of the P-type field-effect transistor MP7, the source of the P-type field-effect transistor MP8, the source of the P-type field-effect transistor MP9, the source of the P-type field-effect transistor MP10, the source of the P-type field-effect transistor MP11, the source of the P-type field-effect transistor MP12, the source of the P-type field-effect transistor MP13, the source of the P-type field-effect transistor MP14, the source of the P-type field-effect transistor MP15, and the source of the P-type field-effect transistor MP16 are connected. The drain is connected to one end of resistor R1, one end of resistor R2, the negative input terminal of amplifier A2, and the positive input terminal of amplifier A1.

[0031] The gate of P-type field-effect transistor MP7 is connected to the output terminal of amplifier A1, the gate of P-type field-effect transistor MP3, the gate of P-type field-effect transistor MP4, the gate of P-type field-effect transistor MP6, the gate of P-type field-effect transistor MP8, the gate of P-type field-effect transistor MP11, and the gate of P-type field-effect transistor MP16. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, and the gate of P-type field-effect transistor M... The source of P5, the source of P-type field-effect transistor MP6, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP11, the source of P-type field-effect transistor MP12, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, and the source of P-type field-effect transistor MP16 are connected. The drain is connected to one end of resistor R4, the emitter of bipolar PNP transistor Q2, and the negative input terminal of amplifier A1.

[0032] The gate of P-type field-effect transistor MP8 is connected to the output terminal of amplifier A1, the gate of P-type field-effect transistor MP3, the gate of P-type field-effect transistor MP4, the gate of P-type field-effect transistor MP6, the gate of P-type field-effect transistor MP7, the gate of P-type field-effect transistor MP11, and the gate of P-type field-effect transistor MP16. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, and the P-type field-effect transistor... The sources of P-type field-effect transistors MP5, MP6, MP7, MP9, MP10, MP11, MP12, MP13, MP14, MP15, and MP16 are connected together. Their drains are connected to one end of resistor R5 and are also connected to the output port VREF.

[0033] The gate of P-type field-effect transistor MP9 is connected to the gate of P-type field-effect transistor MP10, the drain of P-type field-effect transistor MP10, the drain of P-type field-effect transistor MP11, and the drain of N-type field-effect transistor MN6. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, and the source of P-type field-effect transistor MP... The source of P-type field-effect transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP15, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP12, and the source of P-type field-effect transistor MP11 are connected. The drain is connected to one end of resistor R5, one end of resistor R6, and the drain of P-type field-effect transistor MP13.

[0034] The width-to-length ratio of PMOS transistors MP9 and MP10 is A1:1.

[0035] The gate of P-type field-effect transistor MP10 is connected to the gate of P-type field-effect transistor MP9, the drain of P-type field-effect transistor MP10, the drain of P-type field-effect transistor MP11, and the drain of N-type field-effect transistor MN6. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, and the source of P-type field-effect transistor MP6. The source of field-effect transistor MP7, the source of P-type field-effect transistor MP15, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP12, and the source of P-type field-effect transistor MP11 are connected, and the drain is connected to the gate of P-type field-effect transistor MP9, the gate of P-type field-effect transistor MP10, and the drain of N-type field-effect transistor MN6.

[0036] The gate of P-type field-effect transistor MP11 is connected to the output terminal of amplifier A1, the gates of P-type field-effect transistors MP3, MP4, MP6, MP7, MP8, and MP16. The source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP5, and the P-type field-effect transistor... The source of transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP12, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, and the source of P-type field-effect transistor MP16 are connected. The drain of P-type field-effect transistor MP10, the gate of P-type field-effect transistor MP10, the gate of P-type field-effect transistor MP9, and the drain of N-type field-effect transistor MN6 are connected.

[0037] The gate of P-type field-effect transistor MP12 is connected to the output terminal of amplifier A2, the gate of P-type field-effect transistor MP5, and the gate of P-type field-effect transistor MP15. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, the source of P-type field-effect transistor MP6, and the source of P-type field-effect transistor MP7. The source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, and the source of P-type field-effect transistor MP11 are connected. The drain of P-type field-effect transistor MN6, the gate of N-type field-effect transistor MN7, and the drain of N-type field-effect transistor MN7 are connected.

[0038] The gate of P-type field-effect transistor MP13 is connected to the gate of P-type field-effect transistor MP14, the drain of P-type field-effect transistor MP14, the drain of P-type field-effect transistor MP15, and the drain of N-type field-effect transistor MN8. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, and the source of P-type field-effect transistor M... The source of P6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP15, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP12, and the source of P-type field-effect transistor MP11 are connected. The drain is connected to one end of resistor R5, one end of resistor R6, and the drain of P-type field-effect transistor MP9.

[0039] The width-to-length ratio of PMOS transistors MP13 and MP14 is A2:1.

[0040] The gate of P-type field-effect transistor MP14 is connected to the gate of P-type field-effect transistor MP13, the drain of P-type field-effect transistor MP14, the drain of P-type field-effect transistor MP15, and the drain of N-type field-effect transistor MN8. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, the source of P-type field-effect transistor MP6, and the source of P-type field-effect transistor MP... The source of transistor 7, the source of P-type field-effect transistor MP15, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP12, and the source of P-type field-effect transistor MP11 are connected. The drain of P-type field-effect transistor MP13, the gate of P-type field-effect transistor MP14, the drain of P-type field-effect transistor MP15, and the drain of N-type field-effect transistor MN8 are connected.

[0041] The gate of P-type field-effect transistor MP15 is connected to the output terminal of amplifier A2, the gate of P-type field-effect transistor MP5, and the gate of P-type field-effect transistor MP12. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, the source of P-type field-effect transistor MP6, and the source of P-type field-effect transistor MP7. The source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP12, and the source of P-type field-effect transistor MP11 are connected to the gate of P-type field-effect transistor MP13, the gate of P-type field-effect transistor MP14, and the drain of P-type field-effect transistor MP14.

[0042] The gate of P-type field-effect transistor MP16 is connected to the output terminal of amplifier A1, the gates of P-type field-effect transistors MP3, MP4, MP6, MP7, MP8, and MP11. Its source is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, and the source of P-type field-effect transistor MP5. The source of P-type field-effect transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP12, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, and the source of P-type field-effect transistor MP11 are connected to the drain of N-type field-effect transistor MN9, the gate of N-type field-effect transistor MN9, and the gate of N-type field-effect transistor MN8.

[0043] The gate of N-type field-effect transistor MN1 is connected to the gate of N-type field-effect transistor MN2, the gate of N-type field-effect transistor MN4, the gate of N-type field-effect transistor MN5, and the drain of N-type field-effect transistor MN5. The drain is connected to the drain of P-type field-effect transistor MP1, the gate of P-type field-effect transistor MP1, and the gate of P-type field-effect transistor MP2. The source is connected to ground GND.

[0044] The gate of N-type field-effect transistor MN2 is connected to the gates of N-type field-effect transistors MN1, MN4, and MN5, and the drain of N-type field-effect transistor MN5. The drain is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN3, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, the source of P-type field-effect transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP12, and the source of P-type field-effect transistor MP11. The source is connected to ground (GND).

[0045] The gate of N-type field-effect transistor MN3 is connected to the drain of N-type field-effect transistor MN4 and the drain of P-type field-effect transistor MP3. The drain of MP3 is connected to the drain of P-type field-effect transistor MP2, the drain of N-type field-effect transistor MN2, the source of P-type field-effect transistor MP3, the source of P-type field-effect transistor MP4, the source of P-type field-effect transistor MP16, the source of P-type field-effect transistor MP6, the source of P-type field-effect transistor MP7, the source of P-type field-effect transistor MP14, the source of P-type field-effect transistor MP15, the source of P-type field-effect transistor MP9, the source of P-type field-effect transistor MP8, the source of P-type field-effect transistor MP5, the source of P-type field-effect transistor MP10, the source of P-type field-effect transistor MP13, the source of P-type field-effect transistor MP12, and the source of P-type field-effect transistor MP11. The source of MP11 is connected to ground GND.

[0046] The gate of N-type field-effect transistor MN4 is connected to the gate of N-type field-effect transistor MN1, the gate of N-type field-effect transistor MN2, the gate of N-type field-effect transistor MN5, and the drain of N-type field-effect transistor MN5. The drain is connected to the gate of N-type field-effect transistor MN3 and the drain of P-type field-effect transistor MP3. The source is connected to ground GND.

[0047] The gate of N-type field-effect transistor MN5 is connected to the gate of N-type field-effect transistor MN1, the gate of N-type field-effect transistor MN2, the gate of N-type field-effect transistor MN4, and the drain of N-type field-effect transistor MN5. The drain is connected to the gate of N-type field-effect transistor MN5 and the drain of P-type field-effect transistor MP4. The source is connected to ground GND.

[0048] The gate of N-type field-effect transistor MN6 is connected to the gate of N-type field-effect transistor MN7, the drain of N-type field-effect transistor MN7, and the drain of P-type field-effect transistor MP12. The drain of MP6 is connected to the drain of P-type field-effect transistor MP11, the drain of P-type field-effect transistor MP10, the gate of P-type field-effect transistor MP10, and the gate of P-type field-effect transistor MP9. The source of MP6 is connected to ground GND.

[0049] The width-to-length ratio of NMOS transistors MN6 and MN7 is A4:1.

[0050] The gate of N-type field-effect transistor MN7 is connected to the gate of N-type field-effect transistor MN6, the drain of N-type field-effect transistor MN7, and the drain of P-type field-effect transistor MP12. The drain is connected to the gate of N-type field-effect transistor MN6, the gate of N-type field-effect transistor MN7, and the drain of P-type field-effect transistor MP12. The source is connected to ground GND.

[0051] The gate of N-type field-effect transistor MN8 is connected to the gate of N-type field-effect transistor MN9, the drain of N-type field-effect transistor MN9, and the drain of P-type field-effect transistor MP16. The drain of MP18 is connected to the drain of P-type field-effect transistor MP15, the drain of P-type field-effect transistor MP14, the gate of P-type field-effect transistor MP14, and the gate of P-type field-effect transistor MP13. The source of MP18 is connected to ground GND.

[0052] The width-to-length ratio of NMOS transistors MN8 and MN9 is A3:1.

[0053] The gate of N-type field-effect transistor MN9 is connected to the gate of N-type field-effect transistor MN8, the drain of N-type field-effect transistor MN9, and the drain of P-type field-effect transistor MP16. The drain is connected to the gate of N-type field-effect transistor MN8, the gate of N-type field-effect transistor MN9, and the drain of P-type field-effect transistor MP16. The source is connected to ground GND.

[0054] Figure 1 In the middle, V ZTAT This refers to the zero-temperature-drift gate voltage of PMOS transistors MP6 and MP7, used to replicate the zero-temperature-coefficient current; V CTAT1 This is the negative temperature coefficient gate voltage of PMOS transistor MP5, used to replicate the negative temperature coefficient current; a1I ZTAT Given that the width-to-length ratio of PMOS transistors MP7 and MP8 is 1:a1, I ZTAT Copy a1 times; a2I ZTAT Given that the width-to-length ratio of PMOS transistors MP7 and MP11 is 1:a2, I ZTAT Copy a2 times; a3I ZTATGiven that the width-to-length ratio of PMOS transistors MP7 and MP15 is 1:a3, I ZTAT Copy a3 times; a4I CTAT1 Given that the width-to-length ratio of PMOS transistors MP5 and MP12 is 1:a4, I ZTAT Copy a4 times; a5I CTAT1 Given that the width-to-length ratio of PMOS transistors MP5 and MP16 is 1:a5, I ZTAT Copy a5 times.

[0055] like Figure 2 The figure shows the AC small-signal simulation of the output voltage VREF / VDD in the range of 0.01Hz-10GHz. With a 1V AC voltage supplied to the VDD input terminal, the PSRR curve can be directly obtained from the simulation. It can be found that the PSRR of this circuit in DC state is -112.88dB.

[0056] like Figure 3 The figure shows a simulation diagram with an output voltage of 1.425V in the temperature range of -40℃ to 125℃, after high-order temperature compensation. The figure shows that the difference between the maximum and minimum output voltage is 280.51μV, and the temperature drift coefficient is 1.195PPM / ℃.

[0057] The above description is only a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims.

Claims

1. A low-temperature drift high PSRR bandgap reference circuit, characterized in that: It includes a positive temperature current generation circuit, a negative temperature current generation circuit, a zero temperature current generation circuit, a power supply rejection ratio (PSRR) enhancement circuit, a segmented curvature compensation circuit, and a current-to-voltage conversion circuit. The PSRR enhancement circuit is used to improve the suppression of power supply fluctuations by the reference voltage VREF; the positive temperature current generation circuit is used to generate a current I that is positively correlated with the absolute temperature. PTAT The negative temperature current generating circuit is used to generate a current I that is negatively correlated with absolute temperature. CTAT and I CTAT1 The zero-temperature current generating circuit is used to generate a current I that is independent of absolute temperature. ZTAT , which is composed of I CTAT and I PTAT The summation yields I; the segmented curvature compensation circuit generates I. COMP It is used to compensate for current in high-temperature and low-temperature regions; The voltage conversion circuit is used to convert the positive temperature coefficient current I... PTAT Negative temperature coefficient current I CTAT The superposition current of the piecewise curvature compensation current, i.e., I COMP Convert to the target voltage VREF.

2. The low-temperature drift high PSRR bandgap reference circuit according to claim 1, characterized in that: The PSRR enhancement circuit includes PMOS transistors MP1, MP2, MP3, and MP4, and NMOS transistors MN1, MN2, MN3, MN4, and MN5. The gates of MP1 and MP2 are connected to the drains of MP1 and MN1; the drains of MP2, MN2, and MN3 are connected to the sources of MP3 and MP4; the gates of MN1, MN2, MN4, and MN5 are connected to the drains of MN5 and MP4; the gate of MN3 is connected to the drains of MP3 and MN4; the sources of MN1, MN2, MN3, MN4, and MN5 are connected to ground (GND); and the sources of MP1 and MP2 are connected to the power supply (VDD).

3. The low-temperature drift high PSRR bandgap reference circuit according to claim 1, characterized in that: The segmented curvature compensation circuit includes PMOS transistors MP9, MP10, MP11, MP12, MP13, MP14, MP15, and MP16, and NMOS transistors MN6, MN7, MN8, and MN9. The gates of MP9 and MP10 are connected to the drains of MP10, MP11, and MN6. MP11, MP16, and V... ZTAT Connected; MP12, MP15 and V CTAT1 The drains of MP12 and MN7 are connected to the gates of MN6 and MN7; the gates of MP13 and MP14 are connected to the drains of MP14, MP15, and MN8; the drains of MP16 and MN9 are connected to the gates of MN8 and MN9; the drains of MP9 and MP13 are connected to one end of R5 and R6; the sources of MP9, MP10, MP11, MP12, MP13, MP14, MP15, and MP16 are connected to VREG; the sources of MN6, MN7, MN8, and MN9 are connected to ground (GND).

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