Processing core state adjusting method and device, equipment, chip and medium
By identifying processor operating status parameters, the core state of a multi-core processor can be determined and adjusted, solving the problem of inaccurate core state adjustment in existing technologies and achieving more efficient power consumption management and system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING X RING TECHNOLOGY CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-05
AI Technical Summary
In existing technologies, multi-core processors have difficulty in accurately adjusting the core state of the processor cores during operation, resulting in inaccurate power consumption adjustment and affecting system stability and efficiency.
By identifying the processor's operating status parameters, it can determine whether there is a need for core state adjustment, identify the target processing core and its state to be adjusted, and use hardware devices such as MPMU to perform state adjustment, including sleep state and low power state, thereby improving adjustment accuracy and response speed.
It improves the accuracy and response speed of core state adjustment, reduces software overhead, and optimizes the stability and security of system operation.
Smart Images
Figure CN121979375A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of data processing technology, and in particular to a method, apparatus, device, chip, and medium for processing core state adjustment. Background Technology
[0002] With the development of technology, multi-core processors have been widely used in various fields of people's work and life. During the operation of a multi-core processor, it may be necessary to adjust the state of the cores in the processor core in order to adjust the overall operating power consumption of the CPU.
[0003] Therefore, it is very important to know how to accurately adjust the state of the core. Summary of the Invention
[0004] This disclosure aims to at least partially address one of the technical problems in the related art.
[0005] Therefore, the first aspect of this disclosure proposes a method for handling core state adjustments.
[0006] The second aspect of this disclosure proposes a device for processing core state adjustment.
[0007] The third aspect of this disclosure proposes an electronic device.
[0008] The fourth aspect of this disclosure provides for a computer-readable storage medium.
[0009] The fifth aspect of this disclosure proposes a chip.
[0010] The first aspect of this disclosure proposes a method for adjusting the state of a processing core, comprising: identifying, based on the processor's operating state parameters, whether there is a core state adjustment requirement for the processor's processing core; in response to identifying that there is a core state adjustment requirement for the processor's processing core, determining the target processing core to be adjusted and the target adjustment state that the target processing core needs to reach, and adjusting the state of the target processing core, wherein the target state includes one of a sleep state and a low-power state.
[0011] A second aspect of this disclosure provides a processing core state adjustment device, comprising: an identification module, configured to identify whether a processing core of the processor has a core state adjustment requirement based on the processor's operating state parameters; and an adjustment module, configured to, in response to the identification that the processor has a core state adjustment requirement, determine the target processing core to be adjusted and the target adjustment state that the target processing core needs to reach, and adjust the state of the target processing core, wherein the target state includes one of a sleep state and a low-power state.
[0012] A third aspect of this disclosure provides an electronic device, comprising: a processor; a memory for storing executable instructions of the processor; wherein the processor is configured to execute instructions to implement the processing core state adjustment method as described in the first aspect above.
[0013] This disclosure provides a fourth aspect of a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the processing core state adjustment method as described in the first aspect above.
[0014] This disclosure provides a fifth aspect of a chip, including one or more interface circuits and one or more processors; the interface circuits are configured to receive signals and send the signals to the processors, the signals including computer instructions stored in a memory, which, when executed by the processors, cause the chip to perform the processing core state adjustment method as described in the first aspect above.
[0015] The processing core state adjustment method and apparatus proposed in this disclosure identify whether the processor has a core state adjustment requirement based on the processor's operating state parameters, and then determine the target processing core to be adjusted and the corresponding target adjustment state. This expands the data range used to determine the target processing core and target adjustment state, improves the accuracy and precision of obtaining the target processing core and target adjustment state, thereby improving the accuracy of processing core state adjustment and the scenario adaptability of the processing core state adjustment method. In scenarios where processing core state adjustment is implemented based on hardware devices, it improves the response speed of processing core state adjustment, reduces software overhead, improves system stability, and optimizes the processing core state adjustment method.
[0016] It should be understood that the description herein is not intended to identify key or essential features of the embodiments thereof, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0017] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a flowchart illustrating a core state adjustment method according to an embodiment of the present disclosure; Figure 2 This is a flowchart illustrating a core state adjustment method according to another embodiment of the present disclosure; Figure 3 This is a flowchart illustrating a core state adjustment method according to another embodiment of the present disclosure; Figure 4This is a schematic diagram of the structure of a core state adjustment device according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the structure of a chip according to an embodiment of the present disclosure. Detailed Implementation
[0018] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.
[0019] The following description, with reference to the accompanying drawings, describes a method, apparatus, device, and medium for processing core state adjustment according to embodiments of the present disclosure.
[0020] Figure 1 This is a flowchart illustrating a core state adjustment method according to an embodiment of this disclosure, as shown below. Figure 1 As shown, the method includes: S101 determines whether the processor's processing core requires core state adjustment based on the processor's operating state parameters.
[0021] In this embodiment of the disclosure, the processor such as the central processing unit (CPU) or graphics processing unit (GPU) of the system can be deployed with multiple processing cores. Taking the CPU as an example, during the daily operation of the CPU, some of the multiple processing cores may need to be adjusted in state. For example, for any processing core, when the CPU meets the set conditions, it can be determined that the processing core needs to be adjusted to a sleep state. In this scenario, the processing core can be controlled to enter a sleep state to realize the state control and adjustment of the processing core.
[0022] In some possible implementations, the descriptive parameters of the operating state of the system to which the CPU belongs can be obtained as the operating state parameters of the system. Based on the various descriptive parameters included in the operating state parameters, the current operating state of the CPU can be evaluated, and then the evaluation results can be used to determine whether the CPU needs to adjust the state of the processing core.
[0023] Specifically, when it is detected that the CPU needs to adjust the state of its processing core, it can be determined that the CPU has a core state adjustment requirement.
[0024] S102, in response to the detection that the processor has a core state adjustment requirement for the processing core, determines the target processing core to be adjusted and the target adjustment state that the target processing core needs to reach, and adjusts the state of the target processing core, wherein the target state includes one of sleep state and low power state.
[0025] In this embodiment of the disclosure, when it is detected that the processor has a core state adjustment requirement for the processing core, the processing core that needs to be adjusted can be determined from the processing cores included in the processor based on the current operating state of the processor, and the target processing core to be adjusted can be selected.
[0026] The state that the processing core needs to be adjusted to can be either a sleep state or a low-power state; no specific limitation is made here.
[0027] In scenarios where the target adjustment processing core needs to be adjusted to a sleep state, after the target adjustment processing core is identified, the sleep state that the target adjustment processing core needs to reach after state adjustment can be determined based on the processor's running state. This sleep state can be determined as the target adjustment state that the target adjustment processing core needs to reach.
[0028] The target adjustment state can include light sleep, light sleep, deep sleep, and even deeper sleep, etc., without being specifically limited here.
[0029] In this scenario, the core state adjustment method in the relevant technology can be used to adjust the state of the target adjustment processing core based on the target adjustment state, thereby adjusting the target adjustment processing core to the target adjustment state.
[0030] It should be noted that the processor can be deployed with corresponding state adjustment hardware devices. The state adjustment of the processing core is realized based on the deployment of state adjustment hardware devices. The state adjustment hardware devices can be multi-core power management units (MPMUs) or other devices, without specific limitations here.
[0031] In scenarios where the target adjustment processing core is controlled to enter a sleep state, the MPMU can predefine a sleep handshake signal with the processor's processing core. This handshake signal can be identified as a sleep req and a sleep pack. After identifying the target adjustment processing core, the MPMU can send a handshake signal (sleepreq) to that core. Once the processing core is ready to sleep, it can return a handshake signal (sleep ack) to the MPMU. Upon receiving the sleep ack, the MPMU can control the power supply and clock module to adjust the power supply and clock for the target adjustment processing core, thereby controlling the core to enter the corresponding sleep state.
[0032] The core sleep preparation mentioned above can refer to saving the context or other operations; no specific limitations are made here.
[0033] The processing core state adjustment method proposed in this disclosure identifies whether the processor has a core state adjustment requirement based on the processor's operating state parameters, and then determines the target processing core to be adjusted and the corresponding target adjustment state. This expands the data range used to determine the target processing core and target adjustment state, improves the accuracy and precision of obtaining the target processing core and target adjustment state, thereby improving the accuracy of processing core state adjustment and the scenario adaptability of the processing core state adjustment method. In scenarios where processing core state adjustment is implemented based on hardware devices, it improves the response speed of processing core state adjustment, reduces software overhead, improves system stability, and optimizes the processing core state adjustment method.
[0034] In the above embodiments, the state adjustment of the target adjustment processing core can also be combined with... Figure 2 To understand further, Figure 2 This is a flowchart illustrating a core state adjustment method according to another embodiment of this disclosure, as shown below. Figure 2 As shown, the method includes: S201, based on operating status parameters, obtains the core idle rate of the processing core, the core temperature of the processing core, and the remaining power supply of the processing core.
[0035] In this embodiment of the disclosure, the operating status of the processor's processing core can be obtained based on the various parameters included in the operating status parameters, so as to identify whether the processing core needs to be adjusted to a sleep state.
[0036] Based on the operating status parameters, the core idle description data of the processing core can be obtained. The core idle clock cycle number of the processing core can be obtained based on the core status signal of the processing core, and the core idle rate of the processing core can be determined based on the core idle clock cycle.
[0037] In this embodiment of the disclosure, the processor's processing core is deployed with a corresponding idle state counter. Based on the idle state counter, the number of clock cycles corresponding to when the processing core is in the core idle state can be obtained, thereby obtaining the core idle clock cycle number of the processing core.
[0038] In some possible implementations, the idle state signal of the processing core is obtained from the core state signal of the processing core, and the number of core idle clock cycles of the processing core is determined based on the number of signals in the idle state signal, wherein the idle state signal is the signal in the core state signal that is in a high level state.
[0039] In this embodiment of the disclosure, the core status signal of the processing core can be detected. When the core status signal is detected to be in a high-level state, the core status signal can be determined as the idle state signal of the processing core. In this scenario, the idle state counter can count the number of detected idle state signals to obtain the core idle clock cycles of the processing core.
[0040] In some possible implementations, the core idle clock cycles of the processing core and the system clock cycles are obtained, and the core idle rate of the processing core is obtained based on the relationship between the core idle clock cycles and the system clock cycles.
[0041] In this embodiment of the disclosure, the processor's processing core is equipped with a counter corresponding to the system clock cycle. In this scenario, the counter can be used to count all the clock cycles experienced by the processing core, and the value can be determined as the number of system clock cycles of the processing core.
[0042] In this scenario, the ratio of the number of core idle clock cycles to the number of system clock cycles can be obtained, and the core idle rate of the processing core can be determined based on this ratio.
[0043] It should be noted that the idle counter and system counter mentioned above can be 32-bit counters or counters with other configurations; no specific limitation is made here.
[0044] During the daily operation of a processor, it can be powered by a single power supply based on a unified power supply mode, or it can be powered by multiple power supplies based on a regional power supply mode.
[0045] In the regional power supply mode, the power supply for each processing core in the processor may be different. In this scenario, the remaining power supply of each processing core in the processor will vary.
[0046] In this scenario, the remaining power supply of each processing core in the processor can be obtained to determine whether each processing core needs to be adjusted.
[0047] The remaining power supply of the processing core can be obtained based on the remaining power supply acquisition method in related technologies, or it can be obtained through the output data of the battery power meter. No specific limitation is made here.
[0048] It should be noted that the remaining power supply of the processing core can include the remaining power of the power supply originally deployed on the processing core, or it can include the remaining power of the external power supply corresponding to the processing core; no specific limitation is made here.
[0049] In addition, a temperature acquisition device is deployed on the processor, which can collect data on the operating temperature of the processor's core. The collected temperature value can be determined as the core temperature of the processing core.
[0050] S202, determine whether the processing core has a state adjustment requirement based on at least one of core idle rate, core temperature and remaining power supply.
[0051] In this embodiment of the disclosure, the determination conditions that must be met to process the core existence state adjustment requirement include at least one of the following: The core idle rate is greater than or equal to the first idle rate threshold and the duration is greater than or equal to the preset duration.
[0052] The remaining power supply is less than or equal to the preset lower limit.
[0053] The processor's input voltage is abnormal.
[0054] The core temperature is greater than or equal to the preset upper limit of the core temperature.
[0055] In some possible implementations, in response to a core idle rate greater than or equal to a first idle rate threshold and a duration greater than or equal to a preset duration, it is determined that the processor has a core state adjustment requirement.
[0056] In this embodiment of the disclosure, the core idle rate of the processing core is set with a corresponding first idle rate threshold. When the core idle rate is greater than or equal to the first idle rate threshold and the duration of this state is greater than or equal to the set duration, it can be determined that the processing core currently meets the conditions for entering a sleep state. In this scenario, it can be determined that the processor has a core state adjustment requirement.
[0057] In some possible implementations, a core state adjustment requirement for the processor is determined in response to the remaining power supply being less than or equal to a preset lower power limit, or when the processor's input voltage is abnormal.
[0058] In this embodiment of the disclosure, when the remaining power supply of the processing core is less than or equal to a preset lower limit, it can be determined that the processing core may be in a state of insufficient power supply. In this scenario, the processing core may not be able to operate normally, and it can be determined that the processing core needs to enter a sleep state. In this scenario, it can be determined that the processor has a need to adjust the core state.
[0059] In some possible implementations, a core state adjustment requirement is determined in response to the core temperature being greater than or equal to a preset upper limit value for the core temperature.
[0060] In this embodiment of the disclosure, when the core temperature is greater than or equal to the preset upper limit of the core temperature, it can be determined that the core temperature may have a certain impact on the normal operation of the processing core. In this scenario, it is necessary to adjust the core temperature of the processing core. This can be achieved by controlling the processing core to enter a sleep state to reduce the core temperature of the processing core. In this scenario, it can be determined that the processing core needs to be adjusted to a sleep state, and thus it can be determined that the processor has a core state adjustment requirement.
[0061] S203, in response to the detection that the processor has a core state adjustment requirement, determines the target processing core to be adjusted and the corresponding target adjustment state based on the core idle rate, core temperature and remaining power of the processing core.
[0062] In some possible implementations, for any processing core in the processor, in response to the processing core's core idle rate being greater than or equal to a preset second idle rate threshold corresponding to a deep sleep state, and the core temperature being less than or equal to a preset upper core temperature value, and the remaining power supply being greater than or equal to a preset lower power limit value, the processing core is determined as the target adjustment processing core, and the deep sleep state is determined as the target adjustment state.
[0063] In this embodiment of the disclosure, for any processing core, when the processing core meets the above conditions, it can be determined that there are no task processes that need to be processed on the processing core, and the processing core meets the relevant conditions for entering deep sleep. In this scenario, the processing core can be identified as the target adjustment processing core, and the deep sleep state can be identified as the target adjustment state of the target adjustment processing core.
[0064] In some possible implementations, in response to the core idle rate of the processing core being greater than or equal to the third idle rate threshold corresponding to shallow sleep, and the core temperature being less than or equal to the upper limit of the core temperature, and the remaining power supply being greater than or equal to the lower limit of the power supply, the processing core is determined as the target adjustment processing core, and the shallow sleep state is determined as the target adjustment state.
[0065] In this embodiment of the disclosure, for any processing core, when the processing core meets the above conditions, it can be determined that there are no task processes that need to be processed on the processing core, and the processing core meets the relevant conditions for entering light sleep. In this scenario, the processing core can be identified as the target adjustment processing core, and the light sleep state can be identified as the target adjustment state of the target adjustment processing core.
[0066] In some possible implementations, in response to a core temperature exceeding an upper limit and remaining power supply falling below a lower limit, the processing core is identified as the target adjustment core, and a deeper sleep state is identified as the target adjustment state.
[0067] In this embodiment of the disclosure, for any processing core, when the processing core meets the above conditions, it can be determined that there are no task processes that need to be processed on the processing core, and the processing core meets the relevant conditions for entering deeper sleep. In this scenario, the processing core can be identified as the target adjustment processing core, and the deeper sleep state can be identified as the target adjustment state of the target adjustment processing core.
[0068] It should be noted that the second idle rate threshold corresponding to the deep sleep state mentioned above can be set to 95%, and the third idle rate threshold corresponding to the light sleep state can be set to 80%. The second idle rate threshold corresponding to the deep sleep state and the third idle rate threshold corresponding to the light sleep state can also be set to other thresholds, without specific limitations here.
[0069] Additionally, the upper limit of the core temperature can be set to 85°C or other temperatures; no specific restrictions are imposed here.
[0070] In addition, the lower limit of the remaining power supply corresponding to the processing core can be set to the remaining power value corresponding to 20%, or it can be set to the remaining power value corresponding to other percentages. No specific limitation is made here.
[0071] S204, adjust the state of the target adjustment processing core based on the target adjustment state.
[0072] In this embodiment of the disclosure, the state of the target adjustment processing core can be adjusted based on the processing core state condition method in the related technology so that it reaches the corresponding target adjustment state.
[0073] The processing core state adjustment method proposed in this disclosure identifies whether the processor needs core state adjustment based on the processor's core idle rate, core temperature, and remaining power supply. It then determines the target processing core to be adjusted and its corresponding target adjustment state. This expands the data range used to determine the target processing core and target adjustment state, improves the accuracy and precision of acquiring these parameters, and consequently improves the accuracy of processing core state adjustment. It also enhances the scenario adaptability of the processing core state adjustment method. By adjusting the processing core state based on core temperature, it reduces the possibility of thermal runaway in the processing core, improves the safety and stability of processor operation, and optimizes the processing core state adjustment method.
[0074] In the above embodiments, regarding the processing core that enters a sleep state, this disclosure also proposes a state adjustment method to wake it up, which can be combined with... Figure 3 understand, Figure 3 This is a flowchart illustrating a core state adjustment method according to another embodiment of this disclosure, as shown below. Figure 3 As shown, the method includes: S301, in response to the detection that the processor has a core wake-up request, determines the target wake-up processing core to be woken up from the sleep processing cores that are in a sleep state, and wakes up the target wake-up processing core.
[0075] In this embodiment of the disclosure, the processor's operating status parameters can be analyzed based on preset conditions to identify whether the processor is currently capable of waking up the processing core. When it is identified that the processor needs to wake up the processing core, it can be determined that the processor has a core wake-up requirement.
[0076] In this scenario, based on the set filtering conditions, the processing cores that need to be woken up can be determined from the processing cores that are in a sleep state. Specifically, the processing cores that are in a sleep state can be identified as sleep processing cores, and the identified processing cores that need to be woken up can be identified as target wake-up processing cores.
[0077] In some possible implementations, the processor's power parameters, operating frequency, module temperature of the processor's key power modules, sleep state data of each sleep processing core, and historical wake-up data can be obtained. Based on the analysis algorithms in related technologies, the above data can be analyzed to select the sleep processing core that meets the processor's requirements from the sleep cores, which can then be used as the target wake-up processing core that needs to be woken up.
[0078] The analysis algorithm mentioned above can be based on a weighted algorithm or other analysis algorithms; no specific limitation is made here.
[0079] In some possible implementations, the processor has a core wake-up requirement determination condition, including at least one of the following: The processor's operating frequency is greater than or equal to a preset operating frequency threshold, and the processor's load is greater than or equal to a preset load threshold.
[0080] The processor has received a new task workload request.
[0081] The processor received a system interrupt request.
[0082] The processor's core area temperature is higher than or equal to the set area temperature threshold.
[0083] The temperature of the corresponding power module of the processor is higher than or equal to the set module temperature threshold.
[0084] In this embodiment of the disclosure, when the processor encounters an event that meets the above conditions, it can be determined that the processing core needs to be woken up to deal with the relevant event. The interrupt request may include external interrupts and timer interrupts, etc., which are not specifically limited here.
[0085] In some possible implementations, there are multiple sleep processing cores. In response to a core wake-up request from the processor, a target wake-up processing core to be woken up is determined from the shallow sleep processing cores included in the multiple sleep processing cores, and the target wake-up processing core is woken up.
[0086] In this embodiment of the disclosure, for multiple sleep processing cores, the processing cores that are in a light sleep state can be obtained as light sleep processing cores. In this scenario, the light sleep processing cores can be screened based on a preset wake-up core screening strategy to determine the target wake-up processing core that needs to be woken up from the light sleep processing cores.
[0087] It should be noted that there can be multiple target wake-up processing cores in the light sleep processing core. In this scenario, the wake-up order and wake-up speed of each of the multiple target wake-up processing cores in the light sleep processing core can be determined based on a preset processing strategy, and then the multiple target wake-up processing cores can be woken up one by one.
[0088] In some possible implementations, in response to waking up the target wake-up processing core in a light sleep state, the processor still has a core wake-up requirement, and determines and wakes up the next target wake-up processing core to be woken up from among the deep sleep processing cores, including the deep sleep processing cores. The target wake-up processing core to be woken up among the deep sleep processing cores is determined based on the energy efficiency ratio of the deep sleep processing cores.
[0089] In this embodiment of the disclosure, when the target adjustment processing core in a light sleep state is awakened, the processor may still need to wake up a new processing core. In this scenario, the target wake-up processing core to be awakened can be determined from the processing cores in a deep sleep state. The processing core in a deep sleep state can be determined as the deep sleep processing core.
[0090] In this scenario, the energy efficiency ratio of each deep sleep processing core can be obtained based on the core energy efficiency ratio acquisition algorithm. Then, the target wake-up processing core that needs to be woken up can be selected from the deep sleep processing cores and the wake-up operation can be performed on it.
[0091] It should be noted that there can be multiple target wake-up processing cores in the deep sleep processing core. In this scenario, the wake-up order and wake-up speed of each of the multiple target wake-up processing cores in the deep sleep processing core can be determined based on a preset processing strategy, and then the multiple target wake-up processing cores can be woken up one by one.
[0092] In scenarios where processor core wake-up is achieved through a state adjustment hardware device (MPMU) deployed on the processor, the MPMU can predefine a wake-up handshake signal with the processor core. This handshake signal can be identified as a wakeereq signal and a wake ack signal. After identifying the target wake-up core, the MPMU can send a handshake signal (wake req) to that target wake-up core. Once the wake-up core is ready to wake up, it can return a handshake signal (wake ack) to the MPMU. Upon receiving the handshake signal (wake ack), the MPMU can control the power supply and clock module to adjust the power supply and clock configuration for the target wake-up core, thereby achieving the purpose of waking up the target wake-up core.
[0093] The processing core state adjustment method proposed in this disclosure wakes up the processing core based on the sleep state when a relevant wake-up event is detected, and wakes up the target processing core, thereby improving the wake-up accuracy of the processing core, avoiding the possibility of power waste caused by waking up unnecessary processing cores, improving the CPU response performance, providing a wake-up mechanism for the sleep state of the processing core, and optimizing the processing core state adjustment method.
[0094] Corresponding to the processing core state adjustment methods proposed in the above embodiments, an embodiment of this disclosure also proposes a processing core state adjustment device. Since the processing core state adjustment device proposed in this disclosure corresponds to the processing core state adjustment methods proposed in the above embodiments, the implementation methods of the above processing core state adjustment methods are also applicable to the processing core state adjustment device proposed in this disclosure, and will not be described in detail in the following embodiments.
[0095] Figure 4 This is a schematic diagram of the structure of a processing core state adjustment device according to an embodiment of the present disclosure, as shown below. Figure 4 As shown, the core state adjustment device 400 includes an identification module 41 and an adjustment module 42, wherein: The identification module 41 is used to identify whether the processor's processing core has a core state adjustment requirement based on the processor's operating state parameters. The adjustment module 42 is used to respond to the detection that the processor has a core state adjustment requirement for the processing core, determine the target adjustment processing core to be adjusted and the target adjustment state that the target adjustment processing core needs to reach, and adjust the state of the target adjustment processing core, wherein the target state includes one of a sleep state and a low power state.
[0096] In this embodiment of the disclosure, the identification module 41 is further configured to: obtain the core idle rate, core temperature, and remaining power supply of the processing core based on the operating status parameters; and determine whether the processing core has a status adjustment requirement based on at least one of the core idle rate, core temperature, and remaining power supply.
[0097] In this embodiment of the disclosure, the identification module 41 is further configured to: obtain the number of core idle clock cycles of the processing core based on the core status signal of the processing core; and determine the core idle rate of the processing core based on the core idle clock cycles.
[0098] In this embodiment of the disclosure, the identification module 41 is further configured to: obtain the idle state signal of the processing core from the core state signal of the processing core, and determine the core idle clock cycle number of the processing core based on the number of signals in the idle state signal, wherein the idle state signal is a signal in the core state signal that is in a high level state; obtain the core idle clock cycle number of the processing core and the system clock cycle number of the system, and obtain the core idle rate of the processing core according to the relationship between the core idle clock cycle number and the system clock cycle number.
[0099] In this embodiment of the disclosure, the determination conditions required for processing the core existence state adjustment requirement include at least one of the following: the core idle rate is greater than or equal to a first idle rate threshold and the duration is greater than or equal to a preset duration; the remaining power supply is less than or equal to a preset lower power limit; the processor's input voltage is abnormal; and the core temperature is greater than or equal to a preset upper core temperature limit.
[0100] In this embodiment of the disclosure, the adjustment module 42 is further configured to: in response to the detection that the processor has a core state adjustment requirement, determine the target adjustment processing core and the corresponding target adjustment state based on the core idle rate, core temperature and remaining power supply of the processing core; and adjust the state of the target adjustment processing core based on the target adjustment state.
[0101] In this embodiment of the present disclosure, the adjustment module 42 is further configured to: for any processing core in the processor, in response to the processing core's core idle rate being greater than or equal to a preset second idle rate threshold corresponding to a deep sleep state, and the processing core's core temperature being less than or equal to a preset upper core temperature value, and the processing core's remaining power supply being greater than or equal to a preset lower power supply value, determine the processing core as the target adjustment processing core, and determine the deep sleep state as the target adjustment state; in response to the processing core's core idle rate being greater than or equal to a third idle rate threshold corresponding to a shallow sleep state, and the processing core's core temperature being less than or equal to an upper core temperature value, and the processing core's remaining power supply being greater than or equal to a lower power supply value, determine the processing core as the target adjustment processing core, and determine the shallow sleep state as the target adjustment state; in response to the processing core's core temperature being greater than the upper core temperature value, and the processing core's remaining power supply being less than the lower remaining power supply value, determine the processing core as the target adjustment processing core, and determine the deeper sleep state as the target adjustment state.
[0102] In this embodiment of the present disclosure, the device includes a wake-up module, configured to: in response to detecting that the processor has a core wake-up request, determine the target adjustment processing core to be woken up from the sleep processing cores in a sleep state, and wake up the target adjustment processing core.
[0103] In this embodiment of the disclosure, the wake-up module is further configured to: in response to a core wake-up requirement of the processor, determine a target wake-up processing core to be woken up from among the shallow sleep processing cores included in the plurality of sleep processing cores, and wake up the target wake-up processing core; in response to the processor still having a core wake-up requirement after waking up the target wake-up processing core in the shallow sleep state, determine the next target wake-up processing core to be woken up from among the deep sleep processing cores included in the plurality of sleep processing cores and wake it up, wherein the target wake-up processing core to be woken up in the deep sleep processing cores is determined based on the energy efficiency ratio of the deep sleep processing cores.
[0104] In this embodiment of the disclosure, the determination conditions for the processor to have a core wake-up requirement include at least one of the following: the processor's operating frequency is greater than or equal to a preset operating frequency threshold, and the processor's load is greater than or equal to a preset load threshold; the processor receives a new task load requirement; the processor receives a system interrupt request; the processor's core area temperature is higher than or equal to a set area temperature threshold; the module temperature of the processor's corresponding power module is higher than or equal to a set module temperature threshold.
[0105] The processing core state adjustment device proposed in this disclosure identifies whether the processor has a core state adjustment requirement based on the processor's operating state parameters, and then determines the target processing core to be adjusted and the corresponding target adjustment state. This expands the data range used to determine the target processing core and target adjustment state, improves the accuracy and precision of obtaining the target processing core and target adjustment state, thereby improving the accuracy of processing core state adjustment and the scenario adaptability of the processing core state adjustment method. In scenarios where processing core state adjustment is implemented based on hardware devices, it improves the response speed of processing core state adjustment, reduces software overhead, improves system stability, and optimizes the processing core state adjustment method.
[0106] To achieve the above embodiments, this disclosure also provides a vehicle for implementing the processing core state adjustment method as proposed in the above embodiments.
[0107] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. For example, the electronic device 500 may be a vehicle, mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.
[0108] Reference Figure 5 The electronic device 500 may include one or more of the following components: processing component 502, memory 504, power component 506, multimedia component 508, audio component 510, input / output (I / O) interface 512, sensor component 514, and communication component 516.
[0109] Processing component 502 typically controls the overall operation of electronic device 500, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 502 may include one or more processors 520 to execute instructions to complete all or part of the steps of the processing core state adjustment method described above. Furthermore, processing component 502 may include one or more modules to facilitate interaction between processing component 502 and other components. For example, processing component 502 may include a multimedia module to facilitate interaction between multimedia component 508 and processing component 502.
[0110] Memory 504 is configured to store various types of data to support the operation of electronic device 500. Examples of this data include instructions for any application or method operating on electronic device 500, contact data, phonebook data, messages, pictures, videos, etc. Memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.
[0111] Power component 506 provides power to various components of electronic device 500. Power component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 500.
[0112] Multimedia component 508 includes a screen that provides an output interface between electronic device 500 and user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a Touch Panel, the screen may be implemented as a touchscreen to receive input signals from the user. The Touch Panel includes one or more touch sensors to sense touches, swipes, and gestures on the Touch Panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 508 includes a front-facing camera and / or a rear-facing camera. When electronic device 500 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
[0113] Audio component 510 is configured to output and / or input audio signals. For example, audio component 510 includes a microphone (MIC) configured to receive external audio signals when electronic device 500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 504 or transmitted via communication component 516. In some embodiments, audio component 510 also includes a speaker for outputting audio signals.
[0114] I / O interface 512 provides an interface between processing component 502 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.
[0115] Sensor assembly 514 includes one or more sensors for providing state assessments of various aspects of electronic device 500. For example, sensor assembly 514 may detect the on / off state of electronic device 500, the relative positioning of components such as the display and keypad of electronic device 500, changes in position of electronic device 500 or a component of electronic device 500, the presence or absence of user contact with electronic device 500, orientation or acceleration / deceleration of electronic device 500, and temperature changes of electronic device 500. Sensor assembly 514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 514 may also include an optical sensor, such as a complementary metal-oxide-semiconductor (CMOS) or charge-coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, sensor assembly 514 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.
[0116] Communication component 516 is configured to facilitate wired or wireless communication between electronic device 500 and other devices. Electronic device 500 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 516 also includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), Bluetooth, and other technologies.
[0117] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to execute the aforementioned core state adjustment method.
[0118] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, which can be executed by a processor 520 of an electronic device 500 to complete the aforementioned processing core state adjustment method. For example, the non-transitory computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.
[0119] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the processing core state adjustment method provided in this disclosure.
[0120] Alternatively, the computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.
[0121] To implement the above embodiments, this disclosure also proposes a chip including an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the processing core state adjustment method provided in this disclosure.
[0122] Figure 6 This is a schematic diagram of the structure of a chip according to an embodiment of this disclosure. See also... Figure 6 The diagram shown is a schematic representation of the structure of chip 600, but it is not limited to this.
[0123] Chip 600 includes processing circuit 601, which is configured to execute any of the above-mentioned core state adjustment methods.
[0124] In some embodiments, chip 600 further includes one or more interface circuits 602. Optionally, the interface circuit 602 is connected to memory 603, and the interface circuit 602 can be used to receive signals from memory 603 or other devices, and the interface circuit 602 can be used to send signals to memory 603 or other devices. For example, the interface circuit 602 can read instructions stored in memory 603 and send the instructions to processing circuit 601.
[0125] In some embodiments, the interface circuit 602 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 601 performs other steps.
[0126] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.
[0127] In some embodiments, chip 600 further includes one or more memories 603 for storing instructions. Optionally, all or part of the memories 603 may be located outside of chip 600.
[0128] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program, which, when executed by a processor, implements the steps of the processing core state adjustment method provided in this disclosure.
[0129] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.
[0130] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A method for processing core state adjustment, characterized in that, The method includes: Based on the processor's operating status parameters, determine whether the processor's processing core requires core state adjustment. In response to the processor having a core state adjustment requirement for a processing core, the target adjustment processing core to be adjusted and the target adjustment state that the target adjustment processing core needs to reach are determined, and the state of the target adjustment processing core is adjusted, wherein the target state includes one of a sleep state and a low power state.
2. The method according to claim 1, characterized in that, The step of determining whether the processor's processing cores require core state adjustment based on the processor's operating state parameters includes: Based on the operating status parameters, the core idle rate of the processing core, the core temperature of the processing core, and the remaining power supply of the processing core are obtained. The state adjustment requirement for the processing core is determined based on at least one of the core idle rate, the core temperature, and the remaining power supply.
3. The method according to claim 2, characterized in that, The step of obtaining the core idle rate of the processing core based on the operating status parameters includes: Based on the core status signal of the processing core, the number of core idle clock cycles of the processing core is obtained; The core idle rate of the processing core is determined based on the core idle clock cycle.
4. The method according to claim 3, characterized in that, Determining the core idle rate of the processing core based on the core idle clock cycle includes: The idle state signal of the processing core is obtained from the core state signal of the processing core, and the number of core idle clock cycles of the processing core is determined based on the number of signals in the idle state signal, wherein the idle state signal is the signal in the core state signal that is in a high level state. The number of idle clock cycles of the processing core and the number of system clock cycles of the system are obtained, and the core idle rate of the processing core is obtained according to the relationship between the number of idle clock cycles of the core and the number of system clock cycles.
5. The method according to claim 2, characterized in that, The processing core has the determination conditions required to meet the state adjustment requirement, including at least one of the following: The core idle rate is greater than or equal to the first idle rate threshold and the duration is greater than or equal to the preset duration; The remaining power supply is less than or equal to a preset lower limit value; The processor's input voltage is abnormal; The core temperature is greater than or equal to the preset upper limit value of the core temperature.
6. The method according to claim 1, characterized in that, The step of responding to the detection that the processor has a core state adjustment requirement, determining the target adjustment processing core and the target adjustment state that the target adjustment processing core needs to reach, and adjusting the state of the target adjustment processing core includes: In response to the detection that the processor has a core state adjustment requirement, the target processing core to be adjusted and the corresponding target adjustment state are determined based on the core idle rate of the processing core, the core temperature of the processing core and the remaining power supply of the processing core. The target adjustment processing core is adjusted based on the target adjustment state.
7. The method according to claim 6, characterized in that, In response to the detection that the processor has a core state adjustment requirement, the process determines the target processing core to be adjusted and the corresponding target adjustment state based on the core idle rate, core temperature, and remaining power of the processing core, including: For any processing core in the processor, in response to the core idle rate of the processing core being greater than or equal to a second idle rate threshold corresponding to a preset deep sleep state, and the core temperature of the processing core being less than or equal to a preset upper limit core temperature, and the remaining power supply of the processing core being greater than or equal to a preset lower limit power supply, the processing core is determined to be the target adjustment processing core, and the deep sleep state is determined to be the target adjustment state. In response to the fact that the core idle rate of the processing core is greater than or equal to the third idle rate threshold corresponding to shallow sleep, and the core temperature of the processing core is less than or equal to the upper limit of the core temperature, and the remaining power supply of the processing core is greater than or equal to the lower limit of the power supply, the processing core is determined to be the target adjustment processing core, and the shallow sleep state is determined to be the target adjustment state. In response to the core temperature of the processing core being greater than the upper limit of the core temperature and the remaining power of the processing core being less than the lower limit of the remaining power, the processing core is determined to be the target adjustment processing core, and a deeper sleep state is determined to be the target adjustment state.
8. The method according to any one of claims 1-7, characterized in that, The method includes: In response to the detection that the processor has a core wake-up request, a target wake-up processing core to be woken up is determined from the sleep processing cores that are in a sleep state, and the target wake-up processing core is woken up.
9. The method according to claim 8, characterized in that, The sleep processing cores are multiple. In response to detecting a core wake-up request from the processor, the process of determining the target wake-up processing core to be woken up from the sleep processing cores in a sleep state and waking up the target wake-up processing core includes: In response to a core wake-up request from the processor, a target wake-up processing core to be woken up is determined from the shallow sleep processing cores among the multiple sleep processing cores, and the target wake-up processing core is woken up. In response to waking up the target wake-up processing core in a light sleep state, the processor still has the core wake-up requirement, and determines and wakes up the next target wake-up processing core from the deep sleep processing cores included in the plurality of sleep processing cores, wherein the target wake-up processing core to be woken up in the deep sleep processing cores is determined based on the energy efficiency ratio of the deep sleep processing cores.
10. The method according to claim 8, characterized in that, The criteria for determining whether the processor has a core wake-up requirement include at least one of the following: The processor's operating frequency is greater than or equal to a preset operating frequency threshold, and the processor's load is greater than or equal to a preset load threshold. The processor receives a new task load requirement; The processor receives a system interrupt request; The core area temperature of the processor is higher than or equal to a set area temperature threshold. The module temperature of the corresponding power module of the processor is higher than or equal to the set module temperature threshold.
11. A device for adjusting the core state, characterized in that, The device includes: The identification module is used to identify whether the processor's processing core has a core state adjustment requirement based on the CPU's operating state parameters. An adjustment module is configured to, in response to the detection of a core state adjustment requirement for a processing core in the processor, determine the target processing core to be adjusted and the target adjustment state that the target processing core needs to reach, and adjust the state of the target processing core, wherein the target state includes one of a sleep state and a low-power state.
12. The apparatus according to claim 11, characterized in that, The identification module is also used for: Based on the operating status parameters, the core idle rate of the processing core, the core temperature of the processing core, and the remaining power supply of the processing core are obtained. The state adjustment requirement for the processing core is determined based on at least one of the core idle rate, the core temperature, and the remaining power supply.
13. The apparatus according to claim 11, characterized in that, The adjustment module is also used for: In response to the detection that the processor has a core state adjustment requirement, the target processing core to be adjusted and the corresponding target adjustment state are determined based on the core idle rate of the processing core, the core temperature of the processing core and the remaining power supply of the processing core. The target adjustment processing core is adjusted based on the target adjustment state.
14. The apparatus according to claim 13, characterized in that, The adjustment module is also used for: For any processing core in the processor, in response to the core idle rate of the processing core being greater than or equal to a second idle rate threshold corresponding to a preset deep sleep state, and the core temperature of the processing core being less than or equal to a preset upper core temperature value, and the remaining power supply of the processing core being greater than or equal to a preset lower power limit value, the processing core is determined to be the target processing core, and the deep sleep state is determined to be the target adjustment state. In response to the fact that the core idle rate of the processing core is greater than or equal to the third idle rate threshold corresponding to shallow sleep, and the core temperature of the processing core is less than or equal to the upper limit of the core temperature, and the remaining power supply of the processing core is greater than or equal to the lower limit of the power supply, the processing core is determined to be the target adjustment processing core, and the shallow sleep state is determined to be the target adjustment state. In response to the core temperature of the processing core being greater than the upper limit of the core temperature and the remaining power of the processing core being less than the lower limit of the remaining power, the processing core is determined to be the target adjustment processing core, and a deeper sleep state is determined to be the target adjustment state.
15. The apparatus according to any one of claims 11-14, characterized in that, The device includes a wake-up module for: In response to the detection that the processor has a core wake-up request, a target wake-up processing core to be woken up is determined from the sleep processing cores that are in a sleep state, and the target wake-up processing core is woken up.
16. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute instructions to implement the method as described in any one of claims 1-10.
17. A computer-readable storage medium, wherein when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as described in any one of claims 1-10.
18. A chip, characterized in that, The device includes one or more interface circuits and one or more processors; the interface circuits are used to receive signals and send the signals to the processors, the signals including computer instructions stored in a memory, which, when executed by the processors, cause the chip to perform the steps of the method according to any one of claims 1-10.