Zero arithmetic overhead address generation method and circuit based on bit extraction
By replacing arithmetic operations with bit extraction operations, the problems of high resource consumption and large latency in lookup table address generation are solved, achieving low-latency and low-resource-consumption address generation, which is suitable for resource-constrained embedded systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINLING INST OF TECH
- Filing Date
- 2026-02-02
- Publication Date
- 2026-05-05
AI Technical Summary
Existing methods for generating lookup table addresses suffer from high overhead of division and multiplication operations, high logical complexity, and increased latency, which limit the system's resource utilization and pipeline efficiency.
A zero-arithmetic-overhead address generation method based on bit extraction is adopted. It replaces traditional arithmetic operations with bit detection and bit extraction operations, directly maps the range index using priority encoding logic, extracts the offset index through a multiplexer, and finally generates the storage address by bit concatenation.
It achieves extremely low logic resource consumption and combinational logic-level latency, supports high-frequency operation and high throughput, and is suitable for resource-constrained embedded systems.
Smart Images
Figure CN121979481A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of digital circuit design and FPGA hardware implementation technology, specifically to a zero-arithmetic-overhead address generation method and circuit based on bit extraction for lookup table addressing, which is particularly suitable for piecewise approximation calculation of nonlinear functions such as cube root, square root, and logarithm. Background Technology
[0002] Look-up tables (LUTs) are a commonly used function approximation technique in digital signal processing and hardware acceleration. By pre-compiling function values and storing them in memory, they enable fast approximation of complex functions. In look-up table-based function approximation systems, address generation is a critical step, and its efficiency directly affects the overall system performance and resource consumption.
[0003] Traditional lookup table address generation methods typically require input normalization and index calculation. Taking nonlinear functions such as cube roots as an example, to efficiently utilize storage space, the input domain is usually divided into multiple sub-intervals, and an independent lookup table is built for each sub-interval. At runtime, it is necessary to first determine the sub-interval to which the input belongs, and then calculate the relative position of the input within that interval as the lookup table index.
[0004] Existing address generation methods mainly face the following technical problems:
[0005] (1) Division operation overhead: In traditional methods, calculating the offset index within an interval requires a division operation. Let the input be y, the lower bound of the interval be Lr, the interval width be Wr, and the number of sampling points be N, then the offset index idx = floor((y - Lr) / Wr × N). In hardware implementation, the division operation requires a large amount of logic resources or a dedicated divider, which significantly increases the system complexity and latency.
[0006] (2) Multiplication overhead: Even if shifting is used to replace some operations, the normalized index mapping may still require multiplication operations, consuming DSP resources or a large amount of LUT resources.
[0007] (3) Interval detection complexity: Existing methods usually use comparator cascade or binary search to determine the interval to which the input belongs. As the number of intervals increases, the logical complexity and delay also increase accordingly.
[0008] (4) Pipeline efficiency: The introduction of arithmetic operations increases the critical path length, which limits the system’s maximum operating frequency and pipeline efficiency.
[0009] Therefore, there is an urgent need for a method that can eliminate arithmetic operations and generate addresses through simple logical operations to meet the requirements of resource-constrained embedded systems for low latency and low resource consumption. Summary of the Invention
[0010] To address the problems of high resource consumption and large latency caused by the need for division, multiplication and other arithmetic operations in existing lookup table address generation methods, this invention provides a zero-arithmetic-overhead address generation method and circuit based on bit extraction. By completely replacing traditional arithmetic operations through bit detection and bit extraction operations, it achieves extremely low logic resource consumption and combinational logic-level latency.
[0011] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0012] The zero-arithmetic-overhead address generation method based on bit extraction includes the following steps:
[0013] S1. Determining the interval index:
[0014] For the input fixed-point integer Detect the position of the most significant bit in its binary representation. Using a preset priority encoding logic, the position is directly... Mapped to range index ;
[0015] S2, Bit Extraction Operation:
[0016] Based on range index Bit extraction from fixed-point integers Directly extract the offset index within the interval :
[0017] ;
[0018] in To input the decimal places, As a benchmark index, The index width;
[0019] S3, Address Concatenation:
[0020] range index Offset index within the interval Perform bit concatenation to generate the final storage address: .
[0021] As a preferred technical solution of the present invention: In step S1, the fixed-point integer... The most significant bit detection uses priority encoding logic, as follows:
[0022] like ,but ;
[0023] like ,but ;
[0024] And so on, until the range index is determined. .
[0025] As a preferred technical solution of the present invention: In step S1, when the input is a floating-point number, the fixed-point integer... This corresponds to the mantissa portion of a floating-point number.
[0026] As a preferred technical solution of the present invention: In step S2, the bit extraction operation is implemented in hardware through a multiplexer, and the bit extraction operation is as follows:
[0027] ;
[0028] in For the first The lower bound of each interval, The interval width, This represents the number of sampling points.
[0029] As a preferred technical solution of the present invention: In step S2, for different interval indices Extracting fixed-point integers The different bit segments are as follows:
[0030] when At that time, extract ;
[0031] when At that time, extract ;
[0032] when At that time, extract .
[0033] The zero-arithmetic-overhead address generation circuit based on bit extraction includes:
[0034] Most significant bit detection module:
[0035] A priority encoder structure is used to detect fixed-point integers. Most significant bit position and output the range index. ;
[0036] Bit extraction module:
[0037] A multiplexer structure is employed to determine the range index. From fixed-point integers Select and extract the corresponding Bit data as an offset index within the interval ;
[0038] Address concatenation module:
[0039] Used for range indexing Offset index within the interval Perform bit concatenation to generate a memory address. .
[0040] As a preferred embodiment of the present invention, it further includes a first-level address pipeline register, which is connected to the output of the address concatenation module. The first-level address pipeline register is used to latch the generated storage address at the clock edge. The address generation combinational logic is isolated from the subsequent memory read path, ensuring that address generation and table lookup operations are performed in different clock cycles.
[0041] As a preferred embodiment of the present invention: the most significant bit detection module includes a bit detection unit, which detects fixed-point integers respectively. The Ranked first The bits are assigned to specific positions, and the interval index is determined according to the priority encoding logic and the output of the bit detection unit. .
[0042] As a preferred embodiment of the present invention: the bit extraction module includes... Each bit segment extraction channel and multiplexer, with each bit segment extraction channel corresponding to a range index value, are used to extract fixed-point integers. The corresponding Bit data, the multiplexer is Select 1 multiplexer, based on range index Select the output of the corresponding channel as the offset index within the interval. .
[0043] As a preferred technical solution of the present invention: the address splicing module will... bit range index Placed in a high position Intra-range offset index of bits Placed in a low position, thus forming The storage address of a bit .
[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0045] 1. Zero arithmetic circuit overhead: This invention completely eliminates arithmetic operations such as division and multiplication in the address generation process, using only priority encoders, multiplexers and bit concatenation logic, without containing any adders, multipliers or dividers.
[0046] 2. Combinational logic level delay: Since it does not involve carry propagation in arithmetic operations, the delay in address generation is only the propagation delay of simple combinational logic, which can be completed within a single clock cycle and supports high-frequency operation.
[0047] 3. Extremely low logic resource consumption: The entire address generation circuit only requires a priority encoder (a few LUTs) and a multiplexer (a few LUTs), and the total resource consumption can be as low as a single-digit number of LUTs.
[0048] 4. Parametric Design: The bit extraction range of this invention is determined by parameters. , , , The system can flexibly adapt to different input formats and lookup table sizes, and has good scalability.
[0049] 5. Pipeline friendly: The zero arithmetic overhead characteristic ensures that address generation will not become a bottleneck in the pipeline, which is conducive to achieving a high-throughput fully pipelined system. Attached Figure Description
[0050] Figure 1 This is an overall flowchart of the bit-based zero-arithmetic-overhead address generation method in this invention;
[0051] Figure 2 Fixed-point integer The bit structure (Q2.22 format, 24 bits);
[0052] Figure 3 Encode the priority logic diagram;
[0053] Figure 4 Mapping relationship between MSB position and range index ( );
[0054] Figure 5 For an example of most significant bit detection and range index determination, input... ( );
[0055] Figure 6 Bit structure and extraction range for fixed-point integer Y (Q2.22 format) );
[0056] Figure 7 A mapping table for the bit extraction range;
[0057] Figure 8 Diagram of a multiplexer hardware implementation;
[0058] Figure 9 Specific examples of the present invention: , , ;
[0059] Figure 10 This is a block diagram of the zero-arithmetic-overhead address generation circuit based on bit extraction according to the present invention. Detailed Implementation
[0060] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.
[0061] like Figure 1 As shown, the zero-arithmetic-overhead address generation method based on bit extraction proposed in this invention includes the following steps:
[0062] S1. Determining the interval index:
[0063] For the input fixed-point integer Detect the position of the most significant bit in its binary representation. Using a preset priority encoding logic, the position is directly... Mapped to range index ;
[0064] Among them, fixed-point integers The most significant bit detection uses priority encoding logic, as follows:
[0065] like ,but ;
[0066] like ,but ;
[0067] And so on, until the range index is determined. .
[0068] When the input is a floating-point number, the fixed-point integer This corresponds to the mantissa portion of a floating-point number.
[0069] S2, Bit Extraction Operation:
[0070] Based on range index Bit extraction from fixed-point integers Directly extract the offset index within the interval :
[0071] (1);
[0072] in To input the decimal places, As a benchmark index, The index width;
[0073] The bit extraction operation is implemented in hardware using a multiplexer, and the specific bit extraction operation is as follows:
[0074] (2);
[0075] in For the first The lower bound of each interval, The interval width, This represents the number of sampling points.
[0076] As a preferred technical solution of the present invention: In step S2, for different interval indices Extracting fixed-point integers The different bit segments are as follows:
[0077] when At that time, extract ;
[0078] when At that time, extract ;
[0079] when At that time, extract ;
[0080] For example:
[0081] when , , hour:
[0082] when At that time, extract ;
[0083] when At that time, extract ;
[0084] when At that time, extract .
[0085] Based on range index The entire address generation process does not involve any arithmetic operation circuits, but rather selects different bit segments for input.
[0086] S3, Address Concatenation:
[0087] range index Offset index within the interval Perform bit concatenation to generate the final storage address: .
[0088] The method of the present invention is applicable to any condition that satisfies The address generation of the system is approximated by nonlinear functions of the form including, but not limited to, cube root, square root, logarithmic function or reciprocal function.
[0089] like Figure 2-5 The diagram shown illustrates the most significant bit detection and interval index determination in this invention.
[0090] like Figure 6-9 The diagram shown is a schematic of the bit extraction operation in this invention.
[0091] Introduction to the principle of the zero-arithmetic-overhead address generation method based on bit extraction.
[0092] 1. Problem Background
[0093] In lookup table-based function approximation systems, the input domain is typically divided into multiple sub-intervals, each corresponding to a lookup table.
[0094] The core task of address generation is:
[0095] (1) Determine the index of the sub-interval to which the input belongs. ;
[0096] (2) Calculate the offset index of the input within this interval. ;
[0097] (3) and Combined into memory address .
[0098] In existing methods, offset index calculation requires normalization and multiplication operations, resulting in high hardware implementation costs.
[0099] 2. Power interval partitioning of 2
[0100] This invention utilizes the mathematical properties of interval partitioning by powers of 2 to eliminate arithmetic operations.
[0101] Let the input field be , Classified as Sub-intervals:
[0102] The lower bound of each subinterval and width All are powers of 2: This characteristic allows both interval detection and offset calculation to be converted into bit operations.
[0103] 3. Most significant bit detection
[0104] For input fixed-point integers (Format: Qm.n, where n is the decimal width), and its interval is uniquely determined by the position of the most significant bit (MSB). Let... The MSB is located in the first bit (i.e.) and Then the interval index is:
[0105] ;
[0106] in, This is the reference position.
[0107] 4. Derivation of the bit extraction formula
[0108] Existing offset index formula: ;
[0109] Will , , Substitute:
[0110] =
[0111] =
[0112] =
[0113] = (3);
[0114] because Belongs to the interval (Fixed-point integer representation), after right shift, its highest bit (the first bit) The bit is 1, that is .minus This is equivalent to clearing the highest bit, therefore:
[0115] (4);
[0116] This formula shows that the offset index Can be extracted directly The Ranked first The position was obtained.
[0117] The zero-arithmetic-overhead address generation circuit based on bit extraction proposed in this invention includes:
[0118] Most significant bit detection module:
[0119] A priority encoder structure is used to detect fixed-point integers. Most significant bit position and output the range index. ;
[0120] Bit extraction module:
[0121] A multiplexer structure is employed to determine the range index. From fixed-point integers Select and extract the corresponding Bit data as an offset index within the interval ;
[0122] Address concatenation module:
[0123] Used for range indexing Offset index within the interval Perform bit concatenation to generate a memory address. .
[0124] It also includes a first-level address pipeline register, which is connected to the output of the address concatenation module. The first-level address pipeline register is used to latch the generated memory address at the clock edge. The address generation combinational logic is isolated from the subsequent memory read path, ensuring that address generation and table lookup operations are performed in different clock cycles.
[0125] The most significant bit detection module includes a bit detection unit, which detects fixed-point integers respectively. The Ranked first The bits are assigned to specific positions, and the interval index is determined according to the priority encoding logic and the output of the bit detection unit. .
[0126] The bit extraction module includes Each bit segment extraction channel and multiplexer, with each bit segment extraction channel corresponding to a range index value, are used to extract fixed-point integers. The corresponding Bit data, the multiplexer is Select 1 multiplexer, based on range index Select the output of the corresponding channel as the offset index within the interval. .
[0127] The address concatenation module will bit range index Placed in a high position Intra-range offset index of bits Placed in a low position, thus forming The storage address of a bit .
[0128] The circuit of this invention does not contain adders, multipliers, or dividers; it consists only of a priority encoder, a multiplexer, and bit concatenation logic, enabling address generation with zero arithmetic circuit overhead.
[0129] Specifically, such as Figure 10 As shown:
[0130] Most significant bit detection module:
[0131] by Taking a sub-interval as an example, the most significant bit detection uses priority encoding logic:
[0132] like ,but ;
[0133] Otherwise if ,but ;
[0134] otherwise ;
[0135] for , , Specific configuration:
[0136] like ,but (Input belongs to) );
[0137] Otherwise if ,but (Input belongs to) );
[0138] otherwise (Input belongs to) ).
[0139] This logic can be implemented with only 2-3 LUTs.
[0140] Among them, the bit extraction module:
[0141] The bit extraction module uses the range index. choose Different segments. With For example, (128 sampling points per interval), as shown in Table 1:
[0142]
[0143] Table 1
[0144] This module is accessed through a Implemented using a selector-to-one multiplexer, based on... The value is selected as the corresponding 7-bit data. Output. For Only one 3-to-1 MUX is needed, consuming approximately 2-4 LUTs.
[0145] The address concatenation module includes:
[0146] The address concatenation module will ceil( ) range index Placed in a high position bit offset index Placed in the least significant bit, forming a complete memory address:
[0147] ;
[0148] for , Configuration, address 9 bits (2 bits) Bit It supports addressing up to 512 entries. This module is pure combinational logic and does not consume any LUT resources.
[0149] The specific application of this invention is illustrated using a cube root function lookup table as an example.
[0150] 1. System parameters:
[0151] Input format: Q2.22 fixed-point format (24 bits, including 2 integer bits and 22 decimal bits);
[0152] Input range: ;
[0153] Number of subintervals: ;
[0154] Sampling points per interval: ( );
[0155] Benchmark Index: ;
[0156] Decimal places width: .
[0157] 2. Example of address generation process:
[0158] Assuming input The corresponding fixed-point integer representation is:
[0159] ;
[0160] Binary representation: (24-bit)
[0161] Step 1:
[0162] Most significant bit detection:
[0163] , Therefore, MSB is located at position 22. ;
[0164] Step 2:
[0165] Bit extraction:
[0166] according to ,extract :
[0167] ;
[0168] ;
[0169] therefore ;
[0170] Step 3:
[0171] Address concatenation:
[0172] .
[0173] Verification: Address 192 corresponds to the 64th entry in Range1 (addresses 128-255), i.e. The nearby lookup table entry is correct.
[0174] Implementation results:
[0175] The implementation results on a Xilinx Kintex-7 FPGA show that the zero-arithmetic-overhead address generation circuit of this invention has the following performance characteristics, as shown in Table 2:
[0176]
[0177] Table 2
[0178] The zero arithmetic overhead of this invention makes it particularly suitable for: resource-constrained embedded FPGA systems; data stream processing applications requiring high throughput; latency-sensitive real-time control systems; and prototype systems requiring rapid deployment.
[0179] It should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any other way. Any modifications or equivalent changes made based on the technical essence of the present invention shall still fall within the scope of protection claimed by the present invention.
Claims
1. A zero-arithmetic-overhead address generation method based on bit extraction, characterized in that, Includes the following steps: S1. Determining the interval index: For the input fixed-point integer Detect the position of the most significant bit in its binary representation. Using a preset priority encoding logic, the position is directly... Mapped to range index ; S2, Bit Extraction Operation: Based on range index Bit extraction from fixed-point integers Directly extract the offset index within the interval : ； in To input the decimal places, As a benchmark index, The index width; S3, Address Concatenation: range index Offset index within the interval Perform bit concatenation to generate the final storage address: .
2. The zero-arithmetic-overhead address generation method based on bit extraction according to claim 1, characterized in that, In step S1, fixed-point integers The most significant bit detection uses priority encoding logic, as follows: like ,but ; like ,but ; And so on, until the range index is determined. .
3. The zero-arithmetic-overhead address generation method based on bit extraction according to claim 1, characterized in that, In step S1, when the input is a floating-point number, the fixed-point integer... This corresponds to the mantissa portion of a floating-point number.
4. The zero-arithmetic-overhead address generation method based on bit extraction according to claim 1, characterized in that, In step S2, the bit extraction operation is implemented in hardware using a multiplexer, and the specific bit extraction operation is as follows: ； in For the first The lower bound of each interval, The interval width, This represents the number of sampling points.
5. The zero-arithmetic-overhead address generation method based on bit extraction according to claim 1, characterized in that, In step S2, for different interval indices Extracting fixed-point integers The different bit segments are as follows: when At that time, extract ; when At that time, extract ; when At that time, extract .
6. A zero-arithmetic-overhead address generation circuit based on bit extraction, characterized in that, include: Most significant bit detection module: A priority encoder structure is used to detect fixed-point integers. Most significant bit position and output the range index. ; Bit extraction module: A multiplexer structure is employed to determine the range index. From fixed-point integers Select and extract the corresponding Bit data as an offset index within the interval ; Address concatenation module: Used for range indexing Offset index within the interval Perform bit concatenation to generate a memory address. .
7. The zero-arithmetic-overhead address generation circuit based on bit extraction according to claim 6, characterized in that, It also includes a first-level address pipeline register, which is connected to the output of the address concatenation module. The first-level address pipeline register is used to latch the generated memory address at the clock edge. The address generation combinational logic is isolated from the subsequent memory read path, ensuring that address generation and table lookup operations are performed in different clock cycles.
8. The zero-arithmetic-overhead address generation circuit based on bit extraction according to claim 6, characterized in that, The most significant bit detection module includes a bit detection unit, which detects fixed-point integers respectively. The Ranked first The bits are assigned to specific positions, and the interval index is determined according to the priority encoding logic and the output of the bit detection unit. .
9. The zero-arithmetic-overhead address generation circuit based on bit extraction according to claim 6, characterized in that, The bit extraction module includes Each bit segment extraction channel and multiplexer, with each bit segment extraction channel corresponding to a range index value, are used to extract fixed-point integers. The corresponding Bit data, the multiplexer is Select 1 multiplexer, based on range index Select the output of the corresponding channel as the offset index within the interval. .
10. The zero-arithmetic-overhead address generation circuit based on bit extraction according to claim 6, characterized in that, The address concatenation module will bit range index Placed in a high position Intra-range offset index of bits Placed in a low position, thus forming The storage address of a bit .