Data transmission method and device, electronic equipment and medium

Abstract

The invention provides a data transmission method and device, electronic equipment and a medium, and relates to the technical field of chips. Comprising the steps that a first descriptor in a buffer area is written into a descriptor storage area, a write pointer in a local register is updated, the write pointer indicates the position of the first descriptor in the descriptor storage area, and the first descriptor indicates storage information of data to be transmitted; and pushing the write pointer to a local mirror image register of the sending end to form a write pointer mirror image in the mirror image register, wherein the write pointer mirror image is used for the sending end to read the first descriptor from the descriptor storage area to obtain the to-be-transmitted data. According to the data transmission method provided by the invention, the mirror image register is locally maintained to store the pointer mirror image of the opposite end, and the pointer does not need to be acquired from the opposite end across a bus, so that the descriptor interaction rate is accelerated; software participation is not needed, complex software and hardware interaction is reduced, software overhead is effectively reduced, and the cross-domain interaction rate of the descriptors is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data transmission method and apparatus, electronic device and medium. Background Technology

[0002] In chip design, modules need to interact via descriptors for the transfer of data, instructions, etc. With the rapid development of high-speed services, the requirements for the interaction rate of descriptors between modules are becoming increasingly higher. Summary of the Invention

[0003] A first aspect of this disclosure provides a data transmission method, comprising: writing a first descriptor in a buffer region into a descriptor storage region and updating a write pointer in a local register, the write pointer indicating the position of the first descriptor in the descriptor storage region, the first descriptor indicating storage information of data to be transmitted; and pushing the write pointer to a local mirror register of the sending end to form a write pointer mirror in the mirror register, the write pointer mirror being used by the sending end to read the first descriptor from the descriptor storage region to obtain the data to be transmitted.

[0004] In some embodiments of this disclosure, the first descriptor is at least one descriptor in a buffer region, and the method further includes: in response to the number of descriptors stored in the buffer region reaching a receive buffer threshold, determining the number of free descriptors in the descriptor storage region; determining the number of pushes based on the number of stored descriptors and the number of free descriptors; and determining the descriptor in the buffer region that represents the number of pushes as the first descriptor.

[0005] In some embodiments of this disclosure, determining the number of free spaces in the descriptor storage area includes: determining the free spaces in the descriptor storage area based on the read pointer mirror of the local storage, wherein the read pointer mirror is formed by the local mirror register of the receiver based on the read pointer pushed by the sender; and determining the number of free spaces as the number of free spaces.

[0006] In some embodiments of this disclosure, writing the first descriptor into the descriptor storage area and updating the write pointer in the local register includes: writing the first descriptor into an empty location via the system bus and determining the location identifier of the first descriptor; determining the first write pointer corresponding to the first descriptor based on the location identifier; and storing the first write pointer in the local register.

[0007] In some embodiments of this disclosure, pushing a write pointer to a local mirror register at the transmitting end to form a write pointer mirror in the mirror register includes: pushing a first write pointer in a local register to a local mirror register at the transmitting end via a system bus to form a first write pointer mirror of the first write pointer.

[0008] In some embodiments of this disclosure, the method further includes: in response to a descriptor write instruction, storing a first descriptor corresponding to the descriptor write instruction into a buffer area; after writing the first descriptor into the descriptor storage area, managing the storage location corresponding to the first descriptor in the buffer area based on a preset caching strategy.

[0009] In the above embodiments, a highly efficient, decoupled, and low-overhead receiver-driven data transmission mechanism is constructed. High-bandwidth data / descriptor transmission is transformed into low-bandwidth pointer synchronization. Through strategies such as batch push, buffer management, and mirrored pointer coordination, system bus contention and access latency are significantly reduced. It empowers the receiver to actively manage the data transmission process, while ensuring efficient and secure collaboration with the sender through shared storage and lock-free pointer communication, ultimately improving the overall performance and scalability of the data transmission system.

[0010] A second aspect of this disclosure provides a data transmission method executed by a sending end, comprising: storing a first descriptor corresponding to the write pointer mirror in a descriptor storage area into a local buffer area based on the write pointer mirror in a local mirror register, wherein the write pointer mirror is formed by the sending end based on the write pointer pushed by the receiving end; updating the read pointer in a local register based on the first descriptor in the buffer area, and pushing the read pointer to the local mirror register of the receiving end.

[0011] In some embodiments of this disclosure, storing the first descriptor corresponding to the write pointer image in the descriptor storage area to a local buffer area based on the write pointer image in the local mirror register includes: determining the number of reads of the first descriptor in response to the fact that the number of descriptors in the buffer area has not reached the send buffer threshold; determining the write pointer image of the read count in the local mirror register; determining the position identifier of the first descriptor in the descriptor storage area based on the write pointer image; and storing the first descriptor corresponding to the position identifier in the descriptor storage area to the buffer area.

[0012] In some embodiments of this disclosure, determining the number of reads for the first descriptor includes: determining the number of descriptors that can be stored in the buffer region; determining the number of unread descriptors in the descriptor storage region; and determining the number of reads based on the number of storeable descriptors and the number of unread descriptors.

[0013] In some embodiments of this disclosure, updating the read pointer in the local register based on the first descriptor in the buffer region and pushing the read pointer to the local mirror register of the receiving end includes: storing the pre-read pointer corresponding to the first descriptor in the local register based on the first descriptor in the buffer region; determining the pre-read pointer corresponding to the descriptor call instruction in the local register as the read pointer in response to the descriptor call instruction; and pushing the read pointer to the local mirror register of the receiving end through the system bus to form a read pointer mirror in response to the number of read pointers reaching the push threshold, wherein the read pointer mirror is used by the receiving end to determine the free space in the descriptor storage region.

[0014] In some embodiments of this disclosure, in response to a descriptor call instruction, determining the pre-read pointer corresponding to the descriptor call instruction in the local register as a read pointer includes: in response to the descriptor call instruction, determining a second descriptor corresponding to the descriptor call instruction in a buffer area; determining storage information based on the second descriptor; reading the data to be transmitted corresponding to the second descriptor based on the storage information, and determining the pre-read pointer corresponding to the second descriptor as a read pointer.

[0015] In the above embodiment, the generation and push of the "read pointer" are separated, and a "pre-read pointer" is introduced as an intermediate state. The sending end generates the pre-read pointer when storing the descriptor in the local buffer, and only confirms it as the formal read pointer and pushes it in batches after the descriptor is actually used (called). This fine-grained management of the timing of completion confirmation, aggregating the completion confirmation of multiple data packets into a single pointer push, greatly reducing the communication overhead used for flow control and improving confirmation efficiency.

[0016] A third aspect of this disclosure provides a data transmission method executed by a data transmission system, which includes a transmitter and a receiver. The method includes: the receiver writing a first descriptor in a buffer region into a descriptor storage region and updating a write pointer in a local register, the write pointer indicating the position of the first descriptor in the descriptor storage region, the first descriptor indicating storage information of data to be transmitted; pushing the write pointer to a local mirror register of the transmitter via a system bus to form a write pointer mirror in the mirror register, the write pointer mirror being used by the transmitter to read the first descriptor from the descriptor storage region to obtain the data to be transmitted; the transmitter storing the first descriptor corresponding to the write pointer mirror in the descriptor storage region into a local buffer region based on the write pointer mirror in the local mirror register; and updating a read pointer in the transmitter's local register based on the first descriptor in the transmitter's buffer region and pushing the read pointer to the local mirror register of the receiver.

[0017] In the above embodiments, a closed-loop bidirectional pointer synchronization system is defined. This achieves the separation and cooperation of data flow (indirectly indicated through descriptors) and control flow (synchronized through pointer mirroring). This system approach ensures the orderliness, reliability, and efficiency of data transmission. The combination of push-driven operation by the receiving end and pull-driven feedback by the sending end forms an efficient producer-consumer model, minimizing synchronization overhead on the core path.

[0018] A fourth aspect of this disclosure provides a receiving apparatus, which includes an access module and a transceiver module. The access module is used to write a first descriptor in a buffer region into a descriptor storage region and update a write pointer in a local register. The write pointer indicates the position of the first descriptor in the descriptor storage region, and the first descriptor indicates storage information of data to be transmitted. The transceiver module is used to push the write pointer to a local mirror register of the transmitting end to form a write pointer mirror in the mirror register. The write pointer mirror is used by the transmitting end to read the first descriptor from the descriptor storage region to obtain the data to be transmitted.

[0019] In some embodiments of this disclosure, the receiving device further includes a processing module, which is configured to: determine the number of free space in the descriptor storage area in response to the number of descriptors already stored in the buffer area reaching a receiving buffer threshold; determine the number of pushes based on the number of stored descriptors and the number of free space; and determine the descriptors in the buffer area that are pushed as the first descriptors.

[0020] In some embodiments of this disclosure, the processing module is used to: determine the free space in the descriptor storage area based on the read pointer mirror of local storage, wherein the read pointer mirror is formed by the local mirror register of the receiving end based on the read pointer pushed by the sending end; and determine the number of free spaces as the number of free spaces.

[0021] In some embodiments of this disclosure, the access module is configured to: write a first descriptor to an empty location via the system bus, determine the location identifier of the first descriptor; determine a first write pointer corresponding to the first descriptor based on the location identifier; and store the first write pointer in a local register.

[0022] In some embodiments of this disclosure, the transceiver module is configured to: push the first write pointer in the local register to the local mirror register of the transmitting end via the system bus to form a first write pointer mirror of the first write pointer.

[0023] In some embodiments of this disclosure, the access module is configured to: in response to a descriptor write instruction, store the first descriptor corresponding to the descriptor write instruction into a buffer area; and after writing the first descriptor into the descriptor storage area, manage the storage location corresponding to the first descriptor in the buffer area based on a preset caching strategy.

[0024] In the above embodiments, the receiving device transforms high-bandwidth data / descriptor transmission into low-bandwidth pointer synchronization. Through strategies such as batch push, buffer management, and mirrored pointer coordination, it significantly reduces system bus contention and access latency. The receiving device's ability to actively manage the data transmission process, while ensuring efficient and secure collaboration with the transmitting device through shared storage and lock-free pointer communication, ultimately improves the overall performance and scalability of data transmission.

[0025] A fifth aspect embodiment of this disclosure provides a transmitting apparatus, which includes an access module and a transceiver module. The access module is used to store a first descriptor corresponding to the write pointer image in the descriptor storage area into a local buffer area based on the write pointer image in the local mirror register. The write pointer image is formed by the transmitting end based on the write pointer pushed by the receiving end. The transceiver module is used to update the read pointer in the local register based on the first descriptor in the buffer area and push the read pointer to the local mirror register of the receiving end.

[0026] In some embodiments of this disclosure, the access module is configured to: determine the number of first descriptors to be read in response to the number of descriptors in the buffer area not reaching the send buffer threshold; determine the write pointer mirror of the number of reads in a local mirror register; determine the position identifier of the first descriptor in the descriptor storage area based on the write pointer mirror; and store the first descriptor corresponding to the position identifier in the descriptor storage area into the buffer area.

[0027] In some embodiments of this disclosure, the access module is configured to: determine the number of descriptors that can be stored in the buffer area; determine the number of unread descriptors in the descriptor storage area; and determine the number of reads based on the number of storeable descriptors and the number of unread descriptors.

[0028] In some embodiments of this disclosure, the access module is configured to: store the pre-read pointer corresponding to the first descriptor in the buffer area into a local register based on the first descriptor in the buffer area; the transceiver module is configured to, in response to a descriptor call instruction, determine the pre-read pointer corresponding to the descriptor call instruction in the local register as a read pointer; and, in response to the number of read pointers reaching a push threshold, push the read pointers to the local mirror register of the receiving end through the system bus to form a read pointer mirror, the read pointer mirror being used by the receiving end to determine the free space in the descriptor storage area.

[0029] In some embodiments of this disclosure, the apparatus further includes a processing module, which is configured to: in response to a descriptor invocation instruction, determine a second descriptor corresponding to the descriptor invocation instruction in a buffer area; determine storage information based on the second descriptor; read the data to be transmitted corresponding to the second descriptor based on the storage information, and determine the pre-read pointer corresponding to the second descriptor as a read pointer.

[0030] In the above embodiments, the transmitting device can process data streams more efficiently and smoothly through event-driven batch prefetching, local buffering, and aggregated read pointer push. This not only reduces the access pressure on the shared bus and storage area but also optimizes its own processing pipeline, forming a highly efficient collaborative system together with the receiving device.

[0031] A sixth aspect of this disclosure provides an electronic device including: a processor and a memory for storing a computer program capable of running on the processor, wherein the processor, when running the computer program, performs the method described in any one of the first or second aspects of this disclosure.

[0032] A seventh aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the methods described in any of the first or second aspects of this disclosure.

[0033] An eighth aspect of this disclosure provides a program product including computer instructions for causing a computer to perform the methods described in any of the first or second aspects of this disclosure.

[0034] A ninth aspect embodiment of this disclosure provides a chip including at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method of any one of the first or second aspects of this disclosure through logic circuits or execution code instructions.

[0035] In summary, the data transmission method, apparatus, electronic device, and medium proposed in this disclosure, through a core architecture of "centralized storage of descriptors, pointer mirroring synchronization, and dual-end local buffering," transforms high-bandwidth data transfer into low-bandwidth pointer synchronization. The receiving end updates and pushes write pointers in batches, driving the sending end to pre-read descriptors on demand; after processing the data, the sending end aggregates and pushes read pointers, completing the acknowledgment loop. This design achieves lock-free collaboration, batch processing, and asynchronous decoupling, significantly reducing system bus contention and access latency, and significantly improving the overall throughput, real-time performance, and scalability of the data transmission system.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0038] Figure 1 A flowchart of the processing for receiving descriptors;

[0039] Figure 2 This is a schematic diagram of the structure of a descriptor transceiver device; Figure 3 This is a flowchart illustrating the data transmission method of the receiving end proposed in the embodiments of this disclosure; Figure 4 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure; Figure 6 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure; Figure 7 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure; Figure 8 This is a schematic flowchart of the data transmission method for the sending end proposed in an embodiment of this disclosure; Figure 9 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure; Figure 10 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure; Figure 11 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure; Figure 12A A schematic diagram of a device for receiving descriptors; Figure 12B A schematic diagram of the descriptor delivery and write pointer push processing steps for the descriptor receiving device; Figure 12C A schematic diagram of a device used for descriptor transmission; Figure 12D A schematic diagram of the descriptor prefetching process of the descriptor sending device; Figure 13 This is a schematic diagram of the structure of a receiving device according to an embodiment of the present disclosure; Figure 14 This is a schematic diagram of the structure of a transmitting device according to an embodiment of the present disclosure; Figure 15 This is a schematic diagram of the structure of the electronic device proposed in the embodiments of this disclosure; Figure 16 This is a schematic diagram of the structure of a chip for implementing the above-described data transmission method, according to an exemplary embodiment. Detailed Implementation

[0040] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0041] In related technologies, a combination of hardware and software is usually used to realize the descriptor interaction between modules. The hardware and software interaction mechanism is complex, and the software side needs to obtain the latest information from the hardware side across the bus, resulting in a low descriptor interaction rate.

[0042] Taking descriptor reception as an example, such as Figure 1 The diagram shown is a flowchart of the relevant technology. The following is a brief description of the process: 1. After receiving the descriptor to be released, the descriptor receiver will release the descriptor into the receiver's first-in-first-out (FIFO) through the bus. After the release is completed, the local write pointer will be updated, an interrupt will be issued, and the software will be notified. 2. After receiving an interrupt, the software will first read the receive control register through the second bus to obtain the latest write pointer; 3. Then, the software will read the descriptor to be released from the receiver FIFO through the second bus according to the write pointer of the descriptor receiver; 4. After obtaining the descriptor, update the read pointer in the receive control register via the second bus; thus completing the descriptor reception.

[0043] The descriptor sending scheme is similar to the descriptor receiving scheme and will not be described further.

[0044] Based on the above scheme Figure 2 This is a schematic diagram of a descriptor transceiver device. In order to realize the cross-domain transfer of descriptors from hardware region 1 to hardware region 2, the software, as an intermediary, needs to continuously interact with the descriptor receiving device and the descriptor sending device, and move the descriptors from the receiving FIFO to the sending FIFO. For the software, the overhead is large; and there are redundant moving operations of descriptors in the memory space, resulting in low speed and high power consumption.

[0045] To address the aforementioned issues, this disclosure proposes a data transmission method that maintains mirror registers on both the receiving and sending ends to store the pointer mirror generated on the other side. This avoids the need to cross the bus to retrieve pointers from the other side for data access to memory regions, enabling the local acquisition of pointers without cross-bus access, thus accelerating descriptor interaction. Furthermore, it eliminates the need for software intervention, reducing complex hardware and software interactions, effectively lowering software overhead, and improving the cross-domain interaction rate of descriptors.

[0046] The data transmission method provided in this application will now be described in detail with reference to the accompanying drawings.

[0047] The data transmission method proposed in this disclosure can be applied to a data transmission system, which includes a sending end and a receiving end. Here, the sending end and receiving end are names of the execution entities from an external perspective; that is, the sending end can be the end that sends the descriptor when data is sent from inside to outside, and the receiving end can be the end that receives the descriptor when data is stored from outside to inside.

[0048] In some embodiments, the receiver and transmitter can be hardware modules or software modules, and this disclosure does not limit them.

[0049] In some embodiments, the receiver may be a descriptor receiving component, and the sender may be a descriptor sending component.

[0050] Figure 3 This is an interactive schematic diagram of a data transmission method proposed in an embodiment of this disclosure, which is executed by the receiving end. Figure 3 As shown, the method includes the following steps: Step 301: Write the first descriptor in the buffer area to the descriptor storage area and update the write pointer in the local register.

[0051] In some embodiments, the write pointer indicates the location of the first descriptor in the descriptor storage area, and the first descriptor indicates the data to be transferred.

[0052] In some embodiments, the buffer area may be a receive buffer for the receiving end to receive descriptors written by external hardware modules.

[0053] In some embodiments, multiple descriptors are cached in the buffer area. When the number of descriptors in the buffer area meets a certain condition, the cached descriptors are written to the descriptor storage area.

[0054] In some embodiments, the condition for the number of descriptors in the buffer area can be customized according to the scenario or requirements. For example, when the number of descriptors reaches the maximum value that the buffer area can cache, a portion of the descriptors can be output to the descriptor storage area; or, when the number of descriptors reaches a preset fixed value, a certain number of descriptors can be output to the descriptor storage area. The specific values ​​of the preset fixed number and the number of descriptors output are not limited in this disclosure.

[0055] In some embodiments, the first descriptor is at least one descriptor in the buffer region.

[0056] In some embodiments, the descriptor storage area is a shared memory area between the receiving end and the sending end, used to store descriptors exchanged between the two ends.

[0057] In some embodiments, descriptors in the descriptor storage area are stored in a queue, i.e., they are stored and retrieved according to a first-in, first-out (FIFO) rule.

[0058] For example, the descriptor storage area can be as follows: Figure 12A The FIFO descriptor shown in the diagram is located in the memory area and is used to store descriptors for interaction between hardware area 1 and hardware area 2 / software area.

[0059] In some embodiments, when the receiving end receives the first descriptor sent from the outside, it caches the first descriptor in the buffer area. The first descriptor indicates the storage location of the data to be transmitted in memory, that is, it indicates the position and length of the data to be transmitted, so that after the sending end obtains the first descriptor, it can read the data to be transmitted in the memory area according to the position and length in the first descriptor.

[0060] For example, the receiving end can be as follows: Figure 12A The hardware area 1 in the schematic diagram of the device is used to receive descriptors stored in by external hardware modules and push the descriptors to hardware area 2 / software area through the bus to realize cross-domain interaction of descriptors.

[0061] In some embodiments, the receiving end can generate a write pointer corresponding to the first descriptor based on the first descriptor. The write pointer is the command passed between the receiving end and the sending end during descriptor interaction.

[0062] In some embodiments, the receiver's receive control register can be configured with a corresponding write pointer based on the first descriptor that needs to be sent to the sender. The write pointer is stored in a local register of the receiver and points to the first descriptor in the descriptor storage area.

[0063] In some embodiments, the write pointer can indicate the location of the first descriptor in the descriptor storage area.

[0064] For example, such as Figure 12A The diagram shows a device for receiving descriptors. The receive buffer is used to cache descriptors written by the hardware module. The descriptor FIFO is stored in the memory area and is used to store descriptors and perform relay. The receive control register is used to configure the relevant parameters of the descriptor FIFO, including the base address and total depth of the memory space where the descriptor FIFO is located, the current read / write pointer, and the receive buffer threshold.

[0065] Step 302: Push the write pointer to the local mirror register of the sending end via the system bus to form a write pointer mirror in the mirror register.

[0066] In some embodiments, write pointer mirroring is used by the sending end to read a first descriptor from the descriptor storage area to obtain the data to be transmitted.

[0067] In some embodiments, the receiving end pushes the write pointer of the first descriptor that needs to be transmitted to the sending end to the mirror register maintained locally by the sending end through the system bus, and the mirror register forms a write pointer mirror corresponding to the write pointer.

[0068] In some embodiments, the mirror register maintained locally at the sending end is used to form a mirror of the write pointer or read pointer pushed by the peer, so that the sending end can know the relevant information of the descriptor that the peer needs to transmit locally.

[0069] For example, such as Figure 12A The schematic diagram of the device shows that the receiving controller is used to control the descriptor receiving device to write the descriptors in the receiving buffer into the descriptor FIFO through the first bus, and after the writing is completed, update the write pointer in the local receiving control register, and push the latest write pointer to the write pointer in the local register of the descriptor sending component (software area / hardware area 2) through the first bus.

[0070] Specifically, the configuration of the receive control register and the local registers in the peer descriptor sending component needs to point to the same descriptor FIFO, and a pointer-based image management system is adopted. That is, the descriptor receiving device is responsible for maintaining the write pointers of both parties. Maintaining the pointers of both parties means that after updating the local register, it actively updates the peer mirror register through the bus. The descriptor sending component is responsible for maintaining the read pointers of both parties, so that both parties can directly obtain the read and write pointer information of the shared descriptor FIFO from the local register, thereby delivering / receiving descriptors in a timely and efficient manner, and realizing cross-domain interaction of descriptors from hardware area 1 to the peer area.

[0071] In some embodiments, the receiving end that receives the first descriptor pushes the write pointer to the local mirror register of the sending end through the system bus, forming a write pointer mirror in the mirror register of the sending end. When the sending end has a write pointer mirror stored in its local mirror register, it can read the first descriptor from the descriptor storage area based on the position indicated by the written write pointer mirror, thereby realizing cross-domain interaction of the first descriptor from the receiving end to the sending end. The sending end can then read the data to be transmitted from the memory area based on the first descriptor.

[0072] In the above embodiments, the data transmission process is optimized by decoupling the write pointer from the descriptor and pushing it asynchronously. After updating its local write pointer, the receiving end only needs to push the pointer value (a small amount of data) to the sending end through the system bus, without immediately transmitting the entire descriptor or data synchronously. This reduces the instantaneous occupancy of bus bandwidth and reduces the access latency and conflicts caused by the sending end polling the descriptor storage area, thereby improving the overall system efficiency and the real-time performance of data transmission.

[0073] Figure 4 This is a flowchart illustrating the data transmission method proposed in an embodiment of this disclosure, based on... Figure 3 The embodiment shown, Figure 4 Further explanation is needed, such as Figure 4 As shown, the method includes the following steps: Step 401: In response to the number of descriptors already stored in the buffer area reaching the receive buffer threshold, determine the number of free space in the descriptor storage area.

[0074] In some embodiments, the receive buffer threshold may be a pre-set threshold for the receiver to determine whether to submit a descriptor to the sender. Its specific value may be customized according to the scenario or requirements, and this disclosure does not limit it.

[0075] In some embodiments, the number of descriptors stored in the buffer region can be the number of descriptors cached in the buffer region.

[0076] For example, such as Figure 12B The diagram illustrates the descriptor delivery and write pointer push processing steps. Whenever the hardware module writes a descriptor to the descriptor receiving device and puts it into the receive buffer, the number of descriptors in the receive buffer gradually increases. First, it is determined whether the number of descriptors in the receive buffer has reached the receive buffer threshold. If the receive buffer threshold has not been reached, the process continues to wait. Otherwise, the number of descriptors that can be delivered this time is calculated based on the relevant information of the descriptor FIFO in the receive control register.

[0077] In some embodiments, when the number of descriptors already cached in the receiver's buffer reaches a receive buffer threshold, it is determined that a descriptor needs to be delivered to the sender, and thus the number of free space in the descriptor storage area needs to be determined. In other words, when a descriptor needs to be delivered to the sender, it is first necessary to determine whether the shared descriptor storage area between the two ends can be used to write descriptors, so as to provide a location for the delivered descriptor.

[0078] In some embodiments, determining the number of free spaces in the descriptor storage area includes: determining the free locations in the descriptor storage area based on a local storage read pointer mirror, wherein the read pointer mirror is formed by the local mirror register of the receiver based on the read pointer pushed by the sender; and determining the number of free locations as the number of free spaces.

[0079] In some embodiments, the receiving end locally maintains a mirror register for receiving the read pointer pushed by the sending end. It is understood that both the receiving end and the sending end locally maintain mirror registers on opposite sides. The mirror registers on the receiving end are used to receive the read pointer pushed by the sending end to form a read pointer mirror, and the mirror registers on the sending end are used to receive the write pointer pushed by the sending end to form a write pointer mirror.

[0080] In some embodiments, the receiving end can determine the positions in the descriptor storage area that have been written to based on the read pointer mirror in the local mirror register, thereby determining the empty positions in the descriptor storage area that have not been written to, and determining the total number of empty positions as the number of empty positions.

[0081] For example, such as Figure 12A The diagram shown illustrates that, due to the use of pointer mirroring management, there is no need to obtain the latest read pointer from the other end across the bus. The read pointer in the local receive control register can be used directly for judgment, resulting in a significant improvement in processing speed.

[0082] In the above embodiments, by maintaining and utilizing the "read pointer mirror" from the sending end, the receiving end can accurately and in real-time perceive free locations in the descriptor storage area. This ensures that when the receiving end writes a new descriptor, it will not overwrite an old descriptor that has not been read, realizing lock-free collaboration between the sending and receiving ends, preventing data overwriting or conflicts, and improving the security and reliability of shared storage area management.

[0083] Step 402: Determine the number of pushes based on the number of stored descriptors and the number of free descriptors.

[0084] In some embodiments, the push quantity can be the number of descriptors that the receiver needs to push to the sender after the number of stored descriptors reaches the receive buffer threshold. In other words, the push quantity can also be the number of descriptors that the receiver can write to the descriptor storage area after the number of stored descriptors reaches the receive buffer threshold.

[0085] In some embodiments, the number of pushes is determined based on the number of stored descriptors and the number of free descriptors, or by averaging the two.

[0086] In some embodiments, the number of pushes is determined based on the number of stored descriptors and the number of free descriptors, which may be determined by the median value between the two.

[0087] In some embodiments, the number of pushes is determined based on the number of stored descriptors and the number of free descriptors, which may be determined by a weighted average of the two.

[0088] In some embodiments, the number of pushes is determined based on the number of stored descriptors and the number of free descriptors, and the smaller value between the two can be used as the number of pushes.

[0089] For example, such as Figure 12B The diagram shows the descriptor submission and write pointer push processing steps. The number of descriptors that can be submitted this time is min{the number of descriptors in the receive buffer and the number of descriptors that can be filled in the descriptor FIFO}, which is the smaller of the two.

[0090] In some embodiments, the number of pushes can be at least one.

[0091] Step 403: Determine the descriptor of the number of pushes in the buffer area as the first descriptor.

[0092] In some embodiments, determining the descriptor of the number of pushes in the buffer area as the first descriptor may involve determining at least one descriptor as the first descriptor among multiple descriptors cached in the buffer area.

[0093] In some embodiments, the number of pushes determined at different times in response to the number of descriptors stored in the buffer area reaching the receive buffer threshold can be the same or different, and the number of descriptors pushed to the sender each time can be the same or different, which is not limited in this disclosure.

[0094] In some embodiments, if the number of pushes determined in step 402 is zero, the receiving end does not push descriptors to the sending end.

[0095] In the above embodiments, by introducing "receive buffer threshold" and "number of free spaces" as judgment conditions, batch and intelligent push of descriptors is realized. It avoids the frequent bus interaction and performance overhead caused by the receiver triggering a push operation every time a descriptor is generated, and aggregates scattered push requests, improving bus utilization efficiency and batch processing capability of push operations.

[0096] Figure 5 A flowchart illustrating another data transmission method proposed in this disclosure embodiment is based on... Figure 3-4 The illustrated embodiments, such as 5 pairs Figure 3 Step 301 in the document will be further explained, such as... Figure 5As shown, it includes the following steps: Step 501: Write the first descriptor to an empty location via the system bus to determine the location identifier of the first descriptor.

[0097] In some embodiments, after determining the number of first descriptors to be pushed, the receiving end writes the first descriptors stored in the buffer area into the empty space in the descriptor storage area via the system bus. Each time a first descriptor is written, the position identifier of the first descriptor in the descriptor storage area is determined.

[0098] In some embodiments, the first descriptor of the push quantity is sequentially written into the empty positions in the descriptor storage area. Since the push quantity is less than or equal to the number of empty positions, it can be guaranteed that the first descriptor written by the receiving end can be written into the descriptor storage area without the descriptor storage area being full and unable to be written.

[0099] In some embodiments, when each first descriptor is written to the descriptor storage area, its location identifier is determined. This identifier can be calculated using the base address of the descriptor storage area and the write pointer. The write pointer can be understood as an offset based on the base address. Adding this offset to the base address yields the location identifier of the first descriptor.

[0100] For example, such as Figure 12B The schematic diagram shows that the descriptor receiving device writes a batch of descriptors into the corresponding positions of the descriptor FIFO through the first bus. The corresponding positions of the descriptor FIFO can be calculated using the base address and the write pointer.

[0101] Step 502: Based on the location identifier, determine the first write pointer corresponding to the first descriptor.

[0102] In some embodiments, the first write pointer corresponding to the first descriptor can be obtained based on the position identifier of the first descriptor in the descriptor storage area.

[0103] In some embodiments, the first write pointer points to the first descriptor identified by that location in the descriptor storage area.

[0104] Step 503: Store the first write pointer in the local register.

[0105] In some embodiments, after writing the first descriptor is completed, the first write pointer corresponding to the first descriptor is determined, thereby updating the local register, that is, storing the first write pointer in the local register for use in pushing the first write pointer to the mirror register of the other end.

[0106] In some embodiments, the local register of the receiving end is used to store locally generated write pointers, read pointers, and related information of the descriptor storage area, such as the base address and total depth of the descriptor storage area, and the local register can also be configured with a receive buffer threshold.

[0107] For example, such as Figure 12A The schematic diagram shows that the receive control register in the descriptor receiving device is used to configure relevant parameters of the descriptor FIFO, including the base address and total depth of the memory space where the descriptor FIFO is located, the current read / write pointer, and the receive buffer area.

[0108] For example, such as Figure 12B The diagram shows that after the descriptor is written, the write pointer in the local receive control register is updated.

[0109] In the above embodiments, the operation sequence of the receiving end is clearly defined: first, the descriptor content is written, and then the write pointer is updated and stored. This "data first, pointer later" process ensures that the position pointed to by the write pointer must have a valid and complete descriptor. This eliminates the risk of inconsistency between the pointer and the data state, providing the sending end with a reliable basis for data access.

[0110] Figure 6 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure, based on... Figure 3-5 The illustrated embodiments, such as 6 pairs Figure 3 Step 302 in the document will be further explained, such as... Figure 6 As shown, it includes the following steps: Step 601: Push the first write pointer in the local register to the local mirror register of the sending end through the system bus to form the first write pointer mirror of the first write pointer.

[0111] In some embodiments, after the receiving end completes updating the write pointer in its local register, it pushes the updated first write pointer to the local mirror register of the sending end via the system bus, and a first write pointer mirror of the first write pointer is formed in the local mirror register of the sending end.

[0112] For example, such as Figure 12A The diagram shows that after the receive controller completes the write operation, it updates the write pointer in the local receive control register and pushes the latest write pointer to the write pointer in the local register of the peer descriptor transmit component via the bus.

[0113] For example, such as Figure 12BThe diagram shows that the descriptor receiving device pushes the latest write pointer to the write pointer register in the local register of the peer through the first bus, so that the peer can read a valid descriptor from the descriptor FIFO according to its own latest local write pointer.

[0114] In some embodiments, if there is a new write pointer image in the local image register, the sending end can obtain the first descriptor corresponding to the first write pointer image from the descriptor storage area based on the first write pointer image, and then read the data to be transmitted corresponding to the first descriptor from the memory area based on the first descriptor.

[0115] In the above embodiments, by explicitly pushing the first write pointer through the system bus, it is ensured that the sender obtains the pointer mirror of the first write pointer in the mirror register, avoiding the need for the sender to cross the bus to the receiver to obtain the write pointer, thus improving the descriptor interaction speed, reducing the bus load, and enhancing the accuracy of synchronization.

[0116] Figure 7 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure, based on... Figure 3-6 The illustrated embodiment, as shown in example 7, will be further described, as follows: Figure 7 As shown, it includes the following steps: Step 701: In response to the descriptor write instruction, the first descriptor corresponding to the descriptor write instruction is stored in the buffer area.

[0117] In some embodiments, the descriptor write instruction may be an external instruction to write a descriptor to the receiving end, the instruction including a first descriptor to be written.

[0118] In some embodiments, after receiving a descriptor write instruction, the receiving end writes the first descriptor into the buffer area.

[0119] Step 702: After writing the first descriptor into the descriptor storage area, manage the storage location corresponding to the first descriptor in the buffer area based on the preset caching strategy.

[0120] In some embodiments, after the first descriptor in the buffer area is written to the descriptor storage area, that is, the descriptor pushed locally by the receiving end has been written to the shared storage area, the location in the buffer area used to store the first descriptor can be managed.

[0121] In some embodiments, the preset caching strategy can be a pre-set rule for managing the buffer area, which can be customized according to the scenario or requirements.

[0122] In some embodiments, the preset caching strategy may be an immediate release strategy, that is, the storage location of the first descriptor in the buffer area is released immediately after the first descriptor is written to the descriptor storage area.

[0123] In some embodiments, the preset caching strategy can be an acknowledgment-release strategy, that is, releasing the storage location of the first descriptor in the buffer area after receiving the sender's acknowledgment of consumption of the first descriptor. Here, consumption acknowledgment may mean that the sender has already retrieved the first descriptor from the descriptor storage area based on the first write pointer.

[0124] In some embodiments, the preset caching strategy can be a reuse strategy, that is, organizing the buffer area into a circular buffer area and reusing the storage location in a circular manner.

[0125] In the above embodiments, by setting up a local buffer area at the receiving end and managing it using a preset caching strategy, flexible space is provided for descriptor generation and submission. This decouples the descriptor generation rate from the write rate to the shared memory area, allowing the receiving end to continuously receive and cache pending transmission requests even when the system bus is busy or the sending end experiences processing delays, thereby improving system throughput and resilience against sudden traffic surges.

[0126] In summary, the data transmission method implemented by the receiver proposed in this disclosure constructs an efficient, decoupled, and low-overhead receiver-driven data transmission mechanism. It transforms high-bandwidth data / descriptor transmission into low-bandwidth pointer synchronization, significantly reducing system bus contention and access latency through strategies such as batch push, buffer management, and mirrored pointer coordination. It empowers the receiver to actively manage the data transmission process, while ensuring efficient and secure collaboration with the sender through shared storage and lock-free pointer communication, ultimately improving the overall performance and scalability of the data transmission system.

[0127] Figure 8 This is a flowchart illustrating a data transmission method proposed in an embodiment of this disclosure, executed by the sending end, such as... Figure 8 As shown, it includes the following steps: Step 801: Based on the write pointer mirror in the local mirror register, store the first descriptor corresponding to the write pointer mirror in the descriptor storage area to the local buffer area.

[0128] In some embodiments, the write pointer mirror is formed by the sender based on the write pointer pushed by the receiver.

[0129] In some embodiments, the sending end may be a hardware module or software module that receives a write pointer pushed by the receiving end and sends a descriptor to the outside.

[0130] In some embodiments, the local mirror register is a register maintained locally by the sender to store the write pointer mirror pushed by the receiver.

[0131] In some embodiments, the sending end can determine the write pointer mirror stored therein based on the local mirror register, and can determine the first descriptor stored in the descriptor storage area based on the write pointer mirror, and read and store the first descriptor into the local buffer area.

[0132] In some embodiments, the first descriptor in the descriptor storage area is written by the receiving end; for details on the writing method, please refer to [link / reference needed]. Figures 3 to 7 Specific implementation methods in any of the embodiments.

[0133] In some embodiments, when a new write pointer is mirrored in the mirror register, the sending end can read the corresponding first descriptor from the descriptor storage area into the buffer area.

[0134] Step 802: Based on the first descriptor in the buffer area, update the read pointer in the local register and push the read pointer to the local mirror register of the receiving end.

[0135] In some embodiments, the sending end can form a read pointer corresponding to the first descriptor based on the first descriptor in the local buffer area and update it in the local register.

[0136] In some embodiments, the read pointer is used to push the read pointer to the local mirror register of the receiving end when an external hardware module requests it.

[0137] In some embodiments, the local mirror register of the receiver is a mirror of the read pointer maintained locally by the receiver for storing the read pointer pushed by the sender, thereby avoiding the need for the receiver to cross the bus to the sender to obtain the read pointer.

[0138] For example, such as Figure 12C The schematic diagram of the descriptor transmission device shown includes a transmission control register for configuring relevant parameters of the descriptor FIFO, including the base address and total depth of the memory space where the descriptor FIFO resides, the current read / write pointer, the pre-read pointer, and the transmission buffer threshold and read pointer push threshold. The transmission controller pushes the latest read pointer via the bus to the read pointer in the local register of the descriptor receiving component at the other end. The transmission buffer caches pre-read descriptors for easy allocation by the hardware module. The descriptor FIFO, stored in memory, is used to store descriptors and act as an intermediary. The descriptor receiving component generates the descriptors within the descriptor FIFO; this can be either software-based or hardware-based, and its core function lies in the maintenance of the local register.

[0139] In the above embodiments, the sending end obtains the descriptor based on the write pointer image pushed by the receiving end, realizing an "on-demand, event-driven" pull mode instead of active polling. This reduces the number of blind accesses to the descriptor storage area by the sending end, reducing bus load and power consumption. At the same time, the sending end actively pushes the read pointer after reading data, forming a complete feedback loop, enabling the receiving end to reclaim storage resources in a timely manner.

[0140] Figure 9 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure, based on... Figure 8 The embodiment shown, Figure 9 right Figure 8 Step 801 in the text will be further explained, such as Figure 9 As shown, it includes the following steps: Step 901: In response to the fact that the number of descriptors in the buffer area has not reached the send buffer threshold, determine the number of reads of the first descriptor.

[0141] In some embodiments, the sending end needs to determine the relationship between the number of descriptors in the buffer area and the sending buffer threshold, and then, when the sending buffer threshold is reached, start the descriptor pre-reading process, which first determines the number of descriptors to be read in the first pre-read.

[0142] In some embodiments, the sending end needs to pre-read the descriptor to the local buffer area so that when an external module requests a descriptor, the corresponding read pointer can be pushed to the receiving end in a timely manner, thereby speeding up the efficiency of external modules requesting descriptors.

[0143] In some embodiments, the transmit buffer threshold may be a pre-set judgment threshold for the sender to pre-read the descriptor, which may be customized according to the scenario or requirements, and this disclosure does not limit it.

[0144] In some embodiments, determining the number of reads for the first descriptor includes: determining the number of descriptors that can be stored in the buffer area; determining the number of unread descriptors in the descriptor storage area; and determining the number of reads based on the number of storeable descriptors and the number of unread descriptors.

[0145] In some embodiments, the number of descriptors that can be stored in the buffer area can be the number of positions in the sender's buffer area that have not yet been written with descriptors.

[0146] In some embodiments, the number of unread descriptors in the descriptor storage area may be the number of descriptors that the receiver has written to the descriptor storage area but has not yet been read by the sender, and which are still stored in the descriptor storage area.

[0147] In some embodiments, the number of reads is determined based on the number of storable descriptors and the number of unread descriptors, and the intermediate value between the two can be used as the number of reads.

[0148] In some embodiments, the number of reads is determined based on the number of storeable descriptors and the number of unread descriptors, or by averaging the two.

[0149] In some embodiments, the number of reads is determined based on the number of storeable descriptors and the number of unread descriptors, and the smaller of the two values ​​can be used as the number of reads.

[0150] For example, such as Figure 12D The diagram illustrates the descriptor pre-reading process of the descriptor transmitting device. 1. Determine if the number of descriptors in the transmit buffer has reached the transmit buffer threshold. If it has, continue waiting, i.e., do not perform descriptor pre-reading. Otherwise, calculate the number of descriptors that can be pre-read this time based on the relevant information of the descriptor FIFO in the transmit control register: Number of descriptors that can be pre-read this time = min{number of descriptors that can be filled in the transmit buffer, number of descriptors that have not been pre-read in the descriptor FIFO}, i.e., take the smaller value of the two.

[0151] In the above embodiments, the addition of a transmit buffer threshold judgment allows for batch pre-reading of descriptors, thereby improving bus utilization.

[0152] In the above embodiments, when determining the number of reads, the sending end comprehensively considers both the capacity of its local buffer (the number that can be stored) and the number of descriptors actually available in the shared storage area (the number that has not been read). This dual-judgment mechanism achieves dynamic optimization of the number of reads, making full use of the local buffer space for pre-reading while avoiding excessive reading at one time, which would cause waste of local resources or processing delays, thus achieving efficient resource balance.

[0153] Step 902: In the local mirror register, determine the number of write pointer mirrors to be read.

[0154] In some embodiments, after determining the number of reads, that number of descriptors can be read, i.e., determining that number of write pointer mirrors in the locally maintained mirror register.

[0155] In some embodiments, since the location of the descriptor in the descriptor storage area is stored in the write pointer mirror in the mirror register, the sending end needs to first determine the number of write pointer mirrors to be read from the mirror register, and then determine the corresponding descriptor.

[0156] Step 903: Based on the write pointer mirroring, determine the location identifier of the first descriptor in the descriptor storage area.

[0157] In some embodiments, the write pointer mirror corresponds to the write pointer generated by the receiving end when writing a descriptor to the descriptor storage area. The write pointer stores the specific location of the first descriptor in the descriptor storage area.

[0158] In some embodiments, the location identifier of the first descriptor that needs to be pre-read in the descriptor storage area can be determined based on the write pointer mirroring.

[0159] Step 904: Store the first descriptor corresponding to the location identifier in the descriptor storage area to the buffer area.

[0160] In some embodiments, the sender can pre-read the first descriptor stored in the descriptor storage area based on the location identifier, and store the first descriptor in the buffer area.

[0161] For example, such as Figure 12C The schematic diagram shows that the descriptor sending device includes a sending controller, which controls the descriptor sending device to pre-read descriptors from the descriptor FIFO to the local sending buffer via a second bus, update the read pointer in the local sending control register after the pre-read is completed, and push the latest read pointer to the read pointer in the local register of the descriptor receiving component at the other end via the bus; the sending buffer is used to cache the pre-read descriptors for easy hardware module request.

[0162] For example, such as Figure 12D The schematic diagram shows that the descriptors in batches are pre-read into the transmit buffer from the corresponding position of the descriptor FIFO via the second bus.

[0163] In the above embodiments, by pre-reading a sufficient number of descriptors from the memory space into the send buffer, the efficiency of the hardware module in requesting descriptors can be accelerated to some extent.

[0164] In the above embodiments, batch pre-reading and caching of descriptors are achieved by using a "send buffer threshold" and dynamically determining the "read quantity". This allows the sender to pull multiple descriptors to be processed from the shared area to the local buffer at once, avoiding the performance bottleneck caused by accessing the remote shared storage once for each data packet, and improving the continuity of data acquisition and the efficiency of local processing.

[0165] Figure 10 This is a flowchart illustrating another data transmission method proposed in an embodiment of this disclosure, based on... Figure 8-9 The embodiment shown, Figure 10 right Figure 8 Step 802 in the text will be further explained, such as Figure 10 As shown, it includes the following steps: Step 1001: Based on the first descriptor in the buffer area, store the prefetch pointer corresponding to the first descriptor into the local register.

[0166] In some embodiments, a first descriptor for pre-reading is stored in the buffer area. Based on the first descriptor, a pre-read pointer corresponding to the first descriptor is generated. The pre-read pointer is a pointer that the sender is waiting to be pushed. In other words, after the pre-read pointer is generated, it has not yet been pushed to the receiver. Only when there is a request from an external hardware module or software module will the corresponding pre-read pointer be used as a read pointer to be pushed to the receiver.

[0167] In some embodiments, the prefetch pointer generated based on the first descriptor is stored in the local register of the sender. The local register stores prefetch pointers to be pushed, and each prefetch pointer corresponds to the first descriptor in the buffer area.

[0168] In some embodiments, the local register of the sending end may store relevant parameters of the descriptor storage area, including the base address and total depth; as well as the current read / write pointer, pre-read pointer, send buffer threshold, read pointer push threshold, etc.

[0169] For example, such as Figure 12C The schematic diagram shows that the descriptor sending component includes a sending control register, which is used to configure relevant parameters of the descriptor FIFO, including the base address and total depth of the memory space where the descriptor FIFO is located, the current read / write pointer, the pre-read pointer, as well as the sending buffer threshold and the read pointer push threshold.

[0170] Step 1002: In response to the descriptor call instruction, the prefetch pointer corresponding to the descriptor call instruction in the local register is determined as the read pointer.

[0171] In some embodiments, the descriptor invocation instruction may be an instruction from an external hardware module to request a descriptor from the sending end.

[0172] In some embodiments, after receiving the descriptor call instruction, the sending end determines the pre-read pointer in its local register and uses the pre-read pointer as the read pointer to be pushed to the receiving end.

[0173] For example, such as Figure 12C As shown in the diagram, after the descriptor sending component completes the descriptor pre-read, it updates the pre-read pointer in the local sending control register; whenever the hardware module requests a descriptor from the descriptor sending device, the read pointer in the local sending control register is continuously updated.

[0174] In some embodiments, in response to a descriptor call instruction, determining the prefetch pointer corresponding to the descriptor call instruction in the local register as a read pointer includes: in response to the descriptor call instruction, determining a second descriptor corresponding to the descriptor call instruction in a buffer area; determining storage information based on the second descriptor; reading the data to be transmitted corresponding to the second descriptor based on the storage information, and determining the prefetch pointer corresponding to the second descriptor as a read pointer.

[0175] In some embodiments, after receiving a descriptor invocation instruction, the sending end determines a second descriptor from at least one first descriptor stored in the buffer area for pre-reading, and the second descriptor is the descriptor for the external request invocation.

[0176] In some embodiments, after determining the second descriptor, the storage information of the data to be transmitted corresponding to the second descriptor can be determined based on the second descriptor. Then, the data to be transmitted is read from memory based on the storage information, and the pre-read pointer corresponding to the second descriptor is determined as the read pointer. This enables timely determination of the read pointer and timely completion of the push in the event of an external call, further improving the efficiency of descriptor transmission.

[0177] In the above embodiments, the specific data processing chain at the sending end is clearly defined: selecting a descriptor from the local buffer according to the instruction -> retrieving data based on the descriptor information -> simultaneously confirming that the descriptor processing is complete (updating the read pointer). This process ensures the atomicity and consistency of data acquisition and process advancement; that is, only after the data is successfully read will the corresponding storage space be marked as reclaimable, preventing data loss or premature space release.

[0178] Step 1003: In response to the number of read pointers reaching the push threshold, the read pointers are pushed to the local mirror register of the receiving end via the system bus to form a read pointer mirror.

[0179] In some embodiments, the read pointer mirror is used by the receiving end to determine the available space in the descriptor storage area.

[0180] In some embodiments, the push threshold can be a threshold pre-configured locally on the sending end to determine whether to push the read pointer. Its specific value can be customized according to the scenario or requirements.

[0181] In some embodiments, after a pre-read pointer is identified as a read pointer, it is not pushed immediately. Instead, a push threshold is added. That is, only after the number of read pointers identified reaches a preset push threshold will these read pointers be pushed to the receiving end through the system bus, thereby avoiding frequent pushes of read pointers and reducing bus load.

[0182] In some embodiments, the read pointer of the sending end is continuously updated, that is, the pre-read pointer is continuously updated to the read pointer. When the number of read pointers reaches the push threshold, the latest read pointer is pushed to the receiving end. The receiving end maintains a mirror register of the sending end locally, which is used to receive the read pointer pushed by the sending end and form a mirror of the read pointer.

[0183] In some embodiments, the read pointer is located in the mirror register on the receiver's local side, and is used by the receiver to determine the space consumed in the descriptor storage area so as to write the descriptors in the receiver's buffer area into the descriptor storage area in a timely manner.

[0184] In the above embodiment, the generation and push of the "read pointer" are separated, and a "pre-read pointer" is introduced as an intermediate state. The sending end generates the pre-read pointer when storing the descriptor in the local buffer, and only confirms it as the formal read pointer and pushes it in batches after the descriptor is actually used (called). This fine-grained management of the timing of completion confirmation, aggregating the completion confirmation of multiple data packets into a single pointer push, greatly reducing the communication overhead used for flow control and improving confirmation efficiency.

[0185] In summary, the data transmission method proposed in this disclosure defines an intelligent, batch-processing, and low-interference data processing mechanism for the sender. This frees the sender from frequent remote storage accesses and fine-grained completion acknowledgments. Through event-driven batch pre-reading, local buffering, and aggregated read pointer pushing, the sender can process data streams more efficiently and smoothly. This not only reduces the access pressure on the shared bus and storage areas but also optimizes the sender's own processing pipeline. Combined with the receiver method, this forms a highly efficient collaborative system.

[0186] Figure 11 This is a flowchart illustrating a data transmission method proposed in an embodiment of this disclosure, executed by a data transmission system, such as... Figure 11 As shown, it includes the following steps: Step 1101: The receiving end writes the first descriptor in the buffer area into the descriptor storage area and updates the write pointer in the local register.

[0187] In some embodiments, the write pointer indicates the location of the first descriptor in the descriptor storage area, and the first descriptor indicates the storage information of the data to be transferred.

[0188] In some embodiments, optional implementations of step 1101 can be found in [reference needed]. Figure 3 Step 301 Figure 4 , Figure 5 The specific implementation details of the embodiments shown will not be repeated here.

[0189] Step 1102: Push the write pointer to the local mirror register of the sending end via the system bus to form a write pointer mirror in the mirror register.

[0190] In some embodiments, write pointer mirroring is used by the sending end to read a first descriptor from the descriptor storage area to obtain the data to be transmitted.

[0191] In some embodiments, optional implementations of step 1102 can be found in [reference needed]. Figure 3 Step 302 Figure 6 , Figure 7 The specific implementation details of the embodiments shown will not be repeated here.

[0192] Step 1103: The sending end stores the first descriptor corresponding to the write pointer image in the descriptor storage area to the local buffer area based on the write pointer image in the local image register.

[0193] In some embodiments, optional implementations of step 1103 may be found in [reference needed]. Figure 8 Step 801 Figure 9 The specific implementation details of the embodiments shown will not be repeated here.

[0194] Step 1104: The sending end updates the read pointer in its local register based on the first descriptor in the sending end's buffer area, and pushes the read pointer to the receiving end's local mirror register.

[0195] In some embodiments, optional implementations of step 1104 may refer to [reference needed]. Figure 8 Step 802 Figure 10 The specific implementation details of the embodiments shown will not be repeated here.

[0196] In the above embodiments, a closed-loop bidirectional pointer synchronization system is defined. This achieves the separation and cooperation of data flow (indirectly indicated through descriptors) and control flow (synchronized through pointer mirroring). This system approach ensures the orderliness, reliability, and efficiency of data transmission. The combination of push-driven operation by the receiving end and pull-driven feedback by the sending end forms an efficient producer-consumer model, minimizing synchronization overhead on the core path.

[0197] The following is a specific implementation of a data transmission method provided in this disclosure: Figure 12AThe diagram illustrates a device for descriptor reception, comprising the following components: 1. A receive control register, used to configure parameters of the descriptor FIFO, including the base address and total depth of the memory space where the descriptor FIFO resides, the current read / write pointers, and the receive buffer threshold; 2. A receive controller, used to control the descriptor receiving device to write descriptors from the receive buffer into the descriptor FIFO via a first bus, update the write pointer in the local receive control register after writing, and push the latest write pointer to the write pointer in the local register of the descriptor sending component at the other end via the bus; 3. A receive buffer, used to cache descriptors written by the hardware module; 4. A descriptor FIFO, stored in the memory area, used to store descriptors and for relaying; 5. A descriptor sending component, used to acquire descriptors from the descriptor FIFO, regardless of whether it is software or hardware-based, its core lies in the maintenance of the local register.

[0198] Specifically, the configuration of the receive control register and the local registers in the peer descriptor sending component must point to the same descriptor FIFO, and a pointer mirroring management method is used. That is, the descriptor receiving device is responsible for maintaining the write pointers of both parties (note that maintaining the pointers of both parties means actively updating the peer register through the bus after updating its own local register), and the descriptor sending component is responsible for maintaining the read pointers of both parties. This allows both ends to directly obtain the read and write pointer information of the shared descriptor FIFO from their local registers, thereby enabling timely and efficient delivery / retrieval of descriptors and realizing cross-domain interaction of descriptors from hardware area 1 to the peer area. For the hardware module, its interface with the descriptor receiving device is a simple and universal FIFO write port. By using this scheme to receive descriptors, the hardware module does not need to worry about complex bus operations, greatly simplifying its control logic.

[0199] Each time the hardware module writes a descriptor to the receive buffer of the descriptor receiving device, the number of descriptors in the receive buffer gradually increases. The descriptor delivery and write pointer push processing steps of the descriptor receiving device are as follows: Figure 12B As shown, it includes the following steps: 1. Hardware module write descriptor; 2. The number of receive buffer descriptors has increased; 3. Determine if the number of descriptors in the receive buffer has reached the receive buffer threshold; if it has not reached the receive buffer threshold, continue waiting; otherwise, proceed to step 4. (1) Add a threshold judgment for receiving buffer to enable batch delivery of descriptors and improve bus utilization; 4. Calculate the number of submittable descriptors; Based on the relevant information in the FIFO descriptor in the receive control register, calculate the number of descriptors that can be delivered this time; (1) The number of descriptors that can be delivered this time = min{the number of descriptors in the receive buffer, the number of descriptors that can be filled in the descriptor FIFO}, that is, the smaller of the two values; (2) Due to the use of pointer mirroring management, there is no need to obtain the latest read pointer from the other end across the bus. The read pointer in the local receive control register can be used directly for judgment, which significantly improves the processing speed. 5. Deposit the descriptor to the descriptor FIFO via the bus; The descriptors are written in batches to the corresponding positions in the descriptor FIFO via the first bus. (1) The corresponding position of the FIFO descriptor can be calculated using the base address and the write pointer; 6. Update the local receive control register – write pointer; After the descriptor writing is complete, update the write pointer in the local receive control register; 7. Push the write pointer via the bus; The latest write pointer is pushed to the write pointer register in the local register of the peer through the first bus, so that the peer can read the valid descriptor from the descriptor FIFO according to its own latest local write pointer; (1) The peer does not need to cross the bus to receive the latest write pointer from the descriptor, which significantly improves the processing speed; After the write pointer update is completed, the current descriptor submission process ends, and we return to step 1.

[0200] akin, Figure 12C The diagram illustrates a device for descriptor transmission, comprising the following components: 1. A transmission control register, used to configure parameters of the descriptor FIFO, including the base address and total depth of the memory space where the descriptor FIFO resides, the current read / write pointer, the pre-read pointer, and the transmission buffer threshold and read pointer push threshold; 2. A transmission controller, used to control the descriptor transmission device, pre-reading descriptors from the descriptor FIFO to the local transmission buffer via a first bus, updating the read pointer in the local transmission control register after pre-reading, and pushing the latest read pointer to the read pointer in the local register of the descriptor receiving component at the other end via the bus; 3. A transmission buffer, used to cache pre-read descriptors for easy hardware module allocation; 4. A descriptor FIFO, stored in the memory area, used to store descriptors and for relaying; 5. A descriptor receiving component, used to generate descriptors within the descriptor FIFO, regardless of whether it is software or hardware-based, its core lies in the maintenance of the local register.

[0201] Specifically, the configuration of the transmit control register and the local register in the peer descriptor receiving component needs to point to the same descriptor FIFO, and the pointer mirroring management is adopted. That is, the descriptor transmitting device is responsible for maintaining the write pointers of both parties, and the descriptor receiving component is responsible for maintaining the read pointers of both parties. This allows both ends to directly obtain the read and write pointer information of the shared descriptor FIFO from the local register, thereby enabling timely and efficient pre-reading / writing of the descriptor and realizing cross-domain interaction of the descriptor from the peer region to hardware region 1. For the hardware module, the interface with the descriptor sending device is a simple and universal FIFO read port. By using this scheme to send descriptors, the hardware module does not need to worry about complex bus operations, which greatly simplifies its control logic.

[0202] The descriptor sending device pre-reads descriptors into its local send buffer and provides this buffer to the hardware module for requesting descriptors, such as... Figure 12D The diagram shown is a schematic of the descriptor pre-reading process of the descriptor sending device. The following describes some parts of this process, including the pre-reading process and the push process.

[0203] The pre-reading process includes: 1. Hardware module requesting descriptors leads to a reduction in the number of transmit buffer descriptors; 2. Determine if the number of descriptors in the send buffer has reached the send buffer threshold; if not, proceed to step 3; otherwise, continue waiting. (1) Add a judgment on the transmit buffer threshold, which can pre-read descriptors in batches and improve bus utilization; (2) By pre-reading a sufficient number of descriptors from the memory space into the send buffer in advance, the efficiency of hardware modules in requesting descriptors can be accelerated to a certain extent. 3. Calculate the number of pre-readable descriptors; Based on the relevant information in the FIFO descriptor in the transmit control register, calculate the number of descriptors that can be read in this operation. (1) The number of descriptors that can be read in this time = min{the number of descriptors that can be filled in the transmit buffer, the number of descriptors that have not been read in the descriptor FIFO}, that is, the smaller of the two values; 4. Prefetch descriptors to transmit buffers via the bus; The descriptors in batches are pre-read into the transmit buffer from the corresponding positions in the descriptor FIFO via the second bus. (1) The corresponding position of the FIFO descriptor can be calculated using the base address and the prefetch pointer; 5. Update the local transmit control register – read-ahead pointer; After completing the descriptor prefetch, update the prefetch pointer in the local transmit control register; Whenever a hardware module requests a descriptor from the descriptor sending device, the read pointer in the local send control register is continuously updated. The read pointer push process is as follows: 1. The hardware module requests a descriptor and updates the local transmit control register—reading the pointer; 2. Determine if the change in the read pointer has reached the read pointer push threshold; if it has not reached the read pointer push threshold, continue waiting; otherwise, proceed to step 3. (1) Adding a read pointer push threshold can avoid frequent read pointer pushes and reduce bus load. (Note that this is different from the write pointer push bound to descriptor delivery in the descriptor receiving device. This is because, for the descriptor receiving device, descriptors are delivered in batches and the write pointer is updated once after batch delivery, while for the descriptor sending device, descriptors are read one by one and the read pointer is continuously updated by incrementing one.) 3. Push the read pointer via the bus; The latest read pointer is pushed to the peer descriptor receiving component via the first bus, so that the peer can continue to write valid descriptors to the range where the descriptor has been consumed. In addition, by connecting these two devices, a software-friendly cross-domain descriptor interaction structure can be realized. After the configuration of the control registers at both ends is completed during the initialization phase, no software intervention is required during operation. The hardware devices at both ends automatically complete the continuous transfer of descriptors from hardware region 1 to hardware region 2 through the mirror pointer management mechanism. Through this structure, software overhead can be effectively reduced and the cross-domain descriptor interaction rate can be improved during operation.

[0204] In summary, the beneficial effects of this embodiment are as follows: 1. By adopting pointer mirroring management, both ends can directly obtain read / write pointer information from the local registers without having to cross the bus to obtain read / write pointers from the other end, which effectively speeds up the descriptor interaction rate; 2. After the initial configuration is completed, subsequent operations are performed by pushing pointers between the two hardware ends without the need for software intervention. This reduces complex hardware and software interaction operations, effectively reduces software overhead, and improves the cross-domain interaction rate of descriptors. 3. By connecting the receiving and transmitting devices, both ends share a descriptor FIFO. The descriptor does not need to be copied from the receiving end FIFO to the transmitting end FIFO in the memory space, which reduces the bus burden, effectively reduces hardware power consumption, and improves the cross-domain interaction rate of descriptors.

[0205] Figure 13 This is a schematic diagram of the structure of a receiving device 1300 according to an embodiment of this disclosure. Figure 13 As shown, the device includes: an access module 1301 and a transceiver module 1302. The access module is used to write the first descriptor in the buffer area into the descriptor storage area and update the write pointer in the local register. The write pointer indicates the position of the first descriptor in the descriptor storage area, and the first descriptor indicates the storage information of the data to be transferred. The transceiver module is used to push the write pointer to the local mirror register of the sender to form a write pointer mirror in the mirror register. The write pointer mirror is used by the sender to read the first descriptor from the descriptor storage area to obtain the data to be transmitted.

[0206] In some embodiments, the receiving device further includes a processing module, which is configured to: determine the number of free space in the descriptor storage area in response to the number of descriptors stored in the buffer area reaching a receiving buffer threshold; determine the number of pushes based on the number of stored descriptors and the number of free space; and determine the descriptors in the buffer area that are pushed as the first descriptors.

[0207] In some embodiments, the access module is configured to: write a first descriptor to an empty location via the system bus, determine the location identifier of the first descriptor; determine a first write pointer corresponding to the first descriptor based on the location identifier; and store the first write pointer in a local register.

[0208] In some embodiments, the transceiver module is configured to: push the first write pointer in the local register to the local mirror register of the transmitting end via the system bus to form a first write pointer mirror of the first write pointer.

[0209] In the above embodiments, the receiving device transforms high-bandwidth data / descriptor transmission into low-bandwidth pointer synchronization. Through strategies such as batch push, buffer management, and mirrored pointer coordination, it significantly reduces system bus contention and access latency. The receiving device's ability to actively manage the data transmission process, while ensuring efficient and secure collaboration with the transmitting device through shared storage and lock-free pointer communication, ultimately improves the overall performance and scalability of data transmission.

[0210] Figure 14 This is a schematic diagram of the structure of a transmitting device 1400 according to an embodiment of this disclosure. Figure 14 As shown, the device includes: an access module 1401 and a transceiver module 1402. The access module is used to store the first descriptor corresponding to the write pointer mirror in the descriptor storage area to the local buffer area based on the write pointer mirror in the local mirror register. The write pointer mirror is formed by the sender based on the write pointer pushed by the receiver. The transceiver module is used to update the read pointer in the local register based on the first descriptor in the buffer area, and push the read pointer to the local mirror register of the receiving end.

[0211] In some embodiments, the access module is configured to: determine the number of first descriptors to be read in response to the number of descriptors in the buffer area not reaching the send buffer threshold; determine the write pointer mirror of the number of reads in a local mirror register; determine the position identifier of the first descriptor in the descriptor storage area based on the write pointer mirror; and store the first descriptor corresponding to the position identifier in the descriptor storage area into the buffer area.

[0212] In some embodiments, the access module is configured to: store the pre-read pointer corresponding to the first descriptor in the buffer area into a local register based on the first descriptor in the buffer area; the transceiver module is configured to, in response to a descriptor call instruction, determine the pre-read pointer corresponding to the descriptor call instruction in the local register as a read pointer; and, in response to the number of read pointers reaching a push threshold, push the read pointers to the local mirror register of the receiving end through the system bus to form a read pointer mirror, the read pointer mirror being used by the receiving end to determine the free space in the descriptor storage area.

[0213] In some embodiments, the apparatus further includes a processing module, which is configured to: in response to a descriptor invocation instruction, determine a second descriptor corresponding to the descriptor invocation instruction in a buffer area; determine storage information based on the second descriptor; read the data to be transmitted corresponding to the second descriptor based on the storage information, and determine the pre-read pointer corresponding to the second descriptor as a read pointer.

[0214] In the above embodiments, the transmitting device can process data streams more efficiently and smoothly through event-driven batch prefetching, local buffering, and aggregated read pointer push. This not only reduces the access pressure on the shared bus and storage area but also optimizes its own processing pipeline, forming a highly efficient collaborative system together with the receiving device.

[0215] Figure 15 This is a schematic diagram of the structure of an electronic device 1500 for implementing the above-described data transmission method, according to an exemplary embodiment.

[0216] Reference Figure 15 The electronic device 1500 may include one or more of the following components: a processing component 1502, a memory 1504, a power supply component 1506, a multimedia component 1508, an audio component 1510, an input / output (I / O) interface 1512, a sensor component 1514, and a communication component 1516.

[0217] Processing component 1502 typically controls the overall operation of electronic device 1500, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1502 may include one or more processors 1520 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1502 may include one or more modules to facilitate interaction between processing component 1502 and other components. For example, processing component 1502 may include a multimedia module to facilitate interaction between multimedia component 1508 and processing component 1502.

[0218] Memory 1504 is configured to store various types of data to support the operation of electronic device 1500. Examples of this data include instructions for any application or method operating on electronic device 1500, contact data, phonebook data, messages, pictures, videos, etc. Memory 1504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0219] Power supply component 1506 provides power to various components of electronic device 1500. Power supply component 1506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1500.

[0220] Multimedia component 1508 includes a screen that provides an output interface between electronic device 1500 and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1508 includes a front-facing camera and / or a rear-facing camera. When electronic device 1500 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0221] Audio component 1510 is configured to output and / or input audio signals. For example, audio component 1510 includes a microphone (MIC) configured to receive external audio signals when electronic device 1500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1504 or transmitted via communication component 1516. In some embodiments, audio component 1510 also includes a speaker for outputting audio signals.

[0222] I / O interface 1512 provides an interface between processing component 1502 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0223] Sensor assembly 1514 includes one or more sensors for providing state assessments of various aspects of electronic device 1500. For example, sensor assembly 1514 may detect the on / off state of electronic device 1500, the relative positioning of components such as the display and keypad of electronic device 1500, changes in position of electronic device 1500 or a component of electronic device 1500, the presence or absence of user contact with electronic device 1500, the orientation or acceleration / deceleration of electronic device 1500, and temperature changes of electronic device 1500. Sensor assembly 1514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1514 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1514 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0224] Communication component 1516 is configured to facilitate wired or wireless communication between electronic device 1500 and other devices. Electronic device 1500 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 1516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1516 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0225] In an exemplary embodiment, the electronic device 1500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0226] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1504 including instructions, which can be executed by a processor 1520 of an electronic device 1500 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0227] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the data transmission method described in the above embodiments of this disclosure.

[0228] Embodiments of this disclosure also provide a computer program product, including a computer program that is executed by a processor using the data transmission method described in the above embodiments of this disclosure.

[0229] Figure 16 This is a schematic diagram illustrating the structure of a chip 1600 for implementing the above-described data transmission method, according to an exemplary embodiment. (Refer to...) Figure 16 The chip 1600 includes at least one communication interface 1601 and a processor 1602. The communication interface 1601 is used to receive signals input to the chip 1600 or signals output from the chip 1600. The processor 1602 communicates with the communication interface 1601 and implements the data transmission method described in the above embodiments of this disclosure through logic circuits or executed code instructions.

[0230] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses, systems, and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0231] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0232] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0233] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0234] It should be understood that various parts of the embodiments of this disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0235] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0236] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a single processing module, or each unit can exist physically separately, or two or more units can be integrated into a single module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The aforementioned storage medium can be a read-only memory, a hard disk, or an optical disk, etc.

[0237] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A data transmission method, characterized in that, The method is executed by the receiving end, and the method includes: Write the first descriptor in the buffer area to the descriptor storage area and update the write pointer in the local register. The write pointer indicates the position of the first descriptor in the descriptor storage area. The first descriptor indicates the storage information of the data to be transmitted. The write pointer is pushed to the local mirror register of the sending end to form a write pointer mirror in the mirror register. The write pointer mirror is used by the sending end to read the first descriptor from the descriptor storage area to obtain the data to be transmitted.

2. The method according to claim 1, characterized in that, The first descriptor is at least one descriptor in the buffer region, and the method further includes: In response to the number of descriptors already stored in the buffer area reaching the receive buffer threshold, the number of free space in the descriptor storage area is determined. The number of pushes is determined based on the number of stored descriptors and the number of available descriptors; The descriptor for the number of pushes in the buffer area is determined as the first descriptor.

3. The method according to claim 2, characterized in that, Determining the amount of free space in the descriptor storage area includes: Based on the local storage read pointer mirror, the free space in the descriptor storage area is determined. The read pointer mirror is formed by the local mirror register of the receiving end based on the read pointer pushed by the sending end. The number of vacant positions is defined as the number of vacant positions.

4. The method according to claim 3, characterized in that, The step of writing the first descriptor to the descriptor storage area and updating the write pointer in the local register includes: The first descriptor is written to the empty location via the system bus to determine the location identifier of the first descriptor; Based on the location identifier, determine the first write pointer corresponding to the first descriptor; Store the first write pointer into the local register.

5. The method according to claim 4, characterized in that, The step of pushing the write pointer to the local mirror register of the sending end to form a mirror of the write pointer in the mirror register includes: The first write pointer in the local register is pushed to the local mirror register of the sending end via the system bus to form a first write pointer mirror of the first write pointer.

6. The method according to claim 1, characterized in that, The method further includes: In response to a descriptor write instruction, the first descriptor corresponding to the descriptor write instruction is stored in the buffer area; After the first descriptor is written into the descriptor storage area, the storage location corresponding to the first descriptor in the buffer area is managed based on a preset caching strategy.

7. A data transmission method, characterized in that, The method is executed by the sending end, and the method includes: Based on the write pointer mirror in the local mirror register, the first descriptor corresponding to the write pointer mirror in the descriptor storage area is stored in the local buffer area. The write pointer mirror is formed by the sending end based on the write pointer pushed by the receiving end. Based on the first descriptor in the buffer area, update the read pointer in the local register and push the read pointer to the local mirror register of the receiving end.

8. The method according to claim 7, characterized in that, The write pointer mirroring based on the local mirror register stores the first descriptor corresponding to the write pointer mirroring in the descriptor storage area to the local buffer area, including: In response to the fact that the number of descriptors in the buffer area has not reached the send buffer threshold, the number of reads of the first descriptor is determined; In the local mirror register, determine the number of write pointer mirrors to be read; Based on the write pointer mirroring, determine the location identifier of the first descriptor in the descriptor storage area; Store the first descriptor corresponding to the location identifier in the descriptor storage area into the buffer area.

9. The method according to claim 8, characterized in that, Determining the number of reads of the first descriptor includes: Determine the number of descriptors that can be stored in the buffer area; Determine the number of unread descriptors in the descriptor storage area; The number of reads is determined based on the number of storable descriptors and the number of unread descriptors.

10. The method according to claim 8, characterized in that, The step of updating the read pointer in the local register based on the first descriptor in the buffer region and pushing the read pointer to the local mirror register of the receiving end includes: Based on the first descriptor in the buffer area, the prefetch pointer corresponding to the first descriptor is stored in the local register; In response to a descriptor call instruction, the prefetch pointer corresponding to the descriptor call instruction in the local register is determined as the read pointer; In response to the number of read pointers reaching the push threshold, the read pointers are pushed to the local mirror register of the receiving end via the system bus to form a read pointer mirror. The read pointer mirror is used by the receiving end to determine the free space in the descriptor storage area.

11. The method according to claim 10, characterized in that, The step of determining the prefetch pointer corresponding to the descriptor call instruction in the local register as the read pointer in response to the descriptor call instruction includes: In response to the descriptor invocation instruction, a second descriptor corresponding to the descriptor invocation instruction is determined in the buffer area; Based on the second descriptor, the storage information is determined; Based on the stored information, the data to be transmitted corresponding to the second descriptor is read, and the pre-read pointer corresponding to the second descriptor is determined as the read pointer.

12. A data transmission method, characterized in that, Performed by a data transmission system, the data transmission system including a sender and a receiver, the method includes: The receiving end writes the first descriptor in the buffer area into the descriptor storage area and updates the write pointer in the local register. The write pointer indicates the position of the first descriptor in the descriptor storage area, and the first descriptor indicates the storage information of the data to be transmitted. The write pointer is pushed to the local mirror register of the sending end via the system bus to form a write pointer mirror in the mirror register. The write pointer mirror is used by the sending end to read the first descriptor from the descriptor storage area to obtain the data to be transmitted. The sending end stores the first descriptor corresponding to the write pointer image in the descriptor storage area to the local buffer area based on the write pointer image in the local mirror register. Based on the first descriptor in the buffer area of ​​the transmitting end, the read pointer in the local register of the transmitting end is updated, and the read pointer is pushed to the local mirror register of the receiving end.

13. A receiving device, characterized in that, Includes storage and retrieval modules and transceiver modules. The access module is used to write the first descriptor in the buffer area into the descriptor storage area and update the write pointer in the local register. The write pointer indicates the position of the first descriptor in the descriptor storage area, and the first descriptor indicates the storage information of the data to be transmitted. The transceiver module is used to push the write pointer to the local mirror register of the sending end to form a write pointer mirror in the mirror register. The write pointer mirror is used by the sending end to read the first descriptor from the descriptor storage area to obtain the data to be transmitted.

14. The receiving device according to claim 13, characterized in that, The receiving device further includes a processing module, the processing module being used for: In response to the number of descriptors already stored in the buffer area reaching the receive buffer threshold, the number of free space in the descriptor storage area is determined. The number of pushes is determined based on the number of stored descriptors and the number of available descriptors; The descriptor for the number of pushes in the buffer area is determined as the first descriptor.

15. The receiving device according to claim 14, characterized in that, The access module is used for: The first descriptor is written to the empty location via the system bus to determine the location identifier of the first descriptor; Based on the location identifier, determine the first write pointer corresponding to the first descriptor; Store the first write pointer into the local register.

16. The receiving device according to claim 15, characterized in that, The transceiver module is used for: The first write pointer in the local register is pushed to the local mirror register of the sending end via the system bus to form a first write pointer mirror of the first write pointer.

17. A transmitting device, characterized in that, Includes storage and retrieval modules and transceiver modules. The access module is used to store the first descriptor corresponding to the write pointer image in the descriptor storage area to the local buffer area based on the write pointer image in the local mirror register. The write pointer image is formed by the sending end based on the write pointer pushed by the receiving end. The transceiver module is used to update the read pointer in the local register based on the first descriptor in the buffer area, and push the read pointer to the local mirror register of the receiving end.

18. The transmitting device according to claim 17, characterized in that, The access module is used for: In response to the fact that the number of descriptors in the buffer area has not reached the send buffer threshold, the number of reads of the first descriptor is determined; In the local mirror register, determine the number of write pointer mirrors to be read; Based on the write pointer mirroring, determine the location identifier of the first descriptor in the descriptor storage area; Store the first descriptor corresponding to the location identifier in the descriptor storage area into the buffer area.

19. The transmitting device according to claim 18, characterized in that, The access module is used for: Based on the first descriptor in the buffer area, the prefetch pointer corresponding to the first descriptor is stored in the local register; The transceiver module is configured to, in response to a descriptor call instruction, determine the pre-read pointer corresponding to the descriptor call instruction in the local register as the read pointer; In response to the number of read pointers reaching the push threshold, the read pointers are pushed to the local mirror register of the receiving end via the system bus to form a read pointer mirror. The read pointer mirror is used by the receiving end to determine the free space in the descriptor storage area.

20. The transmitting device according to claim 19, characterized in that, The device further includes a processing module, the processing module being used for: In response to the descriptor invocation instruction, a second descriptor corresponding to the descriptor invocation instruction is determined in the buffer area; Based on the second descriptor, the storage information is determined; Based on the stored information, the data to be transmitted corresponding to the second descriptor is read, and the pre-read pointer corresponding to the second descriptor is determined as the read pointer.

21. An electronic device, characterized in that, include: A processor and a memory for storing a computer program capable of running on the processor, wherein the processor, when running the computer program, performs the method of any one of claims 1 to 6 or 7 to 11.

22. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 6 or 7 to 11.

23. A program product, characterized in that, Includes computer instructions for causing a computer to perform the method of any one of claims 1 to 6 or 7 to 11.

24. A chip, characterized in that, It includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 1 to 6 or 7 to 11 through logic circuits or executing code instructions.

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