Multi-core hybrid real-time scheduling method and system based on job-level priority and stepped resource recovery

Abstract

The invention provides a multi-core hybrid real-time scheduling method and system based on job-level priority and stepped resource recovery. The invention provides a job-level priority dynamic scheduling mechanism which is different from the traditional fixed priority, and the mechanism is based on a Markov state transition model and dynamically adjusts the priority according to the historical execution state of the task, namely the number of continuous hit / missing times. According to the method, a stepped resource recovery technology is initiated, static resource reservation is abandoned, stepped resource distribution is generated through offline analysis of a task execution form, and the core number is dynamically adjusted in combination with online progress. The recycled idle resources are backfilled to the soft real-time task in real time, so that the win-win situation of the hard / weak hard real-time task and the soft real-time task is realized.

Description

Technical Field

[0001] This invention relates to the fields of spacecraft guidance, autonomous driving, and industrial control technologies, and in particular to a multi-core hybrid real-time scheduling method and system based on job-level priority and tiered resource recovery. Background Technology

[0002] In multi-core real-time systems, task scheduling needs to strike a balance between "time-limit guarantee" and "resource utilization". Traditional hard real-time scheduling (RM, EDF) aims for "zero errors" and statically allocates cores based on worst-case execution time (WCET), resulting in a large amount of idle computing resources under average load. Although global RM / EDF can improve utilization, the error rate of weakly-hard tasks increases sharply under high load, and parallel directed acyclic graph (DAG) tasks cannot reclaim idle cores in the later stages due to static allocation, resulting in particularly significant resource waste.

[0003] In 2022, Vreman et al. proposed the “Weakly-hard.jl” global fixed priority framework, which for the first time introduced weak hard constraints (mk model) into schedulability analysis, but did not consider job-level dynamic priorities, and the miss rate was still 3.8%.

[0004] In 2023, He et al. presented "Conditional DAG Task Priority Allocation" in IEEE TCAD, which improves parallelism by prioritizing tasks within the critical path. However, once resources are allocated, they cannot be reclaimed, and experiments show that resources are reserved excessively by 37%.

[0005] In 2024, Moyano et al. proposed "Job-Level PriorityClasses" for global scheduling, which sets job-level priority classes for weak and hard tasks, reducing the miss rate to 2.1%. However, the priority classes use static thresholds, which cannot be adjusted online according to the execution mode, and the cores for parallel tasks are still pre-allocated according to the maximum parallelism, resulting in a 0% recycling rate.

[0006] In the same year, Liang et al. proposed "mutually exclusive execution-aware DAG response time optimization" in DAC. They reduced interference through offline analysis. However, there was no resource reclamation mechanism in the online stage, and the soft real-time task completion rate was only 71.5%. A large number of idle cores were in C-State but could not be reused.

[0007] In summary, existing technologies generally suffer from the following shortcomings: 1. For weak or hard tasks with static or semi-static priority, the miss rate increases sharply with the increase of load; 2. Parallel DAG tasks allocate cores all at once based on the "maximum parallelism of the critical path". When the parallelism decreases in the later stages of execution, the cores cannot be reclaimed, resulting in an excess of 30%–50% of resources reserved. 3. The lack of a collaborative mechanism between "job-level dynamic priority" and "tiered resource recycling" means that when hard real-time, weak hard real-time, and soft real-time tasks are deployed in a mixed manner, the system's schedulability, resource utilization, and soft real-time completion rate cannot be improved simultaneously. 4. The schedulability analysis is still based on the assumptions of fixed priority and maximum resource demand, and cannot reflect the reduction of interference caused by priority changes and resource reclamation online. The analysis results are too conservative and further waste resources. Summary of the Invention

[0008] The purpose of this invention is to address the problems in existing technologies by proposing a multi-core hybrid real-time scheduling method and system based on job-level priority and tiered resource reclamation. This invention targets hard real-time multi-core SoCs for applications such as spacecraft guidance, autonomous driving, and industrial control, and is suitable for scenarios involving a mix of weak and soft real-time tasks. It can significantly improve resource utilization and reduce task failure rates.

[0009] This invention is achieved through the following technical solution: This invention proposes a multi-core hybrid real-time scheduling method based on job-level priority and tiered resource reclamation, the method comprising: Hybrid task modeling: defining weak and hard real-time tasks The constraint is that the maximum number of times the deadline can be missed within k consecutive job windows is m; at the same time, the parallel DAG task is analyzed offline to generate a ladder resource vector describing the change of its parallelism over time. Dynamic adjustment of job priority: When a weak or hard task is running, the job priority is dynamically calculated based on its historical failure status, and the load is balanced by reducing the priority in a safe state and resetting the priority in a critical state. Tiered resource allocation and recycling: The core is dynamically allocated to parallel tasks based on the tiered resource vector, and the number of active subtasks is monitored in real time to reclaim idle resources; Closed-loop feedback scheduling: The recovered core is backfilled to the soft real-time task in real time, and the system security is verified by extending the response time analysis.

[0010] Furthermore, the specific strategy for dynamically adjusting job-level priorities adopts a nonlinear mapping strategy based on Markov state transitions: Linear decreasing logic: When a task is in a "safe state" where it continuously meets its deadline, the job priority is determined by the formula... Settings, in which As the baseline priority, For linear step size, This refers to the number of consecutive hits. Reset recovery logic: When a task is missed or Approaching Upon entering the "critical state", the priority reset mechanism is immediately triggered, elevating the current and subsequent tasks to the highest critical priority. Until the condition is restored.

[0011] Furthermore, a weak-hard constraint transformation step is introduced before scheduling to transform the complex... Sliding window constraints are equivalent to a single "critical sequence". The system only needs to verify that... Whether the worst-case response time under the sequence meets the deadline can determine the original... Whether the constraints are globally satisfied can reduce the state space complexity of online scheduling.

[0012] Furthermore, the offline generation method for the ladder resource vector involves tracking the execution trajectory of the DAG parallel task, discretizing the task execution cycle into S stages, and generating vectors. Resource allocation value for each stage Strictly defined as ,in To ensure the minimum number of cores required for the critical path to advance in this phase, This represents the maximum parallelism of this stage.

[0013] Furthermore, the online execution mechanism for tiered resource allocation involves the scheduler maintaining task execution progress pointers. Real-time indexing of offline generated ladder vectors When a task enters a new execution phase, the system checks the global idle resource pool and uses a CPU affinity mask to dynamically bind the task to a pool of available resources. Instead of locking the maximum resources on the physical core cluster throughout its entire lifecycle.

[0014] Furthermore, a hysteresis comparison mechanism is established as the trigger criterion for resource recycling: the system periodically samples the actual number of active subtasks of the parallel tasks. Only if the condition is met Furthermore, the duration of this state exceeds a preset hysteresis threshold. Only then will the resource reclamation operation be triggered to release resources. Each core is moved to the global pool to prevent frequent inter-core migrations caused by momentary fluctuations. This is the current allocation number.

[0015] Furthermore, the allocation logic for idle resource backfilling is to establish a tiered backfilling strategy: Performance-first mode: If the ready queue for soft real-time tasks is not empty, the reclaimed cores are immediately mapped to soft real-time tasks to increase their concurrency and improve throughput. Energy efficiency priority mode: If there are no ready soft real-time tasks, the reclaimed idle cores are placed into C-state deep sleep state through the DVFS interface to reduce the dynamic power consumption of the system.

[0016] Furthermore, the verification formula for response time analysis is extended by adopting a modified iterative formula. Calculate the worst-case response time; Dynamic interference items : Quantify the interference changes caused by the priority fluctuations of high-priority tasks due to the JLPS mechanism on low-priority tasks; Recovery gain term When calculating interference from parallel tasks, deduct the computing resources released due to the step-by-step recycling to reduce the upper bound of the worst-case interference.

[0017] The present invention also proposes a multi-core hybrid real-time scheduling system for implementing the method, the system comprising: Offline morphology parser: used to generate ladder resource description files; Extended Task Control Block (TCB): Built-in for recording historical error states. and consecutive hit count Register fields; Dynamic scheduling engine: includes a JLPS priority calculation unit and a Ladder-RAM resource allocation unit; Resource monitoring and recycling system: used for real-time monitoring And the kernel module that performs core stripping and backfilling operations.

[0018] The present invention also proposes a computer-readable storage medium for storing computer instructions, which, when executed by a processor, implement the steps of the multi-core hybrid real-time scheduling method based on job-level priority and tiered resource reclamation.

[0019] The beneficial effects of this invention are: ① Significantly reduce the error rate of both hard and soft tasks This invention proposes a job-level priority dynamic scheduling mechanism. Unlike the traditional fixed priority, this mechanism is based on the Markov state transition model and dynamically adjusts the priority according to the historical execution state of the task, that is, the number of consecutive hits / misses.

[0020] The advantages are reflected in the fact that by linearly reducing priority during consecutive hits to reduce interference, and resetting high priority to accelerate recovery when a miss occurs, the load is effectively balanced. Moreover, experiments show that under high load conditions, the method described in this invention reduces the miss rate of weak-hard tasks from a high level of global rate monotonic scheduling / earliest deadline first scheduling (RM / EDF) to 1.2%, successfully satisfying strict weak-hard constraints such as (2,5), and improving the schedulability rate by 21.8% compared to traditional job-level scheduling.

[0021] ② Significantly improves the efficiency of parallel resource utilization This invention pioneers a tiered resource recycling technology, which abandons static resource reservation and generates a "tiered" resource distribution by analyzing task execution patterns offline, and dynamically adjusts the number of cores in conjunction with online progress.

[0022] The advantage lies in the fact that this mechanism can accurately match the actual needs of the task and reclaim idle resources in real time while ensuring the time limit of the critical path. Experimental data shows that compared with the mainstream federated scheduling, the resource recovery rate of the method described in this invention is improved by an average of 37.8%, and the maximum recovery rate can reach 48.3% in some scenarios.

[0023] ③ Significantly improves the performance of soft real-time tasks By real-time backfilling of the recovered idle resources to soft real-time tasks, this invention achieves a win-win situation for both hard / weak hard real-time tasks and soft real-time tasks.

[0024] The advantage lies in the direct conversion of recovered resources into productivity, which increases the deadline fulfillment rate of soft real-time tasks by 24.9%, reaching 89.3%, thus verifying the significant advantage of the hybrid scheduling framework in improving the overall system throughput.

[0025] ④ Theoretical analysis of low cost and high efficiency This invention utilizes "critical sequences" to simplify complex... The constraints are simplified, and schedulability is demonstrated through extended response time analysis, avoiding the high computational overhead of ILP.

[0026] The advantages are reflected in the actual test results of the RTEMS platform, where the average runtime overhead for dynamic priority adjustment is only 53.7ns, which fully meets the stringent requirements of high-frequency real-time scheduling. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0028] Figure 1 This is a flowchart of the hybrid scheduling framework. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] The technical problem to be solved by this invention: ① The challenge of ensuring time limits for weak hardware real-time tasks under high load As embedded systems evolve towards multi-core architectures, traditional hard real-time scheduling requires tasks to complete within strict deadlines, leading to low resource utilization due to conservative estimates of worst-case execution times. While weak hard real-time models allow for a limited number of deadline misses, existing global scheduling strategies cannot effectively control consecutive misses under high loads, resulting in a sharp increase in task miss rates and failing to meet the demands of scenarios such as aerospace guidance and autonomous driving. Strict requirements of constraint (i.e., a maximum of m errors in k operations).

[0031] ② Resource waste caused by static allocation of parallel DAG tasks Parallel tasks, such as those with a Directed Acyclic Graph (DAG) structure, possess inherent parallelism, but their degree of parallelism changes dynamically during execution. Existing scheduling methods, such as federated scheduling, typically allocate resources statically based on the task's maximum parallelism or critical path. This approach ignores the "long tail" phase where parallelism decreases in the later stages of task execution, resulting in a large number of core resources being locked and idle, unable to be utilized by other tasks, severely reducing the overall resource efficiency of multi-core systems.

[0032] ③ Lack of a collaborative optimization mechanism for time constraints and resource recycling Existing technologies often treat "satisfying weak hard constraints" and "parallel resource reclamation" as two separate issues. There is a lack of a unified scheduling framework that can dynamically adjust priorities to ensure the timeliness of critical tasks while simultaneously identifying and reclaiming idle resources from parallel tasks for use by soft real-time tasks. This disconnect prevents the system from maximizing the throughput of soft real-time tasks while ensuring the reliability of critical tasks.

[0033] ④ The problem of excessive computational overhead in schedulability analysis Traditional verification methods for weak-hard real-time constraints typically rely on integer linear programming, which has extremely high computational complexity and is difficult to apply to online systems with high real-time requirements or rapid iterative design processes. A more efficient analysis method is needed to define the schedulability boundary of a system under weak-hard constraints.

[0034] In response to the problems in existing technologies, combined with Figure 1 This invention proposes a multi-core hybrid real-time scheduling method based on job-level priority and tiered resource reclamation, the method comprising: Hybrid task modeling: defining weak and hard real-time tasks The constraint is that the maximum number of times the deadline can be missed within k consecutive job windows is m; at the same time, the parallel DAG task is analyzed offline to generate a ladder resource vector describing the change of its parallelism over time. Dynamic adjustment of job priority: When a weak or hard task is running, the job priority is dynamically calculated based on its historical failure status, and the load is balanced by reducing the priority in a safe state and resetting the priority in a critical state. Tiered resource allocation and recycling: The core is dynamically allocated to parallel tasks based on the tiered resource vector, and the number of active subtasks is monitored in real time to reclaim idle resources; Closed-loop feedback scheduling: The recovered core is backfilled to the soft real-time task in real time, and the system security is verified by extending the response time analysis.

[0035] Furthermore, the specific strategy for dynamically adjusting job-level priorities adopts a nonlinear mapping strategy based on Markov state transitions: Linear decreasing logic: When the task is in a "safe state" where it continuously hits the deadline (i.e., the cumulative number of missed attempts) much smaller Task priority is based on the formula Settings, in which As the baseline priority, For linear step size, This refers to the number of consecutive hits. Reset recovery logic: When a task is missed or Approaching Upon entering the "critical state", the priority reset mechanism is immediately triggered, elevating the current and subsequent tasks to the highest critical priority. Until the condition is restored.

[0036] Furthermore, a weak-hard constraint transformation step is introduced before scheduling to transform the complex... Sliding window constraints are equivalent to a single "critical sequence". The system only needs to verify that... Whether the worst-case response time under the sequence meets the deadline can determine the original... Whether the constraints are globally satisfied can reduce the state space complexity of online scheduling.

[0037] Furthermore, the offline generation method for the ladder resource vector involves tracking the execution trajectory of the DAG parallel task, discretizing the task execution cycle into S stages, and generating vectors. Resource allocation value for each stage Strictly defined as ,in To ensure the minimum number of cores required for the critical path to advance in this phase, This represents the maximum parallelism of this stage.

[0038] Furthermore, the online execution mechanism for tiered resource allocation involves the scheduler maintaining task execution progress pointers. Real-time indexing of offline generated ladder vectors When a task enters a new execution phase, the system checks the global idle resource pool and uses a CPU affinity mask to dynamically bind the task to a pool of available resources. Instead of locking the maximum resources on the physical core cluster throughout its entire lifecycle.

[0039] Furthermore, a hysteresis comparison mechanism is established as the trigger criterion for resource recycling: the system periodically samples the actual number of active subtasks of the parallel tasks. Only if the condition is met Furthermore, the duration of this state exceeds a preset hysteresis threshold. Only then will the resource reclamation operation be triggered to release resources. Each core is moved to the global pool to prevent frequent inter-core migrations caused by momentary fluctuations. This is the current allocation number.

[0040] Furthermore, the allocation logic for idle resource backfilling is to establish a tiered backfilling strategy: Performance-first mode: If the ready queue for soft real-time tasks is not empty, the reclaimed cores are immediately mapped to soft real-time tasks to increase their concurrency and improve throughput. Energy efficiency priority mode: If there are no ready soft real-time tasks, the reclaimed idle cores are placed into C-state deep sleep state through the DVFS interface to reduce the dynamic power consumption of the system.

[0041] Furthermore, the verification formula for response time analysis is extended by adopting a modified iterative formula. Calculate the worst-case response time; Dynamic interference items : Quantify the interference changes caused by the priority fluctuations of high-priority tasks due to the JLPS mechanism on low-priority tasks; Recovery gain term When calculating interference from parallel tasks, deduct the computing resources released due to the step-by-step recycling to reduce the upper bound of the worst-case interference.

[0042] The present invention also proposes a multi-core hybrid real-time scheduling system for implementing the method, the system comprising: Offline morphology parser: used to generate ladder resource description files (.lad); Extended Task Control Block (TCB): Built-in for recording historical error states. and consecutive hit count Register fields; Dynamic scheduling engine: includes a JLPS priority calculation unit and a Ladder-RAM resource allocation unit; Resource monitoring and recycling system: used for real-time monitoring And the kernel module that performs core stripping and backfilling operations.

[0043] Example 1 This invention proposes a multi-core hybrid real-time scheduling method based on job-level priority and tiered resource reclamation. By coordinating "job-level priority dynamic scheduling" and "tiered resource allocation," it satisfies both weak and hard real-time constraints. Under the premise of maximizing the resource utilization of parallel tasks, this method decomposes the scheduling process into three levels: offline analysis, online dynamic mapping, and closed-loop resource reclamation. The specific implementation steps are as follows: ① Establish a multi-dimensional hybrid task model and define weak and hard constraints. First, construct a set of weak and hard real-time tasks. and parallel task sets The system model. For any weak or hard task. Define its time constraint as a tuple ,in For the worst execution time, For a period of time, For relative deadlines, introduce weak-hard constraints. That is, the task requires In any continuity Within the sliding window of each assignment, the maximum number of times the deadline is missed is strictly limited to no more than [number missing]. For parallel tasks Using a directed acyclic graph Modeling, in which Represents a set of subtasks. This indicates the dependency relationship, which serves as the basis for subsequent resource form analysis.

[0044] ② Perform offline task morphology analysis and ladder vector generation For parallel tasks It abandons the traditional static allocation based on a single worst-case execution time, and instead generates a tiered resource demand curve through offline analysis. This is achieved through analysis... The topology and ideal resource requirements of the computation task at different execution times t. The system identifies the inflection points of the critical path and high-parallelism stages, discretizes the execution process into S stages, and generates a tiered resource vector. The allocation value for each stage. Must meet That is, not less than the minimum number of cores required to advance the critical path. (To ensure timeliness), and not exceeding the maximum parallelism of this stage. (To avoid idleness), it provides an accurate resource benchmark for online scheduling.

[0045] ③ Implement dynamic mapping of job-level priorities based on historical status. During the online scheduling phase, for tasks with both weak and strong hardware... Introducing state variables Records the number of missed attempts within the current sliding window in real time. For The qth assignment Its priority Instead of being fixed, it is achieved through a dynamic mapping function. Sure: like Furthermore, since there is still a margin before reaching the default threshold, the system determines it to be in a "safe state," and the task priority is adjusted linearly. Decreasing, that is ( (to increase the number of consecutive hits), thereby proactively reducing interference with low-priority tasks; once Approaching the threshold If a new error occurs, triggering the "reset mechanism," the priority will be forcibly raised to the highest critical priority. This mechanism ensures that critical operations can seize resources to restore time limits before the "missed quota" is exhausted, thus achieving [the desired outcome]. Adaptive satisfaction of constraints.

[0046] ④ Constraint transformation and critical sequence construction To reduce the complexity of the state space in dynamic scheduling, the constraint transformation theorem is used to simplify the complex... The constraints are simplified to a typical "critical sequence". .definition The sequence of job states that makes the system most difficult to schedule (e.g., occurring consecutively) (Recovery process after the first failure). The system uses a monitoring state machine to identify whether the current job sequence matches. Once a match is found, a high-priority strategy is locked in. This step theoretically reduces the need to iterate through all... The analysis process for each state is simplified to the verification of the response time of a specific critical sequence, which greatly reduces the scheduling overhead.

[0047] ⑤ Tiered online resource allocation and core binding When parallel tasks When scheduled for execution, the scheduler reads the vectors generated offline. Combined with the current execution progress pointer Dynamically request processor cores. If the task is in phase S, the system attempts to allocate them. Each physical core. If the system has a number of idle cores... Then, in order to ensure Under the premise of meeting the bottom line, downgraded allocation is performed. After allocation, the sub-task set is divided using affinity masking. Bind to a specified core cluster to ensure cache locality and reduce inter-core migration overhead.

[0048] ⑥ Real-time resource recycling and soft real-time task backfilling During task execution, a resource recovery feedback loop is established. The system periodically monitors the task. The actual number of active subtasks And calculate the amount of idle resources. When detected And the duration exceeds the threshold When this happens, the scheduler immediately triggers a recycling operation, which will... Each core is stripped and returned to the global resource pool. The reclaimed cores are prioritized for allocation to soft real-time tasks in the ready queue via a "zero-jitter backfill" mechanism, or placed into deep sleep via the Dynamic Voltage Frequency Scaling (DVFS) interface when there is no load, thereby improving resource utilization. A dual improvement in energy efficiency.

[0049] ⑦ Extended response time analysis and access control To ensure the security of the aforementioned dynamic mechanism, Extended Response Time Analysis (RTA) is used for schedulability determination. The classic RTA iterative formula is modified by introducing an interference term introduced by dynamic priorities. And the factor for reducing interference from parallel tasks caused by resource recycling Computational tasks Upper bound of response time in worst case :

[0050] in This is a perturbation weighting function based on critical sequence priority. It applies only if all weak and hard tasks are within any window. Internal derivation error count satisfy And the time limit of the critical path of the parallel task is satisfied. Only then is the task set deemed schedulable and allowed to be accepted by the system.

[0051] Example 2 The specific implementation of this invention adopts a three-layer architecture of "offline morphological analysis—online dynamic scheduling—closed-loop feedback verification," deployed in a multi-core real-time operating system. The specific process is detailed into the following eight steps: Step 1: Establish a multi-dimensional hybrid task model and generate offline ladder vectors The system first constructs a global task model in the offline phase, including weak and hard real-time tasks. Given Constraints, i.e., in any continuous The maximum number of times a deadline can be missed within a single job window is [number]. 1111. For parallel DAG tasks The system abandons the traditional static resource reservation model based on a single worst-case execution time, and instead adopts a method combining static code analysis and execution trajectory tracing to analyze the changes in parallelism over time. The system identifies the critical path and turning points of high-parallelism intervals in task execution, discretizes the entire execution process into S stages, and generates a "ladder resource vector" that precisely matches the task's characteristics. ,in This vector represents the minimum number of cores required to guarantee the time limit in Phase S, and it is then written into the Task Control Block (TCB) for the online scheduler to read.

[0052] Step 2: Initialize the hardware resource pool and job-level priority configuration Upon system startup, the resource management unit in the FPGA (Field-Programmable Gate Array) or kernel is initialized, and the initial mask and resource reclamation FIFO queue for the entire system core are configured. For weak hardware tasks, the system initializes their historical state counters. Set to 0, and load the baseline priority derived from the critical sequence. With priority reset At this point, the system also needs to set the linear step size parameter for dynamic adjustment based on the results of the extended response time analysis. This ensures that dynamic changes in priority under different loads do not violate the schedulability boundary of the system.

[0053] Step 3: Implement dynamic mapping of job-level priorities based on historical status During online operation, whenever a weak hardware task New assignment Upon arrival, the scheduler reads its historical state variables. (Cumulative number of errors in the current window). If much smaller The system determines that the task is in a "safe state" and then executes a degradation strategy, calculating the number of consecutive hits. Set the priority to Actively reduce the competitiveness of this task to minimize interference with other tasks. If near (i.e., insufficient remaining error quota), the system determines that the task is in a "critical state" and immediately triggers the reset mechanism, forcibly raising the priority to [priority]. This ensures that the operation can secure sufficient resources to avoid default, thereby achieving... Adaptive satisfaction of constraints.

[0054] Step 4: Tiered resource allocation for executing parallel tasks When parallel tasks When a task is scheduled for execution, the scheduler no longer locks the maximum resource at once, but instead indexes the vector generated offline based on the task's current execution progress pointer. Obtain the target number of cores for the current stage The system checks the global idle core pool, ensuring that the number of allocated cores is not less than the critical path requirement. Under this premise, CPU affinity masks are used to bind tasks to designated physical core clusters. This tiered allocation ensures that tasks only occupy the amount of resources actually needed for their current execution phase, avoiding resource stagnation and waste caused by reserving resources based on maximum parallelism.

[0055] Step 5: Runtime Parallelism Monitoring and Dynamic Resource Reclamation During task execution, the system periodically samples the actual number of active subtasks of the parallel task using hardware performance counters or kernel hooks. and compare it with the currently allocated core number. Real-time comparison is performed. Once detected... If the duration exceeds the preset hysteresis threshold (indicating that the task has entered a phase of decreasing parallelism), the system immediately triggers the resource reclamation mechanism to calculate the amount of idle resources. The ownership of these cores is then stripped from the original task and marked as "dirty" for redistribution.

[0056] Step Six: Soft Real-Time Backfilling and Energy Efficiency Management of Idle Resources The scheduler will reclaim the waste from step five. Each core is placed into the global shared resource pool, and a "backfilling" strategy is immediately initiated. The system prioritizes scanning the ready queue of the soft real-time task set, dynamically mapping the reclaimed cores to computationally intensive soft real-time tasks, thus expanding their parallelism. This significantly reduces response time. If there are no ready soft real-time tasks, the system uses a dynamic voltage and frequency adjustment interface to put these idle cores into a low-power sleep mode (C-state) until the next high-priority request arrives.

[0057] Step 7: Extended Response Time Analysis Closed-Loop Verification To ensure the security of the aforementioned dynamic mechanism, the system periodically performs extended response time analysis. This analysis introduces interference variables caused by dynamic priorities. In addition to the interference reduction factor brought about by resource recycling, the upper bound of the response time of weak-hard tasks in the worst case is calculated. Only when the derivation error rate for all weak and hard tasks satisfies Furthermore, the current scheduling parameters are considered valid only if the critical path time limit of the parallel task is guaranteed; otherwise, the system will dynamically adjust the priority step size through a feedback loop. Or correct the step vector .

[0058] Step 8: System performance index verification and result output Experimental verification based on a 4-core RTEMS (Real-Time Executive for Multiprocessor Systems) platform shows that this implementation method achieves significant results in ensuring timeliness and improving efficiency: under high load conditions, the deadline miss rate for weak hardware real-time tasks is reduced from 3.8% in traditional global scheduling to 1.2%, successfully meeting the strict requirements. Constraints. The tiered resource reclamation mechanism reduces resource reservation by an average of 37.8% compared to federated scheduling. Thanks to the backfilling of reclaimed resources, the completion rate of soft real-time tasks increased by 24.9%, reaching 89.3%. Meanwhile, the average runtime overhead of dynamic priority adjustment is only 53.7ns, fully meeting the scheduling requirements of microsecond-level real-time systems.

[0059] The key technical aspects of this invention cover the entire process from offline model construction to online scheduling, execution, and verification, specifically including the following nine parts: ① Historical execution feature tracing technology based on Markov state machines This invention constructs a job-level state tracking mechanism, which maintains historical execution state variables of weak-hard real-time tasks in the task control block. This technology records the sliding window in real time. The deadline miss distribution within the task is analyzed, and the current "health" of the task is quantified into specific discrete states (safe state, critical state, default state) using a Markov chain model, providing accurate data support for dynamic priority decision-making.

[0060] ② Dynamic priority adjustment logic combining linear decrement and threshold reset A nonlinear priority mapping function was designed. It includes a dual adjustment strategy: one is an "active avoidance strategy," which adjusts the strategy by linear steps when the task is in a safe state of continuously hitting the deadline. Decrease priority successively The first strategy is to allocate resources to urgent tasks; the second is a "rapid recovery strategy" to address situations where the accumulated number of missed attempts approaches a threshold. If this occurs, an interrupt-level priority reset is immediately triggered, elevating the task to the highest critical priority. This ensures that the deadline for recovery is met.

[0061] ③ Weak hard constraints To the critical sequence Equivalent transformation method To solve the traditional Constraint validation requires traversal. To address the computational bottleneck in certain states, this invention proposes a constraint transformation algorithm. This technique defines and identifies "critical sequences." (The specific job sequence that makes the system most difficult to schedule) proves that as long as the system satisfies the critical sequence The schedulability is equivalent to satisfying the global... This simplifies the verification of complex weak and hard constraints into a single sequence response time determination.

[0062] ④ Offline analysis and discretization modeling of parallel task execution patterns For DAG parallel tasks, a morphological resource modeling method is proposed. Unlike a single WCET value, this method uses offline trace tracking to depict the parallelism fluctuation curve of the task on the time axis, and discretizes the curve into S execution stages to identify the critical path stage and the high-concurrency stage, thus establishing a benchmark for refined resource management.

[0063] ⑤ Tiered resource vector Generation and definition technology A ladder vector is defined to describe the resource requirements of parallel tasks. Resource allocation values ​​for each stage All are strictly defined in Within the range: lower limit Ensure the critical path is not blocked to meet time limits and upper limits. Limit over-allocation to create a tiered resource reservation scheme.

[0064] ⑥ Progress-based online resource dynamic mapping and core binding A ladder vector parsing engine is embedded in the scheduler to achieve dynamic mapping of resources as execution progresses. The scheduler reads the task's program counter or progress pointer in real time and indexes the ladder vector. It also uses CPU affinity masks to dynamically bind tasks to a specified number of physical core clusters, achieving precise supply of "as much as needed".

[0065] ⑦ Real-time stripping mechanism for idle resources under hysteresis threshold control The triggering criteria and hysteresis control logic for resource recycling were constructed. The system periodically samples the number of actual active subtasks. When detected And the duration exceeds the set anti-shake hysteresis threshold. When the time comes, a core stripping operation is immediately triggered, marking idle cores as "dirty" and returning them to the global pool. This ensures timely recycling and avoids frequent inter-core migration caused by minor fluctuations.

[0066] ⑧ Zero-jitter backfilling technology for resource recovery in soft real-time tasks Establish a global shared resource pool and a fast backfill channel for soft real-time tasks. Prioritize mapping the recovered computing resources to computationally intensive soft real-time tasks, thereby increasing throughput by expanding their concurrency. When there are no soft real-time tasks (SRT) available, automatically put the cores into C-state sleep mode via the DVFS interface to achieve adaptive switching between performance improvement and energy consumption reduction.

[0067] ⑨ Extended response time analysis with the introduction of dynamic disturbance terms An improved schedulability test formula is proposed for system admission control. The classical RTA equation is modified by introducing two correction factors: one is a dynamic priority disturbance term. First, it quantifies the worst-case interference caused by priority fluctuations; second, it recovers the gain factor by deducting the amount of resources recovered and released when calculating interference from high-priority parallel tasks, thereby reducing the pessimism of theoretical analysis and improving the system's task acceptance capability. The present invention also proposes a computer-readable storage medium for storing computer instructions, which, when executed by a processor, implement the steps of the multi-core hybrid real-time scheduling method based on job-level priority and tiered resource reclamation.

[0068] The memory in this application embodiment can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the methods described in this invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0069] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0070] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0071] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as execution by a hardware decoding processor, or as a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0072] The above provides a detailed description of the multi-core hybrid real-time scheduling method and system based on job-level priority and tiered resource reclamation proposed in this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A multi-core hybrid real-time scheduling method based on job-level priority and tiered resource reclamation, characterized in that, The method includes: Hybrid task modeling: defining weak and hard real-time tasks The constraint is that the maximum number of times the deadline can be missed within k consecutive job windows is m; at the same time, the parallel DAG task is analyzed offline to generate a ladder resource vector describing the change of its parallelism over time. Dynamic adjustment of job priority: When a weak or hard task is running, the job priority is dynamically calculated based on its historical failure status, and the load is balanced by reducing the priority in a safe state and resetting the priority in a critical state. Tiered resource allocation and recycling: The core is dynamically allocated to parallel tasks based on the tiered resource vector, and the number of active subtasks is monitored in real time to reclaim idle resources; Closed-loop feedback scheduling: The recovered core is backfilled to the soft real-time task in real time, and the system security is verified by extending the response time analysis.

2. The method according to claim 1, characterized in that, The specific strategy for dynamically adjusting job-level priorities adopts a nonlinear mapping strategy based on Markov state transitions: Linear decreasing logic: When a task is in a "safe state" where it continuously meets its deadline, the job priority is determined by the formula... Settings, in which As the baseline priority, For linear step size, This refers to the number of consecutive hits. Reset recovery logic: When a task is missed or Approaching Upon entering the "critical state", the priority reset mechanism is immediately triggered, elevating the current and subsequent tasks to the highest critical priority. Until the condition is restored.

3. The method according to claim 1, characterized in that, Introducing a weak-hard constraint transformation step before scheduling will transform the complex... Sliding window constraints are equivalent to a single "critical sequence". The system only needs to verify that... Whether the worst-case response time under the sequence meets the deadline can determine the original... Whether the constraints are globally satisfied can reduce the state space complexity of online scheduling.

4. The method according to claim 1, characterized in that, An offline method for generating tiered resource vectors involves tracking the execution trajectory of a DAG parallel task, discretizing the task execution cycle into S stages, and generating vectors. Resource allocation value for each stage Strictly defined as ,in To ensure the minimum number of cores required for the critical path to advance in this phase, This represents the maximum parallelism of this stage.

5. The method according to claim 4, characterized in that, The online execution mechanism of tiered resource allocation: The scheduler maintains the execution progress pointer of the tasks. Real-time indexing of offline generated ladder vectors When a task enters a new execution phase, the system checks the global idle resource pool and uses a CPU affinity mask to dynamically bind the task to a pool of available resources. Instead of locking the maximum resources on the physical core cluster throughout its entire lifecycle.

6. The method according to claim 1, characterized in that, The triggering criteria for resource recycling establish a hysteresis comparison mechanism: the system periodically samples the actual number of active subtasks of parallel tasks. Only if the condition is met Furthermore, the duration of this state exceeds a preset hysteresis threshold. Only then will the resource reclamation operation be triggered to release resources. Each core is moved to the global pool to prevent frequent inter-core migrations caused by momentary fluctuations. This is the current allocation number.

7. The method according to claim 1, characterized in that, The allocation logic for idle resource backfilling is used to establish a tiered backfilling strategy: Performance-first mode: If the ready queue for soft real-time tasks is not empty, the reclaimed cores are immediately mapped to soft real-time tasks to increase their concurrency and improve throughput. Energy efficiency priority mode: If there are no ready soft real-time tasks, the reclaimed idle cores are placed into C-state deep sleep state through the DVFS interface to reduce the dynamic power consumption of the system.

8. The method according to claim 1, characterized in that, The validation formula for extended response time analysis adopts a modified iterative formula. Calculate the worst-case response time; Dynamic interference items : Quantify the interference changes caused by the priority fluctuations of high-priority tasks due to the JLPS mechanism on low-priority tasks; Recovery gain term When calculating interference from parallel tasks, deduct the computing resources released due to the step-by-step recycling to reduce the upper bound of the worst-case interference.

9. A multi-core hybrid real-time scheduling system for implementing the method of any one of claims 1-8, characterized in that, The system includes: Offline morphology parser: used to generate ladder resource description files; Extended Task Control Block (TCB): Built-in for recording historical error states. and consecutive hit count Register fields; Dynamic scheduling engine: includes a JLPS priority calculation unit and a Ladder-RAM resource allocation unit; Resource monitoring and recycling system: used for real-time monitoring And the kernel module that performs core stripping and backfilling operations.

10. A computer-readable storage medium for storing computer instructions, characterized in that, When the computer instructions are executed by the processor, they implement the steps of the method according to any one of claims 1-8.

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