Ultra-low noise tile-type phased array plane based on silicon-based chip

Abstract

The embodiment of the invention provides an ultra-low noise tile-type phased array plane based on a silicon-based chip, and the phased array plane comprises an antenna part PCB, and the antenna part PCB comprises an array antenna, an LNA chip, a board-level filter, a BFIC chip based on a silicon-based technology, and a power division network which are connected in sequence; wherein the array antenna is provided with a patch antenna, and a feed point of the patch antenna is directly connected with the LNA chip through a plated-through hole; the LNA chip is connected with the board-level filter through a plated-through hole, the board-level filter is connected with the BFIC chip through a plated-through hole, and the BFIC chip is connected with the power division network through a plated-through hole; the LNA chip is integrated with a dynamic tuning matching circuit, and dynamic impedance matching can be carried out according to the working condition of the patch antenna. Therefore, the tile-type phased array plane provided by the embodiment of the invention realizes the consideration of high integration level, low noise, low loss, dynamic matching and interference resistance, and overcomes the defects of the traditional tile-type phased array plane in the aspects of integration level, noise, loss, matching flexibility, filtering and the like.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an ultra-low noise tile-type phased array based on a silicon-based chip. Background Technology

[0002] With the trend of RF phased array technology towards miniaturization, high integration, and low power consumption, the tile-type phased array has become the mainstream architecture due to its layered arrangement and high space utilization. Silicon-based processes, with their advantages of low cost and easy mass production, are gradually replacing compound semiconductors such as gallium arsenide and are widely used in communications, radar, and other fields. Especially in the millimeter-wave and microwave bands, silicon-based integrated phased arrays have achieved multi-channel beamforming capabilities, and performance optimization has become a key research focus in the industry.

[0003] Currently, most existing tile-type phased arrays adopt an architecture of patch antenna + coaxial via + RF feed line + beamforming integrated circuit (BFIC) chip. This architecture has the following problems: 1. If BFIC chips use silicon-based technology, the noise figure of a single chip is relatively large. The overall noise figure after cascading is greatly affected by the BFIC chip. Although using compound process chips can reduce the noise figure of the link, compound chips have high power consumption and cost.

[0004] 2. The patch antenna and BFIC chip are mostly connected by RF feed lines. The feed line loss will be introduced into the link noise, resulting in an increase in the noise figure of the phased array.

[0005] 3. The patch antenna and the BFIC chip can only be matched with a fixed impedance on the RF feed line. In actual use, when the antenna conditions change, it cannot be dynamically adjusted, which will lead to impedance mismatch and affect signal transmission.

[0006] 4. The existing architecture lacks a filtering device, making it unable to filter out strong interference signals. Summary of the Invention

[0007] In a first aspect, embodiments of this disclosure provide an ultra-low noise tile-type phased array based on a silicon-based chip. The tile-type phased array includes: an antenna PCB board, which includes, in sequence: an array antenna, a low-noise amplifier (LNA) chip, a board-level filter, a silicon-based BFIC chip, and a power divider network. The array antenna has a patch antenna, the feed point of which is directly connected to the LNA chip via a metallized via. The LNA chip is connected to the board-level filter via a metallized via, the board-level filter is connected to the BFIC chip via a metallized via, and the BFIC chip is connected to the power divider network via a metallized via. The LNA chip integrates a dynamic tuning matching circuit capable of dynamic impedance matching based on the operating conditions of the patch antenna.

[0008] In some possible implementations of the first aspect, the BFIC chip and LNA chip are deployed on the top layer of the antenna section PCB, the power divider network is deployed on the second layer of the antenna section PCB, the board-level filter is deployed on the third layer of the antenna section PCB, and the array antenna is deployed on the bottom layer of the antenna section PCB.

[0009] In some possible implementations of the first aspect, the board-level filter is deployed in the form of a stripline on the third layer of the antenna section PCB.

[0010] In some possible implementations of the first aspect, the metallized vias include: coaxial vias and blind vias; wherein the feed point of the patch antenna is directly connected to the LNA chip through a coaxial via; the LNA chip is connected to the board-level filter through a blind via, the board-level filter is connected to the BFIC chip through a blind via, and the BFIC chip is connected to the power divider network through a blind via.

[0011] In some possible implementations of the first aspect, a BFIC chip is placed at the center of every four patch antennas, and four LNA chips are surrounded around each BFIC chip. The input of each LNA chip coincides with the two feed points of the corresponding patch antenna and is directly connected through a coaxial via.

[0012] In some possible implementations of the first aspect, the spacing between patch antennas is determined by the operating frequency of the tile phased array.

[0013] In some possible implementations of the first aspect, the tile-type phased array also includes a non-antenna portion PCB board, which includes: a power module, a control module, and external interfaces. The power module is used to power the Watt-type phased array. The control module is used to control the tile-type phased array. External interfaces are used for external communication.

[0014] In some possible implementations of the first aspect, the BFIC chip is an 8-channel BFIC chip. When the phased array is working, the RF link corresponding to each channel receives RF signals through a patch antenna. The RF signals enter the LNA chip through a coaxial via for low-noise amplification. The amplified RF signals enter the board-level filter through a blind via for interference filtering. The filtered RF signals enter the BFIC chip through a blind via for beamforming. Then, the BFIC chip combines the beams corresponding to the 8 channels into one output to the power divider network. The power divider network then combines the beams output by each BFIC chip into one to obtain a directional receiving beam, which is then output to the outside through an external interface.

[0015] In some possible implementations of the first aspect, the operating conditions of the patch antenna include: beam scanning angle and ambient temperature drift.

[0016] Secondly, embodiments of this disclosure provide an electronic device that includes the Watt-type phased array as described above.

[0017] In summary, the ultra-low noise tile-type phased array based on silicon-based chips provided in this disclosure significantly reduces the link noise figure by directly connecting the feed point of the patch antenna to the LNA chip via a metallized via (such as a coaxial via). This eliminates the losses introduced by traditional RF feed lines. The dynamic tuning matching circuit integrated in the LNA chip can dynamically adjust the impedance according to the antenna operating conditions, effectively avoiding impedance mismatch problems. The added board-level filter can filter out strong interference signals, improving anti-interference capability. Overall, this architecture continues to use low-cost, easily mass-producible silicon-based BFIC chips, while optimizing overall performance by adding an LNA chip, a board-level filter, and a structure that directly connects the LNA chip to the patch antenna feed point. Without increasing the array size or the physical distance between the transmit and receive arrays, it achieves a balance of high integration, low noise, low loss, dynamic matching, and anti-interference, overcoming the shortcomings of traditional tile-type phased arrays in terms of integration, noise, loss, matching flexibility, and filtering function.

[0018] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0019] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1An overall architecture diagram of an ultra-low noise tile-type phased array based on a silicon-based chip provided in this disclosure embodiment; Figure 2 A circuit schematic diagram of an antenna section PCB board provided in an embodiment of this disclosure is shown; Figure 3 A cross-sectional layout diagram of an antenna section PCB board provided in an embodiment of this disclosure; Figure 4 This is a partial top perspective view of an antenna portion PCB board provided in an embodiment of this disclosure. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0022] To address the problems in the background art, this disclosure provides an ultra-low noise tile-type phased array based on silicon-based chips. This can overcome the shortcomings of traditional tile-type phased arrays in terms of integration, noise, loss, matching flexibility, and filtering function by adding an LNA chip, a board-level filter, and a structure that directly connects the LNA chip to the patch antenna feed point.

[0023] The following detailed description, with reference to the accompanying drawings and specific embodiments, illustrates an ultra-low noise tile-type phased array based on a silicon-based chip provided in this disclosure.

[0024] Figure 1 This illustration shows a structural diagram of an ultra-low noise tile-type phased array based on a silicon-based chip, as provided in an embodiment of this disclosure. Figure 1 As shown, the Watt-type phased array includes: a non-antenna PCB board and an antenna PCB board.

[0025] like Figure 1 As shown, the PCB board in the non-antenna section includes: a power supply module, a control module, and an external interface. The power supply module supplies power to the watt-type phased array; the control module controls the watt-type phased array; and the external interface is used for external communication.

[0026] like Figure 2 As shown, the antenna section PCB board includes, in sequence: an array antenna, an LNA chip, a board-level filter, a silicon-based BFIC chip, and a power divider network. The array antenna features a patch antenna, whose feed point is directly connected to the LNA chip via a metallized via. The LNA chip is connected to the board-level filter via a metallized via, the board-level filter is connected to the BFIC chip via a metallized via, and the BFIC chip is connected to the power divider network via a metallized via. The LNA chip integrates a dynamic tuning matching circuit, capable of dynamic impedance matching based on the operating conditions of the patch antenna (such as beam scanning angle, ambient temperature drift, etc.).

[0027] In some embodiments, to save PCB space, the BFIC chip and LNA chip are deployed on the top layer (first layer) of the antenna section PCB, the power divider network is deployed on the second layer of the antenna section PCB, the board-level filter is deployed on the third layer of the antenna section PCB, and the array antenna is deployed on the bottom layer (last layer) of the antenna section PCB. See details below. Figure 3 Specifically, the board-level filter is deployed in the form of a stripline on the third layer of the antenna section PCB.

[0028] In some embodiments, the metallized vias include: coaxial vias and blind vias; wherein, the feed point of the patch antenna is directly connected to the LNA chip through a coaxial via; the LNA chip is connected to the board-level filter through a blind via, the board-level filter is connected to the BFIC chip through a blind via, and the BFIC chip is connected to the power divider network through a blind via.

[0029] In some embodiments, a BFIC chip is placed at the center of every four patch antennas, and four LNA chips surround each BFIC chip. The input terminal of each LNA chip coincides with the two feed points of the corresponding patch antenna and is directly connected through a coaxial via. Exemplarily, the above structure can be as follows: Figure 4 As shown, there are 16 patch antennas in total. Each rectangular grid is the grid of a patch antenna. The circles within the rectangular grid are the radiating patches of the patch antenna, and the two smaller circles on the radiating patches are the two feed points of the antenna. The spacing between the patch antennas is determined by the operating frequency of the Watt phased array. A BFIC chip is placed at the center of every four patch antennas. Four LNA chips surround each BFIC chip. The input terminal of each LNA chip coincides with the two feed points of the corresponding patch antenna and is directly connected through coaxial vias. The small frame within every four patch antennas indicates the placement position of the board-level filter.

[0030] In some embodiments, the BFIC chip is an 8-channel BFIC chip, which connects to 8 identical RF links, as detailed below. Figure 2Accordingly, when the phased array is working, the RF link corresponding to each channel receives RF signals through a patch antenna. The RF signals pass through a coaxial via into the LNA chip for low-noise amplification. The amplified RF signals then pass through a blind via into a board-level filter for interference filtering. The filtered RF signals then pass through a blind via into the BFIC chip for beamforming. The BFIC chip then combines the beams corresponding to the eight channels into one output to the power divider network. The power divider network then combines the beams output from each BFIC chip into one to obtain a directional receiving beam, which is then output to the outside through an external interface.

[0031] In summary, the embodiments disclosed herein achieve at least the following technical effects: (1) A key performance indicator for a phased array is G / T (the ratio of receiving antenna gain to equivalent noise temperature). This indicator is a core parameter for measuring the receiving system's ability to detect weak signals. The higher the value, the stronger the system's performance in receiving weak signals. To improve the G / T ratio, existing technologies generally increase the number of channels in the phased array, thereby increasing the receiving gain G of the array and ultimately improving the G / T ratio. However, this disclosure improves the G / T ratio by reducing the equivalent noise temperature T through an innovative RF link architecture. In the subsequent description of the effects, the reduction of RF link noise and the adjustment of circuit matching are all aimed at reducing the equivalent noise temperature T.

[0032] (2) An LNA chip with dynamic tuning matching circuit and a board-level filter are added between the array antenna and the BFIC chip to reduce link noise, improve impedance matching between the antenna and the chip, and filter out interference signals. Specifically, the noise figure of the LNA chip can be kept below 1dB, while the gain can easily be kept above 15dB. Compared with the BFIC chip, it has a lower noise figure and higher gain. By directly connecting the LNA chip after the patch antenna, according to the RF link noise cascading formula, this architecture can significantly reduce the impact of the BFIC chip noise and the power divider network loss on the overall link noise.

[0033] (3) In the prior art, the matching network between the array antenna and LNA chip, and between LNA chip and BFIC chip of the phased array, is mostly composed of microstrip lines or discrete components with fixed parameters. It is impossible to dynamically adjust the impedance parameters according to the operating conditions such as beam scanning angle (impedance fluctuation >15% within ±60°) and ambient temperature drift (impedance change rate >10% due to -40℃~85℃). This not only causes signal reflection loss (generally >1.5dB), but also excites standing wave interference and parasitic noise. Ultimately, it is difficult for the overall noise figure (NF) of the phased array to be lower than 3dB, which seriously restricts the detection sensitivity of weak signals (such as weak radar echoes and low-power communication signals). However, the LNA chip used in this disclosure has a dynamic tuning matching circuit inside. It can adjust the internal matching circuit according to the operating conditions such as the beam scanning angle of the array antenna and ambient temperature drift to achieve the purpose of link impedance matching and improve signal quality.

[0034] (4) Due to the large size of the BFIC chip, in the prior art, the feed point of the array antenna and the BFIC chip generally need to be connected through a coaxial via and a PCB-level feed line. This feed line is mostly in the form of a coplanar waveguide ground or a stripline. According to the RF link noise cascading formula, the insertion loss of the feed line will be added to the link noise, reducing the system sensitivity. However, the LNA chip is smaller and can be flexibly laid out on the PCB. In this disclosure, the feed point of the array antenna and the input terminal of the LNA chip are directly connected through a coaxial via, avoiding the use of a feed line connection and reducing the noise of the entire link.

[0035] (5) For phased arrays in the millimeter-wave band, the top layer of the PCB board has limited space and cannot accommodate more RF devices. This disclosure innovates the layout of the RF link on the PCB board by placing only the BFIC chip and LNA chip on the top layer of the PCB board, while the filter is placed on the third layer of the PCB board in the form of a PCB board-level stripline. After the signal is output from the LNA chip, it enters the filter through multiple blind vias. After being filtered, the signal returns to the top layer of the PCB board through multiple blind vias and enters the BFIC chip, thus realizing the signal transmission of the entire RF link. Adding a filter to the RF link can filter out interference signals outside the operating frequency band and improve the signal quality of the RF link. The filter can be simulated and designed according to the needs of the usage environment to filter specific interference signals. This is especially true for satellite communication terminal applications. Since the physical distance between the receiving antenna and the transmitting antenna is very close, sometimes even sharing a PCB board, and the transmitting power of the transmitting antenna is much greater than that of the receiving antenna, the transmitted signal is very likely to leak into the receiving antenna during the application process. At this time, the filter in the receiving link can effectively filter out the transmitted signal, improve the link signal quality, and ensure the normal operation of the antenna.

[0036] The above is an introduction to an embodiment of a tile-type phased array. Based on this, the present disclosure also provides an electronic device that includes the tile-type phased array as described above.

[0037] It is worth noting that the specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A silicon-based chip-based ultra-low noise tile-type phased array, characterized in that, The Watt-type phased array includes: an antenna section PCB board, which includes: an array antenna, an LNA chip, a board-level filter, a silicon-based BFIC chip, and a power divider network connected in sequence; wherein, the array antenna has a patch antenna, and the feed point of the patch antenna is directly connected to the LNA chip through a metallized via; the LNA chip is connected to the board-level filter through a metallized via, the board-level filter is connected to the BFIC chip through a metallized via, and the BFIC chip is connected to the power divider network through a metallized via; the LNA chip integrates a dynamic tuning matching circuit, which can perform dynamic impedance matching according to the operating conditions of the patch antenna.

2. The tile-type phased array surface according to claim 1, characterized in that, The BFIC chip and the LNA chip are deployed on the top layer of the antenna section PCB board, the power divider network is deployed on the second layer of the antenna section PCB board, the board-level filter is deployed on the third layer of the antenna section PCB board, and the array antenna is deployed on the bottom layer of the antenna section PCB board.

3. The tile-type phased array surface according to claim 2, characterized in that, The board-level filter is deployed in the form of a stripline on the third layer of the PCB board of the antenna section.

4. The tile-type phased array surface according to claim 3, characterized in that, The metallized vias include: coaxial vias and blind vias; wherein, the feed point of the patch antenna is directly connected to the LNA chip through a coaxial via; the LNA chip is connected to the board-level filter through a blind via, the board-level filter is connected to the BFIC chip through a blind via, and the BFIC chip is connected to the power divider network through a blind via.

5. The tile-type phased array surface according to claim 4, characterized in that, A BFIC chip is placed at the center of every four patch antennas, and four LNA chips surround each BFIC chip. The input terminal of each LNA chip coincides with the two feed points of the corresponding patch antenna and is directly connected through a coaxial via.

6. The tile-type phased array surface according to claim 5, characterized in that, The spacing between the patch antennas is determined by the operating frequency of the tile-type phased array.

7. The tile-type phased array surface according to claim 6, characterized in that, The tile-type phased array also includes a non-antenna PCB board, which includes a power module, a control module, and an external interface. The power module is used to supply power to the Watt-type phased array. The control module is used to control the Watt-type phased array. The external interface is used for external communication.

8. The tile-type phased array surface according to claim 7, characterized in that, The BFIC chip is an 8-channel BFIC chip. When the Watt-type phased array is working, the RF link corresponding to each channel receives RF signals through the patch antenna. The RF signals pass through a coaxial via and enter the LNA chip for low-noise amplification. The amplified RF signals pass through a blind via and enter the board-level filter for interference filtering. The filtered RF signals pass through a blind via and enter the BFIC chip for beamforming. Then, the BFIC chip combines the beams corresponding to the 8 channels into one output to the power divider network. The power divider network then combines the beams output by each BFIC chip into one to obtain a directional receiving beam, which is then output to the outside through the external interface.

9. The tile-type phased array surface according to claim 8, characterized in that, The operating conditions of the patch antenna include: beam scanning angle and ambient temperature drift.

10. An electronic device, characterized in that, The electronic device includes the Watt-type phased array as described in any one of claims 1-9.

Images