Linear voltage-to-time converter circuit supporting rail-to-rail input and implementation method

Abstract

The invention discloses a linear voltage-time converter circuit supporting rail-to-rail input and an implementation method. The circuit structurally comprises a main input branch, an auxiliary input branch, a differential output node, an output buffer stage and a reset module. The non-linearity of the first differential pair of the main input branch is compensated through the auxiliary input branch, and the compression non-linearity of the voltage-time transmission characteristic of the auxiliary input branch and the expansion non-linearity of the voltage-time transmission characteristic of the main input branch are approximately offset in a wide input voltage range. Therefore, good linearity can be maintained under high input voltage swing. According to the invention, a full parallel structure is adopted, the design is simple, and the robustness is high; the linear input range is expanded to the whole power rail, the problem of distortion under large signal input is solved, the available input dynamic range of the circuit is greatly widened, the gain is adjustable, and the circuit is suitable for various application scenes needing high-linearity large signal processing.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, specifically relating to signal processing and conversion circuit technology, and particularly to a linear voltage-to-time converter circuit that supports rail-to-rail input, which is a voltage-to-time converter (VTC) with a wide linear input range. Background Technology

[0002] A voltage-to-time converter is a core circuit unit that linearly converts analog voltage signals into time signals (such as pulse width or delay). It has wide applications in time-domain signal processing, high-speed communication interfaces, precision measuring instruments, and analog-to-digital conversion systems.

[0003] Common existing voltage-to-time converter technologies are based on the principle of constant current discharge. Their basic structure typically includes: an input differential pair transistor, a constant current source, a switch, and a load capacitor. The working principle is as follows: During the reset phase, the switch is open, and the load capacitor is pre-charged to an initial voltage; during the conversion phase, the switch is open, and the input differential pair differentially distributes the current of the constant current source according to the input voltage to be converted, thereby generating a discharge current related to the input voltage. This current discharges the load capacitor. The time required for the capacitor voltage to drop to a preset threshold voltage is the conversion result.

[0004] However, an inherent drawback of this structure is the severe coupling between its input voltage swing and conversion linearity. When the input voltage swing is too large, the conversion linearity deteriorates significantly. When the input voltage swing is too large, one transistor in the input differential pair may approach or even enter the cutoff region due to an insufficient gate-source voltage, resulting in an insufficient output current. Consequently, the load capacitor voltage cannot drop to the preset threshold voltage, causing the time edge to fail to generate or to take an excessively long time to generate, severely disrupting the linearity of the discharge process. Therefore, traditional voltage-to-time converters cannot simultaneously achieve both wide input swing and high conversion linearity, greatly limiting their deployment in high-performance applications. Summary of the Invention

[0005] This invention aims to solve the technical problem of the mutual constraint between input voltage swing and conversion linearity in existing voltage-to-time converter circuits, and provides a linear voltage-to-time converter circuit and implementation method that supports rail-to-rail input. It designs a voltage-to-time converter circuit structure that can achieve good linearity under high input voltage swing and realize rail-to-rail linear input range.

[0006] The core of this invention lies in compensating for the nonlinearity of the first differential pair (including positive and negative differential inputs) of the main input branch through an auxiliary input branch. Traditional voltage-to-time converters only have a main input branch and lack the auxiliary input branch proposed in this invention. When the input voltage swing increases, for example, when the positive differential input V of the main input branch increases... in+ The differential input V at the negative terminal of the main input branch is close to the power supply voltage. in- When the voltage approaches ground, the NMOS transistor at the negative end of the first differential pair in the main input branch tends to saturate or even enter the linear region, slowing the growth of its discharge current. Simultaneously, the NMOS transistor at the negative end of the first differential pair in the main input branch enters the cutoff region, causing the discharge current to approach zero. The voltage change at the negative output node in the differential output node is slow, and the connected output buffer stage requires a longer time to generate a level transition, resulting in an excessively large output edge time difference and causing expansive nonlinearity in the output time. In this invention, the auxiliary input branch connected in parallel with the main input branch plays a crucial role in improving the output linearity under large-swing voltage inputs. The source follower of the auxiliary input branch itself has compressive nonlinear voltage transfer characteristics and DC level shift characteristics. The voltage input of the voltage-to-time converter is applied to the gate of the second differential input pair after being processed by the source follower with compressive nonlinearity and DC level shift characteristics. At the differential output node, the first discharge current from the main input branch and the second discharge current from the auxiliary input branch are added together. With proper configuration of the width-to-length ratio (W / L) of the first differential input pair, the second differential input pair, and the source follower, the compressive nonlinearity of the voltage-time transfer characteristic of the auxiliary input branch and the expansive nonlinearity of the voltage-time transfer characteristic of the main input branch can be approximately canceled out over a wide input voltage range. Furthermore, by adjusting the source follower bias current I... B It can change the magnitude of the DC level shift of the source follower, thereby changing the magnitude of the second discharge current, and can adjust the gain of the entire voltage-time converter circuit.

[0007] In this technical solution, in order to achieve approximate compensation of the compressive and expansive nonlinear characteristics, it is necessary to scan and configure the design parameters of the width-to-length ratio (W / L) of the first differential input pair transistor and the second differential input pair transistor, as well as the width-to-length ratio (W / L) of the source follower. The transmission characteristic relationship between the input voltage and the output square wave time is simulated, and the set of parameters with the smallest nonlinearity of the transmission characteristic relationship is taken as the final design parameters. At this time, the compressive nonlinearity generated by the auxiliary input branch and the expansive nonlinearity generated by the main input branch can be approximately equal in amplitude and opposite in trend, achieving first-order cancellation of nonlinearity. Thus, the present invention can maintain good linearity under high input voltage swing.

[0008] The implementation method of the linear voltage-to-time converter circuit supporting rail-to-rail input provided by the present invention includes the following steps:

[0009] 1) An auxiliary input branch is set up in parallel with the main input branch for signal splitting and preprocessing, and the design parameters of the circuit transistors are scanned and configured:

[0010] The main input branch includes a first differential input pair; the auxiliary input branch includes a pair of source followers and a second differential input pair. The source followers receive the externally input differential voltage signal, perform a DC level shift on it, and output it to the second differential input pair. The second differential input pair generates a second discharge current based on the level-shifted signal. The transfer characteristic from the input voltage of the source follower to its output voltage (i.e., the input voltage of the second differential input pair) exhibits a compressive nonlinearity.

[0011] The externally input differential voltage signal is simultaneously applied to the first differential input pair of the main input branch and the source follower of the auxiliary input branch. The source follower is used to DC-shift the input signal, and the shifted signal is transmitted to the second differential input pair. The design parameters of the width-to-length ratio (W / L) of the transistors of the first and second differential input pairs and the width-to-length ratio (W / L) of the source follower are scanned and configured. The transmission characteristic relationship between the input voltage and the output time signal is simulated. The set of parameters with the smallest nonlinearity of the transmission characteristic relationship is taken as the final design parameters. At this time, the compression nonlinearity generated by the auxiliary input branch and the expansion nonlinearity generated by the main input branch can be approximately equal in amplitude and opposite in trend, realizing the approximate linearization of the final voltage to time signal transfer function.

[0012] 2) Complementary nonlinear current generation: The first differential input pair generates a first discharge current based on the input voltage signal; at the same time, the second differential input pair with configured design parameters (width-to-length ratio and bias state) generates a second discharge current based on the signal after DC level shift.

[0013] 3) Current superposition: The first discharge current and the second discharge current are superimposed at the differential output node of the circuit to obtain the total discharge current;

[0014] 4) Time signal conversion: The total discharge current is used to discharge the load capacitor connected to the differential output node. When the capacitor voltage drops to the preset output buffer stage threshold voltage, a rising or falling edge is generated, thereby converting the voltage signal into a time signal. The input voltage and the output time signal have an approximately linear relationship.

[0015] 5) Gain Adjustment: By adjusting the bias current of the source follower in the auxiliary input branch, the operating point and DC level shift of the source follower are changed, and the overall voltage-to-time conversion gain is fine-tuned according to the application scenario and purpose of the voltage-to-time converter circuit.

[0016] In specific implementation, the present invention utilizes the above method to realize a linear voltage-to-time converter circuit that supports rail-to-rail input, characterized by:

[0017] Main input branch: Includes a first differential input pair for receiving a differential voltage signal from an external input and generating a first discharge current based on that signal. The first differential input pair exhibits an expansive nonlinear transmission characteristic from input voltage to output time under large signal input conditions.

[0018] Auxiliary input branch: Connected in parallel with the main input branch, it includes a pair of source followers and a second differential input pair. The source followers receive the differential voltage signal from the external input, perform DC level shifting on it, and output it to the second differential input pair. The second differential input pair generates a second discharge current based on the level-shifted signal. The transfer characteristic from the input voltage of the source followers to their output voltage (i.e., the input voltage of the second differential input pair) exhibits compressive nonlinearity, which is the opposite of the expansive nonlinearity of the voltage-time transfer characteristic of the main input branch.

[0019] Differential Output Nodes: Each output node in a pair of differential output nodes is connected to a load capacitor. The first discharge current generated by the main input branch and the second discharge current generated by the auxiliary input branch converge and superimpose at the differential output nodes. The compressive nonlinearity of the source follower in the auxiliary input branch is used to approximately compensate for the expansive nonlinearity of the main input branch, jointly discharging the load capacitor. This results in a decreasing ramp voltage at each of the positive and negative differential output nodes. The larger the input voltage, the greater the slope of the ramp voltage at the differential output node.

[0020] Output buffer stage: Composed of multiple cascaded inverters or buffers, with the aforementioned differential output node as its input. It is used to shape the ramp voltage on the differential output node, generating a steep rising or falling edge when the ramp voltage passes the threshold voltage of the inverter or buffer, thus obtaining the final time signal represented by the time difference between the rising or falling edges.

[0021] The reset module includes a pair of reset switches and a switching current source. The pair of reset switches are respectively connected to the differential output node and the power supply voltage. One end of the switching current source is connected to the source terminals of the first and second differential pairs, and the other end is connected to ground. During voltage-to-time converter reset, the pair of reset switches close, pre-charging the load capacitor of the differential output node to the power supply voltage. This prepares the load capacitor for discharge current generated by the first and second differential pairs during voltage-to-time converter operation. Simultaneously, the switching current source opens, disconnecting the path from the first and second differential pairs to ground, reducing power consumption during reset. During voltage-to-time converter operation, the reset switches open to avoid interfering with the load capacitor discharge; simultaneously, the switching current source closes, providing a path to ground for the discharge current generated by the first and second differential pairs.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] This invention provides a linear voltage-to-time converter circuit and implementation method supporting rail-to-rail input. By compensating for the nonlinearity of the first differential pair of the main input branch through an auxiliary input branch, the compression nonlinearity of the voltage-to-time transfer characteristics of the auxiliary input branch and the expansion nonlinearity of the voltage-to-time transfer characteristics of the main input branch are approximately canceled out over a wide input voltage range. This allows the invention to maintain good linearity even with high input voltage swings. The technical advantages of this invention include:

[0024] Significantly widens the input voltage range: By introducing a parallel auxiliary input branch with a source follower, its compressive nonlinearity is used to compensate for the expansive nonlinearity of the main input branch, cleverly solving the distortion problem of traditional voltage-time converters under large signal input. The linear input range is extended to the entire power rail (rail-to-rail), greatly widening the circuit's usable input dynamic range and making it suitable for various application scenarios that require high linearity to process large signals.

[0025] Simple and effective structure: This invention adopts a fully parallel structure, which achieves linearization by canceling out the inherent characteristics of the devices, avoiding complex feedback loops or post-processing correction algorithms. The design is simple and robust.

[0026] Adjustable gain: It retains control over the source follower bias current, provides an interface for calibrating the voltage-to-time converter gain, and enhances the circuit's adaptability to process, voltage, and temperature (VT) variations. Attached Figure Description

[0027] Figure 1This is a schematic diagram of a voltage-to-time converter circuit according to an embodiment of the present invention.

[0028] Figure 2 This is a timing diagram of a voltage-to-time converter circuit according to an embodiment of the present invention. Detailed Implementation

[0029] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but this does not limit the scope of the present invention in any way.

[0030] This invention provides a linear voltage-to-time converter circuit supporting rail-to-rail input and its implementation method, comprising the following steps:

[0031] 1) An auxiliary input branch is set up in parallel with the main input branch for signal splitting and preprocessing, and the design parameters of the circuit transistors are scanned and configured:

[0032] The main input branch includes a first differential input pair; the auxiliary input branch includes a pair of source followers and a second differential input pair. The source followers receive the externally input differential voltage signal, perform a DC level shift on it, and output it to the second differential input pair. The second differential input pair generates a second discharge current based on the level-shifted signal. The transfer characteristic from the input voltage of the source follower to its output voltage (i.e., the input voltage of the second differential input pair) exhibits a compressive nonlinearity.

[0033] The externally input differential voltage signal is simultaneously applied to the first differential input pair of the main input branch and the source follower of the auxiliary input branch. The source follower is used to DC-shift the input signal, and the shifted signal is transmitted to the second differential input pair. The design parameters of the width-to-length ratio (W / L) of the transistors of the first and second differential input pairs and the width-to-length ratio (W / L) of the source follower are scanned and configured. The transmission characteristic relationship between the input voltage and the output time signal is simulated. The set of parameters with the smallest nonlinearity of the transmission characteristic relationship is taken as the final design parameters. At this time, the compression nonlinearity generated by the auxiliary input branch and the expansion nonlinearity generated by the main input branch can be approximately equal in amplitude and opposite in trend, realizing the approximate linearization of the final voltage to time signal transfer function.

[0034] 2) Complementary nonlinear current generation: The first differential input pair generates a first discharge current based on the input voltage signal; at the same time, the second differential input pair with configured design parameters (width-to-length ratio and bias state) generates a second discharge current based on the signal after DC level shift.

[0035] 3) Current superposition: The first discharge current and the second discharge current are superimposed at the differential output node of the circuit to obtain the total discharge current;

[0036] 4) Time signal conversion: The total discharge current is used to discharge the load capacitor connected to the differential output node. When the capacitor voltage drops to the preset output buffer stage threshold voltage, a rising or falling edge is generated, thereby converting the voltage signal into a time signal. The input voltage and the output time signal have an approximately linear relationship.

[0037] 5) Gain Adjustment: By adjusting the bias current of the source follower in the auxiliary input branch, the operating point and DC level shift of the source follower are changed, and the overall voltage-to-time conversion gain is fine-tuned according to the application scenario and purpose of the voltage-to-time converter circuit.

[0038] In specific implementation, the present invention utilizes the above method to realize a linear voltage-to-time converter circuit that supports rail-to-rail input, and the circuit structure is described in detail below.

[0039] like Figure 1 As shown in the figure, the rail-to-rail input voltage-time converter circuit provided by the embodiment of the present invention mainly consists of a main input branch (first differential input pair), two auxiliary input branches connected in parallel with DC level shift (including a pair of source followers and a second differential input pair), a pair of reset switches, a switching current source, two load capacitors, and an output buffer stage.

[0040] The main input branch consists of NMOS transistors M1 and M2 of the first differential input pair. Their gates receive the external differential input voltage signal V. in+ and V in- Their sources are connected to the drain of the switching current source, and their drains are connected to the differential output node V. out+ and V out- This differential pair is the core component for voltage-to-time conversion. Its function is to generate the first discharge current based on the input signal. However, under large input swings, it can cause an expanding nonlinearity in the output time. The switching current source is composed of an NMOS transistor M9, whose gate receives a control clock signal Φ. vtc The switching current source NMOS transistor M9 is used to turn on during the switching phase to provide current to the entire circuit, and to turn off during the reset phase.

[0041] An auxiliary input branch (positive terminal) with DC level shift is connected in parallel with the positive terminal of the main input branch (i.e., the positive terminal NMOS transistor M1 of the first differential input pair) to compensate for its nonlinearity. It includes a source follower consisting of a positive-terminal source follower input transistor (NMOS transistor M3) and a current mirror load (PMOS transistor M...). 10 PMOS transistor M 11 It is composed of ( ). The gate of the positive terminal source follower input transistor M3 receives the input signal V.in+ Current mirror loaded PMOS transistor M 10 and PMOS transistor M 11 bias current I B (Source bias current) is generated by a separate current source, and the gate bias voltage V of the current mirror load is... B PMOS transistor M 10 The diode connection structure is generated. The source follower generates a DC-level-shifted and compressively nonlinear positive input signal of the second differential pair at its output (the source of the source follower input transistor M3). This branch also includes an NMOS transistor M5 at the positive terminal of the second differential input pair, whose gate receives the signal from the source of the positive source follower input transistor M3, whose source is connected to the source of the NMOS transistors M1 and M2 of the first differential input pair, and whose drain is connected to the drain of the NMOS transistor M1 of the first differential input pair (i.e., V). out+ The auxiliary branch (negative terminal) with DC level shift is completely symmetrical to the positive branch and is connected in parallel with the negative terminal NMOS transistor M2 of the first differential input pair. The auxiliary branch (negative terminal) with DC level shift consists of the source follower input transistor (NMOS transistor M4) and the current mirror load PMOS transistor M... 12 And the second differential input pair negative terminal NMOS transistor M6 is used to process the input signal V. in- The same processing is performed as for the auxiliary branch with DC level shift at the positive terminal. The NMOS transistor M5 at the positive terminal of the second differential input pair and the NMOS transistor M6 at the negative terminal of the second differential input pair form the second differential input pair. Their gates receive the output from the source follower and generate a second discharge current based on this signal.

[0042] Output node at Figure 1 This is reflected in the difference node V. out+ and V out- With V out+ For example, this node is connected to a load capacitor to ground. The first discharge current from the main input branch (generated by NMOS transistor M1 at the positive terminal of the first differential input pair) and the second discharge current from the auxiliary input branch (generated by NMOS transistor M5 at the positive terminal of the second differential input pair) converge at this node to discharge the load capacitor. The gates of PMOS transistors M7 and M8, which act as reset switches, receive the control clock signal Φ. vtc Used during the reset phase (control clock signal Φ) vtc (When low) the output node V is turned on. out+ and V out- Pull up to the power supply voltage to complete the reset.

[0043] The output buffer stage consists of two pairs of cascaded inverters and buffers, used to output differential output node V. out+ and V out- The analog voltage ramp is shaped to generate a time signal T with steep rising and falling edges. out+ and T out- .

[0044] Workflow and Implementation Methods

[0045] The operation of this circuit is controlled by the clock signal Φ. vtc The control is mainly divided into the voltage-to-time converter reset stage and the voltage-to-time conversion stage, such as... Figure 2 The timing diagram is shown.

[0046] During the voltage-to-time converter reset phase, i.e., the control clock signal Φ vtc When the voltage is low (times t < t1 and t > t1), the switching current source NMOS transistor M9 is turned off, and the reset switching transistors PMOS transistors M7 and M8 are turned on, switching the differential output node V... out+ and V out- The voltage is quickly pulled up to the positive supply voltage. At this time, the output T of the output buffer stage... out+ and T out- All are low level.

[0047] During the voltage-to-time conversion phase (time t1 < t < t4), the control clock signal Φ vtc The signal transitions to a high level. The reset switches PMOS transistors M7 and M8 are turned off, while the switching current source NMOS transistor M9 is turned on, providing a ground return node for the voltage-to-time converter. Assume the input differential voltage V... in+ > V in- The total current will be asymmetrically distributed between the positive and negative terminals of the circuit. The total current flowing through the positive terminal (NMOS transistor M2 at the positive terminal of the first differential input pair and NMOS transistor M5 at the positive terminal of the second differential input pair) is greater than that flowing through the negative terminal (NMOS transistor M2 at the negative terminal of the first differential input pair and NMOS transistor M6 at the negative terminal of the second differential input pair). Therefore, the positive terminal output node V in the differential output node... out+ The discharge speed will be faster than that of the negative output node V. out- The voltages at the two nodes begin to drop from the supply voltage, but the slopes of the drop are different, and the difference in slopes is related to the input differential voltage (V). in+ -V in- They are positively correlated.

[0048] The generation process of the time signal is as follows: At time t2, the positive output node V of the differential output node with the faster descent rate... out+First, the inverter's threshold voltage is reached, causing its corresponding output time signal T to... out+ The signal transitions from low to high. At time t3, the negative output node V in the differential output node with the slower falling speed... out- When the threshold voltage of the inverter is reached, its output time signal T out- It also jumps to a high level. The final voltage-to-time conversion result can be represented by the edge time difference (t3 - t2) between the two time signals mentioned above. This time difference is related to the input differential voltage V. in+ - V in- The relationship is approximately linear. At time t4, the control clock signal Φ... vtc Returning to a low level signifies the end of the transition, and the circuit enters the next reset phase.

[0049] In summary, this invention proposes an innovative voltage-to-time converter architecture. Its core innovation lies in connecting an auxiliary input branch, comprising a source follower and a second differential input pair, in parallel with the main input branch (consisting of a first differential input pair). This invention utilizes the inherent compressive nonlinearity of the source follower to first-order cancel the expansive nonlinear voltage-to-time transmission characteristics generated by the first differential input pair under large signal inputs. This hardware compensation design achieves true rail-to-rail linear input without adding complex calibration algorithms and feedback loops, thereby enhancing the application value of voltage-to-time converters in high-performance signal processing.

[0050] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A method for implementing a linear voltage-to-time converter circuit supporting rail-to-rail input, characterized in that, Includes the following steps: 1) An auxiliary input branch is set up in parallel with the main input branch to perform signal splitting and preprocessing, and to scan and configure the design parameters of the circuit transistors; The main input branch includes the first differential input pair; The auxiliary input branch includes a pair of source followers and a second differential input pair; the source followers are used to receive the differential voltage signal from the external input, perform DC level shifting, and output to the second differential input pair; The second differential input pair generates a second discharge current based on the level-shifted signal; the transfer characteristics from the input voltage of the source follower to the output voltage of the source follower exhibit compressive nonlinearity; The design parameters of the first differential input pair transistor, the second differential input pair transistor, and the source follower are scanned and configured, and the transmission characteristics of the input voltage and the output time signal are simulated. 2) Generate complementary nonlinear current: The first differential input pair generates a first discharge current based on the input voltage signal; at the same time, the second differential input pair with configured design parameters generates a second discharge current based on the signal after DC level shift. 3) Current superposition: The first discharge current and the second discharge current are superimposed at the differential output node of the circuit to obtain the total discharge current; 4) Time signal conversion: The total discharge current is used to discharge the load capacitor connected to the differential output node, converting the voltage signal into a time signal; the input voltage and the output time signal have an approximately linear relationship. 5) Gain Adjustment: By adjusting the bias current of the source follower in the auxiliary input branch, the operating point and DC level shift of the source follower are changed, and the overall voltage-to-time conversion gain is fine-tuned.

2. The method for implementing the linear voltage-to-time converter circuit supporting rail-to-rail input as described in claim 1, characterized in that, In step 1), the externally input differential voltage signal is applied simultaneously to the first differential input pair of the main input branch and the source follower of the auxiliary input branch; the source follower is used to perform DC level shifting on the input signal, and the shifted signal is transmitted to the second differential input pair.

3. The method for implementing the linear voltage-to-time converter circuit supporting rail-to-rail input as described in claim 1, characterized in that, Design parameters include aspect ratio and offset state.

4. The method for implementing the linear voltage-to-time converter circuit supporting rail-to-rail input as described in claim 1, characterized in that, Specifically, the set of parameters with the smallest nonlinearity in the transmission characteristic relationship is selected as the final design parameters.

5. The method for implementing the linear voltage-to-time converter circuit supporting rail-to-rail input as described in claim 1, characterized in that, In step 4), specifically, when the capacitor voltage drops to the preset output buffer stage threshold voltage, a rising edge or falling edge is generated to convert the voltage signal into a time signal.

6. The method for implementing the linear voltage-to-time converter circuit supporting rail-to-rail input as described in claim 1, characterized in that, In step 3), the first discharge current generated by the main input branch and the second discharge current generated by the auxiliary input branch converge and superimpose at the differential output node, jointly discharging the load capacitor and forming a ramp voltage that decreases with time at the differential output node; the larger the input voltage, the greater the slope of the ramp voltage at the differential output node.

7. A linear voltage-to-time converter circuit supporting rail-to-rail input implemented using the method of claim 1, characterized in that, include: The system consists of a main input branch, an auxiliary input branch, a differential output node, an output buffer stage, and a reset module; among which: The main input branch includes a first differential input pair for receiving a differential voltage signal from an external input and generating a first discharge current based on the signal. Auxiliary input branch: Connected in parallel with the main input branch, it includes a pair of source followers and a second differential input pair; Differential output node: Each output node in a pair of differential output nodes is connected to a load capacitor; the differential output node combines the first discharge current and the second discharge current to form a ramp voltage that decreases over time. Output buffer stage: Composed of multiple cascaded inverters or buffers, used to shape the ramp voltage on the differential output node, and generate a steep rising edge or falling edge when the ramp voltage passes the threshold voltage of the inverter or buffer, so as to obtain the final time signal represented by the time difference between the rising edge or falling edge. Reset module: includes a pair of reset switches and a switching current source; the pair of reset switches are respectively connected to the differential output node to the power supply voltage, and one end of the switching current source is connected to the source end of the first differential pair and the second differential pair, and the other end is connected to the ground voltage.

8. The linear voltage-to-time converter circuit supporting rail-to-rail input as described in claim 7, characterized in that, When the voltage-time converter is reset, the pair of reset switches close to precharge the load capacitor of the differential output node to the power supply voltage, in preparation for the discharge current generated by the first differential pair and the second differential pair during the operation of the voltage-time converter to discharge the load capacitor; at the same time, the switch current source is turned off to disconnect the path from the first differential pair and the second differential pair to ground.

9. The linear voltage-to-time converter circuit supporting rail-to-rail input as described in claim 8, characterized in that, When the voltage-time converter is operating, the reset switch is open to avoid interfering with the discharge of the load capacitor; at the same time, the switch current source is closed to provide a path to ground for the discharge current generated by the first differential pair and the second differential pair.

Images