Offshore underground high-frequency wireless communication device

Abstract

The invention relates to an offshore underground high-frequency wireless communication device which comprises a transmitting unit and a receiving unit. The transmitting unit comprises a transmitting master control module, a transmitting circuit and a transmitting coil; the receiving unit comprises a receiving coil, a receiving circuit and a receiving main control module; the emission master control module controls the emission circuit to start and stop according to needs and outputs a coded modulation signal; the transmitting circuit carries out push-pull driving and resonance processing on the coded modulation signal and then loads the coded modulation signal to a transmitting coil to generate an alternating magnetic field; the receiving coil induces a signal of the alternating magnetic field and outputs an induction signal; the receiving circuit amplifies, filters and shapes the induction signal and then outputs a sampling signal; and the receiving master control module demodulates and processes the sampling signal to obtain a wireless receiving signal. The problem that data transmission between two short sections can be achieved only through traditional integrated manufacturing or mutual communication is solved, the problem that the working endurance time of an underground circuit is short under the battery power supply condition can also be solved, and reliable transmission of underground data is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of marine exploration technology, and more specifically, to a high-frequency wireless communication device for offshore wells. Background Technology

[0002] During offshore exploration well operations, it is necessary to collect various downhole parameters such as pressure and temperature in real time and reliably transmit the data to the wellhead system. In some cases, due to environmental limitations, complex mechanical structures, or certain construction techniques, data acquisition and data transmission tools cannot be directly interconnected. Under such conditions, wireless transmission is required to complete the data transfer between different downhole instruments and tools.

[0003] Currently, two common wireless communication methods used in wells are low-frequency carrier and high-frequency carrier. Low-frequency methods have a longer transmission distance but higher power consumption, making them suitable for long-distance, low-data-volume applications. High-frequency methods have a shorter communication distance but lower power consumption, making them suitable for short-distance, high-data-volume applications. Therefore, considering both reliability and endurance, mature technologies for downhole data transmission are not yet widely used in offshore well drilling and formation testing operations. For example, traditional solutions require integrated manufacturing or interconnection between measurement and communication sub-sections to achieve data transmission between them. Furthermore, downhole circuits have short operating times under battery power, compromising reliable data transmission. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-frequency wireless communication device for offshore wells, addressing the problems existing in the prior art.

[0005] The technical solution adopted by this invention to solve its technical problem is: to construct a high-frequency wireless communication device for offshore wells, comprising: a transmitting unit and a receiving unit; the transmitting unit comprises: a transmitting main control module, a transmitting circuit, and a transmitting coil; the receiving unit comprises: a receiving coil, a receiving circuit, and a receiving main control module; The transmitting main control module, the transmitting circuit, and the transmitting coil are connected in sequence; the receiving coil, the receiving circuit, and the receiving main control module are connected in sequence. The main control module for transmitting is used to control the transmitting circuit to start and stop as needed, wake up at regular intervals, and read data from external sensors, and output coded modulation signals to the transmitting circuit based on the data from the external sensors; the transmitting circuit is used to apply the coded modulation signals to the transmitting coil after push-pull driving and resonance processing, and generate an alternating magnetic field through the transmitting coil; The receiving coil is used to sense the signal of the alternating magnetic field and output a corresponding induced signal to the receiving circuit; the receiving circuit amplifies, filters and shapes the induced signal and outputs a sampled signal to the receiving main control module; the receiving main control module is used to demodulate and process the sampled signal to obtain a wireless received signal.

[0006] In the offshore downhole high-frequency wireless communication device of the present invention, the transmitting circuit includes: a push-pull drive circuit, a signal transformer and a resonant circuit; The push-pull drive circuit, the signal transformer, and the resonant circuit are connected in sequence, and the input terminal of the push-pull drive circuit is connected to the transmitting main control module, and the output terminal of the resonant circuit is connected to the transmitting coil. The push-pull drive circuit amplifies the voltage of the encoded modulation signal and outputs a large current alternating signal to the signal transformer. The secondary winding of the signal transformer, the resonant circuit, and the transmitting coil form an LC resonant circuit to generate the alternating magnetic block according to the set operating frequency.

[0007] In the offshore downhole high-frequency wireless communication device of the present invention, the push-pull drive circuit includes: a first DC blocking capacitor, a second DC blocking capacitor, a first current limiting resistor, a second current limiting resistor, a first drive transistor, a second drive transistor, a first output MOS transistor, and a second output MOS transistor; the resonant circuit includes: a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The base of the first driving transistor is connected to the first output terminal of the transmitting main control module through the first current-limiting resistor and the first DC blocking capacitor in sequence. The base of the second driving transistor is connected to the second output terminal of the transmitting main control module through the second current-limiting resistor and the second DC blocking capacitor in sequence. The collector of the first driving transistor is connected to the gate of the first output MOS transistor, and the emitter of the first driving transistor is grounded. The collector of the second driving transistor is connected to the gate of the second output MOS transistor, and the emitter of the second driving transistor is grounded. The source of the first output MOS transistor is grounded, and the drain of the first output MOS transistor is connected to the first input terminal of the primary winding of the signal transformer. The source of the second output MOS transistor is grounded, and the drain of the second output MOS transistor is connected to the second input terminal of the primary winding of the signal transformer. The first terminal of the first capacitor is connected to the first output terminal of the secondary winding of the signal transformer, the second terminal of the first capacitor is connected to the second output terminal of the secondary winding of the signal transformer, the second capacitor, the third capacitor and the fourth capacitor are connected in parallel with the first capacitor in sequence, the first terminal of the fourth capacitor is connected to the first terminal of the transmitting coil, and the second terminal of the fourth capacitor is connected to the second terminal of the transmitting coil.

[0008] In the offshore downhole high-frequency wireless communication device of the present invention, the transmitting main control module includes: a transmitting main control unit and a transmitting power management module; the transmitting power management module is connected to the transmitting main control unit, the transmitting circuit and the first battery respectively. The main control unit for transmitting is used to control the transmitting circuit to start and stop as needed, wake it up at regular intervals, read the data from the external sensor, and output an encoded modulation signal to the transmitting circuit based on the data from the external sensor. The transmission power management module is used to provide power or cut off power supply according to the control of the transmission master control unit.

[0009] In the offshore downhole high-frequency wireless communication device of the present invention, the transmitting main control unit includes: a first main control MCU and a first FPGA module; the transmitting power management module includes: a transmitting power switch circuit, a first transmitting switch circuit, a second transmitting switch circuit and a third transmitting switch circuit; The first main control MCU is connected to the first FPGA module. The transmit power switch circuit is connected to the first main control MCU, the second transmit switch circuit, the third transmit switch circuit and the first battery respectively. The first transmit switch circuit is connected to the first battery and the first main control MCU respectively. The second transmit switch circuit is connected to the transmit circuit. The third transmit switch circuit and the transmit power switch circuit are connected to the first FPGA module. The first main control MCU is used to control the transmitting circuit to start and stop as needed, wake it up at regular intervals, and read the data from the external sensor, and send an input signal to the first FPGA module based on the data from the external sensor; the first FPGA module is used to encode and modulate the input and output the encoded and modulated signal to the transmitting circuit; The transmit power switch circuit is used to control the power supply of the second transmit switch circuit and the third transmit switch circuit according to the control signal of the first master control MCU, and to supply power to the first FPGA module; the first transmit switch circuit is used to supply power to the first master control MCU, the second transmit switch circuit is used to supply power to the transmit circuit, and the third transmit switch circuit is used to supply power to the first FPGA module.

[0010] In the offshore downhole high-frequency wireless communication device of the present invention, the transmitting power switch circuit includes: a thirtieth resistor, a fifth transistor, a sixth MOSFET, and a seventh MOSFET; the first transmitting switch circuit includes: a first conversion chip; the second transmitting switch circuit includes: a second conversion chip; and the third transmitting switch circuit includes: a third conversion chip. The base of the fifth transistor is connected to the first main control MCU through the thirtieth resistor. The emitter of the fifth transistor is grounded. The collector of the fifth transistor is connected to the first battery through the twenty-eighth resistor. The collector of the fifth transistor is also connected to the gate of the sixth MOS transistor and the gate of the seventh MOS transistor. The source of the sixth MOS transistor is connected to the first battery. The drain of the sixth MOS transistor is connected to the power supply input terminal of the second conversion chip and the power supply input terminal of the third conversion chip. The source of the seventh MOS transistor is connected to the power supply output terminal of the first conversion chip, and the drain of the seventh MOS transistor is connected to the first FPGA module; the power supply input terminal of the first conversion chip is connected to the first battery, the power supply output terminal of the second conversion chip is connected to the transmitting circuit, and the power supply output terminal of the third conversion chip is connected to the first FPGA module.

[0011] In the offshore downhole high-frequency wireless communication device of the present invention, the receiving circuit includes: a first-stage amplifier circuit, a second-stage amplifier circuit, a first-stage filter circuit, a second-stage filter circuit, a third-stage amplifier circuit, and a shaping circuit. The first-stage amplifier circuit, the second-stage amplifier circuit, the first-stage filter circuit, the second-stage filter circuit, the third-stage amplifier circuit, and the shaping circuit are sequentially connected between the receiving coil and the receiving main control module. The first-stage amplifier circuit is used to invert and amplify the induced signal output by the receiving coil; The second-stage amplifier circuit is used to amplify the signal after it has been inverted and amplified by the first-stage amplifier circuit a second time. The first-stage filter circuit is used to perform low-pass filtering; The second-stage filter circuit is used to perform high-pass filtering; The third-stage amplifier circuit is used to amplify the signal after it has been filtered by the second-stage filter circuit; The shaping circuit is used to shape the signal amplified by the third-stage amplifier circuit to obtain the sampled signal.

[0012] In the offshore downhole high-frequency wireless communication device of the present invention, the receiving main control module includes: a receiving main control unit and a receiving power management module; the receiving power management module is connected to the receiving main control unit, the receiving circuit and the second battery respectively; The receiving main control unit is used to demodulate and process the sampled signal to obtain a wireless received signal; The receiving power management module is used to provide power or cut off power supply according to the control of the receiving main control unit.

[0013] In the offshore downhole high-frequency wireless communication device of the present invention, the receiving main control unit includes: a second main control MCU and a second FPGA module; the receiving power management module includes: a receiving power switch circuit, a first receiving switch circuit, a second receiving switch circuit and a third receiving switch circuit; The second main control MCU is connected to the second FPGA module. The receiving power switch circuit is connected to the second main control MCU, the second receiving switch circuit, the third receiving switch circuit and the second battery respectively. The first receiving switch circuit is connected to the second battery and the second main control MCU respectively. The second receiving switch circuit is connected to the second main control MCU. The receiving power switch circuit and the third receiving switch circuit are connected to the second FPGA module respectively. The second main control MCU is used to control the on / off state of the receiving power switch circuit and to parse and process the sample before transmitting it to the second FPGA module. The second FPGA module is used to demodulate and process the sampled signal transmitted by the second main control MCU and then output the wireless received signal. The receiving power switch circuit is used to control the power supply of the second receiving switch circuit and the third receiving switch circuit according to the control signal of the second main control MCU, and to supply power to the second FPGA module; the first receiving switch circuit is used to supply power to the second main control MCU, the second receiving switch circuit is used to supply power to the operational amplifier in the second main control MCU, and the third receiving switch circuit is used to supply power to the second FPGA module.

[0014] In the offshore downhole high-frequency wireless communication device of the present invention, the receiving power switch circuit includes: a twenty-seventh resistor, an eighth transistor, a ninth MOSFET, and a tenth MOSFET; the first receiving switch circuit includes: a fourth conversion chip; the second receiving switch circuit includes: a fifth conversion chip; and the third receiving switch circuit includes: a sixth conversion chip. The base of the eighth transistor is connected to the second main control MCU through the second seventeenth resistor. The emitter of the eighth transistor is grounded. The collector of the eighth transistor is connected to the second battery through the thirty-second resistor. The collector of the eighth transistor is also connected to the gate of the ninth MOS transistor and the gate of the tenth MOS transistor. The source of the ninth MOS transistor is connected to the second battery. The drain of the ninth MOS transistor is connected to the power supply input terminal of the fifth conversion chip and the power supply input terminal of the sixth conversion chip. The source of the tenth MOSFET is connected to the power output terminal of the fourth conversion chip, and the drain of the tenth MOSFET is connected to the second FPGA module; the power input terminal of the fourth conversion chip is connected to the second battery, the power output terminal of the fifth conversion chip is connected to the second main control MCU, and the power output terminal of the sixth conversion chip is connected to the second FPGA module.

[0015] The offshore downhole high-frequency wireless communication device of the present invention has the following beneficial effects: It includes a transmitting unit and a receiving unit; the transmitting unit includes a transmitting main control module, a transmitting circuit, and a transmitting coil; the receiving unit includes a receiving coil, a receiving circuit, and a receiving main control module; the transmitting main control module controls the transmitting circuit to start and stop as needed and outputs coded modulation signals; the transmitting circuit applies the coded modulation signals to the transmitting coil after push-pull driving and resonance processing to generate an alternating magnetic field; the receiving coil senses the signal from the alternating magnetic field and outputs an induced signal; the receiving circuit amplifies, filters, and shapes the induced signal before outputting a sampled signal; the receiving main control module demodulates and processes the sampled signal to obtain a wireless received signal. This invention solves the problem of data transmission between two short sections that require traditional integrated manufacturing or interconnection, and also addresses the problem of short operating time of downhole circuits under battery power conditions, ensuring reliable transmission of downhole data. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a schematic diagram of the structure of the offshore underground high-frequency wireless communication device provided by the present invention; Figure 2 This is a schematic diagram of the offshore downhole high-frequency wireless communication device provided by the present invention; Figure 3 This is a circuit schematic diagram of the transmitting main control unit provided by the present invention; Figure 4 This is the circuit schematic diagram of the first FPGA module provided by the present invention; Figure 5 This is a circuit schematic diagram of the transmitting circuit provided by the present invention; Figures 6-7 This is a circuit schematic diagram of the transmitting power supply module provided by the present invention; Figure 8 This is a circuit diagram of the receiving circuit provided by the present invention; Figure 9 This is a circuit schematic diagram of the receiving main control unit provided by the present invention; Figure 10 This is the circuit schematic diagram of the second FPGA module provided by the present invention; Figures 11-12 This is a circuit schematic diagram of the receiving power management module provided by the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] The present invention provides a high-frequency wireless communication device for offshore wells. The purpose of this device is to transmit downhole measurement data wirelessly to the wireless communication circuit of a specific downhole receiving device. This circuit enables data transmission between the measurement sub-section and the communication sub-section, solving the problem of traditional methods requiring integrated manufacturing or interconnection to achieve data transmission between two sub-sections. Simultaneously, by designing the carrier frequency at approximately 20kHz, and through higher carrier frequency and signal tuning, the transmission power is reduced while the tuning effectively improves transmission efficiency, thus solving the problem of short operating time of downhole circuits under battery power conditions.

[0019] The offshore underground high-frequency wireless communication device provided by this invention mainly comprises two parts: a transmitting unit and a receiving unit. The transmitting unit includes a transmitting main control module, a transmitting circuit, and a transmitting coil; the receiving unit includes a receiving coil, a receiving circuit, and a receiving main control module.

[0020] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the offshore underground high-frequency wireless communication device provided by the present invention. Figure 1 As shown, the transmitting unit 100 also includes a transmitter body, and the receiving unit 200 also includes a receiver body. The receiving unit 200 is embedded inside the transmitting unit 100 and is connected to the inner wall of the transmitting unit 100 via the upper centralizer 4 and the lower centralizer 3. During operation, the coded modulation signal output from the transmitting main control module 101 by the transmitting circuit 102 is applied to the transmitting coil 103 after passing through a push-pull drive and a resonant network. The alternating current in the transmitting coil 103 generates an alternating magnetic field within the coil core. According to Faraday's principle of electromagnetic induction, this alternating magnetic field will... Figure 1 In the closed loop formed by the upper centralizer 4 → receiver body 1 → lower centralizer 3 → transmitter body 5, an induced current is generated, which in turn induces an electromotive force in the receiving coil 201. After the induced signal is amplified, filtered, detected and shaped at the front end of the receiving circuit 202, it is converted by an AD converter and demodulated by the receiving main control module 203, thereby realizing wireless data transmission. Figure 1 In the diagram, 6 represents the transmitting antenna.

[0021] To meet the requirements of low power consumption and long battery life for downhole tools, this invention introduces a power management circuit in the circuit design: both the transmitting circuit 102 and the receiving circuit 202 are controlled by an MCU, and will only be turned on when data acquisition and transmission are required, and will remain off at other times to reduce the static power consumption of the circuit; at the same time, the MCU itself will enter a low power mode during non-operating phases, further reducing the static power consumption of the circuit.

[0022] like Figure 2 As shown, in this embodiment of the invention, the transmitting main control module 101, the transmitting circuit 102, and the transmitting coil 103 are connected in sequence; the receiving coil 201, the receiving circuit 202, and the receiving main control module 203 are connected in sequence. Specifically, the transmitting main control module 101 controls the transmitting circuit 102 to start and stop as needed, wakes it up at regular intervals, and reads data from external sensors, and outputs an encoded modulation signal to the transmitting circuit 102 based on the external sensor data; the transmitting circuit 102 applies push-pull drive and resonance processing to the encoded modulation signal and then loads it onto the transmitting coil 103, generating an alternating magnetic field through the transmitting coil 103; the receiving coil 201 senses the signal from the alternating magnetic field and outputs a corresponding sensed signal to the receiving circuit 202; the receiving circuit 202 amplifies, filters, and shapes the sensed signal before outputting a sampled signal to the receiving main control module 203; and the receiving main control module 203 demodulates and processes the sampled signal to obtain a wireless received signal.

[0023] In a preferred embodiment, the transmission master control module 101 includes: a transmission master control unit and a transmission power management module 105; the transmission power management module 105 is connected to the transmission master control unit, the transmission circuit 102 and the first battery 104 respectively. The main control unit controls the transmitter circuit 102 to start and stop as needed, wake it up at regular intervals, and read data from external sensors. Based on this data, it outputs coded and modulated signals to the transmitter circuit 102. The transmitter power management module 105 provides or cuts off power according to the control of the main control unit. Specifically, for example... Figure 3 As shown and Figure 4 As shown, the transmission control unit includes: a first main control MCU and a first FPGA module. Among them, Figure 3 This includes IC5 as the primary control MCU. Figure 3It also includes a 485 transmitter module (i.e., IC4). The first main control MCU communicates with external sensors (including but not limited to pressure sensors, temperature sensors, flow sensors, etc.) through the 485 transmitter module, wakes up periodically to read data from external sensors, packages the acquired data and transmits it to the first FPGA module. The first FPGA module (i.e., IC1) modulates the data and outputs a pair of differential signals (i.e., encoded modulation signals (TXP, TXN)), which are input to the transmitter circuit 102.

[0024] In some embodiments, the transmit power management module 105 includes: a transmit power switch circuit, a first transmit switch circuit, a second transmit switch circuit, and a third transmit switch circuit. A first main control MCU is connected to a first FPGA module. The transmit power switch circuit is connected to the first main control MCU, the second transmit switch circuit, the third transmit switch circuit, and the first battery 104, respectively. The first transmit switch circuit is connected to the first battery 104 and the first main control MCU, respectively. The second transmit switch circuit is connected to the transmit circuit 102. The third transmit switch circuit and the transmit power switch circuit are connected to the first FPGA module. The first main control MCU is used to control the transmit circuit 102 to start and stop on demand, wake it up at regular intervals, and read data from external sensors, and send input signals to the first FPGA module based on the data from external sensors. The first FPGA module is used to encode and modulate the input and output an encoded and modulated signal to the transmit circuit 102. The transmit power switch circuit is used to control the power supply of the second and third transmit switch circuits according to the control signal of the first main control MCU, and is used to supply power to the first FPGA module. The first transmit switch circuit is used to supply power to the first main control MCU, the second transmit switch circuit is used to supply power to the transmit circuit 102, and the third transmit switch circuit is used to supply power to the first FPGA module.

[0025] In some embodiments, the transmitting circuit 102 includes a push-pull drive circuit, a signal transformer T1, and a resonant circuit. The push-pull drive circuit, the signal transformer T1, and the resonant circuit are connected in sequence, and the input terminal of the push-pull drive circuit is connected to the transmitting main control module 101, and the output terminal of the resonant circuit is connected to the transmitting coil 103. The push-pull drive circuit is used to amplify the voltage of the encoded modulation signal and output a large current alternating signal to the signal transformer T1. The secondary winding of the signal transformer T1, the resonant circuit, and the transmitting coil 103 form an LC resonant circuit to generate an alternating magnetic block according to the set operating frequency.

[0026] In a preferred embodiment, such as Figure 5As shown, the push-pull drive circuit includes: a first DC blocking capacitor C18, a second DC blocking capacitor C24, a first current limiting resistor R28, a second current limiting resistor R34, a first drive transistor Q2, a second drive transistor Q4, a first output MOSFET Q1, and a second output MOSFET Q3; the resonant circuit includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.

[0027] The base of the first driving transistor Q2 is connected to the first output terminal of the transmitter main control module 101 via the first current-limiting resistor R28 and the first DC blocking capacitor C18. The base of the second driving transistor Q4 is connected to the second output terminal of the transmitter main control module 101 via the second current-limiting resistor R34 and the second DC blocking capacitor C24. The collector of the first driving transistor Q2 is connected to the gate of the first output MOSFET Q1, and the emitter of the first driving transistor Q2 is grounded. The collector of the second driving transistor Q4 is connected to the gate of the second output MOSFET Q3, and the emitter of the second driving transistor Q4 is grounded. The source of the first output MOSFET Q1 is grounded. The drain of capacitor C1 is connected to the first input terminal of the primary winding of signal transformer T1. The source of the second output MOSFET Q3 is grounded, and the drain of the second output MOSFET Q3 is connected to the second input terminal of the primary winding of signal transformer T1. The first terminal of the first capacitor C1 is connected to the first output terminal of the secondary winding of signal transformer T1, and the second terminal of the first capacitor C1 is connected to the second output terminal of the secondary winding of signal transformer T1. The second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are connected in parallel with the first capacitor C1. The first terminal of the fourth capacitor C4 is connected to the first terminal of the transmitting coil 103, and the second terminal of the fourth capacitor C4 is connected to the second terminal of the transmitting coil 103.

[0028] Specifically, the pair of differential signals output by the first FPGA module after modulating the data are coupled through the first DC blocking capacitor C18 and the second DC blocking capacitor C24, and respectively fed to the bases of the first driving transistor Q2 and the second driving transistor Q4 in the preceding stage. The first driving transistor Q2 and the second driving transistor Q4 further drive the push-pull power stage. That is, the first driving transistor Q2 and the second driving transistor Q4 amplify the input differential signals and drive the first output MOSFET Q1 and the second output MOSFET Q3. The first output MOSFET Q1 and the second output MOSFET Q3 are alternately turned on, forming a push-pull output stage, which amplifies the small signal into a large current alternating signal. The high-current alternating signal output from the push-pull circuit is applied to the signal transformer T1. The secondary winding of the signal transformer T1, together with parallel capacitors (C1, C2, C3, and C4) and the transmitting coil 103, forms an LC resonant circuit. The capacitance of the parallel capacitors is calculated given the inductance of the secondary winding of the signal transformer T1, the transmitting coil 103, and the signal frequency, to better ensure signal transmission efficiency and integrity. Resistor R3 in the circuit is used to suppress parasitic oscillations. The resonant circuit is connected to the transmitting coils 103 (COIL_H1 and COIL_H2), generating an alternating magnetic field at the set operating frequency to complete signal transmission.

[0029] In a preferred embodiment, such as Figure 6 and Figure 7 As shown, the transmit power switch circuit includes: the thirtieth resistor R30, the fifth transistor Q5, the sixth MOSFET Q6, and the seventh MOSFET Q7; the first transmit switch circuit includes: the first conversion chip U1; the second transmit switch circuit includes: the second conversion chip U2; and the third transmit switch circuit includes: the third conversion chip U3.

[0030] The base of the fifth transistor Q5 is connected to the first main control MCU through the thirtieth resistor R30. The emitter of the fifth transistor Q5 is grounded. The collector of the fifth transistor Q5 is connected to the first battery 104 through the twenty-eighth resistor. The collector of the fifth transistor Q5 is also connected to the gate of the sixth MOSFET Q6 and the gate of the seventh MOSFET Q7. The source of the sixth MOSFET Q6 is connected to the first battery 104. The drain of the sixth MOSFET Q6 is connected to the power supply input terminal of the second conversion chip U2 and the power supply input terminal of the third conversion chip U3. The source of the seventh MOSFET Q7 is connected to the power supply output terminal of the first conversion chip U1. The drain of the seventh MOSFET Q7 is connected to the first FPGA module. The power supply input terminal of the first conversion chip U1 is connected to the first battery 104. The power supply output terminal of the second conversion chip U2 is connected to the transmitter circuit 102. The power supply output terminal of the third conversion chip U3 is connected to the first FPGA module.

[0031] Specifically, in order to meet the long-term power supply requirements of downhole tools, this invention designs a transmitting power management circuit and a receiving power management circuit. The transmitting power management circuit includes three main parts: a transmitting power switch circuit, a first transmitting switch circuit, a second transmitting switch circuit, and a third transmitting switch circuit.

[0032] like Figure 6 and Figure 7 As shown, the voltage Vin1 of the first battery 104 is converted to CPU 3.3V by the first conversion chip U1. This power supply is normally open (i.e., the CPU continuously and stably outputs 3.3V) to ensure that the first main control MCU is always online, so as to implement power control logic through pins. The first main control MCU drives the fifth transistor Q5 through the Power_Control_1 signal, thereby controlling the gates of the P-channel MOSFETs (i.e., the sixth MOSFET Q6 and the seventh MOSFET Q7). When Power_Control_1 outputs a high level, the fifth transistor Q5 is turned on, the gate potentials of the sixth MOSFET Q6 and the seventh MOSFET Q7 decrease, and the sixth MOSFET Q6 and the seventh MOSFET Q7 are turned on, thus providing operating power to the controlled modules (i.e., providing power to the first FPGA module, the second transmit switch circuit, and the third transmit switch circuit); when Power_Control_1 is low, the fifth transistor Q5 is turned off, the sixth MOSFET Q6 and the seventh MOSFET Q7 are turned off, and the power supply to the controlled modules is cut off.

[0033] like Figure 6 and Figure 7 As shown, the Vin_s output from the transmit power switch circuit is transmitted to the second conversion chip U2 and the third conversion chip U3, respectively. The FPGA 3.3V output from the transmit power switch circuit powers the first FPGA module. Specifically, the second conversion chip U2 converts Vin_s to 10V, and the third conversion chip U3 converts Vin_s to 1.5V. This 10V power supply is then used to power the transmit drive power stage Vtx, and this 1.5V (i.e., FPGA 1.5V) powers the first FPGA module. Preferably, in this embodiment of the invention, the first conversion chip U1, the second conversion chip U2, and the third conversion chip U3 can all be TPS40200.

[0034] In some embodiments, the receiving circuit 202 includes: a first-stage amplifier circuit, a second-stage amplifier circuit, a first-stage filter circuit, a second-stage filter circuit, a third-stage filter circuit, and a shaping circuit. The first-stage amplifier circuit, the second-stage amplifier circuit, the first-stage filter circuit, the second-stage filter circuit, the third-stage amplifier circuit, and the shaping circuit are sequentially connected between the receiving coil 201 and the receiving main control module 203. The first-stage amplifier circuit is used to invert and amplify the induced signal output by the receiving coil 201; the second-stage amplifier circuit is used to amplify the signal after inversion amplification by the first-stage amplifier circuit a second time; the first-stage filter circuit is used to perform low-pass filtering; the second-stage filter circuit is used to perform high-pass filtering; the third-stage amplifier circuit is used to amplify the signal after filtering by the second-stage filter circuit; and the shaping circuit is used to shape the signal amplified by the third-stage amplifier circuit to obtain a sampled signal.

[0035] Specifically, such as Figure 8 As shown, the receiving circuit 202 mainly consists of a receiving coil 201, a first-stage amplifier circuit, a second-stage amplifier circuit, a first-stage filter circuit, a second-stage filter circuit, a third-stage amplifier circuit, and a shaping circuit. The weak signal (i.e., the induced signal) sensed by the receiving coil 201 (Coil_Rx) is first blocked by capacitor C19 and then sent to the first-stage operational amplifier U1.1 for inverting amplification. In the inverting amplification structure, the amplification factor is determined by the input resistor Rin and the feedback resistor Rf. In this circuit, the gain of the first-stage amplifier circuit (i.e., the gain of the first operational amplifier U1A) is R39 / R38, the gain of the second-stage amplifier circuit (i.e., the gain of the second operational amplifier U1B) is R47 / R45, and the gain of the third-stage amplifier circuit (i.e., the gain of the third operational amplifier U3A) is R49 / R51. Through step-by-step amplification, the originally weak induced signal is boosted to the amplitude range required by the subsequent filtering and processing circuits. After being amplified by the first and second stage amplifier circuits, the signal passes through the first and second stage filter circuits in sequence, and then is amplified again by the third stage amplifier circuit before entering the shaping circuit.

[0036] The first-stage filter circuit, consisting of U2A and its peripheral circuitry, forms a low-pass filter, allowing signal components below the cutoff frequency to pass through while suppressing high-frequency noise. The second-stage filter circuit, consisting of U2B and its peripheral circuitry, forms a high-pass filter, allowing signal components above the cutoff frequency to pass through while suppressing low-frequency interference and drift. A band-pass filter is formed by cascading U2A and U2B. When the low-pass and high-pass filters are cascaded, the overall circuit behaves as a band-pass filter, retaining only signals within the target frequency range, thus achieving effective extraction of the carrier component. Its cutoff frequency is determined by the resistor and capacitor parameters. This invention, through the rational design of resistor and capacitor values, can precisely control the filter's cutoff frequency and bandwidth while ensuring the required gain, ensuring that the target signal component is extracted and interference is effectively suppressed.

[0037] The filtered signal is then fed into U3A for further amplification, and then enters the shaping circuit consisting of operational amplifier U3B and its peripheral circuitry. In this circuit, operational amplifier U3B, in conjunction with Zener diodes D2 and D4, performs a clamping effect. When the input amplitude is large, the output is limited to a stable range and shaped into a near-square wave; if the signal amplitude is insufficient, the output remains a sine wave. Finally, the shaped signal is sent to the AinH pin (reference). Figure 9 The analog voltage signal (i.e., the sampling signal) is sampled and quantized into a digital signal, which is then demodulated and processed by the second main control MCU and the second FPGA module to complete the recovery of the wireless signal at the receiving end.

[0038] In some embodiments, the receiving master control module 203 includes: a receiving master control unit and a receiving power management module 204; the receiving power management module 204 is connected to the receiving master control unit, the receiving circuit 202, and the second battery 205 respectively; the receiving master control unit is used to sample signals, demodulate and process them to obtain wireless receiving signals; the receiving power management module 204 is used to provide power or cut off power supply according to the control of the receiving master control unit.

[0039] Preferably, such as Figure 9 and Figure 10As shown, the receiving main control unit includes: a second main control MCU (i.e., IC8) and a second FPGA module (i.e., IC9). The receiving power management module 204 includes: a receiving power switch circuit, a first receiving switch circuit, a second receiving switch circuit, and a third receiving switch circuit; a second main control MCU is connected to a second FPGA module; the receiving power switch circuit is connected to the second main control MCU, the second receiving switch circuit, the third receiving switch circuit, and a second battery 205; the first receiving switch circuit is connected to the second battery 205 and the second main control MCU; the second receiving switch circuit is connected to the second main control MCU; the receiving power switch circuit and the third receiving switch circuit are connected to the second FPGA module; the second main control MCU controls the on / off state of the receiving power switch circuit and transmits the sampled data to the second FPGA module after parsing and processing; the second FPGA module demodulates and processes the sampled signal transmitted by the second main control MCU and outputs a wireless receiving signal; the receiving power switch circuit controls the power supply of the second receiving switch circuit and the third receiving switch circuit according to the control signal of the second main control MCU and supplies power to the second FPGA module; the first receiving switch circuit supplies power to the second main control MCU, the second receiving switch circuit supplies power to the operational amplifier in the second main control MCU, and the third receiving switch circuit supplies power to the second FPGA module.

[0040] In a preferred embodiment, such as Figure 11 and Figure 12 As shown, the receiving power switch circuit includes: the twenty-seventh resistor R27, the eighth transistor Q8, the ninth MOSFET Q9, and the tenth MOSFET Q10; the first receiving switch circuit includes: the fourth conversion chip U4; the second receiving switch circuit includes: the fifth conversion chip U5; and the third receiving switch circuit includes: the sixth conversion chip U6.

[0041] The base of transistor Q8 is connected to the second main control MCU through resistor R27. The emitter of transistor Q8 is grounded. The collector of transistor Q8 is connected to the second battery 205 through resistor R27. The collector of transistor Q8 is also connected to the gate of MOSFET Q9 and the gate of MOSFET Q10. The source of MOSFET Q9 is connected to the second battery 205. The drain of MOSFET Q9 is connected to the power input terminals of the fifth conversion chip U5 and the sixth conversion chip U6. The source of MOSFET Q10 is connected to the power output terminal of the fourth conversion chip U4. The drain of MOSFET Q10 is connected to the second FPGA module. The power input terminal of the fourth conversion chip U4 is connected to the second battery 205. The power output terminal of the fifth conversion chip U5 is connected to the second main control MCU. The power output terminal of the sixth conversion chip U6 is connected to the second FPGA module.

[0042] like Figure 11 and Figure 12 As shown, the voltage Vin2 of the second battery 205 is converted to 3.3V for the CPU via the fourth conversion chip U4. This power supply is normally open to ensure that the second main control MCU is always online, enabling power control logic to be implemented through pins. The second main control MCU drives the eighth transistor Q8 via the Power_Control_2 signal, which in turn controls the gates of the P-channel MOSFETs (i.e., the ninth MOSFET Q9 and the tenth MOSFET Q10). When Power_Control_2 outputs a high level, the eighth transistor Q8 is turned on, the gate potentials of the ninth MOSFET Q9 and the tenth MOSFET Q10 decrease, and the ninth MOSFET Q9 and the tenth MOSFET Q10 are turned on, thus providing operating power to the controlled module (i.e., power to the second FPGA module, the second receiving switch circuit, and the third receiving switch circuit); when Power_Control_2 is low, the eighth transistor Q8 is turned off, the ninth MOSFET Q9 and the tenth MOSFET Q10 are turned off, and the power supply to the controlled module is cut off.

[0043] like Figure 11 and Figure 12 As shown, the Vin_s output from the power switch circuit is transmitted to the fifth conversion chip U5 and the sixth conversion chip U6, respectively. The FPGA 3.3V output from the power switch circuit powers the second FPGA module. Specifically, the fifth conversion chip U5 converts Vin_s to 5V, and the sixth conversion chip U6 converts Vin_s to 1.5V (i.e., FPGA 1.5V). This 5V is specifically used to power the OPA2333 operational amplifier in the second main control MCU. The FPGA 3.3V and FPGA 1.5V power the second FPGA module. Preferably, in this embodiment of the invention, the fourth conversion chip U4, the fifth conversion chip U5, and the sixth conversion chip U6 can all be TPS40200.

[0044] In this embodiment of the invention, the transmit power management module 105 and the receive power management module 204 maintain the same architecture, differing only in the intermediate voltage supplied by the TPS40200: 10V for the transmitter (drive power stage) and 5V for the receiver (op-amp power supply). This design strategy ensures that the CPU power supply remains always on to maintain control functions, while the power supplies for peripheral high-power modules are flexibly controlled by MCU pins. When data acquisition and transmission are required, the drive circuit, op-amp, and FPGA power supplies are turned on; during non-operational phases, these modules are turned off, and the CPU itself enters a low-power mode. This "always-on CPU + controlled peripheral power supply" approach significantly reduces overall average power consumption, ensuring long-term battery life for downhole tools.

[0045] This invention achieves the following through the coordinated operation of five circuit components: the transmitting circuit 102, the receiving circuit 202, the power management circuits (transmitting power management module 105 and receiving power management module 204), the transmitting main control module 101, and the receiving main control module 203: stable electromagnetic induction communication—reliable transmission of downhole signals is achieved by utilizing the electromagnetic induction between the high-frequency transmitting coil 103 and the receiving coil 201; high signal-to-noise ratio signal reception—through multi-stage amplification and filtering, weak signals can still be identified in complex environments; and low power consumption and long battery life—through the power switch circuit and the low-power mode of the MCU (first main control MCU / second main control MCU), energy consumption is significantly reduced, meeting the application requirements for long-term downhole operation.

[0046] This invention employs a push-pull drive + LC resonance high-efficiency electromagnetic induction transmission architecture to achieve low-power, high-efficiency downhole high-frequency wireless communication; it designs a dynamic power management strategy based on MCU, which combines the power supply of peripheral modules with low-power mode through MCU control to significantly improve battery life; and it designs multi-stage amplification and filtering circuits to improve signal-to-noise ratio and reception reliability, adapting to complex electromagnetic environments.

[0047] The offshore downhole high-frequency wireless communication device of the present invention has the following advantages: High efficiency: Push-pull drive + LC resonance significantly improves electromagnetic induction transmission efficiency; Reliability: Adaptable to high temperature, high pressure, and vibration environments downhole, requiring no wired connection; Low power consumption: The MCU controls the transmitter circuit 102 to start and stop on demand, resulting in low overall energy consumption; High speed: The downhole high-frequency wireless communication circuit designed in this invention can achieve a communication rate of over 4.8Kbps.

[0048] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0049] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0050] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0051] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They do not limit the scope of protection of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the claims of the present invention.

Claims

1. A high-frequency wireless communication device for offshore wells, characterized in that, include: Transmitting unit and receiving unit; The transmitting unit includes: a transmitting main control module, a transmitting circuit, and a transmitting coil; the receiving unit includes: a receiving coil, a receiving circuit, and a receiving main control module. The transmitting main control module, the transmitting circuit, and the transmitting coil are connected in sequence; the receiving coil, the receiving circuit, and the receiving main control module are connected in sequence. The main control module for transmitting is used to control the transmitting circuit to start and stop as needed, wake up at regular intervals, and read data from external sensors, and output coded modulation signals to the transmitting circuit based on the data from the external sensors; the transmitting circuit is used to apply the coded modulation signals to the transmitting coil after push-pull driving and resonance processing, and generate an alternating magnetic field through the transmitting coil; The receiving coil is used to sense the signal of the alternating magnetic field and output a corresponding induced signal to the receiving circuit; the receiving circuit amplifies, filters and shapes the induced signal and outputs a sampled signal to the receiving main control module; the receiving main control module is used to demodulate and process the sampled signal to obtain a wireless received signal.

2. The offshore downhole high-frequency wireless communication device according to claim 1, characterized in that, The transmitting circuit includes: a push-pull drive circuit, a signal transformer, and a resonant circuit; The push-pull drive circuit, the signal transformer, and the resonant circuit are connected in sequence, and the input terminal of the push-pull drive circuit is connected to the transmitting main control module, and the output terminal of the resonant circuit is connected to the transmitting coil. The push-pull drive circuit amplifies the voltage of the encoded modulation signal and outputs a large current alternating signal to the signal transformer. The secondary winding of the signal transformer, the resonant circuit, and the transmitting coil form an LC resonant circuit to generate the alternating magnetic block according to the set operating frequency.

3. The offshore downhole high-frequency wireless communication device according to claim 2, characterized in that, The push-pull drive circuit includes: a first DC blocking capacitor, a second DC blocking capacitor, a first current limiting resistor, a second current limiting resistor, a first drive transistor, a second drive transistor, a first output MOSFET, and a second output MOSFET; the resonant circuit includes: a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The base of the first driving transistor is connected to the first output terminal of the transmitting main control module through the first current-limiting resistor and the first DC blocking capacitor in sequence. The base of the second driving transistor is connected to the second output terminal of the transmitting main control module through the second current-limiting resistor and the second DC blocking capacitor in sequence. The collector of the first driving transistor is connected to the gate of the first output MOS transistor, and the emitter of the first driving transistor is grounded. The collector of the second driving transistor is connected to the gate of the second output MOS transistor, and the emitter of the second driving transistor is grounded. The source of the first output MOS transistor is grounded, and the drain of the first output MOS transistor is connected to the first input terminal of the primary winding of the signal transformer. The source of the second output MOS transistor is grounded, and the drain of the second output MOS transistor is connected to the second input terminal of the primary winding of the signal transformer. The first terminal of the first capacitor is connected to the first output terminal of the secondary winding of the signal transformer, the second terminal of the first capacitor is connected to the second output terminal of the secondary winding of the signal transformer, the second capacitor, the third capacitor and the fourth capacitor are connected in parallel with the first capacitor in sequence, the first terminal of the fourth capacitor is connected to the first terminal of the transmitting coil, and the second terminal of the fourth capacitor is connected to the second terminal of the transmitting coil.

4. The offshore downhole high-frequency wireless communication device according to claim 1, characterized in that, The launch control module includes a launch control unit and a launch power management module; the launch power management module is connected to the launch control unit, the launch circuit and the first battery respectively. The main control unit for transmitting is used to control the transmitting circuit to start and stop as needed, wake it up at regular intervals, read the data from the external sensor, and output an encoded modulation signal to the transmitting circuit based on the data from the external sensor. The transmission power management module is used to provide power or cut off power supply according to the control of the transmission master control unit.

5. The offshore downhole high-frequency wireless communication device according to claim 4, characterized in that, The main control unit for transmission includes: a first main control MCU and a first FPGA module; the transmission power management module includes: a transmission power switch circuit, a first transmission switch circuit, a second transmission switch circuit, and a third transmission switch circuit; The first main control MCU is connected to the first FPGA module. The transmit power switch circuit is connected to the first main control MCU, the second transmit switch circuit, the third transmit switch circuit and the first battery respectively. The first transmit switch circuit is connected to the first battery and the first main control MCU respectively. The second transmit switch circuit is connected to the transmit circuit. The third transmit switch circuit and the transmit power switch circuit are connected to the first FPGA module. The first main control MCU is used to control the transmitting circuit to start and stop as needed, wake it up at regular intervals, and read the data from the external sensor, and send an input signal to the first FPGA module based on the data from the external sensor; the first FPGA module is used to encode and modulate the input and output the encoded and modulated signal to the transmitting circuit; The transmit power switch circuit is used to control the power supply of the second transmit switch circuit and the third transmit switch circuit according to the control signal of the first master control MCU, and to supply power to the first FPGA module; the first transmit switch circuit is used to supply power to the first master control MCU, the second transmit switch circuit is used to supply power to the transmit circuit, and the third transmit switch circuit is used to supply power to the first FPGA module.

6. The offshore downhole high-frequency wireless communication device according to claim 5, characterized in that, The transmitting power switch circuit includes: a thirtieth resistor, a fifth transistor, a sixth MOSFET, and a seventh MOSFET; the first transmitting switch circuit includes: a first conversion chip; the second transmitting switch circuit includes: a second conversion chip; the third transmitting switch circuit includes: a third conversion chip; The base of the fifth transistor is connected to the first main control MCU through the thirtieth resistor. The emitter of the fifth transistor is grounded. The collector of the fifth transistor is connected to the first battery through the twenty-eighth resistor. The collector of the fifth transistor is also connected to the gate of the sixth MOS transistor and the gate of the seventh MOS transistor. The source of the sixth MOS transistor is connected to the first battery. The drain of the sixth MOS transistor is connected to the power supply input terminal of the second conversion chip and the power supply input terminal of the third conversion chip. The source of the seventh MOS transistor is connected to the power supply output terminal of the first conversion chip, and the drain of the seventh MOS transistor is connected to the first FPGA module; the power supply input terminal of the first conversion chip is connected to the first battery, the power supply output terminal of the second conversion chip is connected to the transmitting circuit, and the power supply output terminal of the third conversion chip is connected to the first FPGA module.

7. The offshore downhole high-frequency wireless communication device according to claim 1, characterized in that, The receiving circuit includes: a first-stage amplifier circuit, a second-stage amplifier circuit, a first-stage filter circuit, a second-stage filter circuit, a third-stage filter circuit, and a shaping circuit; The first-stage amplifier circuit, the second-stage amplifier circuit, the first-stage filter circuit, the second-stage filter circuit, the third-stage amplifier circuit, and the shaping circuit are sequentially connected between the receiving coil and the receiving main control module. The first-stage amplifier circuit is used to invert and amplify the induced signal output by the receiving coil; The second-stage amplifier circuit is used to amplify the signal after it has been inverted and amplified by the first-stage amplifier circuit a second time. The first-stage filter circuit is used to perform low-pass filtering; The second-stage filter circuit is used to perform high-pass filtering; The third-stage amplifier circuit is used to amplify the signal after it has been filtered by the second-stage filter circuit; The shaping circuit is used to shape the signal amplified by the third-stage amplifier circuit to obtain the sampled signal.

8. The offshore downhole high-frequency wireless communication device according to claim 1, characterized in that, The receiving main control module includes: a receiving main control unit and a receiving power management module; the receiving power management module is connected to the receiving main control unit, the receiving circuit, and the second battery, respectively. The receiving main control unit is used to demodulate and process the sampled signal to obtain a wireless received signal; The receiving power management module is used to provide power or cut off power supply according to the control of the receiving main control unit.

9. The offshore downhole high-frequency wireless communication device according to claim 8, characterized in that, The receiving main control unit includes: a second main control MCU and a second FPGA module; the receiving power management module includes: a receiving power switch circuit, a first receiving switch circuit, a second receiving switch circuit and a third receiving switch circuit; The second main control MCU is connected to the second FPGA module. The receiving power switch circuit is connected to the second main control MCU, the second receiving switch circuit, the third receiving switch circuit and the second battery respectively. The first receiving switch circuit is connected to the second battery and the second main control MCU respectively. The second receiving switch circuit is connected to the second main control MCU. The receiving power switch circuit and the third receiving switch circuit are connected to the second FPGA module respectively. The second main control MCU is used to control the on / off state of the receiving power switch circuit and to parse and process the sample before transmitting it to the second FPGA module. The second FPGA module is used to demodulate and process the sampled signal transmitted by the second main control MCU and then output the wireless received signal. The receiving power switch circuit is used to control the power supply of the second receiving switch circuit and the third receiving switch circuit according to the control signal of the second main control MCU, and to supply power to the second FPGA module; the first receiving switch circuit is used to supply power to the second main control MCU, the second receiving switch circuit is used to supply power to the operational amplifier in the second main control MCU, and the third receiving switch circuit is used to supply power to the second FPGA module.

10. The offshore downhole high-frequency wireless communication device according to claim 9, characterized in that, The receiving power switch circuit includes: a 27th resistor, an 8th transistor, a 9th MOSFET, and a 10th MOSFET; the first receiving switch circuit includes: a 4th conversion chip; the second receiving switch circuit includes: a 5th conversion chip; the third receiving switch circuit includes: a 6th conversion chip; The base of the eighth transistor is connected to the second main control MCU through the second seventeenth resistor. The emitter of the eighth transistor is grounded. The collector of the eighth transistor is connected to the second battery through the thirty-second resistor. The collector of the eighth transistor is also connected to the gate of the ninth MOS transistor and the gate of the tenth MOS transistor. The source of the ninth MOS transistor is connected to the second battery. The drain of the ninth MOS transistor is connected to the power supply input terminal of the fifth conversion chip and the power supply input terminal of the sixth conversion chip. The source of the tenth MOSFET is connected to the power output terminal of the fourth conversion chip, and the drain of the tenth MOSFET is connected to the second FPGA module; the power input terminal of the fourth conversion chip is connected to the second battery, the power output terminal of the fifth conversion chip is connected to the second main control MCU, and the power output terminal of the sixth conversion chip is connected to the second FPGA module.

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