Anti-electromagnetic interference TO packaging type optical receiving module and internal routing method thereof

Abstract

The invention discloses an anti-electromagnetic interference TO packaging type optical receiving module and an internal routing method thereof, belongs to the technical field of optical communication, and aims to solve the problems of insufficient anti-interference capability, high cost and limited performance caused by the adoption of a TIA bare chip internal integrated bias and filtering scheme in a traditional ROSA. The core of the invention lies in that internal bias is abandoned, a TO packaging external power supply pin VDDTO directly supplies power to the cathode of the photodiode PD, and a discrete off-chip capacitor is used for filtering. According to the first scheme, a 470pF capacitor and a 1nF capacitor are adopted for filtering a PD cathode and a TIA power source respectively; according to the second scheme, a special capacitor is omitted, and a PD cathode and a TIA power supply share a 1nF capacitor for filtering so as to save cost. The key wire bonding method requires that gold wires connected with the filter capacitors are bonded at the lowest height and the shortest distance so as to minimize parasitic inductance. According to the invention, the electromagnetic compatibility of the module is obviously improved, the sensitivity is obviously improved under strong interference, and the manufacturing cost is reduced at the same time.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, specifically to a TO-packaged optical receiver module with strong electromagnetic interference resistance suitable for FTTR or FTTH scenarios, and its internal wire bonding method. Background Technology

[0002] FTTR (Fiber to the Room) technology extends fiber optic cables from the communication base station to every room in a home, providing home users with extremely high-speed internet access. For example... Figure 1 The FTTR application scenario shown depicts a carrier network transmitting data to a user's home via optical fiber; this segment is typically referred to as FTTH (Fiber to the Home). In this scenario, the carrier-side equipment is similar to the central office OLT (Optical Line Terminal), while the main equipment within the user's home is equivalent to the user-side ONU (Optical Network Unit).

[0003] The core of FTTR technology lies in using fiber optic cables to replace traditional network cables. By deploying optical networking terminals and interconnecting them with home gateways, and combining them with wireless technologies such as dual-band Wi-Fi and Wi-Fi 6, seamless gigabit bandwidth coverage can be achieved throughout the house. This is an important direction for future gigabit home network upgrades.

[0004] In the fiber optic communication modules of an FTTR network, the Receiver Optical Sub-Assembly (ROSA) is a key component, responsible for converting received optical signals into electrical signals. Its core function is accomplished through the collaboration of two key components: a photodiode (PD) performs photoelectric conversion, transforming the optical signal into a weak current signal; and a transimpedance amplifier (TIA) amplifies this current signal and converts it into a voltage signal that can be processed by subsequent circuits. In addition, a typical ROSA also includes capacitors for signal filtering, lenses for focusing light, and a TO (Transistor Outline) metal package providing electromagnetic shielding and mechanical protection.

[0005] In actual TO package structures, the aforementioned functional components are integrated in a specific physical form. The PD and TIA are respectively fixed to the mounting platform inside the package in the form of PD bare dies and TIA bare dies, and then electrically interconnected using gold wires to form a complete signal link.

[0006] However, in the complex electromagnetic environment of the home, the performance of ROSA faces severe challenges. Everyday appliances such as microwave ovens and induction cookers, wireless communication devices such as mobile phones and routers, and motor-driven appliances such as refrigerators and washing machines all generate strong electromagnetic radiation or transient pulses during startup and operation. These electromagnetic interference (EMI) signals can penetrate the ROSA through various pathways.

[0007] like Figure 2 As shown, although the TO package utilizes a grounded metal casing for electromagnetic shielding, its top lens opening and exposed metal leads (like an antenna) still become entry points for EMI. Once interference signals enter the package and couple onto sensitive signal paths—especially the cathode of the PD—they can severely impact the system. Because the transimpedance amplifier (TIA) amplifies extremely weak current signals (typically in the microamplitude range), even small interferences can be significantly amplified, severely reducing the receiver sensitivity of the ROSA and shortening its effective communication range.

[0008] To suppress such interference, traditional ROSA design schemes (such as...) Figure 3 , Figure 4 As shown, a common approach is to integrate bias circuitry and on-chip filter capacitors within the TIA die. This approach uses the TIA die to provide the operating bias voltage to the PD cathode and utilizes internal capacitors for filtering. However, this approach has inherent drawbacks: integrating large-value capacitors on a semiconductor silicon wafer consumes a significant amount of chip area, leading to a sharp increase in manufacturing costs; and due to limitations in process technology and economics, the capacitance values ​​that can be integrated are limited, and their filtering effect often fails to meet stringent EMC (electromagnetic compatibility) requirements, resulting in unstable performance of the ROSA in strong interference environments.

[0009] Therefore, how to design a new internal interconnection and filtering structure for ROSA without significantly increasing costs, so as to greatly improve its ability to suppress high-frequency electromagnetic interference, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0010] To address the issues of insufficient anti-interference capability, high cost, and limited performance of traditional ROSA (Optical Optical Receiver Module) due to its use of TIA (Thin-Insulated Anode) die-integrated bias and filtering schemes in complex electromagnetic environments, this invention provides an anti-electromagnetic interference TO-packaged optical receiver module and its internal wire bonding method.

[0011] In a first aspect, the present invention provides an electromagnetic interference-resistant TO-packaged optical receiver module, comprising a metal casing and a power supply pin VDD_TO, a ground pin GND_TO, a first signal output pin OUTP_TO, and a second signal output pin OUTN_TO extending out of the casing. The metal casing contains a stage. The module is characterized by further comprising:

[0012] TIA and PD wafers are mounted on the platform.

[0013] First filter capacitor C1 and second filter capacitor C2;

[0014] in,

[0015] The TIA die is provided with a power pad VDD_TIA, an input pad PINA_TIA, a ground pad GND_TIA, a first output pad OUTP_TIA, and a second output pad OUTN_TIA.

[0016] The PD die is provided with an anode pad and a cathode pad;

[0017] The first terminal of the first filter capacitor C1 is electrically connected to the cathode pad of the PD die and the power supply pin VDD_TO through the first conductive connector;

[0018] The second terminal of the first filter capacitor C1 is electrically connected to the metal casing;

[0019] The first end of the second filter capacitor C2 is electrically connected to the power supply pin VDD_TO through the second conductive connector, and is electrically connected to the power supply pad VDD_TIA of the TIA die through the third conductive connector;

[0020] The second terminal of the second filter capacitor C2 is electrically connected to the metal casing;

[0021] The anode pad of the PD die is electrically connected to the input pad PINA_TIA of the TIA die via a fourth conductive connector.

[0022] Preferably, the first filter capacitor C1 and the second filter capacitor C2 are discrete surface-mount capacitors; the capacitance of the first filter capacitor C1 is 470pF and the capacitance of the second filter capacitor C2 is 1nF.

[0023] Preferably, the first conductive connector, the second conductive connector, the third conductive connector, and the fourth conductive connector are gold wires.

[0024] Secondly, the internal wire bonding method for an electromagnetic interference-resistant TO-packaged optical receiver module according to the present invention includes the following steps:

[0025] S1. Fix the TIA die and PD die onto the stage inside the TO packaged metal housing;

[0026] S2. Fix the first filter capacitor C1 and the second filter capacitor C2 inside the metal tube or on the platform, and electrically connect the second end of the first filter capacitor C1 and the second end of the second filter capacitor C2 to the metal tube.

[0027] S3. Perform wire bonding, including:

[0028] S31. Use gold wire to interconnect the cathode pad of the PD die, the first end of the first filter capacitor C1 and the power supply pin VDD_TO to form the first conductive connector.

[0029] S32. Connect the first end of the second filter capacitor C2 to the power supply pin VDD_TO using gold wire to form the second conductive connector;

[0030] S33. Use gold wire to connect the first end of the second filter capacitor C2 to the power pad VDD_TIA of the TIA die to form the third conductive connector;

[0031] S34. Use gold wire to connect the anode pad of the PD die to the input pad PINA_TIA of the TIA die to form the fourth conductive connector.

[0032] Preferably, in steps S32 and S33, during the wire bonding process, two gold wires are connected with the lowest possible span and the shortest possible distance.

[0033] Thirdly, the present invention provides an electromagnetic interference-resistant TO-packaged optical receiver module, comprising a metal casing and a power supply pin VDD_TO, a ground pin GND_TO, a first signal output pin OUTP_TO, and a second signal output pin OUTN_TO extending out of the casing. The metal casing contains a stage. The module further comprises:

[0034] TIA die and photodiode PD die are mounted on the platform;

[0035] A second filter capacitor C2;

[0036] in,

[0037] The TIA die is provided with a power pad VDD_TIA, an input pad PINA_TIA, a ground pad GND_TIA, a first output pad OUTP_TIA, and a second output pad OUTN_TIA.

[0038] The PD die is provided with an anode pad and a cathode pad;

[0039] The cathode pad of the PD die is electrically connected to the power supply pin VDD_TO via a fifth conductive connector;

[0040] The first end of the second filter capacitor C2 is electrically connected to the power supply pin VDD_TO through the second conductive connector, and is electrically connected to the power supply pad VDD_TIA of the TIA die through the third conductive connector;

[0041] The second terminal of the second filter capacitor C2 is electrically connected to the metal casing;

[0042] The anode pad of the PD die is electrically connected to the input pad PINA_TIA of the TIA die via a fourth conductive connector.

[0043] Preferably, the second filter capacitor C2 is a discrete surface-mount capacitor; the capacitance of the second filter capacitor C2 is 1nF.

[0044] Preferably, the fifth conductive connector, the second conductive connector, the third conductive connector, and the fourth conductive connector are gold wires.

[0045] Fourthly, the present invention provides an internal wire bonding method for an electromagnetic interference-resistant TO-packaged optical receiver module, comprising the following steps:

[0046] P1. Fix the TIA die and PD die onto the stage inside the TO package metal housing;

[0047] P2. Fix a second filter capacitor C2 inside the metal tube or on the platform, and electrically connect the second end of the second filter capacitor C2 to the metal tube.

[0048] P3. Perform wire bonding, including:

[0049] P31. Use gold wire to connect the cathode pad of the PD die to the power supply pin VDD_TO to form the fifth conductive connector;

[0050] P32. Connect the first end of the second filter capacitor C2 to the power supply pin VDD_TO using gold wire to form the second conductive connector.

[0051] P33. Use gold wire to connect the first end of the second filter capacitor C2 to the power pad VDD_TIA of the TIA die to form the third conductive connector;

[0052] P34. Use gold wire to connect the anode pad of the PD die to the input pad PINA_TIA of the TIA die to form the fourth conductive connector.

[0053] Preferably, in steps P32 and P33, during the wire bonding process, two gold wires are connected with the lowest possible span and the shortest possible distance.

[0054] The beneficial effects of this invention are:

[0055] 1. Significantly improves electromagnetic interference (EMI) immunity performance:

[0056] By directly powering the photodiode (PD) cathode with an external power supply and replacing the traditional integrated capacitors within the TIA die with larger discrete off-chip filter capacitors (such as 470pF and 1nF), an extremely low high-frequency impedance path is provided for the PD cathode node. This allows high-frequency interference currents from spatial coupling or pin intrusion to be effectively bypassed to ground (TO case), significantly reducing the proportion of interference signals entering the transimpedance amplifier (TIA) input stage. Figure 9 and Figure 10 Comparative experiments show that, under the same interference conditions, the solution of the present invention can significantly improve the receiving sensitivity of ROSA (e.g., from -20dBm to -28.8dBm), thereby enhancing the working stability and communication distance of ROSA in complex electromagnetic environments.

[0057] 2. Effectively reduces manufacturing costs and optimizes chip design:

[0058] Option 1 eliminates the complex PD bias voltage generation circuit and large on-chip filter capacitors inside the TIA die, simplifying the TIA die architecture, saving valuable chip area, and reducing the design and manufacturing costs of the TIA die itself. At the same time, it uses mature and inexpensive discrete surface-mount capacitors, avoiding the high cost of integrating large capacitors in the semiconductor process, thus achieving cost optimization at the system level.

[0059] 3. Offers flexible cost optimization options:

[0060] Option 2 further optimizes Option 1 by reusing the 1nF capacitor used for power supply filtering in the transimpedance amplifier (TIA) and simultaneously providing filtering for the PD cathode node, thus eliminating the need for a dedicated 470pF capacitor. While ensuring minimal EMC performance degradation, it further reduces the number of materials and lowers production costs, providing a more competitive solution for cost-sensitive applications.

[0061] 4. Improve system reliability:

[0062] Discrete capacitors offer a wider range of options for capacitance, material, and voltage rating, allowing for precise matching and optimization based on specific EMC standards and application environments. This improves the reliability and consistency of the filter network and reduces the risk of performance fluctuations caused by on-chip capacitor manufacturing process deviations.

[0063] In summary, this invention, through its innovative external power supply and discrete filter wire bonding architecture, fundamentally solves the contradiction between filtering performance and chip cost in traditional solutions. While significantly improving ROSA's anti-interference capability, it also reduces system cost and increases design flexibility. Attached Figure Description

[0064] Figure 1 This is a schematic diagram of an FTTR application scenario.

[0065] Figure 2 This is a schematic diagram of the TO package being affected by electromagnetic interference.

[0066] Figure 3 It is a traditional ROSA_PCB (circuit schematic) with weak electromagnetic interference immunity, which is used in FTTR or FTTH.

[0067] Figure 4 This is a traditional TO wire bonding solution with weak electromagnetic interference resistance, used in FTTR or FTTH (structural diagram).

[0068] Figure 5 This is a ROSA_PCB with strong electromagnetic interference resistance for FTTR or FTTH (Solution 1, dual capacitor circuit schematic).

[0069] Figure 6 This is a schematic diagram showing the specific path of electromagnetic interference entering the TIA from the cathode of the photodiode (PD).

[0070] Figure 7 This is TO wire bonding solution 1 (Solution 1, schematic diagram of dual capacitor structure) with strong anti-electromagnetic interference for FTTR or FTTH.

[0071] Figure 8 This is the ROSA_PCB with stronger electromagnetic interference resistance of Scheme 2 of the present invention (Scheme 2, single capacitor circuit schematic).

[0072] Figure 9 This is TO wire bonding scheme 2 (scheme 2, single capacitor structure schematic diagram) with strong electromagnetic interference resistance for FTTR or FTTH.

[0073] Figure 10 It is an eye diagram generated by a traditional wire bonding scheme with weak anti-interference capabilities.

[0074] Figure 11 This is the eye diagram generated by the wire bonding scheme (Scheme 1 or Scheme 2) of the present invention, which has strong anti-electromagnetic interference. Detailed Implementation

[0075] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0076] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0077] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0078] This invention addresses the problems of weak electromagnetic interference (EMI) immunity and high cost in traditional FTTR / FTTH optical receiver modules (ROSA) caused by the use of internally integrated capacitors on TIA (Transient Atomizer) dies to provide bias and filtering for the photodiode (PD) cathode. A fundamental improvement solution is proposed. The core idea is to abandon the traditional internal biasing scheme and instead directly power the PD cathode with an external power supply VDD_TO package, utilizing a larger-capacitance external capacitor for filtering, thereby significantly improving high-frequency noise suppression. Based on this, this invention specifically provides two optional VPD wire bonding schemes.

[0079] Specific Implementation Method 1 (Scheme 1: Dual Discrete Capacitor Scheme): This implementation method corresponds to... Figure 5 The circuit schematic shown Figure 7 The diagram shows the internal wire bonding structure of the TO package, and Figure 6 and Figure 11 .

[0080] 1. Module Structure

[0081] like Figure 5 As shown, the TO-packaged optical receiver module of this embodiment includes a metal casing (as a grounding shield) and four key pins leading out of the casing: power supply pin VDD_TO, ground pin GND_TO, first signal output pin OUTP_TO (positive phase signal output pin), and second signal output pin OUTN_TO (negative phase signal output pin). An insulating platform is provided inside the metal casing.

[0082] On the shelf, the following are fixed in place by conductive silver paste:

[0083] TIA die (DIE): The core circuit of the transimpedance amplifier is fabricated on it and has multiple pads, including: power pad VDD_TIA, input pad PINA_TIA, ground pad GND_TIA, first output pad OUTP_TIA (positive output pad) and second output pad OUTN_TIA (negative output pad).

[0084] Photodiode (PD) die: Its light-receiving aperture should be located at the horizontal cross intersection inside the packaged metal casing, which is the focal area of ​​the lens at the top of the package. The PD die has anode pads and cathode pads.

[0085] Two separate external filter capacitors:

[0086] The first filter capacitor C1 has a capacitance of 470pF.

[0087] The second filter capacitor C2 has a capacitance of 1nF.

[0088] Figure 5 This patent demonstrates a ROSA_PCB structure solution with strong electromagnetic interference resistance for FTTR or FTTH applications. In traditional receiver ROSA designs, the cathode bias of the PD is generated by the TIA die (DIE), and the PD cathode is filtered by the internal filter capacitor C1 of the TIA die (DIE). However, integrating the filter capacitor on-chip consumes a significant amount of chip area and cannot achieve ideal EMC performance. Electromagnetic interference signals from different sources enter the ROSA metal casing from the condenser lens and the pins of the metal casing (metal antenna). When they couple to the cathode of the PD, the parasitic capacitance of the PD itself couples the interference into the TIA die (DIE). Since the transimpedance amplifier amplifies extremely weak signals, electromagnetic interference greatly reduces the receiving sensitivity of the transimpedance amplifier and shortens the maximum signal range that the ROSA can detect.

[0089] Figure 5 It is an equivalent circuit model, including the TO package and its four pins: VDD_TO, GND_TO, OUTP_TO, OUTN_TO; the bare DIE chip TIA on the TO package and its five pins: VDD_TIA, PINA_TIA, GND_TIA, OUTP_TIA, OUTN_TIA; wire bonding inductors L1, L2, L3, L4, and L5; first filter capacitor C1, second filter capacitor C2, and photodiode model PD.

[0090] One end of the wire bonding inductor L1 is connected to the VDD_TIA pin of the chip, and the other end is connected to the VDD_TO pin of the TO package, the cathode of the photodiode PD, and one end of the filter capacitors C1 and C2.

[0091] One end of the wire bonding inductor L2 is connected to the PINA_TIA pin of the chip, and the other end is connected to the anode of the photodiode PD.

[0092] One end of the wire bonding inductor L3 is connected to the GND_TIA pin of the chip, and the other end is connected to the VDD_TO pin of the TO package and the metal casing of the TO package.

[0093] One end of the wire bonding inductor L4 is connected to the OUTP_TIA pin of the chip, and the other end is connected to the OUTP_TO pin of the TO package.

[0094] One end of the wire bonding inductor L5 is connected to the OUTN_TIA pin of the chip, and the other end is connected to the OUTN_TO pin of the TO package.

[0095] The other end of the first filter capacitor C1 and the second filter capacitor C2 is connected to the TO packaged metal casing.

[0096] 2. Core wire bonding connection relationship

[0097] like Figure 7 As shown, the components are electrically interconnected via gold wires, which are equivalent to wire bonding inductors (L1-L5) in the circuit. The specific connections are as follows:

[0098] The first connection (corresponding to the function of wire bonding inductor L1): A gold wire is used to interconnect the cathode pad of the PD die, the first terminal of the first filter capacitor C1, and the power supply pin VDD_TO of the TO package. This gold wire constitutes the first conductive connection.

[0099] The second and third connections (corresponding to circuit principles, physically they are two independent gold wires):

[0100] A gold wire is used to connect the first end of the second filter capacitor C2 to the power supply pin VDD_TO to form a second conductive connector.

[0101] Use another gold wire to connect the first end of the second filter capacitor C2 to the power pad VDD_TIA of the TIA die to form a third conductive connection.

[0102] Key process requirements: During the wire bonding operations for the second and third connections described above, the operator should control the gold wire bonding machine to ensure that both gold wires are connected with the lowest possible span and the shortest possible straight-line distance. This aims to minimize the parasitic inductance (i.e., the equivalent wire bonding inductance) of these two conductive paths, thereby providing an extremely low high-frequency impedance path for the power node at high operating frequencies.

[0103] Fourth connection (corresponding to wire bonding inductor L2): A gold wire is used to connect the anode pad of the PD die to the input pad PINA_TIA of the TIA die to form a fourth conductive connection.

[0104] Other necessary connections:

[0105] The other end (second end) of C1 and C2 is fixed to the gold-plated gasket by conductive silver paste, thereby achieving connection with the metal casing (ground).

[0106] The ground pad GND_TIA of the TIA die is connected to the casing ground via a gold wire.

[0107] The output pads OUTP_TIA and OUTN_TIA of the TIA die are connected to the output pins OUTP_TO and OUTN_TO of the TO package via gold wires, respectively.

[0108] 3. Working principle and effects

[0109] Figure 6 This diagram illustrates the specific path of electromagnetic interference intruding into the ROSA from the PINK pin. L0 is the parasitic inductance of the ROSA pin, while L1 and L2 are the wire bonding inductances of the TIA die (DIE). Generally, because the ROSA pin traces are longer than the TIA die wire bonding length, the typical value of L0 is much larger than that of L1 and L2. Furthermore, the parasitic capacitance PD_CAP of the photodiode (PD) is typically in the hundreds of fF, and the parasitic resistance PD_RES is typically in the MΩ range. In the context of FTTR or FTTH, the typical transmit and receive rates extend from 1.25Gbps to 10Gbps. The capacitive reactance of capacitors gradually transitions towards a short circuit, and the inductive reactance of inductors gradually transitions towards an open circuit. When electromagnetic interference in space induces a current on the cathode wire of the photodiode PD, if the capacitance values ​​of the filter capacitors C1 and C2 are not designed to be large enough, part of the interference current will invade the interior of the TIA die (DIE) through the parasitic capacitance PD_CAP of the photodiode. After being amplified by the feedback resistor RF, a noise voltage related to the interference signal is generated at the output terminal of the TIA die (DIE), making it impossible to distinguish the real photoelectric signal, thus greatly reducing the sensitivity of ROSA.

[0110] Therefore, in the improved circuit design, this patent uses the same external power supply VDD_ROSA as the chip VDD_TIA to bias the cathode of the photodiode PD. This not only allows for the use of sufficiently large VDD terminal filter capacitors C1 and C2 to filter the cathode of the photodiode PD, but also guides the interference current generated by electromagnetic induction to ground through the capacitive reactance of C1 and C2. Furthermore, the bias circuit of the PD does not need to be integrated inside the TIA die (DIE), which greatly reduces the manufacturing cost of ROSA while improving the overall EMI resistance of ROSA.

[0111] In this structure, the cathode bias voltage (VPD) of the PD is directly derived from a stable external power supply VDD_TO. A proprietary 470pF capacitor C1 provides strong, adjacent filtering for the PD cathode node. Simultaneously, a 1nF capacitor C2 serves both to decouple the TIA power supply VDD_TIA and, together with C1, contributes to the VDD_TO network. When external electromagnetic interference (such as...) occurs... Figure 2 , Figure 6 When coupled to the PD cathode or power network (as shown), the high-frequency interference current will be rapidly guided to ground (casing) via the low capacitive reactance paths of C1 and C2, and will not be able to significantly intrude into the high-gain TIA input stage through the parasitic capacitance of the PD. Therefore, as Figure 10 As shown in the eye diagram on the right, this solution can maintain a clear eye opening even under significant electromagnetic interference, improving the receiving sensitivity from -20dBm in the traditional solution to -28.8dBm.

[0112] Specific Implementation Method Two (Scheme Two: Single Capacitor Sharing Scheme): This implementation method corresponds to... Figure 8 The circuit schematic shown and Figure 9 The diagram shows the internal wire bonding structure of the TO package, and Figure 11 .

[0113] 1. Module Structure

[0114] The module structure of this embodiment is basically the same as that of the first embodiment, with the core difference being that the first filter capacitor C1 with a capacitance of 470pF is removed. Only a second filter capacitor C2 with a capacitance of 1nF is retained inside the module.

[0115] 2. Core string connection relationship

[0116] like Figure 9 As shown, the wire connection relationship is adjusted as follows:

[0117] PD cathode connection: The cathode pad of the PD die is directly connected to the power pin VDD_TO via a gold wire, which constitutes the fifth conductive connection. C1 and its related three-way connection have been eliminated.

[0118] C2 Connection to Power Supply: Completely consistent with the first embodiment, the first terminal of capacitor C2 is connected to VDD_TO via a second conductive connector, and to VDD_TIA via a third conductive connector. Similarly, when wiring these two wires, the minimum and shortest possible length must be followed.

[0119] The remaining connections are the same as in Implementation Method 1: the connection from the PD anode to PINA_TIA (fourth conductive connector), C2 grounding, TIA grounding, and output connection.

[0120] 3. Working principle and effects

[0121] This solution simplifies the design by merging the cathode of the PD die and the power supply VDD_TIA of the TIA die at the VDD_TO pin, sharing the same 1nF high-capacity filter capacitor C2. Although a dedicated C1 is eliminated, the 1nF capacitance is significantly larger than traditional on-chip capacitors, and optimized low-inductance wiring still provides sufficiently effective filtering for the PD cathode node, resulting in EMC performance close to that of Solution 1. Its greatest advantage lies in further reducing bill of materials (BOM) costs, providing a highly competitive solution for cost-sensitive applications. Figure 10 The excellent eye diagram performance is also applicable to this solution.

[0122] In summary, this invention successfully transfers the bias and filtering of the PD cathode from inside the TIA die to the outside through the two specific VPD wire bonding schemes described above. By utilizing discrete large capacitors and optimized low-inductance wire bonding technology, it fundamentally solves the pain point of insufficient anti-interference capability of traditional ROSA, while providing a flexible choice in terms of performance and cost.

[0123] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. An electromagnetic interference-resistant TO-packaged optical receiver module, comprising a metal casing and a power supply pin VDD_TO, a ground pin GND_TO, a first signal output pin OUTP_TO, and a second signal output pin OUTN_TO extending out of the casing, wherein a stage is provided inside the metal casing, characterized in that, Also includes: TIA and PD wafers are mounted on the platform. First filter capacitor C1 and second filter capacitor C2; in, The TIA die is provided with a power pad VDD_TIA, an input pad PINA_TIA, a ground pad GND_TIA, a first output pad OUTP_TIA, and a second output pad OUTN_TIA. The PD die is provided with an anode pad and a cathode pad; The first terminal of the first filter capacitor C1 is electrically connected to the cathode pad of the PD die and the power supply pin VDD_TO through the first conductive connector; The second terminal of the first filter capacitor C1 is electrically connected to the metal casing; The first end of the second filter capacitor C2 is electrically connected to the power supply pin VDD_TO through the second conductive connector, and is electrically connected to the power supply pad VDD_TIA of the TIA die through the third conductive connector; The second terminal of the second filter capacitor C2 is electrically connected to the metal casing; The anode pad of the PD die is electrically connected to the input pad PINA_TIA of the TIA die via a fourth conductive connector.

2. The TO-packaged optical receiver module with electromagnetic interference resistance according to claim 1, characterized in that, The first filter capacitor C1 and the second filter capacitor C2 are discrete surface-mount capacitors; the capacitance of the first filter capacitor C1 is 470pF and the capacitance of the second filter capacitor C2 is 1nF.

3. The TO-packaged optical receiver module with electromagnetic interference resistance according to claim 1, characterized in that, The first conductive connector, the second conductive connector, the third conductive connector, and the fourth conductive connector are made of gold wire.

4. A method for internal wire bonding of a TO-packaged optical receiver module as described in any one of claims 1-3, characterized in that, Includes the following steps: S1. Fix the TIA die and PD die onto the stage inside the TO packaged metal housing; S2. Fix the first filter capacitor C1 and the second filter capacitor C2 inside the metal tube or on the platform, and electrically connect the second end of the first filter capacitor C1 and the second end of the second filter capacitor C2 to the metal tube. S3. Perform wire bonding, including: S31. Use gold wire to interconnect the cathode pad of the PD die, the first end of the first filter capacitor C1 and the power supply pin VDD_TO to form the first conductive connector. S32. Connect the first end of the second filter capacitor C2 to the power supply pin VDD_TO using gold wire to form the second conductive connector; S33. Use gold wire to connect the first end of the second filter capacitor C2 to the power pad VDD_TIA of the TIA die to form the third conductive connector; S34. Use gold wire to connect the anode pad of the PD die to the input pad PINA_TIA of the TIA die to form the fourth conductive connector.

5. The wire bonding method according to claim 4, characterized in that, In steps S32 and S33, during the wire bonding process, two gold wires are connected with the lowest possible span and the shortest possible distance.

6. An electromagnetic interference-resistant TO-packaged optical receiver module, comprising a metal casing and a power supply pin VDD_TO, a ground pin GND_TO, a first signal output pin OUTP_TO, and a second signal output pin OUTN_TO extending out of the casing, wherein a stage is provided inside the metal casing, characterized in that, Also includes: TIA die and photodiode PD die are mounted on the platform; A second filter capacitor C2; in, The TIA die is provided with a power pad VDD_TIA, an input pad PINA_TIA, a ground pad GND_TIA, a first output pad OUTP_TIA, and a second output pad OUTN_TIA. The PD die is provided with an anode pad and a cathode pad; The cathode pad of the PD die is electrically connected to the power supply pin VDD_TO via a fifth conductive connector; The first end of the second filter capacitor C2 is electrically connected to the power supply pin VDD_TO through the second conductive connector, and is electrically connected to the power supply pad VDD_TIA of the TIA die through the third conductive connector; The second terminal of the second filter capacitor C2 is electrically connected to the metal casing; The anode pad of the PD die is electrically connected to the input pad PINA_TIA of the TIA die via a fourth conductive connector.

7. The TO-packaged optical receiver module for electromagnetic interference resistance according to claim 6, characterized in that, The second filter capacitor C2 is a discrete surface-mount capacitor; the capacitance of the second filter capacitor C2 is 1nF.

8. The TO-packaged optical receiver module with electromagnetic interference resistance according to claim 6, characterized in that, The fifth, second, third, and fourth conductive connectors are made of gold wire.

9. A method for internal wire bonding of a TO-packaged optical receiver module as described in any one of claims 6-8, characterized in that, Includes the following steps: P1. Fix the TIA die and PD die onto the stage inside the TO package metal housing; P2. Fix a second filter capacitor C2 inside the metal tube or on the platform, and electrically connect the second end of the second filter capacitor C2 to the metal tube. P3. Perform wire bonding, including: P31. Use gold wire to connect the cathode pad of the PD die to the power supply pin VDD_TO to form the fifth conductive connector; P32. Connect the first end of the second filter capacitor C2 to the power supply pin VDD_TO using gold wire to form the second conductive connector. P33. Use gold wire to connect the first end of the second filter capacitor C2 to the power pad VDD_TIA of the TIA die to form the third conductive connector; P34. Use gold wire to connect the anode pad of the PD die to the input pad PINA_TIA of the TIA die to form the fourth conductive connector.

10. The wire bonding method according to claim 9, characterized in that, In steps P32 and P33, during the wire bonding process, two gold wires are connected with the lowest possible span and shortest possible distance.

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