Power diode based on n-Si / (n-Si)-(ZIF-8) / Ag composite structure, 3D packaging chip and application

Abstract

The invention discloses a power diode based on an MOF, a preparation method, a 3D chip packaging method and application, belongs to the technical field of electronic materials and power devices, and particularly relates to a composite structure based on an n-Si substrate / an (n-Si)-(ZIF-8) composite layer / an Ag layer, preparation, a 3D chip packaging method and application of the composite structure in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate / ''(n-Si)-(ZIF-8) composite layer'' / Ag layer composite structure exceeds 200V, the forward conduction voltage of the power diode is 0.25-1.5 V, the reverse bias voltage applied to the power diode is 0-200V, the reverse leakage current is basically not increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage-100V). Compared with a conventional power diode based on an n-Si substrate / Ag layer Schottky structure, the performance of the power diode provided by the invention has the advantages that although the forward voltage is basically unchanged, the reverse voltage is increased by 80-400%, the reverse saturation current is reduced by 50-800%, and the highest yield reaches 95%.

Description

Technical Field

[0001] This invention belongs to the fields of electronic materials technology and power device technology, specifically relating to a composite structure based on an n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer, its preparation, 3D chip packaging method, and its application in the field of power devices. Background Technology

[0002] With the rapid development of science and technology, microelectronics, as the foundation of electronic information technology and a core technology of the information industry, and materials, as the material basis and supporting industry for social development and the modern economy, are an important research direction in microelectronics and play a vital role in social development. In the current context, with the rise of electric vehicles, renewable energy, and the digital revolution, the global power diode market continues to benefit from the rapid growth in these fields. Power semiconductors, as the core of power electronic devices for power conversion and circuit control, can realize functions such as frequency conversion, phase conversion, voltage conversion, and inversion. They play an irreplaceable key role in current high-power, high-current, high-frequency, and high-speed applications, especially in terms of voltage resistance, conductivity, thermal management, and energy efficiency. However, traditional semiconductor materials such as germanium (Ge), crystalline silicon (Si), and gallium nitride (GaN) typically have complex manufacturing processes and extremely high precision requirements for equipment, greatly increasing process energy consumption and production costs, failing to meet the demands of modern "high-efficiency use." Therefore, exploring new principles, new materials, new structures, and types with superior performance and lower costs has become an urgent need in the current scientific research and production fields.

[0003] MOFs (metal-organic frameworks) are extremely versatile ultraporous nanomaterials that can be used to store, separate, release, and modify virtually anything. Scientists have designed over 88,000 precisely customized MOFs for applications ranging from agriculture to industry. The unique structure and chemical properties of MOFs endow them with excellent insulation and breakdown voltage under electric fields. By optimizing the crystal structure and composition of MOFs, their breakdown voltage performance can be improved, thereby enhancing the safety and reliability of power devices. In device design, precisely controlling the interface between MOFs and other materials can reduce interface defects and enhance breakdown voltage characteristics. This interface optimization can effectively reduce current leakage and improve the breakdown voltage level of devices.

[0004] The paper "Graphene-silicon Schottky devices for operation in aqueous environments: Device performance and sensing application" (ACS Applied Materials & Interfaces. 14.38. 43131-43140) introduces a method for fabricating Schottky junctions. A single layer of CVD-grown graphene is integrated onto an n-type Si substrate using a wet transfer technique. A Cr / Au composite electrode (5–50 nm) is deposited using electron beam evaporation. Annealing at 350–450 °C under nitrogen atmosphere optimizes the interfacial contact, exhibiting typical Schottky characteristics. The current-voltage (IV) characteristic curves of the Schottky junction are measured, and the rectification ratio at 0.3 V is found to be 6.2 × 10⁻⁶. 2 Its rectification ratio is relatively small.

[0005] The paper "Graphene-Silicon Schottky Diodes" (Nano Letters, 11.5, 1863-1867) introduces a method for fabricating Schottky junctions. Vertically oriented graphene nanowalls are directly grown on heavily doped n+ Si. Ti / Pt / Au (20 / 30 / 100 nm) interdigitated electrodes are fabricated using magnetron sputtering. Interfacial defects are eliminated through rapid thermal annealing, exhibiting typical Schottky characteristics. Based on the current-voltage characteristic curves of the Schottky junctions tested in the literature, its rectification ratio at 0.3 V is found to be 0.8 × 10⁻⁶. 3 Its rectification ratio is relatively small. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention provides an n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure, its preparation method, 3D chip packaging method, and its application, in order to repair silicon wafer defects, reduce leakage current, improve reverse withstand voltage and rectification effect, and increase yield.

[0007] To achieve the objectives described in this invention, this invention employs an n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure, wherein ZIF-8 is 2-methylimidazolium zinc MOF.

[0008] Firstly, the composite structure described in this invention is specifically an n-Si / (n-Si)-(ZIF-8) / Ag composite structure, which includes, from bottom to top, an n-Si substrate layer, a (n-Si)-(ZIF-8) composite layer, and an Ag layer.

[0009] Furthermore, within the internal structure of the (n-Si)-(ZIF-8) composite layer, Zn atoms in ZIF-8, Si atoms in n-Si, and -OH groups on the n-Si surface collectively form Si-O-Zn bonds; between the n-Si substrate layer and the (n-Si)-(ZIF-8) composite layer, P atoms in the n-Si substrate layer, -OH groups on the surface of the n-Si substrate layer, -OH groups on the surface of the n-Si substrate layer, and -OH groups on the n-Si surface inside the (n-Si)-(ZIF-8) composite layer, as well as the (n-Si)-(ZIF-8) composite layer, form Si-O-Zn bonds. The Zn atoms in the ZIF-8 composite layer inside the (n-Si)-(ZIF-8) composite layer form PO-Zn bonds; between the Ag layer and the (n-Si)-(ZIF-8) composite layer, the Ag atoms in the Ag layer and the N atoms in the ZIF-8 composite layer inside the (n-Si)-(ZIF-8) composite layer form Ag-N bonds; the thin film structure formed by the Ag layer and the thin film structure formed by the (n-Si)-(ZIF-8) composite layer are in contact through van der Waals forces; the interface between the Ag layer and the n-Si substrate layer forms a Schottky junction.

[0010] Furthermore, the thickness of the n-Si substrate layer is 0.01~2.0 mm, preferably 0.1~1.0 mm, more preferably 0.3~0.6 mm; the thickness of the (n-Si)-(ZIF-8) composite layer is 0.1~1000 nm, preferably 1~500 nm, more preferably 10~200 nm; and the thickness of the Ag layer is 1~1000 nm, preferably 10~500 nm, more preferably 30~200 nm.

[0011] Secondly, the present invention also provides a method for preparing the composite structure, which involves first etching an n-Si substrate, then using ZIF-8 electroplating solution to electrodeposit a (n-Si)-(ZIF-8) composite layer on the etched n-Si substrate, and then depositing an Ag layer.

[0012] Furthermore, the ZIF-8 electroplating solution is prepared by dissolving sodium hyaluronate powder in deionized water, then adding ethanol and mixing thoroughly, and finally adding ZIF-8 powder to the mixed solution. The deposited Ag layer is achieved using a vacuum evaporation method.

[0013] As a preferred method for preparing composite structures, the following steps can be employed:

[0014] (1) Preparation of ZIF-8 electroplating solution: 1×10 -4 mol / L ~ 5×10 -4Dissolve mol / L sodium hyaluronate powder in 10-50 mL of deionized water with stirring to obtain precursor solution 1; then add 40-100 mL of ethanol to precursor solution 1 with continuous stirring and mix well to obtain precursor solution 2; then add 50-200 mg of ZIF-8 particles to precursor solution 2 for dispersion, and finally treat with ultrasound for 10-100 min to obtain electroplating solution.

[0015] (2) Etching n-Si substrate: Cut the n-Si substrate into a substrate with a length of 1.50~2.50 cm and a width of 1.20~1.70 cm. After cleaning, etch the polished surface for 3~12 min.

[0016] (3) Preparation of n-Si substrate / “(n-Si)-(ZIF-8) composite layer” structure: The n-Si substrate prepared in step 2) is used as the working electrode, and a platinum sheet is used as the counter electrode. The three electrodes are immersed in the electroplating solution prepared in step 1). Electrodeposition is performed for 30-500 s under an applied voltage of 1-20 V, followed by annealing at 50-300 ℃ (for 30-240 min).

[0017] (4) Preparation of n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure: Deposit a 30~200 nm Ag layer on the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” structure described in step 3). Then, anneal at 100~600 ℃ for 30~240 min in an inert atmosphere, which is argon or nitrogen, to obtain the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure.

[0018] It should be noted that in this invention, the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure, from bottom to top, consists of a flat n-Si substrate, followed by a (n-Si)-(ZIF-8) composite layer. The n-Si portion within the composite layer has fine and irregular penetrating three-dimensional slits, approximately 20-30 slits per square micrometer, with a slit length of approximately 50-3000 nm and a slit width of approximately 40-600 nm. Furthermore, the walls of these slits are filled with ZIF-8 material of a nano-dodecahedral structure, with a filling degree of 40-80%. The top layer is an Ag layer, where 40-60% of the Ag layer's area is in contact with the n-Si on the upper surface of the (n-Si)-(ZIF-8) composite layer, and the remaining area is in contact with the ZIF-8 structure on the walls of the three-dimensional slits and the bottom n-Si substrate. In its overall structure, the thickness of the n-Si substrate is preferably 0.3~0.6 mm; the thickness of the (n-Si)-(ZIF-8) composite layer is preferably 10~200 nm, and the volume of each ZIF-8 structure is preferably 2.1~3.1 nm. 3 The thickness of the Ag layer is preferably 30~200 nm. Within the internal structure of the "(n-Si)-(ZIF-8) composite layer," Zn atoms in ZIF-8, Si atoms in n-Si, and -OH groups on the n-Si surface together form Si-O-Zn bonds, with a bond length preferably 3.5~3.9 Å. Between the n-Si substrate and the "(n-Si)-(ZIF-8) composite layer," P atoms in the n-Si substrate, -OH groups on the n-Si substrate surface, -OH groups on the n-Si surface inside the "(n-Si)-(ZIF-8) composite layer," and Zn atoms in ZIF-8 inside the "(n-Si)-(ZIF-8) composite layer" together form PO-Zn bonds, with a bond length preferably 3.3~3.8 Å. Between the Ag layer and the (n-Si)-(ZIF-8) composite layer, Ag atoms in the Ag layer and N atoms in the ZIF-8 layer within the (n-Si)-(ZIF-8) composite layer form Ag-N bonds, preferably with a bond length of 2.1~2.5 Å. Simultaneously, the thin film structures formed by the Ag layer and the (n-Si)-(ZIF-8) composite layer are in contact through van der Waals forces, with a distance of 3~5 Å between the two thin films being preferred. A Schottky junction is formed at the interface between the Ag layer and the n-Si substrate.

[0019] The structure contains the elements Si, Ag, O, N, Zn, P and C, with the following mass percentages: Si = (35~45)%, Ag = (20~30)%, O = (5~15)%, N = (5~10)%, Zn = (5~10)%, P = (3~5)%, and the rest is C.

[0020] Thirdly, the present invention provides a Schottky power diode based on the above-mentioned n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure, which uses the composite structure as a substrate and deposits an Ag layer on the back side of the n-Si substrate to obtain Ag layer / n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer.

[0021] In this invention, the Schottky power diode formed by the composite structure of an n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer significantly increases the reverse breakdown voltage. ZIF-8 possesses high porosity and tunable pore size, effectively filling microcracks and grain boundary defects in the silicon substrate. Furthermore, the distribution of ZIF-8 avoids the electric field concentration phenomenon caused by defects in traditional materials, thus achieving interface defect repair and electric field homogenization. Secondly, the metal-organic framework structure of ZIF-8 can adjust its electronic properties through ligands. The imidazole ligands on the ZIF-8 surface adsorb and bind to silicon dangling bonds, reducing the interface state density and suppressing reverse leakage current, thereby optimizing bandgap modulation and the Schottky barrier. Compared to the composite structure without the (n-Si)-(ZIF-8) composite layer, this composite structure increases the reverse breakdown voltage by four times and the rectification ratio to 7 × 10⁻⁶. 4 The reverse leakage current is reduced to 20-60% of its original value.

[0022] Fourth, the present invention also provides a composite power diode chip, which is obtained by packaging and connecting at least three Schottky power diodes using a 3D heterogeneous packaging structure, with the aforementioned composite structure forming a Schottky power diode as the basic unit. Preferably, the composite power diode chip is formed by packaging three Schottky power diodes using a 3D heterogeneous packaging structure, and its overall structure mainly includes a bottom heat dissipation interconnection structure, an intermediate functional layer, and an outer packaging protection structure.

[0023] The bottom heat dissipation interconnection structure includes an alumina ceramic heat dissipation substrate and an insulating substrate. The insulating substrate has rectangular interlocking slots etched in it. The surface of the insulating substrate is covered with a polyimide (PI) insulating adhesive layer, on which is a copper wire network with a microstrip structure. The insulating substrate can be made of materials such as non-conductive glass substrate.

[0024] The middle functional layer consists of two regions: the left region has two Schottky power diodes and the right region has one Schottky power diode.

[0025] The two diodes in the left region are arranged in a double-layer stacked configuration. The lower layer is a horizontal flip-chip Schottky power diode unit SC1, whose anode is bonded to the underlying microstrip line via conductive silver paste. The surface of SC1 is covered with a first PI dielectric isolation layer, and a vertical interconnect cavity is formed in the center of this layer. The upper layer is a horizontal upright Schottky power diode unit SC2, whose surface is covered with a second PI dielectric isolation layer. The cathode of SC2 is connected to the cathode of SC1 via conductive silver paste through the vertical interconnect cavity, and is connected to the underlying microstrip line network by wiring across the surface of the first PI dielectric layer. The anode of SC2 is connected to the corresponding lead frame via a conductive silver paste that extends across the surface of the second PI dielectric isolation layer.

[0026] The right area is a vertically embedded Schottky power diode unit SC3, which is precisely fitted into a rectangular slot in the insulating substrate. The anode and cathode of SC3 are connected to the underlying microstrip network through conductive silver paste.

[0027] The outer encapsulation and protection structure is encapsulated with epoxy resin to form a coating layer; after curing, it is polished to expose the lateral width and height of the alumina ceramic substrate, forming a lateral heat dissipation path.

[0028] The underlying heat dissipation interconnect structure also includes five lead frames, which extend from the top of the cladding layer. The lead frames are connected as follows: Lead frame one is connected to the SC1 anode via a microstrip line; lead frame two is connected to the SC2 anode via a microstrip line; lead frame three serves as a common cathode and is connected to the common junction of SC1 and SC2 via a microstrip line; lead frame four is connected to the SC3 cathode via a microstrip line; and lead frame five is connected to the SC3 anode via a microstrip line. After chip packaging, the five lead frames constitute the five pins of the chip.

[0029] Fifth, the present invention also provides a packaging method for the Schottky composite power diode chip, comprising:

[0030] First, the alumina ceramic plate is plasma cleaned, and an insulating substrate is fixed to its surface. A fitting groove is formed within the insulating substrate using deep reactive ion etching (RIE). After the groove is formed, soluble polyvinyl alcohol (PVA) is used as a sacrificial material to fill it. Chemical mechanical polishing (CMP) is then performed to make its surface highly flush with the insulating substrate, creating a temporary flat working surface. Next, a polyimide (PI) insulating adhesive layer is spin-coated. After the PI layer is coated, the required rectangular contact windows are precisely etched onto the PI layer using photolithography and reactive ion etching (RIE). Finally, the PVA sacrificial layer is dissolved and removed using a warm water bath. Simultaneously, the forming of windows on the PI adhesive layer and the clearing of slots within the insulating substrate were achieved. Subsequently, a copper conductor network with a microstrip structure was constructed on the surface of the PI layer using a vacuum thermal evaporation process combined with mask patterning. Then, gold wire ball bonding was used to bond and interconnect the copper conductors with five lead frames. The specific connection frames are as follows: lead frame one is connected to the SC1 anode port via a microstrip line; lead frame two is connected to the SC2 anode port via a microstrip line; lead frame three serves as a common cathode and is connected to the common connection node of SC1 and SC2 via a microstrip line; lead frame four is connected to the SC3 cathode port via a microstrip line; and lead frame five is connected to the SC3 anode port via a microstrip line.

[0031] Next, the left-side double-layer stack assembly is performed: First, a first PI dielectric isolation layer is spin-coated onto the cathode surfaces of SC1 and SC2 respectively, and windows are created using photolithography to form a cavity structure for vertical interconnection; then, highly conductive silver paste is filled into the cavity, and the silver paste is transferred from the cavity to the edge of the PI layer using a vacuum thermal evaporation process to construct the pre-interconnection end; after completing the above pretreatment, SC1 and SC2 are joined together with their cathode surfaces, and the PI layer and silver paste structure are used to fix them together to form a preliminary "SC1-SC2" stack; then, the stack is rotated 90° so that its side faces upward as a new process plane, and the PI dielectric layer is spin-coated and cured sequentially, and then magnetron sputtering is used on this side. The copper conductors of the microstrip line structure are constructed on the surface. Then, the stacked body with the completed side vertical interconnects is treated as a whole unit, with the anode of SC1 facing down, and is bonded to the preset copper conductor node of the bottom layer in one step using conductive silver paste. Finally, a second PI dielectric isolation layer is spin-coated on the upper surface of SC2. After photolithography to open the window, the horizontal wiring from the anode of SC2 to the side vertical microstrip line structure is completed by magnetron sputtering, thereby forming a complete vertical structure connection. In the right area, SC3 is embedded in the slot and connected to the bottom microstrip line structure network by conductive silver paste. Finally, epoxy resin is poured in by pressure injection and cured to form a coating layer. After curing, it is polished to expose the lateral width and height of the alumina ceramic substrate, forming a lateral heat dissipation path.

[0032] Sixth, the present invention also provides an application of the aforementioned composite power diode chip, which mainly includes the following functional units: a single-channel Schottky rectifier unit, a bipolar overvoltage protection unit, a high-voltage cascade withstand voltage unit, a two-phase common cathode rectifier unit, and a cascaded current-resistant extension unit. More specifically: the single-channel Schottky rectifier unit includes pin 1, pin 2, pin 3, pin 4, and pin 5, for a total of five pins; the bipolar overvoltage protection unit includes pin 1 and pin 2, for a total of two pins; the high-voltage cascade withstand voltage unit includes pin 2 and pin 4, for a total of two pins; the two-phase common cathode rectifier unit includes pin 1, pin 2, and pin 3, for a total of three pins; and the cascaded current-resistant extension unit includes pin 1, pin 2, and pin 5, for a total of three pins.

[0033] The single-channel Schottky rectifier unit uses a fabricated n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure Schottky diode. By connecting the pins (pin 1, pin 2, pin 3, pin 4, and pin 5) of the composite structure Schottky diode to an external circuit, it achieves unidirectional conduction and reverse blocking functions. It is mainly used in: rectifier units in high-frequency switching power supplies, polarity protection circuits in photovoltaic inverters, and reverse voltage protection in low-power devices.

[0034] The bipolar overvoltage protection unit utilizes a Schottky power diode (Schottky composite unit) with an n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure, employing an anti-series configuration. Specifically, the cathodes of Schottky composite unit SC1 and SC2 are connected to form a bidirectional conduction path. It is primarily used for voltage clamping protection in AC circuits, ESD protection modules in communication equipment, and transient voltage suppression in automotive electronic systems. The Schottky composite unit is essentially a Schottky power diode unit.

[0035] The aforementioned high-voltage cascade withstand voltage unit connects the cathode of the Schottky composite unit SC1 to the anode of the Schottky composite unit SC3 in a cascade configuration. High-voltage withstand capability is achieved through stacked reverse withstand voltage, while maintaining low forward conduction voltage drop characteristics. It is primarily used in: high-voltage DC power supply input stages, pre-charging circuits of electric vehicle charging piles, and bus voltage divider protection for industrial frequency converters.

[0036] The two-phase common-cathode rectifier unit connects the cathodes of Schottky composite units SC1 and SC2 together as a common cathode, allowing for independent output from both anodes. It is primarily used in: two-phase AC rectifier bridge common-cathode topologies, common-ground isolation in dual-channel data acquisition systems, and crosstalk protection for high-precision ADC input stages. The cascaded current-capable extension unit connects the cathodes of Schottky composite units SC1 and SC2 in parallel to the anode of Schottky composite unit SC3. It is primarily used in: pre-regulator stages of high-power AC / DC converters, PFC rectifier stages in electric vehicle OBCs, and redundant protection circuits for high-current loads in industrial applications.

[0037] The single-channel Schottky rectifier unit is divided into three groups. The first group includes a Schottky composite unit SC1, pin 1, and pin 3. Pin 1 is the anode, connected to the anode of the Schottky composite unit SC1 via a copper wire. Pin 3 is the cathode, connected to the cathode of the Schottky composite unit SC1 via conductive silver paste and printed copper wire. The second group includes a Schottky composite unit SC2, pin 2, and pin 3. Pin 2 is the anode, connected to the anode of the Schottky composite unit SC2 via conductive silver paste and printed copper wire. Pin 3 is the cathode, connected to the cathode of the Schottky composite unit SC2 via conductive silver paste and printed copper wire. The third group includes a Schottky composite unit SC3, pin 4, and pin 5. Pin 4 is the cathode, connected to the cathode of the Schottky composite unit SC3 via conductive silver paste and printed copper wire. Pin 5 is the anode, connected to the anode of the Schottky composite unit SC3 via conductive silver paste and printed copper wire.

[0038] The bipolar overvoltage protection unit does not distinguish between anode and cathode. Pin 1 is connected to the anode of Schottky composite unit SC1 through a printed copper wire, and pin 2 is connected to the anode of Schottky composite unit SC2 through conductive silver paste and a printed copper wire.

[0039] Pin 2 of the high-voltage cascade withstand voltage unit is the anode, which is connected to the anode of the Schottky composite unit SC2 through conductive silver paste and printed copper wires. Pin 4 is the cathode, which is connected to the cathode of the Schottky composite unit SC3 through conductive silver paste and printed copper wires.

[0040] Pin 3 of the two-phase common cathode rectifier unit is the cathode, which is connected to the cathodes of Schottky composite unit SC1 and Schottky composite unit SC2 through conductive silver paste and printed copper wires; pin 1 is the anode (I), which is connected to the anode of Schottky composite unit SC1 through conductive silver paste and printed copper wires; pin 2 is the anode (II), which is connected to the anode of Schottky composite unit SC2 through conductive silver paste and printed copper wires.

[0041] The cascaded current-resistant extension unit has a first pin as the anode (I), which is connected to the anode of the Schottky composite unit SC1 via conductive silver paste and printed copper wires; a second pin as the anode (II), which is connected to the anode of the Schottky composite unit SC2 via conductive silver paste and printed copper wires; and a fourth pin as the cathode, which is connected to the cathode of the Schottky composite unit SC3 via conductive silver paste and printed copper wires.

[0042] Furthermore, this invention also provides a method for operating the power diode application chip of the aforementioned composite structure. First, upon power-up, the chip supplies power, and each unit module initializes to receive the input voltage. It determines whether the input voltage is forward; if it is, current flows in from the anode. A Schottky junction with an n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure is used. The high porosity and adjustable pore size of ZIF-8 effectively fill the microcracks and grain boundary defects of the silicon substrate, avoiding electric field concentration. This allows for interface defect repair and electric field homogenization, with current flowing out from the cathode. The Schottky diode conducts under forward voltage, achieving unidirectional conduction. The metal-organic framework structure of ZIF-8 reduces interface state density and suppresses reverse leakage current by adjusting its electronic properties through ligands, enabling bandgap modulation and Schottky barrier optimization. Relevant data, such as current and voltage, are collected and exported. A rectification characteristic curve is generated based on the exported data for subsequent analysis and application. If the input voltage is not forward (i.e., reverse), the current is cut off, the diode does not conduct, effectively suppressing reverse leakage current. After processing, the process returns to the power-on state, waiting for the next voltage input. The entire process achieves efficient rectification and protection functions through the coordinated work of each unit module.

[0043] The preparation principle of the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure of the present invention is as follows:

[0044] When preparing the ZIF-8 electroplating solution, the ZIF-8 powder mainly consists of C, H, N, and Zn, with the ratio of C, H, and N atoms ranging from 20% to 30%, 30% to 40%, and 5% to 15%, respectively, and the remainder being Zn. It appears white. Sodium hyaluronate powder mainly consists of C, H, N, O, and Na, with the ratio of C, H, N, and O atoms ranging from 20% to 30%, 40% to 50%, 2% to 8%, and 15% to 25%, respectively, and the remainder being Na. It also appears white. The sodium hyaluronate powder is dissolved in deionized water with stirring. Then, ethanol is added while continuously stirring and mixed thoroughly. The ZIF-8 powder is then added to the mixed solution, and the mixture is ultrasonically treated for 10–100 min at an ultrasonic power of 10–35 W·L. -1After ultrasonic treatment, ZIF-8 powder and sodium hyaluronate powder are thoroughly mixed, allowing hyaluronic acid to coat the outer layer of ZIF-8 powder, forming a stable composite structure that facilitates movement during electroplating. When preparing the n-Si substrate / "(n-Si)-(ZIF-8) composite layer" structure, the working electrode must first be kept clean during electroplating. Its surface needs to be cleaned sequentially with acetone, ethanol, and deionized water, and finally dried with nitrogen and heated in a drying oven at 30-90°C for 3-30 minutes to obtain a clean working electrode. Secondly, the substrate for electroplating also needs to be cleaned. The N-type silicon is treated with nitrogen for 3-60 minutes, then cleaned sequentially with acetone, ethanol, and deionized water, and finally dried with nitrogen and heated in a drying oven at 30-90°C for 3-30 minutes to obtain a clean N-type silicon substrate. After stabilizing the substrate in the working electrode, electrodeposition was performed for 30-500 s under an applied voltage of 1-20 V. Subsequently, the sample was annealed at 50-300 ℃ in a nitrogen atmosphere for 30-240 min.

[0045] When preparing the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure, a vacuum evaporation mask is used. First, to ensure the purity of the Ag particles, the surface is polished with sandpaper for 3-30 minutes. Second, to prevent the introduction of other impurities during the use of the vacuum thermal evaporator, the chamber of the vacuum thermal evaporator needs to be treated with nitrogen for 2-10 minutes. Then, the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure is prepared using the vacuum thermal evaporator. The Ag layer film thickness is approximately 30-200 nm, and the evaporation rate is controlled to obtain a uniformly distributed Ag layer film. The substrate is placed in an inert atmosphere, such as argon or nitrogen, and annealed at 100–600 °C for 30–240 min to obtain an n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure. The main elements are Si, Ag, O, N, Zn, P, and C, with the mass percentages of Si, Ag, O, N, Zn, and P ranging from 35–45%, 20–30%, 5–15%, 5–10%, 5–10%, and 3–5%, respectively, and the remainder being C.

[0046] Within the internal structure of the (n-Si)-(ZIF-8) composite layer, Zn atoms in ZIF-8, Si atoms in n-Si, and -OH groups on the n-Si surface collectively form Si-O-Zn bonds with a bond length of 3.5–3.9 Å. Between the n-Si substrate and the (n-Si)-(ZIF-8) composite layer, P atoms in the n-Si substrate, -OH groups on the n-Si substrate surface, -OH groups on the n-Si surface within the (n-Si)-(ZIF-8) composite layer, and Zn atoms in ZIF-8 within the (n-Si)-(ZIF-8) composite layer collectively form PO-Zn bonds with a bond length of 3.3–3.8 Å. Between the Ag layer and the (n-Si)-(ZIF-8) composite layer, Ag atoms in the Ag layer and N atoms in the ZIF-8 layer within the (n-Si)-(ZIF-8) composite layer together form Ag-N bonds with a bond length of 2.1~2.5 Å. Simultaneously, the thin film structures formed by the Ag layer and the (n-Si)-(ZIF-8) composite layer are connected by van der Waals forces, with a distance of 3~5 Å between the two thin films. A Schottky junction is formed at the interface between the Ag layer and the n-Si substrate.

[0047] The working principle of the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure of the present invention:

[0048] The device of this invention uses a traditional Schottky junction as its core structure and employs an n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure as a power diode device, as shown in Figures 1(a) and 1(b). The Ag layer, serving as the top metal, has a thickness of 30-200 nm and forms dense contacts through vacuum evaporation. The middle "(n-Si)-(ZIF-8) composite layer" is composed of a nanoscale ZIF-8 porous framework chemically bonded to the n-Si surface. The zinc nodes of the ZIF-8 layer are bridged to the silicon lattice through Zn-O-Si covalent bonds, effectively filling lattice defects on the silicon surface and blocking leakage current paths. Under reverse bias, free electrons in the n-Si conduction band migrate toward the cathode under the influence of the reverse electric field, while the quantum confinement effect formed by the periodic channels of ZIF-8 creates an additional barrier, suppressing the lateral diffusion of charge carriers. At the same time, the Ag-N coordination bonds formed at the Ag electrode interface (derived from the imidazole ligand of ZIF-8) and the Ag-O-Si interface dipole layer synergistically enhance the electrode stability, reducing the reverse leakage current to 20-60% of its original value.

[0049] When a forward bias is applied, the hierarchical channels of ZIF-8 provide a fast carrier transport pathway. Its pore size (3.4 Å) matches the silicon lattice spacing, reducing the interfacial barrier through the charge transfer mechanism of the Zn-O-Si bonds. The Ag electrode forms a low-resistance ohmic contact through Ag-Si alloying, stabilizing the on-state voltage in the range of 0.3–3.5 V. Specifically, the hydrophobic properties of ZIF-8 effectively passivate dangling bonds on the silicon surface, and its pore size distribution (5–200 nm) blocks impurity ion migration through a size sieving effect. Ag-N bond reconstruction during annealing eliminates interfacial stress, resulting in a device yield of up to 95%. The high thermal stability of the ZIF-8 framework (decomposition temperature >550 °C) suppresses interfacial delamination at high temperatures. The imidazole ligands of ZIF-8 form a gradient barrier with n-Si, adjusting the Schottky barrier height while suppressing reverse leakage current.

[0050] In the fabrication process, ZIF-8 fills the microcracks and grain boundary defects on the n-Si substrate surface through electrophoretic deposition. Its three-dimensional porous framework effectively passivates the interface states and reduces the interface state density. The Ag electrode adopts vacuum evaporation mask technology. Through mask design, silicon wafer contamination and damage can be effectively reduced. Secondly, the synergistic optimization of Ag electrode and ZIF-8 enables the formation of low barrier contacts and chemical bond bridging. The Ag layer and ZIF-8 / Si composite layer form a uniform Schottky contact with small barrier height fluctuations. Ag forms Ag-N bonds with the imidazole ring of ZIF-8, which enhances the interface mechanical strength and suppresses interface delamination caused by high temperature thermal stress.

[0051] Compared with the prior art, the beneficial effects of the present invention are:

[0052] 1) The paper "Graphene-silicon Schottky devices for operation in aqueous environments: Device performance and sensing application" (ACS Applied Materials & Interfaces. 14.38. 43131-43140) introduces a method for fabricating Schottky junctions. It integrates CVD-grown monolayer graphene on an n-type Si substrate using a wet transfer technique, and deposits a Cr / Au composite electrode (5 / 50 nm) using electron beam evaporation. The interface contact is optimized by annealing at 350-450 °C under nitrogen atmosphere, exhibiting typical Schottky characteristics. The current-voltage (IV) characteristic curve of the Schottky junction is obtained by testing the IV curve, and the rectification ratio at 0.3 V is found to be 6.2 × 10⁻⁶. 2 The reverse leakage current is 0.5~0.8 μA. The rectification ratio of this invention is 4.1×10⁻⁶ at 0.3 V. 3As shown in Figure 6(a), the reverse leakage current is 0.12~0.5 μA.

[0053] 2) Compared to the power diode device shown in Figure 6(b) without the (n-Si)-(ZIF-8) composite layer, which has a reverse breakdown voltage of approximately 30V, the power diode based on the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure described in this invention has a reverse breakdown voltage exceeding 200V (-200~100V). The forward conduction voltage of the power diode is 0.25~1.5V, and when a reverse bias voltage of 0~200V is applied, the reverse leakage current does not increase significantly with increasing reverse bias voltage, remaining at 0.2~2.1 mA (@reverse voltage -100V). Compared to conventional power diodes based on the n-Si substrate / Ag layer Schottky structure, although the forward voltage remains essentially unchanged, the reverse voltage increases by 80~400%, the reverse saturation current decreases by 50~800%, and the yield reaches a maximum of 95%.

[0054] 3) The present invention proposes a Schottky composite power diode chip, which uses a novel 3D packaging method to obtain a 3D chip, greatly increasing the reuse of the composite power diode while reducing chip power consumption. Attached Figure Description

[0055] Figure 1(a) is a macroscopic structural schematic diagram of the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure described in this invention.

[0056] Figure 1(b) is a schematic diagram of the microstructure of the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure described in this invention.

[0057] Figure 1(c) is a schematic diagram of the ZIF-8 structure in the (n-Si)-(ZIF-8) composite layer in the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure of the present invention.

[0058] Figure 2 is a process flow diagram for the preparation of the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure described in this invention.

[0059] Figure 3(a) is a SEM image of the unfilled ZIF-8 silicon layer in the (n-Si)-(ZIF-8) composite layer of the present invention.

[0060] Figure 3(b) is a SEM image of the silicon layer electroplated with ZIF-8 in the (n-Si)-(ZIF-8) composite layer of the present invention.

[0061] Figure 3(c) is a SEM image of the silicon layer filled with ZIF-8 electroplated in the (n-Si)-(ZIF-8) composite layer of the present invention.

[0062] Figure 3(d) is another SEM image of the silicon layer electroplated with ZIF-8 in the (n-Si)-(ZIF-8) composite layer of the present invention.

[0063] Figure 3(e) is another SEM image of the spin-coated ZIF-8 silicon layer in the (n-Si)-(ZIF-8) composite layer of the present invention.

[0064] Figure 4(a) is the AFM image of the unfilled ZIF-8 silicon layer in the (n-Si)-(ZIF-8) composite layer of the present invention.

[0065] Figure 4(b) is an AFM image of the silicon layer filled with ZIF-8 in the (n-Si)-(ZIF-8) composite layer of the present invention.

[0066] Figure 5 is an XPS image of the (n-Si)-(ZIF-8) composite layer described in this invention. Figure 5(a) shows the formation of chemical bonds between Zn and O within the (n-Si)-(ZIF-8) composite layer in the n-Si / (n-Si)-(ZIF-8) / Ag composite structure; Figures 5(b) and 5(c) show the formation of chemical bonds between P, Zn, and hydroxyl groups on the n-Si surface within the (n-Si)-(ZIF-8) composite layer in the n-Si / (n-Si)-(ZIF-8) / Ag composite structure; Figures 5(d) and 5(e) show the formation of chemical bonds between N and Ag in the Ag layer within the (n-Si)-(ZIF-8) composite layer in the n-Si / (n-Si)-(ZIF-8) / Ag composite structure.

[0067] Figure 6(a) shows the rectification characteristic curves of the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure described in this invention, where each curve corresponds to the composite layer formed under different electroplating voltages: (0) Si layer without ZIF-8 filling; (1) Composite layer formed by electroplating ZIF-8 filling at 1V voltage; (2) Composite layer formed at 3V voltage; (3) Composite layer formed at 5V voltage; (4) Composite layer formed at 7V voltage.

[0068] Figure 6(b) shows the withstand voltage test results of the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure described in this invention, where (x) represents the Si layer without ZIF-8 filling, and (y) represents the composite layer formed by electroplating ZIF-8 filling at 5V voltage.

[0069] Figure 6(c) is a partially enlarged view of the pressure resistance test of the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure described in this invention.

[0070] Figure 7(a) is a 3D packaging structure diagram of the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure described in this invention.

[0071] Figure 7(b) is a discrete packaging structure diagram of the n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure described in this invention. In the figure: ① horizontal upright Schottky composite cell, ② horizontal flip-chip Schottky composite cell, ③ vertical embedded Schottky composite cell, ④ non-conductive glass substrate, ⑤ alumina heat dissipation substrate.

[0072] Figure 7(c) is a front view of the packaging of the n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure of the present invention.

[0073] Figure 7(d) is a side view of the packaging of the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure of the present invention.

[0074] Figure 7(e) is a top view of the packaging of the n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure of the present invention.

[0075] Figure 8 shows the main functional units and workflow of the n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite power diode of the present invention. Detailed Implementation

[0077] The following embodiments are further illustrations of the present invention and serve as explanations of the technical content of the present invention. However, the essence of the present invention is not limited to the embodiments described below. Those skilled in the art can and should know that any simple changes or substitutions based on the spirit of the present invention should fall within the protection scope claimed by the present invention.

[0078] Example 1

[0079] A method for preparing an n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure includes the following steps:

[0080] (1) Preparation of ZIF-8 electroplating solution: 1×10 -4mol / L sodium hyaluronate powder was dissolved in 10 mL of deionized water and stirred to obtain precursor solution 1; then 40 mL of ethanol was added to precursor solution 1 under continuous stirring and mixed evenly to obtain precursor solution 2; then 50 mg of ZIF-8 nanoparticles were added to precursor solution 2 for dispersion, and finally the electroplating solution was obtained by ultrasonic treatment for 10 min.

[0081] (2) Etching n-Si substrate: The n-Si substrate is cut into a substrate with a length of 1.50 cm and a width of 1.20 cm. After cleaning, the surface is polished by plasma etching for 3 min.

[0082] (3) Preparation of n-Si substrate / (n-Si)-(ZIF-8) composite layer structure: The n-Si substrate prepared in step 2) is used as the working electrode, and a platinum sheet is used as the counter electrode. The three electrodes are immersed in the electroplating solution prepared in step 1). Electrodeposition is performed for 30 s under an applied voltage of 1 V, followed by annealing at 50 °C for 30 min.

[0083] (4) Preparation of n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure: Vacuum evaporation thermal evaporation deposition of a 30 nm Ag layer is performed on the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” structure described in step 3). Then, it is placed in an inert atmosphere and annealed at 100 °C for 30~240 min. The inert atmosphere is argon or nitrogen to obtain the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure.

[0084] The n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure, from bottom to top, begins with a flat n-Si substrate. Next, on the n-Si substrate is the (n-Si)-(ZIF-8) composite layer. The n-Si portion within this composite layer contains tiny, irregular, penetrating three-dimensional slits, approximately 20 slits per square micrometer, with a slit length of about 50 nm and a width of about 40 nm. Furthermore, the walls of these slits are filled with ZIF-8 material of a nano-dodecahedral structure, with a filling density of 40%. The top layer is an Ag layer, with 40% of its area in contact with the n-Si on the upper surface of the (n-Si)-(ZIF-8) composite layer, and the remaining area in contact with the ZIF-8 structure on the walls of the three-dimensional slits and the bottom n-Si substrate. In its overall structure, the thickness of the n-Si substrate is 0.3 mm; the thickness of the "(n-Si)-(ZIF-8) composite layer" is 10 nm, and the volume of each ZIF-8 structure is 2.1 nm. 3The Ag layer has a thickness of 30 nm. As shown in Figures 1(a), 1(b), and 1(c), in the internal structure of the "(n-Si)-(ZIF-8) composite layer," Zn atoms in ZIF-8, Si atoms in n-Si, and -OH groups on the n-Si surface collectively form Si-O-Zn bonds with a bond length of 3.5 Å. Between the n-Si substrate and the "(n-Si)-(ZIF-8) composite layer," P atoms in the n-Si substrate, -OH groups on the n-Si substrate surface, -OH groups on the n-Si surface inside the "(n-Si)-(ZIF-8) composite layer," and Zn atoms in ZIF-8 inside the "(n-Si)-(ZIF-8) composite layer" collectively form PO-Zn bonds with a bond length of 3.3 Å. Between the Ag layer and the (n-Si)-(ZIF-8) composite layer, Ag atoms in the Ag layer and N atoms in the ZIF-8 layer within the (n-Si)-(ZIF-8) composite layer together form Ag-N bonds with a bond length of 2.1 Å. Simultaneously, the thin film structures formed by the Ag layer and the (n-Si)-(ZIF-8) composite layer are connected by van der Waals forces, with a distance of 3 Å between the two layers. A Schottky junction is formed at the interface between the Ag layer and the n-Si substrate.

[0085] The prepared n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure contains the elements Si, Ag, O, N, Zn, P, and C, with the following mass percentages: Si=35%, Ag=20%, O=5%, N=5%, Zn=5%, P=3%, and the remainder being C. Figures 3(b), 3(c), and 3(e) show SEM images of the n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure, revealing that ZIF-8 nanoparticles penetrate the gaps in the silicon wafer for repair.

[0086] Example 2

[0087] A method for preparing an n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure includes the following steps:

[0088] (1) Preparation of ZIF-8 electroplating solution: 1×10 -4 mol / L sodium hyaluronate powder was dissolved in 10 mL of deionized water and stirred to obtain precursor solution 1; then 40 mL of ethanol was added to precursor solution 1 under continuous stirring and mixed evenly to obtain precursor solution 2; then 50 mg of ZIF-8 nanoparticles were added to precursor solution 2 for dispersion, and finally the electroplating solution was obtained by ultrasonic treatment for 10 min.

[0089] (2) Etching n-Si substrate: The n-Si substrate is cut into a substrate with a length of 1.50 cm and a width of 1.20 cm. After cleaning, the surface is polished by plasma etching for 3 min.

[0090] (3) Preparation of n-Si substrate / (n-Si)-(ZIF-8) composite layer structure: The n-Si substrate prepared in step 2) is used as the working electrode, and a platinum sheet is used as the counter electrode. The three electrodes are immersed in the electroplating solution prepared in step 1). Electrodeposition is performed for 30 s under an applied voltage of 1 V, followed by annealing at 50 °C for 30 min.

[0091] (4) Preparation of n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure: A 30 nm Ag layer is vacuum evaporated and deposited on the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” structure described in step 3). Then, it is placed in an inert atmosphere and annealed at 100 °C for 30 min. The inert atmosphere is argon or nitrogen to obtain the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure.

[0092] The n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure, from bottom to top, begins with a flat n-Si substrate. Next, on the n-Si substrate is the (n-Si)-(ZIF-8) composite layer. The n-Si portion within this composite layer contains tiny, irregular, penetrating three-dimensional slits, approximately 20 slits per square micrometer, with a slit length of about 50 nm and a width of about 40 nm. Furthermore, the walls of these slits are filled with ZIF-8 material of a nano-dodecahedral structure, with a filling density of 40%. The top layer is an Ag layer, with 40% of its area in contact with the n-Si on the upper surface of the (n-Si)-(ZIF-8) composite layer, and the remaining area in contact with the ZIF-8 structure on the walls of the three-dimensional slits and the bottom n-Si substrate. In its overall structure, the thickness of the n-Si substrate is 0.3 mm; the thickness of the "(n-Si)-(ZIF-8) composite layer" is 10 nm, and the volume of each ZIF-8 structure is 2.1 nm. 3The Ag layer has a thickness of 30 nm. As shown in Figures 1(a), 1(b), and 1(c), in the internal structure of the "(n-Si)-(ZIF-8) composite layer," Zn atoms in ZIF-8, Si atoms in n-Si, and -OH groups on the n-Si surface collectively form Si-O-Zn bonds with a bond length of 3.5 Å. Between the n-Si substrate and the "(n-Si)-(ZIF-8) composite layer," P atoms in the n-Si substrate, -OH groups on the n-Si substrate surface, -OH groups on the n-Si surface inside the "(n-Si)-(ZIF-8) composite layer," and Zn atoms in ZIF-8 inside the "(n-Si)-(ZIF-8) composite layer" collectively form PO-Zn bonds with a bond length of 3.3 Å. Between the Ag layer and the (n-Si)-(ZIF-8) composite layer, Ag atoms in the Ag layer and N atoms in the ZIF-8 layer within the (n-Si)-(ZIF-8) composite layer together form Ag-N bonds with a bond length of 2.1 Å. Simultaneously, the thin film structures formed by the Ag layer and the (n-Si)-(ZIF-8) composite layer are connected by van der Waals forces, with a distance of 3 Å between the two layers. A Schottky junction is formed at the interface between the Ag layer and the n-Si substrate.

[0093] In contrast, when the repair method was changed in step 3) to spin-coating, while other steps remained the same, an n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure was obtained, named SB3. Figure 3(b) shows the SEM image of the n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure, which shows that ZIF-8 nanoparticles penetrate into the gaps of the silicon wafer for repair, with minimal impact on the silicon wafer surface. Figure 3(e) shows the SEM image of the n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure, which shows that some ZIF-8 nanoparticles penetrate into the gaps of the silicon wafer for repair, and the penetrated portion causes some stacking on the silicon wafer surface. Therefore, the experiment preferred electroplating method for repair.

[0094] Example 3

[0095] A method for preparing an Ag layer / n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer composite structure includes the following steps:

[0096] (1) Preparation of ZIF-8 electroplating solution: 1×10 -4mol / L sodium hyaluronate powder was dissolved in 10 mL of deionized water and stirred to obtain precursor solution 1; then 40 mL of ethanol was added to precursor solution 1 under continuous stirring and mixed evenly to obtain precursor solution 2; then 50 mg of ZIF-8 nanoparticles were added to precursor solution 2 for dispersion, and finally the electroplating solution was obtained by ultrasonic treatment for 10 min.

[0097] (2) Etching n-Si substrate: The n-Si substrate is cut into a substrate with a length of 1.50 cm and a width of 1.20 cm. After cleaning, the surface is polished by plasma etching for 3 min.

[0098] (3) Preparation of n-Si substrate / (n-Si)-(ZIF-8) composite layer structure: The n-Si substrate prepared in step 2) is used as the working electrode, and a platinum sheet is used as the counter electrode. The three electrodes are immersed in the electroplating solution prepared in step 1). Electrodeposition is performed for 30 s under an applied voltage of 1 V, followed by annealing at 50 °C for 30 min.

[0099] (4) Preparation of n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure: Vacuum evaporation thermal evaporation deposition of a 30 nm Ag layer is performed on the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” structure described in step 3). Then, it is placed in an inert atmosphere and annealed at 100 °C for 30 min. The inert atmosphere is argon or nitrogen to obtain the n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure.

[0100] (5) Preparation of Ag layer / n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure (Schottky power diode): Using the aforementioned n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure as the evaporation substrate, an Ag layer is prepared by thermal evaporation to obtain the Ag layer / n-Si substrate / “(n-Si)-(ZIF-8) composite layer” / Ag layer composite structure.

[0101] The preparation process diagram is as follows Figure 2As shown, the prepared n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure contains the elements Si, Ag, O, N, Zn, P, and C, with the following mass percentages: Si=35%, Ag=20%, O=5%, N=5%, Zn=5%, P=3%, and the remainder being C. Figures 3(b) and 4(b) show the SEM and AFM images of the Ag layer / n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure, respectively. It can be seen that the ZIF-8 nanoparticles penetrate into the gaps in the silicon wafer for repair. The rectification ratio at 0.3 V is 4.1 × 10⁻⁶. 3 As shown in Figure 6(a), the leakage current is 0.12 μA.

[0102] Example 4

[0103] Package structure of composite power diode chip:

[0104] Figure 7(a) shows a 3D overall package structure diagram of a composite power diode chip obtained by 3D heterogeneous packaging of the Schottky power diodes prepared in the three Examples 3. Figure 7(b) shows the discrete package structure diagram of the composite power diode chip. Figures 7(c)-7(e) respectively show the front view, side view, and top view of the composite power diode chip package, and the overall package structure, from bottom to top, includes:

[0105] Bottom heat dissipation interconnection structure: an alumina ceramic plate is used as the heat dissipation substrate, on which a glass substrate is placed. The glass substrate has rectangular interlocking slots of 2.0 mm × 0.2 mm × 0.3 mm etched in it. The surface of the glass substrate is covered with a polyimide insulating adhesive layer, on which a copper wire network of microstrip line structure is placed. Five lead frames are set, and their electrical interconnection with the microstrip lines is achieved through wire bonding process.

[0106] The middle functional layer includes left and right partitions: the left region is a double-layer stacked configuration, with the lower layer being a horizontal flip-chip Schottky composite power diode unit (SC1), whose anode is bonded to the underlying microstrip line via conductive silver paste; the surface of SC1 is covered with a 1 μm thick first PI dielectric isolation layer, with a vertical interconnect cavity in the center of this layer; the upper layer is a horizontal upright Schottky composite power diode unit (SC2), whose surface is covered with a 2 μm thick second PI dielectric isolation layer; the cathode of SC2 is connected to the cathode of SC1 via conductive silver paste through the vertical interconnect cavity, and is connected to the underlying microstrip line network via surface wiring across the first PI dielectric layer; the anode of SC2 is connected to the surface wiring across the second PI dielectric isolation layer via conductive silver paste, and is connected to the corresponding lead frame via an independent microstrip line; the right region has a vertically embedded Schottky composite power diode unit SC3, which is precisely fitted into a rectangular slot in the glass substrate, and the anode and cathode of SC3 are connected to the underlying microstrip line network via conductive silver paste;

[0107] The outer encapsulation protection structure uses epoxy resin encapsulation to form a 150 μm thick coating layer. After curing, the sides of the package are mechanically polished to expose the lateral width and height of the alumina ceramic substrate, forming a lateral heat dissipation path. Five sets of lead frames extend from the top of the coating layer, with a lead protrusion height of 100 μm. The lead frames are connected as follows: lead frame 1 is connected to the SC1 anode via a microstrip line; lead frame 2 is connected to the SC2 anode via a microstrip line; lead frame 3 serves as a common cathode and is connected to the common junction of SC1 and SC2 via a microstrip line; lead frame 4 is connected to the SC3 cathode via a microstrip line; and lead frame 5 is connected to the SC3 anode via a microstrip line.

[0108] Example 5

[0109] Applications of composite power diode chips:

[0110] The main functional units of the composite power diode chip include a single-channel Schottky rectifier unit, a bipolar overvoltage protection unit, a high-voltage cascade withstand voltage unit, a two-phase common cathode rectifier topology unit, and a cascaded current-resistant extension unit.

[0111] The single-channel Schottky rectifier unit has five pins: pin 1, pin 2, pin 3, pin 4, and pin 5; the bipolar overvoltage protection unit has two pins: pin 1 and pin 2; the high-voltage cascade withstand voltage unit has two pins: pin 2 and pin 4; the two-phase common cathode rectifier unit has three pins: pin 1, pin 2, and pin 3; and the cascaded current-resistant extension unit has three pins: pin 1, pin 2, and pin 5.

[0112] The single-channel Schottky rectifier unit uses a fabricated n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure Schottky power diode. By connecting the pins (pin 1, pin 2, pin 3, pin 4, and pin 5) of the composite structure Schottky diode to an external circuit, it achieves unidirectional conduction and reverse blocking functions. It is mainly used in: rectifier units in high-frequency switching power supplies, polarity protection circuits in photovoltaic inverters, and reverse voltage protection in low-power devices.

[0113] The aforementioned bipolar overvoltage protection unit utilizes a Schottky power diode with an n-Si substrate / "(n-Si)-(ZIF-8) composite layer" / Ag layer composite structure, employing an anti-series configuration. This involves connecting the cathodes of Schottky composite unit SC1 and SC2 to form a bidirectional conduction path. One Schottky power diode constitutes one Schottky composite unit. Its main applications include voltage clamping protection in AC circuits, ESD protection modules in communication equipment, and transient voltage suppression in automotive electronic systems.

[0114] The aforementioned high-voltage cascade withstand voltage unit connects the cathode of the Schottky composite unit SC1 to the anode of the Schottky composite unit SC3 in a cascade configuration. High-voltage withstand capability is achieved through stacked reverse withstand voltage, while maintaining low forward conduction voltage drop characteristics. It is primarily used in: high-voltage DC power supply input stages, pre-charging circuits of electric vehicle charging piles, and bus voltage divider protection for industrial frequency converters.

[0115] The two-phase common-cathode rectifier unit connects the cathodes of Schottky composite units SC1 and SC2 together as a common cathode, allowing for independent output from both anodes. It is primarily used in: two-phase AC rectifier bridge common-cathode topologies, common-ground isolation in dual-channel data acquisition systems, and crosstalk protection for high-precision ADC input stages. The cascaded current-capable extension unit connects the cathodes of Schottky composite units SC1 and SC2 in parallel to the anode of Schottky composite unit SC3. It is primarily used in: pre-regulator stages of high-power AC / DC converters, PFC rectifier stages in electric vehicle OBCs, and redundant protection circuits for high-current loads in industrial applications.

[0116] The single-channel Schottky rectifier unit is divided into three groups. The first group includes a Schottky composite unit SC1, pin 1, and pin 3. Pin 1 is the anode, connected to the anode of the Schottky composite unit SC1 via a copper wire. Pin 3 is the cathode, connected to the cathode of the Schottky composite unit SC1 via conductive silver paste and printed copper wire. The second group includes a Schottky composite unit SC2, pin 2, and pin 3. Pin 2 is the anode, connected to the anode of the Schottky composite unit SC2 via conductive silver paste and printed copper wire. Pin 3 is the cathode, connected to the cathode of the Schottky composite unit SC2 via conductive silver paste and printed copper wire. The third group includes a Schottky composite unit SC3, pin 4, and pin 5. Pin 4 is the cathode, connected to the cathode of the Schottky composite unit SC3 via conductive silver paste and printed copper wire. Pin 5 is the anode, connected to the anode of the Schottky composite unit SC3 via conductive silver paste and printed copper wire.

[0117] The bipolar overvoltage protection unit does not distinguish between anode and cathode. Pin 1 is connected to the anode of Schottky composite unit SC1 through a printed copper wire, and pin 2 is connected to the anode of Schottky composite unit SC2 through conductive silver paste and a printed copper wire.

[0118] Pin 2 of the high-voltage cascade withstand voltage unit is the anode, which is connected to the anode of the Schottky composite unit SC2 through conductive silver paste and printed copper wires. Pin 4 is the cathode, which is connected to the cathode of the Schottky composite unit SC3 through conductive silver paste and printed copper wires.

[0119] Pin 3 of the two-phase common cathode rectifier unit is the cathode, which is connected to the cathodes of Schottky composite unit SC1 and Schottky composite unit SC2 through conductive silver paste and printed copper wires; pin 1 is the anode (I), which is connected to the anode of Schottky composite unit SC1 through conductive silver paste and printed copper wires; pin 2 is the anode (II), which is connected to the anode of Schottky composite unit SC2 through conductive silver paste and printed copper wires.

[0120] The cascaded current-resistant extension unit has a first pin as the anode (I), which is connected to the anode of the Schottky composite unit SC1 via conductive silver paste and printed copper wires; a second pin as the anode (II), which is connected to the anode of the Schottky composite unit SC2 via conductive silver paste and printed copper wires; and a fourth pin as the cathode, which is connected to the cathode of the Schottky composite unit SC3 via conductive silver paste and printed copper wires.

[0121] Example 6

[0122] How composite power diode chips work:

[0123] The composite power diode chip achieves multiple operating modes through multiple internally integrated Schottky composite cells (SC1, SC2, SC3) and flexible pin connections. The chip's operation depends on the external circuitry and pin configuration.

[0124] like Figure 8 As shown, select the operating mode, connect the external circuit, collect data, and generate test curves. Five operating modes can be selected through flexible configuration of the five pins: single-pin pair connection forms an independent rectifier unit, achieving unidirectional conduction and reverse blocking; pin 1-2 connection forms a bipolar overvoltage protection unit, achieving bidirectional voltage clamping; pin 2-4 cascaded forms a high-voltage withstand unit, improving withstand voltage capability through series stacking; pin 1-2-3 connection forms a two-phase common cathode rectifier unit, achieving dual-channel full-wave rectification; pin 1-2-4 parallel cascaded forms a current-bearing extension unit, possessing both high current carrying and high-voltage blocking characteristics.

[0125] Example 7

[0126] Methods for compensating for reverse leakage current and temperature of composite power diode chips:

[0127] To address the issue of reverse leakage current drift affecting device stability in composite power diode chips due to temperature variations, this technology provides a precise segmented temperature compensation method. This method divides the chip's operating temperature t (unit: °C) into three ranges: low temperature (-40~6 °C), normal temperature (6~81 °C), and high temperature (81~140 °C). Linear, single-exponential, and double-exponential compensation models are then used to compensate for the reverse leakage current It. _R Real-time correction is performed. Linear compensation model I is used in the low-temperature range. _R_corrected =I _R ×d is used for correction, where the compensation coefficient d (taken as 0.9) is determined by fitting low-temperature test data; when in the normal temperature range, a single exponential compensation model I is used. _R_corrected =I _R / exp[(E _a / k)×(1 / (t+273.15)-1 / T _ref )], where E _a The activation energy is 0.6 eV, k is the Boltzmann constant, and T is the activation energy. _ref The initial temperature is 25℃; after entering the high-temperature range, a double-exponential compensation model I is adopted. _R_corrected =I _R / {A×exp[-(E _a1 / k(t+273.15))]+B×exp[-(E _a2 / k (t+273.15))]}, where E _a1 (0.5 eV) and E _a2(0.8 eV) represent the activation energies of the two mechanisms, respectively. In practical applications, the system monitors the junction temperature in real time through an integrated temperature sensor. The built-in microprocessor automatically switches the compensation model according to a preset temperature threshold and uses calibrated parameters to adjust the original reverse leakage current I. _R Perform real-time calculations and corrections.

[0128] It should be noted that the above-described technical content of this invention is merely an explanation and clarification to enable those skilled in the art to understand the technical essence of this invention, and therefore is not intended to limit the scope of protection of this invention. The scope of protection of this invention should be determined by the claims. Those skilled in the art should understand that any modifications, equivalent substitutions, and improvements made based on the essential spirit of this invention should be within the scope of protection of this invention.

Claims

1. An n-Si / (n-Si)-(ZIF-8) / Ag composite structure, wherein the composite structure comprises, from bottom to top, an n-Si substrate layer, a (n-Si)-(ZIF-8) composite layer and an Ag layer.

2. The composite structure as described in claim 1, characterized in that, In the internal structure of the (n-Si)-(ZIF-8) composite layer, Zn atoms in ZIF-8, Si atoms in n-Si, and -OH groups on the n-Si surface together form Si-O-Zn bonds. Between the n-Si substrate and the (n-Si)-(ZIF-8) composite layer, P atoms in the n-Si substrate, -OH groups on the n-Si substrate surface, -OH groups on the n-Si surface inside the (n-Si)-(ZIF-8) composite layer, and (n-Si)-(ZIF-8) composite layer... The Zn atoms in the ZIF-8 composite layer together form PO-Zn bonds; between the Ag layer and the (n-Si)-(ZIF-8) composite layer, the Ag atoms in the Ag layer and the N atoms in the ZIF-8 composite layer together form Ag-N bonds; the thin film structure formed by the Ag layer and the thin film structure formed by the (n-Si)-(ZIF-8) composite layer are in contact through van der Waals forces; the interface between the Ag layer and the n-Si substrate layer forms a Schottky junction.

3. The composite structure as described in claim 1, characterized in that, The thickness of the n-Si substrate is 0.01~2.0 mm, preferably 0.1~1.0 mm, more preferably 0.3~0.6 mm; the thickness of the (n-Si)-(ZIF-8) composite layer is 0.1~1000 nm, preferably 1~500 nm, more preferably 10~200 nm; and the thickness of the Ag layer is 1~1000 nm, preferably 10~500 nm, more preferably 30~200 nm.

4. The method for preparing the composite structure according to any one of claims 1-3, wherein an n-Si substrate is first etched, and then an (n-Si)-(ZIF-8) composite layer is obtained by electrodeposition on the etched n-Si substrate using a ZIF-8 electroplating solution, followed by deposition of an Ag layer; the ZIF-8 electroplating solution is prepared by dissolving sodium hyaluronate powder in deionized water, then adding ethanol and mixing evenly, and then adding ZIF-8 powder to the mixed solution; the Ag layer is deposited using a vacuum evaporation thermal evaporation method.

5. A Schottky power diode based on the composite structure according to any one of claims 1-3 or based on the composite structure obtained by the preparation method according to claim 4.

6. The Schottky power diode as described in claim 5, characterized in that, Using the composite structure as a substrate, an Ag layer is deposited on the back side of the n-Si substrate to obtain an Ag layer / n-Si substrate / (n-Si)-(ZIF-8) composite layer / Ag layer.

7. A composite power diode chip, which is obtained by packaging and connecting at least three Schottky power diodes using a 3D heterogeneous packaging structure, with the Schottky power diode as the basic unit as described in claim 8.

8. The composite power diode chip as described in claim 7, characterized in that, Three Schottky power diodes are packaged using a 3D heterogeneous packaging structure, which mainly includes a bottom heat dissipation interconnect structure, an intermediate functional layer, and an outer packaging protection structure. The bottom heat dissipation interconnection structure includes an alumina ceramic heat dissipation substrate and an insulating substrate. The insulating substrate has rectangular interlocking slots etched in it. The surface of the insulating substrate is covered with a polyimide (PI) insulating adhesive layer, on which is a copper wire network with a microstrip structure. The middle functional layer consists of two regions: the left region has two Schottky power diodes and the right region has one Schottky power diode. The two diodes in the left region are arranged in a double-layer stacked configuration. The lower layer is a horizontal flip-chip Schottky power diode unit SC1, whose anode is bonded to the underlying microstrip line via conductive silver paste. The surface of SC1 is covered with a first PI dielectric isolation layer, and a vertical interconnect cavity is formed in the center of this layer. The upper layer is a horizontal upright Schottky power diode unit SC2, whose surface is covered with a second PI dielectric isolation layer. The cathode of SC2 is connected to the cathode of SC1 via conductive silver paste through the vertical interconnect cavity, and is connected to the underlying microstrip line network by wiring across the surface of the first PI dielectric layer. The anode of SC2 is connected to the corresponding lead frame via a conductive silver paste that extends across the surface of the second PI dielectric isolation layer. The right area is a vertically embedded Schottky power diode unit SC3, which is precisely fitted into a rectangular slot in the insulating substrate. The anode and cathode of SC3 are connected to the underlying microstrip network through conductive silver paste. Outer encapsulation and protection structure: epoxy resin is used for encapsulation to form a coating layer; after curing, it is polished to expose the lateral width and height of the alumina ceramic substrate, forming a lateral heat dissipation path; The underlying heat dissipation interconnection structure also includes five lead frames, which extend from the top of the cladding layer. The lead frames are connected as follows: lead frame one is connected to the SC1 anode via a microstrip line; lead frame two is connected to the SC2 anode via a microstrip line; lead frame three serves as a common cathode and is connected to the common connection node of SC1 and SC2 via a microstrip line; lead frame four is connected to the SC3 cathode via a microstrip line; and lead frame five is connected to the SC3 anode via a microstrip line.

9. The packaging method of the Schottky composite power diode chip according to claim 8, comprising: First, the alumina ceramic plate is plasma cleaned, and an insulating substrate is fixed to its surface. A fitting groove is formed within the insulating substrate using deep reactive ion etching (RIE). After the groove is formed, soluble polyvinyl alcohol (PVA) is used as a sacrificial material to fill it. Chemical mechanical polishing (CMP) is then performed to make its surface highly flush with the insulating substrate, creating a temporary flat working surface. Next, a polyimide (PI) insulating adhesive layer is spin-coated. After the PI layer is coated, the required rectangular contact windows are precisely etched onto the PI layer using photolithography and reactive ion etching (RIE). Finally, the PVA sacrificial layer is dissolved and removed using a warm water bath. Simultaneously, the forming of windows on the PI adhesive layer and the clearing of slots within the insulating substrate were achieved. Subsequently, a copper conductor network with a microstrip structure was constructed on the surface of the PI layer using a vacuum thermal evaporation process combined with mask patterning. Then, gold wire ball bonding was used to bond and interconnect the copper conductors with five lead frames. The specific connection frames are as follows: lead frame one is connected to the SC1 anode port via a microstrip line; lead frame two is connected to the SC2 anode port via a microstrip line; lead frame three serves as a common cathode and is connected to the common connection node of SC1 and SC2 via a microstrip line; lead frame four is connected to the SC3 cathode port via a microstrip line; and lead frame five is connected to the SC3 anode port via a microstrip line. Next, the left-side double-layer stack assembly is performed: First, the first PI dielectric isolation layer is spin-coated on the cathode surfaces of SC1 and SC2 respectively, and windows are opened by photolithography to form a cavity structure for vertical interconnection; then, highly conductive silver paste is filled into the cavity, and the silver paste is led from the cavity to the edge of the PI layer by vacuum thermal evaporation to build the pre-interconnection end; after completing the above pretreatment, SC1 and SC2 are joined together with their cathode surfaces, and fixed by the PI layer and silver paste structure to form a preliminary "SC1-SC2" stack; Subsequently, the stack was rotated 90° so that its side faces upward as a new process plane. PI dielectric layers were then spin-coated and cured sequentially. Next, copper conductors for the microstrip line structure were constructed on this side using magnetron sputtering. Afterward, the stack with completed vertical interconnections on the sides was treated as a single unit, with the anode of SC1 facing downward, and bonded to the pre-defined copper conductor nodes on the bottom layer using conductive silver paste. Finally, a second PI dielectric isolation layer was spin-coated onto the upper surface of SC2. After photolithography to create windows, horizontal wiring from the anode of SC2 to the vertical microstrip line structure on the side was completed using magnetron sputtering, thus forming a complete vertical structure connection. In the right region, SC3 was embedded in a slot and connected to the underlying microstrip line structure network using conductive silver paste. Finally, epoxy resin was infused using a pressure injection process and cured to form a coating layer. After curing, the surface was polished to expose the lateral width and height of the alumina ceramic substrate, forming a lateral heat dissipation path.

10. The application of the Schottky composite power diode chip of claim 7 or 8, or the Schottky composite power diode chip obtained by the method of claim 9, characterized in that, The Schottky composite power diode chip includes at least one functional unit as described below: a single-channel Schottky rectifier unit, a bipolar overvoltage protection unit, a high-voltage cascaded withstand voltage unit, a two-phase common cathode rectifier topology unit, and a cascaded current-resistant extension unit, wherein... The single-channel Schottky rectifier unit can be applied to at least one of the following scenarios: rectifier unit in high-frequency switching power supply, polarity protection circuit of photovoltaic inverter, and reverse voltage protection of low-power device; The bipolar overvoltage protection unit can be applied to at least one of the following scenarios: voltage clamping protection in AC circuits, ESD protection modules for communication equipment, and transient voltage suppression in vehicle electronic systems; The high-voltage cascade withstand voltage unit can be applied to at least one of the following scenarios: high-voltage DC power supply input stage, pre-charging circuit of electric vehicle charging pile, and bus voltage divider protection of industrial frequency converter; The two-phase common cathode rectifier topology unit can be applied to at least one of the following scenarios: common cathode topology of two-phase AC rectifier bridge, common ground isolation of multi-channel data acquisition system, and anti-crosstalk protection circuit of high-precision ADC input stage; The cascaded current-resistant extension unit can be applied to at least one of the following scenarios: pre-regulator stage of high-power AC / DC converter, PFC rectifier stage of electric vehicle OBC, and redundant protection circuit for industrial high-current loads.

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