Double-sided heat dissipation half-bridge power module based on GaN device and preparation method
By using a double-sided ceramic substrate and horizontally integrated capacitors, the heat dissipation and mechanical stress problems of GaN bare-die devices are solved, achieving efficient heat dissipation and stable operation, and adapting to complex mechanical environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-02-03
- Publication Date
- 2026-05-05
AI Technical Summary
GaN bare die devices face challenges in heat dissipation during packaging, mechanical stress caused by mismatched coefficients of thermal expansion, and parasitic parameters that affect device reliability, making them difficult to adapt to complex mechanical environments.
The design employs a double-sided ceramic substrate, which combines upper and lower ceramic substrates with a metal layer to achieve heat dissipation on both sides. The input capacitor is horizontally integrated into the lower ceramic substrate, reducing parasitic parameters and optimizing the matching of thermal expansion coefficients.
It improves heat dissipation efficiency, reduces parasitic parameters, enhances mechanical strength, and enables stable operation in harsh environments.
Smart Images
Figure CN121985818A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronic power module technology, and in particular to a double-sided heat-dissipating half-bridge power module based on GaN devices and its fabrication method. Background Technology
[0002] Third-generation GaN semiconductor devices are widely used in power converters due to their faster switching frequencies, lower on-resistance, and higher breakdown voltage. However, GaN dies are inherently fragile and require modular design, including packaging, interconnects, and heat dissipation, to meet the complex demands of industrial, automotive, and energy applications. GaN dies face several challenges, such as damage from mechanical stresses like vibration and impact; the generation of significant heat during operation, especially given the extremely high power density of GaN dies, which, when directly exposed, relies solely on air cooling, resulting in high thermal resistance that hinders output power, affects output current, and can even lead to overheating and burnout; and the extremely high switching speed of GaN devices makes them highly sensitive to parasitic parameters, which can easily cause voltage overshoot and damage. Therefore, GaN dies are often packaged into high-performance modules for use.
[0003] In traditional packaging, the substrates mainly use FR-4 PCB substrates and ceramic substrates. Ceramic substrates have good heat dissipation, but they are not flexible or compact in layout, and the parasitic parameters of interconnection via surface-mount capacitors are large. To reduce parasitic parameters, researchers have embedded GaN bare-die devices into FR-4 PCBs. However, GaN devices generate a lot of heat during operation, and the difference in thermal expansion coefficients between the GaN device material and the substrate can cause deformation due to thermomechanical stress, making heat dissipation difficult. Some studies have also used flexible PCBs as substrates to reduce parasitic parameters and improve heat dissipation performance, but flexible PCBs are very soft and not suitable for applications in harsh environments such as vibration and shock. Summary of the Invention
[0004] The purpose of this invention is to provide a double-sided heat-dissipating half-bridge power module based on GaN devices and its fabrication method, based on the synergistic optimization of parasitic parameters, heat dissipation performance, and mechanical strength.
[0005] To achieve the above objectives, the present invention provides a double-sided heat-dissipating half-bridge power module based on GaN devices, including an upper ceramic substrate, a lower ceramic substrate corresponding to the upper ceramic substrate, an upper GaN device and a lower GaN device located between the upper ceramic substrate and the lower ceramic substrate, and an input capacitor integrated in the lower ceramic substrate, wherein the upper GaN device, the lower GaN device and the input capacitor form a power circuit; The lower ceramic substrate comprises, from top to bottom, a first metal layer, a first ceramic layer, a second metal layer, a second ceramic layer, a third metal layer, a third ceramic layer, and a fourth metal layer. The first metal layer and the second metal layer, as well as the second metal layer and the third metal layer, are connected by metal blind vias. The upper GaN device and the lower GaN device are disposed above the first metal layer.
[0006] Preferably, the upper-side GaN device includes a first substrate, a first source, and a first drain. The first substrate is located on the side of the upper-side GaN device close to the upper ceramic substrate. Multiple first sources and first drains are provided and arranged in a comb-like pattern. The first source and first drain are located on the side of the upper-side GaN device close to the first metal layer. The first substrate and the first source are connected by a metal pillar. The lower GaN device includes a second substrate, a second source, and a second drain. The second substrate is located on the side of the lower GaN device closer to the upper ceramic substrate. Multiple second sources and second drains are provided, the same number as the first source and the second drain, and arranged in a comb-like pattern. The second source and the second drain are located on the side of the lower GaN device closer to the first metal layer. The second substrate and the second source are connected by metal pillars.
[0007] Preferably, the first source and the second drain are connected on the first metal layer by metal plating; A cavity is provided within the third ceramic layer. The cavity is located directly below the metal layer connecting the first source and the second drain. The input capacitor is disposed inside the cavity and connected to the third metal layer.
[0008] Preferably, the metal blind via between the first metal layer and the second metal layer is connected to the metal blind via between the second metal layer and the third metal layer, the first drain and the second source are connected to the third metal layer through the connected metal blind via, and the second metal layer serves as a heat dissipation layer.
[0009] Preferably, the first drain, the first source, the second drain, the second source, and the input capacitor form a sub-loop. Current flows sequentially through the first drain, the first source, the second drain, the second source, and the input capacitor to the first drain, forming a closed loop. There are two input capacitors, and the two input capacitors are connected in series.
[0010] Preferably, the upper ceramic substrate is a DBC ceramic substrate or a DPC ceramic substrate.
[0011] Preferably, the metal layer of the upper ceramic substrate, the metal layer of the lower ceramic substrate, the metal pillars, and the metal blind holes are one or more of copper, nickel, gold, silver, chromium, and titanium, and the ceramic layer materials in the upper ceramic substrate and the lower ceramic substrate are one or more of alumina, aluminum nitride, silicon nitride, silicon carbide, and zirconium oxide.
[0012] This invention also provides a method for fabricating a double-sided heat-dissipating half-bridge power module based on GaN devices, comprising the following steps: S1. Fabricate a lower ceramic substrate with an integrated input capacitor; S2. Prepare the ceramic substrate; S3. Package the GaN device, the upper ceramic substrate, and the lower ceramic substrate to achieve electrical conduction.
[0013] Preferably, step S1 specifically includes: S101. A cavity is fabricated on a green ceramic tape. The size of the cavity is adapted to the external size of the input capacitor to be integrated. A conductive metal material is coated on the bottom and periphery of the cavity to form interconnect pads. S102. A high-precision chip mounter is used to integrate the packaged capacitor into the cavity, aligning the component pins with the interconnect pads. Conductive adhesive is applied to the contact interface between the pins and the pads to achieve temporary fixation and initial electrical interconnection of the component. S103. The green ceramic strip with integrated input capacitor is stacked with other green ceramic strips in the design order. The stacked blank is placed in an atmosphere sintering furnace and co-fired at low temperature to obtain the third ceramic layer of integrated encapsulated capacitor. S104. Plate or coat metal onto the surface of the third ceramic layer to form a third metal layer and a fourth metal layer; S105. Pattern the metal layers on both sides of the third ceramic layer, wherein the third metal layer has reserved positioning pads for connection with metal blind holes and sites for interconnection with the second ceramic layer, and the fourth metal layer is etched with grounding pads, heat dissipation areas and external circuit interconnection interfaces. S106. Take the green ceramic strip of the second ceramic layer with the corresponding thickness, process through holes at the preset metal blind hole through position, stack the green ceramic strip on the surface of the third metal layer, align and compact it after positioning reference, and put it into the atmosphere sintering furnace for secondary low temperature co-firing so that the second ceramic layer and the third metal layer are tightly bonded, and at the same time solidify the conductive layer on the inner wall of the through hole. S107. Plate or cover the second ceramic layer with metal to form a second metal layer; etch out the metal blind hole connection pads and the interconnection area with the first ceramic layer by photolithography etching process. S108. Metallize and fill the through holes reserved in the second ceramic layer and the third ceramic layer so that the filling copper forms a strong electrical connection with the connection pads of the second metal layer and the third metal layer, forming a metal blind hole that penetrates the second ceramic layer and the third ceramic layer. S109. Take the green ceramic tape of the first ceramic layer, reserve a clearance hole corresponding to the top position of the metal blind hole, and coat the lower surface of the green ceramic tape with insulating adhesive slurry. Stack the green ceramic tape on the surface of the second metal layer and the metal blind hole, compact it, and then perform a third low-temperature co-firing to make the first ceramic layer, the second ceramic layer, and the second metal layer fit tightly together, while ensuring that the top of the metal blind hole is exposed on the upper surface of the first ceramic layer. S100. Metal is deposited or covered on the upper surface of the first ceramic layer and the top of the metal blind hole to form a first metal layer; the GaN device mounting area, electrode interconnection lines and connection sites with the metal blind hole are etched by photolithography. S111. The prepared ceramic substrate is polished and cleaned to remove residual slurry, metal debris and oil stains from the surface; ultrasonic testing technology is used to check for internal cracks in the ceramic layer, metal layer peeling and metal blind hole filling defects; insulation resistance tester is used to test the insulation performance of each layer; thermal conductivity tester is used to verify the thermal conductivity of the substrate.
[0014] Therefore, the present invention employs the above-described double-sided heat-dissipating half-bridge power module based on GaN devices and its fabrication method, which has the following beneficial effects: (1) It is provided with an upper ceramic substrate and a lower ceramic substrate, and heat dissipation is carried out from both the device substrate and the source and drain electrodes through the double-sided ceramic substrate, which improves the heat dissipation effect; (2) By horizontally integrating the input capacitor in the lower ceramic substrate, the input capacitor is directly connected to the GaN device through the metal layer, thereby reducing the interconnect parasitic parameters of external / surface integrated capacitors in the prior art; (3) The coefficient of thermal expansion of the ceramic substrate is very close to that of GaN devices and input capacitors, which can alleviate the large thermomechanical stress caused by the difference in thermal expansion and withstand harsh working conditions such as vibration and impact.
[0015] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0016] Figure 1 This is a side sectional view of the half-bridge power module of Embodiment 1 of the present invention; Figure 2 This is a top view of the half-bridge power module according to Embodiment 1 of the present invention; Figure 3 This is a thermal simulation analysis diagram of the half-bridge power module in Embodiment 2 of the present invention; Figure 4 This is a thermal simulation analysis diagram of the GaN device power module integrated in an FR-4 PCB according to Embodiment 2 of the present invention; Figure Labels 1. Upper ceramic substrate; 2. Lower ceramic substrate; 21. First metal layer; 22. First ceramic layer; 23. Second metal layer; 24. Second ceramic layer; 25. Third metal layer; 26. Third ceramic layer; 27. Fourth metal layer; 3. Upper GaN device; 31. First substrate; 32. First source; 33. First drain; 4. Lower GaN device; 41. Second substrate; 42. Second source; 43. Second drain; 5. Metal pillar; 6. Metal blind via; 7. Input capacitor. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicating orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the product of the invention is in use. They are only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.
[0018] Example 1 like Figures 1-2 As shown, this invention provides a double-sided heat-dissipating half-bridge power module based on GaN devices. Two ceramic substrates serve as the substrates for the GaN devices, dissipating heat from both the device substrate and the source / drain electrodes. The module includes an upper ceramic substrate 1, a lower ceramic substrate 2 corresponding to the upper ceramic substrate 1, an upper GaN device 3 and a lower GaN device 4 located between the upper and lower ceramic substrates 1 and 2, and an input capacitor 7 integrated within the lower ceramic substrate 2. The upper GaN device 3, the lower GaN device 4, and the input capacitor 7 form a power circuit. The input capacitor 7 is a surface-mount capacitor with a capacitance value more than 100 times the Coss junction capacitance of the GaN device. The package size depends on the bus voltage of the applied converter and the selected capacitance value.
[0019] The lower ceramic substrate 2 includes, from top to bottom, a first metal layer 21, a first ceramic layer 22, a second metal layer 23, a second ceramic layer 24, a third metal layer 25, a third ceramic layer 26, and a fourth metal layer 27. The first metal layer 21 and the second metal layer 23, and the second metal layer 24 and the third metal layer 25 are connected by a metal blind via 6. The upper GaN device 3 and the lower GaN device 4 are disposed above the first metal layer 21.
[0020] The metal layers in ceramic substrates can be made extremely thin, with spacing down to the micrometer level, and the ceramic substrate has a very high dielectric constant. Even with micrometer-level spacing, it can still withstand high-voltage applications. In addition, the coefficient of thermal expansion of the ceramic substrate is very close to that of GaN devices and input capacitors, which can alleviate the large thermomechanical stress caused by differences in thermal expansion and allow it to withstand harsh conditions such as vibration and impact.
[0021] The upper-side GaN device 3 includes a first substrate 31, a first source 32, and a first drain 33. The first substrate 31 is located on the side of the upper-side GaN device 3 near the upper ceramic substrate 1. Multiple first sources 32 and first drains 33 are provided and arranged in a comb-like pattern on the pads of the GaN device. The first sources 32 and first drains 33 are located on the side of the upper-side GaN device 3 near the first metal layer 21. The first substrate 31 and the first source 32 are connected by metal pillars.
[0022] The lower GaN device 3 includes a second substrate 41, a second source 42, and a second drain 43. The second substrate 41 is located on the side of the lower GaN device 4 near the upper ceramic substrate 1. Multiple second sources 42 and second drains 43 are provided, the same number as the first source 32 and second source 42, and are arranged in a comb-like pattern on the pads of the GaN device. The second source 42 and second drain 43 are located on the side of the lower GaN device 4 near the first metal layer 21. The second substrate 41 and the second source 42 are connected by metal pillars.
[0023] A cavity is provided within the third ceramic layer 26, located directly below the metal layer connecting the first source 32 and the second drain 43. The input capacitor 7 is disposed inside the cavity and connected to the third metal layer 25. Because the input capacitor 7 is located inside the cavity, and directly below the metal layer connecting the first source 32 and the second drain 43, the current flow direction of the input capacitor 7 is opposite to the current flow direction of the first source 32-second drain 43, which can achieve magnetic field self-cancellation.
[0024] The first source electrode 32 and the second drain electrode 43 are connected on the first metal layer 21 by metal deposition. In the metal deposition operation, copper (Cu), nickel (Ni), gold (Au), silver (Ag), chromium (Cr), titanium (Ti), and alloys thereof, or free combinations thereof, can be used.
[0025] The metal blind via 6 between the first metal layer 21 and the second metal layer 23 is connected to the metal blind via 6 between the second metal layer 23 and the third metal layer 25. The first drain 33 and the second source 42 are connected to the third metal layer 25 through the connected metal blind via 6. The metal blind via 6 is processed by laser drilling and electroplating filling, taking into account the requirements of small diameter and good conductivity.
[0026] The first drain 33, the first source 32, the second drain 43, the second source 42, and the input capacitor 7 form a sub-loop. Two input capacitors 7 are connected in series in each sub-loop. The redundancy design improves the reliability of the capacitors. Then, each sub-loop is connected in parallel. In the sub-loop, the current flows sequentially through the first drain 33, the first source 32, the second drain 43, the second source 42, and the input capacitor 7 to the first drain 33, forming a closed loop.
[0027] In this example, the first source 32 and the second drain 43 are directly connected on the first metal layer 21 of the lower ceramic substrate 2 by metal deposition. The first drain 33 and the second source 42 are connected to the third metal layer 25 through a metal blind via 6. Therefore, the second metal layer 23 does not participate in the circuit flow. The second metal layer 23 acts as a heat diffusion layer, enhancing the heat dissipation of the device, alleviating the thermal coupling between GaN and the capacitor, and further improving the heat dissipation efficiency of the lower ceramic substrate 2.
[0028] The upper ceramic substrate 1 is either a DBC ceramic substrate (direct copper-clad ceramic substrate) or a DPC ceramic substrate (direct copper-plated ceramic substrate).
[0029] The metal layer of the upper ceramic substrate 1, the metal layer of the lower ceramic substrate 2, the metal pillars 5, and the metal blind holes 6 can be metals and alloys with electrical and thermal conductivity, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), chromium (Cr), titanium (Ti), and their free combinations thereof. The ceramic layer in the ceramic substrate can be one or more of alumina, aluminum nitride, silicon nitride, silicon carbide, zirconium oxide, etc.
[0030] The power module in this invention is applicable to all lateral bare-core devices such as GaN, SiC, GaO, and Si, and can be used on multilayer ceramic substrates without affecting the layout of the metal layer below the power circuit. Therefore, it is applicable to all topologies based on half-bridge circuits, such as Buck, Boost, LLC converters, etc.
[0031] Example 2 This invention presents a preliminary layout design and simulation analysis of a 400V high-voltage power module. The module uses the GS66508D as the switching device, and its thermal performance is simulated using COMSOL software. Figure 3 This is a thermal simulation analysis diagram of the power module proposed in this invention. Figure 4 The figure shows the thermal simulation analysis of the GaN device power module integrated in the FR-4 PCB. As can be seen from the figure, when the GaN device is integrated into the FR-4 PCB, the temperatures of the two devices are 62℃ and 68℃, respectively. In the present invention, the temperatures of the two devices are 35.6℃ and 35.8℃, respectively. Compared with the embedded GaN device, the temperature of the two devices in the present invention is reduced by 26.4℃ and 32.2℃, respectively, which shows that the power module of the present invention has good heat dissipation performance.
[0032] Example 3 This invention also provides a method for fabricating a double-sided heat-dissipating half-bridge power module based on GaN devices, the specific process of which includes: S1. Prepare a lower ceramic substrate 1 with an integrated input capacitor 7; S101. Process a cavity on a green ceramic tape. The size of the cavity is adapted to the external size of the input capacitor 7 to be integrated, and a sintering shrinkage allowance of 0.5%-2% is reserved. Coat the bottom and periphery of the cavity with a metal conductive material to form interconnect pads. S102. A high-precision chip mounter is used to integrate the packaged capacitor into the cavity, aligning the component pins with the interconnect pads, with a mounting accuracy of ≤±5μm; conductive adhesive is applied to the contact interface between the pins and the pads to achieve temporary fixation and initial electrical interconnection of the component. S103. The green ceramic strip with integrated input capacitor 7 is stacked with other green ceramic strips in the design order; the stacked blank is placed in an atmosphere sintering furnace and co-fired at low temperature to obtain the third ceramic layer 26 with integrated encapsulated capacitor. S104. Using DPC or DBC technology, metal is deposited or coated on the surface of the third ceramic layer 26 to form the third metal layer 25 and the fourth metal layer 27. S105. The metal layers on both sides of the third ceramic layer 26 are patterned using photolithography and etching processes. The third metal layer 25 needs to reserve positioning pads for connection with the metal blind hole 6 and sites for interconnection with the second ceramic layer 24. The fourth metal layer 27 needs to be etched with grounding pads, heat dissipation areas and external circuit interconnection interfaces. S106. Take a green ceramic strip of the second ceramic layer 24 of the corresponding thickness, process a through hole at the preset metal blind hole 6 through position, stack the green ceramic strip on the surface of the third metal layer 25, align and compact it after positioning reference, and put it into the atmosphere sintering furnace for a second low temperature co-firing, so that the second ceramic layer 24 and the third metal layer 25 are tightly bonded, and at the same time the conductive layer on the inner wall of the through hole is solidified, laying the foundation for the interconnection of the metal blind hole 6. S107. Using the same DPC or DBC technology as S104, metal is deposited or covered on the upper surface of the second ceramic layer 24 to form a second metal layer 23; metal blind holes 6 are etched through photolithography to connect the pads and the interconnection area with the first ceramic layer 22. S108. The through holes reserved in the second ceramic layer 24 and the third ceramic layer 26 are metallized and filled by electroplating copper, so that the filling copper forms a strong electrical connection with the connection pads of the second metal layer 23 and the third metal layer 25, forming a metal blind hole 6 that penetrates the second ceramic layer 24 and the third ceramic layer 26. S109. Take the green ceramic tape of the first ceramic layer 22, reserve a clearance hole corresponding to the top position of the metal blind hole 6, and coat the lower surface of the green ceramic tape with insulating adhesive slurry. Stack the green ceramic tape on the surface of the second metal layer 23 and the metal blind hole 6, compact it, and then perform a third low-temperature co-firing to make the first ceramic layer 22, the second ceramic layer 24, and the second metal layer 23 fit tightly together, while ensuring that the top of the metal blind hole 6 is exposed on the upper surface of the first ceramic layer 22, and the exposed height matches the designed thickness of the first metal layer 21. S100. Using DPC or DBC technology, metal is deposited or covered on the upper surface of the first ceramic layer 22 and the top of the metal blind hole 6 to form the first metal layer 21. The GaN device mounting area, electrode interconnection lines and connection points with the metal blind hole 6 are etched by photolithography. The device mounting area needs to be roughened to improve the thermal conductivity and adhesion during device mounting. S111. The prepared lower ceramic substrate 2 is polished and cleaned to remove residual slurry, metal debris and oil stains from the surface; ultrasonic testing technology is used to check for internal cracks in the ceramic layer, metal layer peeling and metal blind hole 6 filling defects; insulation resistance tester is used to test the insulation performance of each layer; thermal conductivity tester is used to verify the thermal conductivity of the substrate.
[0033] S2. Prepare the upper ceramic substrate 2, process the green ceramic tape, and use the same DPC or DBC technology as S104 to plate or coat metal on both sides of the green tape to obtain the upper ceramic substrate. Use photolithography etching process to prepare the top layer fine circuit on the surface of the upper ceramic substrate 2.
[0034] S3. Package the GaN device, the upper ceramic substrate, and the lower ceramic substrate to achieve electrical conduction.
[0035] Therefore, the present invention adopts the above-mentioned double-sided heat-dissipating half-bridge power module based on GaN device and its fabrication method, and performs synergistic optimization based on parasitic parameters, heat dissipation performance and mechanical strength.
[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.
Claims
1. A double-sided heat-dissipating half-bridge power module based on GaN devices, characterized in that: The device includes an upper ceramic substrate, a lower ceramic substrate corresponding to the upper ceramic substrate, an upper GaN device and a lower GaN device located between the upper ceramic substrate and the lower ceramic substrate, and an input capacitor integrated in the lower ceramic substrate. The upper GaN device, the lower GaN device and the input capacitor form a power circuit. The lower ceramic substrate comprises, from top to bottom, a first metal layer, a first ceramic layer, a second metal layer, a second ceramic layer, a third metal layer, a third ceramic layer, and a fourth metal layer. The first metal layer and the second metal layer, as well as the second metal layer and the third metal layer, are connected by metal blind vias. The upper GaN device and the lower GaN device are disposed above the first metal layer.
2. The double-sided heat-dissipating half-bridge power module based on GaN devices according to claim 1, characterized in that: The upper-side GaN device includes a first substrate, a first source, and a first drain. The first substrate is located on the side of the upper-side GaN device close to the upper ceramic substrate. Multiple first sources and first drains are provided and arranged in a comb-like pattern. The first source and first drain are located on the side of the upper-side GaN device close to the first metal layer. The first substrate and the first source are connected by a metal pillar. The lower GaN device includes a second substrate, a second source, and a second drain. The second substrate is located on the side of the lower GaN device closer to the upper ceramic substrate. Multiple second sources and second drains are provided, the same number as the first source and the second drain, and arranged in a comb-like pattern. The second source and the second drain are located on the side of the lower GaN device closer to the first metal layer. The second substrate and the second source are connected by metal pillars.
3. The double-sided heat-dissipating half-bridge power module based on GaN devices according to claim 2, characterized in that: The first source and the second drain are connected on the first metal layer by metal plating. A cavity is provided within the third ceramic layer. The cavity is located directly below the metal layer connecting the first source and the second drain. The input capacitor is disposed inside the cavity and connected to the third metal layer.
4. The double-sided heat-dissipating half-bridge power module based on GaN devices according to claim 3, characterized in that: The metal blind via between the first metal layer and the second metal layer is connected to the metal blind via between the second metal layer and the third metal layer. The first drain and the second source are connected to the third metal layer through the connected metal blind via. The second metal layer serves as a heat dissipation layer.
5. A double-sided heat-dissipating half-bridge power module based on GaN devices according to claim 4, characterized in that: The first drain, the first source, the second drain, the second source, and the input capacitor form a sub-loop. Current flows sequentially through the first drain, the first source, the second drain, the second source, and the input capacitor to the first drain, forming a closed loop. There are two input capacitors, and the two input capacitors are connected in series.
6. A double-sided heat-dissipating half-bridge power module based on GaN devices according to claim 2, characterized in that: The upper ceramic substrate is a DBC ceramic substrate or a DPC ceramic substrate.
7. A double-sided heat-dissipating half-bridge power module based on GaN devices according to claim 6, characterized in that: The metal layer of the upper ceramic substrate, the metal layer of the lower ceramic substrate, the metal pillars and the metal blind holes are one or more of copper, nickel, gold, silver, chromium and titanium, and the ceramic layer materials in the upper ceramic substrate and the lower ceramic substrate are one or more of alumina, aluminum nitride, silicon nitride, silicon carbide and zirconium oxide.
8. A method for fabricating a GaN-based double-sided heat-dissipating half-bridge power module, used to fabricate the GaN-based double-sided heat-dissipating half-bridge power module according to any one of claims 1-7, characterized in that, Including the following steps: S1. Fabricate a lower ceramic substrate with an integrated input capacitor; S2. Prepare the ceramic substrate; S3. Package the GaN device, the upper ceramic substrate, and the lower ceramic substrate to achieve electrical conduction.
9. The method for fabricating a double-sided heat-dissipating half-bridge power module based on GaN devices according to claim 8, characterized in that, Step S1 specifically includes: S101. A cavity is fabricated on a green ceramic tape. The size of the cavity is adapted to the external size of the input capacitor to be integrated. A conductive metal material is coated on the bottom and periphery of the cavity to form interconnect pads. S102. A high-precision chip mounter is used to integrate the packaged capacitor into the cavity, aligning the component pins with the interconnect pads. Conductive adhesive is applied to the contact interface between the pins and the pads to achieve temporary fixation and initial electrical interconnection of the component. S103. The green ceramic strip with integrated input capacitor is stacked with other green ceramic strips in the design order. The stacked blank is placed in an atmosphere sintering furnace and co-fired at low temperature to obtain the third ceramic layer of integrated encapsulated capacitor. S104. Plate or coat metal onto the surface of the third ceramic layer to form a third metal layer and a fourth metal layer; S105. Pattern the metal layers on both sides of the third ceramic layer, wherein the third metal layer has reserved positioning pads for connection with metal blind holes and sites for interconnection with the second ceramic layer, and the fourth metal layer is etched with grounding pads, heat dissipation areas and external circuit interconnection interfaces. S106. Take the green ceramic strip of the second ceramic layer with the corresponding thickness, process through holes at the preset metal blind hole through position, stack the green ceramic strip on the surface of the third metal layer, align and compact it after positioning reference, and put it into the atmosphere sintering furnace for secondary low temperature co-firing so that the second ceramic layer and the third metal layer are tightly bonded, and at the same time solidify the conductive layer on the inner wall of the through hole. S107. Plate or cover the second ceramic layer with metal to form a second metal layer; etch out the metal blind hole connection pads and the interconnection area with the first ceramic layer by photolithography etching process. S108. Metallize and fill the through holes reserved in the second ceramic layer and the third ceramic layer so that the filling copper forms a strong electrical connection with the connection pads of the second metal layer and the third metal layer, forming a metal blind hole that penetrates the second ceramic layer and the third ceramic layer. S109. Take the green ceramic tape of the first ceramic layer, reserve a clearance hole corresponding to the top position of the metal blind hole, and coat the lower surface of the green ceramic tape with insulating adhesive slurry. Stack the green ceramic tape on the surface of the second metal layer and the metal blind hole, compact it, and then perform a third low-temperature co-firing to make the first ceramic layer, the second ceramic layer, and the second metal layer fit tightly together, while ensuring that the top of the metal blind hole is exposed on the upper surface of the first ceramic layer. S100. Metal is deposited or covered on the upper surface of the first ceramic layer and the top of the metal blind hole to form a first metal layer; the GaN device mounting area, electrode interconnection lines and connection sites with the metal blind hole are etched by photolithography. S111. The prepared ceramic substrate is polished and cleaned to remove residual slurry, metal debris and oil stains from the surface; ultrasonic testing technology is used to check for internal cracks in the ceramic layer, metal layer peeling and metal blind hole filling defects; insulation resistance tester is used to test the insulation performance of each layer; thermal conductivity tester is used to verify the thermal conductivity of the substrate.