Test method for on-line calibration of WAT automatic test capacitance parameters

Abstract

The invention discloses a test method for on-line calibration of WAT automatic test capacitance parameters, which comprises the following steps of: obtaining machine parasitic parameters: providing a calibration capacitor device of which the type is the same as that of a to-be-tested capacitor device to be calibrated; the calibration capacitor device has first real capacitance and resistance which are acquired in advance; and performing a WAT automatic capacitance test on the calibration capacitor device to obtain a first test capacitance and conductance. And the parasitic parameters of the machine are obtained through conversion of the first test capacitance and conductance and the first real capacitance and resistance. And after the parasitic parameters of the machine are obtained, performing a WAT automatic capacitance test on the to-be-tested capacitor device to be calibrated so as to obtain a second test capacitance and conductance. And second real capacitance and resistance of the to-be-tested capacitor device to be calibrated are obtained through conversion of the second test capacitance and conductance and machine parasitic parameters. According to the invention, the parasitic parameters of the machine can be tested on line, so that the to-be-tested capacitor device needing to be calibrated can be calibrated in time.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit manufacturing method, and more particularly to a test method for online calibration of WAT automatic test capacitor parameters. Background Technology

[0002] An inductance-capacitance-resistance (LCR) tester is an instrument used to measure the electrical parameters of semiconductor inductors, resistors, and capacitors. In wafer-level acceptance testing (WAT) for mass production, the most widespread application of an LCR tester is measuring capacitance parameters. Common capacitance values ​​include: oxide layer capacitance (Cox), diode capacitance (Cj), MOM (Metal Oxide Membrane), and MIM (Metal Oxide Membrane). Typically, the Hi terminal (high voltage side) connects to the bulk region, and the Lo terminal (low voltage side) connects to the gate to ensure measurement accuracy and stability. A simplified measurement circuit diagram is shown below. Figure 1 As shown, Figure 1 In this design, the semiconductor device 102 formed on the wafer is a diode capacitor. The wafer is placed on a wafer chuck 101, which is grounded. The diode capacitor has two terminals, both of which are led out through corresponding pads. An LCR meter 103 is connected to one terminal of the diode capacitor through its high terminal (Hi) and low terminal (Lo). An excitation source 104 applies a test signal, and a voltmeter 105 and an ammeter 106 measure the voltage and current, respectively. Figure 2 yes Figure 1 The equivalent circuit diagram shows that the semiconductor device 102 is equivalent to a parallel structure of a capacitor Cp and a resistor Rp. Figure 2 The voltage V1 is also displayed, which can be measured using voltmeter 105.

[0003] However, in actual batch capacitor testing, such as Figure 3 The N-type capacitor shown is used in Figure 1 However, when using the measurement method shown, test data deviations occurred, which were related to the equipment and probe card used. Correspondingly... Figure 4 The P-type capacitor, however, showed normal test data. Further explanation follows: like Figure 3 The diagram shows a schematic of the measurement structure of an existing N-type diode capacitor. Semiconductor device 102a is an N-type diode capacitor, comprising: a P-well 202 formed on a P-type semiconductor substrate (P-sub) 201; an N+ electrode region 203 and a P+ electrode region 204 formed in the surface region of the P-well 202; and the N+ electrode region 203 intersecting with the CML terminal. Figure 1The Lo terminal is connected, and the P+ electrode region 204 will connect with the CMH terminal. Figure 1 The Hi end is connected, and the P-type semiconductor substrate 201 is placed on the wafer chuck.

[0004] Depend on Figure 3 It can be concluded that in the N-type capacitor, i.e., the N-type diode capacitor structure, the P+ electrode region 204 is connected to the P-type well 202 and the P-type semiconductor substrate 201, without deep N-well (DNW) isolation in between. The signal can directly reach the bottom Chuck through this loop and flow out through the Chuck. It can also be understood that due to insufficient isolation of the N-type capacitor, parasitic capacitance of the Chuck loop in the test equipment is introduced.

[0005] like Figure 4 The diagram shows a schematic of the measurement structure of a conventional P-type diode capacitor. Semiconductor device 102b is a P-type diode capacitor, comprising: a P-well 202 formed on a P-type semiconductor substrate 201; an N-well 206 formed in the P-well 202; an N+ electrode region 203 and a P+ electrode region 204 formed in the surface region of the N-well 206; and the N+ electrode region 203 interacts with the CMH terminal. Figure 1 The Hi terminal is connected, and the P+ electrode region 204 will connect with the CML terminal. Figure 1 The Lo terminals are connected, and the P-type semiconductor substrate 201 is placed on the wafer chuck. Figure 4 As shown, the P-type trap 202 and N-type trap 206 have capacitors as shown in the dashed coil 207, which serve an isolating function and do not introduce parasitic capacitance into the Chuck circuit in the test equipment.

[0006] like Figure 5 As shown, is Figure 3 The graph shows the capacitance test data of the same existing N-type diode capacitor measured on different test equipment and probes. It can be seen that when the test equipment is different, the parasitic parameters of the equipment are also different, and the final measured capacitance is also different.

[0007] Existing methods for resolving differences between machines include: Try to ensure that these capacitance parameters are measured on fixed equipment, probe cards, and other hardware, and avoid using different equipment with large differences.

[0008] Assuming stable processes, this error is manually eliminated after long-term monitoring of differences between machines. However, neither of these methods fundamentally solves the testing problem.

[0009] Alternatively, capacitance calibration can be performed. Existing capacitance calibration methods include: Standard capacitor calibration is performed during annual inspections or when the machine is damaged.

[0010] External calibration devices and equipment, which are not included with the equipment, cannot be used for online calibration at any time.

[0011] The capacitance calibration device is a standard component and does not have parasitic effects. It cannot reflect the characteristics of on-wafer parasitic capacitance parameters changing with the stage hardware. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide a test method for online calibration of WAT automatic test capacitor parameters, which can test the parasitic parameters of the machine online and thus calibrate the capacitor to be tested in a timely manner.

[0013] To solve the above-mentioned technical problems, the present invention provides a test method for online calibration of WAT automatic test capacitor parameters, comprising: Before performing WAT automatic capacitance testing on the capacitor to be calibrated, which involves introducing the parasitic parameters of the WAT automatic testing machine, the step of obtaining the parasitic parameters of the machine is performed.

[0014] The steps for obtaining the parasitic parameters of the machine include: Provide a calibration capacitor of the same type as the capacitor to be calibrated under test.

[0015] The calibration capacitor has a first real capacitance and a first real resistance obtained in advance.

[0016] The calibration capacitor is subjected to WAT automatic capacitance test using the WAT automatic testing machine to obtain the first test capacitance and the first test conductance of the calibration capacitor.

[0017] The parasitic parameters of the machine are obtained by converting the first test capacitor, the first test conductance, the first actual capacitance, and the first actual resistance.

[0018] After obtaining the parasitic parameters of the machine tool, the WAT automatic capacitance test is performed on the capacitor device to be calibrated to obtain the second test capacitance and the second test conductance of the capacitor device to be calibrated.

[0019] The second true capacitance and second true resistance of the capacitor to be calibrated are obtained by converting the second test capacitance, the second test conductance, and the parasitic parameters of the machine tool.

[0020] A further improvement is that the calibration capacitor is fabricated on a corresponding calibration wafer.

[0021] A further improvement is that the first real capacitor and the first real resistor are obtained by testing on a semi-automatic testing machine with better machine isolation and higher accuracy than the WAT automatic testing machine.

[0022] A further improvement is that the WAT automated testing machine has a wafer stage.

[0023] After obtaining the first real capacitance and the first real resistance, the calibration wafer is placed on the wafer stage, and the first real capacitance and the first real resistance corresponding to the calibration capacitor are entered into the record file of the WAT automatic test machine.

[0024] A further improvement is that the parasitic parameters of the machine tool include the parasitic capacitance and the parasitic resistance of the machine tool.

[0025] A further improvement is that the conversion formula for the machine's parasitic parameters includes: (1); (2); Wherein, Cmeas represents the test capacitance measured using the WAT automatic testing machine; Gmeas represents the test conductance measured using the WAT automatic testing machine.

[0026] Rp represents the actual resistance; Cp represents the actual capacitance.

[0027] Rs represents the parasitic resistance of the machine tool, and Cr represents the parasitic capacitance of the machine tool.

[0028] ω represents the measured angular frequency.

[0029] When the parasitic parameters of the machine are obtained by converting the first test capacitor, the first test conductance, the first real capacitor, and the first real resistance, Cmeas is taken as the first test capacitor, Gmeas is taken as the first test conductance, Rp is taken as the first real resistance, and Cp is taken as the first real capacitor.

[0030] When calculating the second true capacitance and second true resistance of the capacitor to be calibrated using the second test capacitance, the second test conductance, and the parasitic parameters of the machine, Cmeas is the second test capacitance, Gmeas is the second test conductance, Rp is the second true resistance, and Cp is the second true capacitance.

[0031] A further improvement is that the type of capacitor device to be calibrated includes N-type diode capacitors without DNW structure; the N-type diode capacitors without DNW structure include: A P-type well formed on a P-type semiconductor substrate.

[0032] An N+ electrode region and a P+ electrode region are formed in a selected area of ​​the surface region of the P-type well, with a spacing between the N+ electrode region and the P+ electrode region.

[0033] A further improvement is that, when the wafer under test, which forms the capacitor device to be tested, begins the WAT automatic capacitance test, it also includes: Determine whether the capacitor to be tested is the capacitor to be tested that needs to be calibrated. If it is not the capacitor to be tested that needs to be calibrated, then directly perform the WAT automatic capacitance test on the capacitor to be tested. If it is determined that the capacitor device to be tested is the capacitor device to be calibrated, then the calibration wafer with the same type as the calibration capacitor device to be calibrated is selected on the wafer stage, and the parasitic parameters of the machine are obtained.

[0034] A further improvement is that the WAT automated testing machine includes: a wafer chuck, a probe card, and a test head; The wafer chuck is used to place the wafers that need to be tested; The probe card is equipped with multiple probes that are connected to the wafer. The parasitic parameters of the machine are related to the wafer chuck, the probe card, the test head, and the corresponding wiring.

[0035] This invention includes a step of obtaining the parasitic parameters of the testing equipment before performing WAT automatic capacitance testing on the capacitor to be calibrated, which introduces parasitic parameters into the WAT automatic testing equipment. This step involves performing WAT automatic capacitance testing on a calibration capacitor of the same type as the capacitor to be calibrated and then converting the results to obtain the parasitic parameters. Since the capacitor to be calibrated and the calibration capacitor are of the same type, the conversion relationships between their test values, true values, and the parasitic parameters are the same. Therefore, after performing WAT automatic capacitance testing on the capacitor to be calibrated, the true value of the capacitor to be calibrated can be calculated using the parasitic parameters. The true value eliminates the parasitic parameters from the test value, resulting in excellent calibration. Furthermore, the step of obtaining the parasitic parameters can be performed online, enabling this invention to test the parasitic parameters online and thus calibrate the capacitor to be calibrated in a timely manner.

[0036] Furthermore, the calibration capacitor of the present invention only needs to be set to the same type as the capacitor to be calibrated and tested. Therefore, the present invention can be applied to various WAT automatic testing machines and can obtain accurate test results on various WAT automatic testing machines. Attached Figure Description

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a circuit diagram for on-wafer capacitance measurement. Figure 2 yes Figure 1 The equivalent circuit diagram; Figure 3 This is a schematic diagram of the measurement structure for an existing N-type diode capacitor; Figure 4 This is a schematic diagram of the measurement structure for an existing P-type diode capacitor; Figure 5 yes Figure 3 The graph shows the capacitance test data obtained by measuring the same existing N-type diode capacitor on different test equipment and probes. Figure 6 This is a flowchart of a test method for online calibration of WAT automatic test capacitor parameters according to an embodiment of the present invention; Figure 7 This is a flowchart of the preparatory work before testing in the online calibration test method for WAT automatic test capacitor parameters according to a preferred embodiment of the present invention; Figure 8 This is a flowchart of the automatic capacitance test in the test method for online calibration of WAT automatic test capacitance parameters according to a preferred embodiment of the present invention; Figure 9 This is the equivalent circuit of the parasitic parameters of the machine in the test method for online calibration of WAT automatic test capacitor parameters in the embodiment of the present invention; Figure 10 yes Figure 9 A simplified diagram; Figure 11 yes Figure 10 A further simplified diagram; Figure 12 The graph shows the capacitance test data obtained by measuring the same capacitor to be calibrated on different machines and probes, implemented by the method of the embodiments of the present invention. Detailed Implementation

[0038] like Figure 6 The diagram shown is a flowchart of a test method for online calibration of WAT automatic test capacitor parameters according to an embodiment of the present invention; as shown... Figure 7 The above is a flowchart of the pre-test preparation work in the online calibration test method for WAT automatic test capacitor parameters according to a preferred embodiment of the present invention; as follows: Figure 8 The diagram shown is a flowchart of the automatic capacitance test in the online calibration method for WAT automatic test capacitance parameters according to a preferred embodiment of the present invention. The online calibration method for WAT automatic test capacitance parameters according to the present invention includes: Before performing WAT automatic capacitance testing on the capacitor to be calibrated that will be introduced into the WAT automatic testing machine, step S101 is performed to obtain the machine parasitic parameters.

[0039] Step S101 of obtaining the parasitic parameters of the machine includes: Step S102: Provide a calibration capacitor of the same type as the capacitor to be calibrated.

[0040] In this embodiment of the invention, the calibration capacitor is fabricated on a corresponding calibration wafer.

[0041] Step S103: The calibration capacitor has a first real capacitance and a first real resistance obtained in advance.

[0042] In this embodiment of the invention, the first true capacitance and the first true resistance are obtained using a semi-automatic testing machine with higher isolation and accuracy than the WAT automatic testing machine. Since the WAT automatic testing machine introduces parasitic capacitance parameters, it cannot measure the true values. Therefore, a machine with higher accuracy and better isolation, such as the semi-automatic machine B1500+Formfactor CM300F, can measure accurate values. In other embodiments, other testing machines that do not generate parasitic parameters can also be used to test and obtain the first true capacitance and the first true resistance.

[0043] In this embodiment of the invention, the WAT automated testing machine has a wafer table.

[0044] After obtaining the first real capacitance and the first real resistance, the calibration wafer is placed on the wafer stage, and the first real capacitance and the first real resistance corresponding to the calibration capacitor are entered into the record file of the WAT automatic test machine.

[0045] like Figure 7 As shown, in a preferred embodiment of the present invention, steps S102 and S103 can be implemented using steps S201 to S203, and both are performed as preparatory work before testing. Steps S201 to S203 are as follows: Step S201: Select a calibration wafer and determine its parasitic characteristics. Step S201 is the same as step S102.

[0046] Step 202: Collect the actual capacitance data on a higher-precision semi-automatic machine and record it in the machine file. Step S202 is the same as step S103.

[0047] Step 203: Place the calibration wafer in the machine's Wafer Table.

[0048] Step S104: Use the WAT automatic testing machine to perform the WAT automatic capacitance test on the calibration capacitor to obtain the first test capacitance and the first test conductance of the calibration capacitor.

[0049] Step S105: The parasitic parameters of the machine are obtained by converting the first test capacitor, the first test conductance, the first real capacitor, and the first real resistance.

[0050] In this embodiment of the invention, the machine parasitic parameters include machine parasitic capacitance and machine parasitic resistance.

[0051] The conversion formulas for the parasitic parameters of the machine tool include: (1); (2); Wherein, Cmeas represents the test capacitance measured using the WAT automatic testing machine; Gmeas represents the test conductance measured using the WAT automatic testing machine.

[0052] Rp represents the actual resistance; Cp represents the actual capacitance.

[0053] Rs represents the parasitic resistance of the machine tool, and Cr represents the parasitic capacitance of the machine tool.

[0054] ω represents the measured angular frequency. ω = 2πf, where f is the measured frequency.

[0055] When the parasitic parameters of the machine are obtained by converting the first test capacitor, the first test conductance, the first real capacitor, and the first real resistance, Cmeas is taken as the first test capacitor, Gmeas is taken as the first test conductance, Rp is taken as the first real resistance, and Cp is taken as the first real capacitor.

[0056] Step S106: After obtaining the parasitic parameters of the machine tool, perform the WAT automatic capacitance test on the capacitor device to be calibrated to obtain the second test capacitance and the second test conductance of the capacitor device to be calibrated.

[0057] Step S107: Calculate the second true capacitance and second true resistance of the capacitor to be calibrated using the second test capacitance, the second test conductance, and the parasitic parameters of the machine tool.

[0058] In this embodiment of the invention, when the second true capacitance and the second true resistance of the capacitor to be calibrated are obtained by converting the second test capacitance, the second test conductance and the parasitic parameters of the machine tool, Cmeas is the second test capacitance, Gmeas is the second test conductance, Rp is the second true resistance and Cp is the second true capacitance.

[0059] In this embodiment of the invention, when the wafer under test, on which the capacitor to be tested is formed, begins the WAT automatic capacitance test, the following steps are also included: Determine whether the capacitor device to be tested is the capacitor device to be calibrated. In a preferred embodiment of the present invention, this step corresponds to... Figure 10 Step S302: Determine whether capacitor calibration is required.

[0060] If the capacitor under test is not required to be calibrated, then the WAT automatic capacitance test is performed directly on the capacitor under test. In a preferred embodiment of the present invention, this step corresponds to... Figure 10 Step S303: Continue testing.

[0061] If it is determined that the capacitor device under test is the capacitor device to be calibrated, then the calibration wafer having the same type as the calibration capacitor device to be calibrated is selected on the wafer stage, and the parasitic parameters of the equipment are obtained. In a preferred embodiment of the present invention, this step corresponds to... Figure 10 Steps S304 and S305 are as follows: Step S304 involves the calibration wafer tests Cmeas and Gmeas in the wafer table. "Meas" is short for "measure." Step S304 also serves to implement step S104.

[0062] Step S305: Call the actual values ​​Cp and Rp of the calibration capacitors, and the parasitic parameters Cr and Rs of the computer station hardware. Step S305 is also used to implement step S105.

[0063] In a preferred embodiment of the present invention, such as Figure 10 As shown, the following also includes: Step S306: Test the wafer under test using Cmeas and Gmeas. Step S306 also serves to implement step S106.

[0064] Step S307: Input the machine hardware parameters Cr and Rs to calculate the true values ​​Cp and Rp of the capacitance of the wafer under test, which are then output as the calibrated data. Step S307 also implements step S107.

[0065] The parasitic parameters of the machine tool and the corresponding formulas (1) and (2) in the embodiments of the present invention are further explained below: like Figure 9 The diagram shows the equivalent circuit of the machine parasitic parameters in the test method for online calibration of WAT automatic test capacitor parameters according to an embodiment of the present invention. Figure 10 yes Figure 9 A simplified diagram; Figure 11 yes Figure 10 A further simplified diagram; in this embodiment of the invention, the type of capacitor device to be calibrated includes an N-type diode capacitor 304 without a DNW structure; the N-type diode capacitor 304 without a DNW structure includes: A P-type well 302 is formed on a P-type semiconductor substrate 301.

[0066] An N+ electrode region 306 and a P+ electrode region 307 are formed in a selected area of ​​the surface region of the P-type well 302, and there is a gap between the N+ electrode region 306 and the P+ electrode region 307.

[0067] Depend on Figure 9 As shown, multiple N-type diode capacitors without DNW structure are simultaneously formed on the P-type semiconductor substrate 301, and multiple P-type diode capacitors 305 are also integrated simultaneously. The P-type diode capacitors 305 include: An N-type well 308 is formed in the surface region of the P-type well 302.

[0068] In a selected area of ​​the surface region of the N-type well 308, the corresponding N+ electrode region 306 and P+ electrode region 307 are formed, and there is a gap between the N+ electrode region 306 and the P+ electrode region 307.

[0069] Shallow trench isolation 303 is also formed on the P-type semiconductor substrate 301.

[0070] In this embodiment of the invention, the WAT automatic testing machine includes: a wafer chuck, a probe card, and a test head (TH).

[0071] The wafer chuck is used to hold the wafers that need to be tested. For example... Figure 9 In this process, the back side of the wafer corresponding to the P-type semiconductor substrate 301 is placed on the wafer chuck 401.

[0072] The probe card is equipped with multiple probes that connect to the wafer. The test head is used to connect to each of the probes and apply various test signals. For example... Figure 9 In the process, the probes of the probe card 402 make contact with the metal pads corresponding to each electrode area on the wafer surface; the probe card 402 is then connected to the test head 403.

[0073] The parasitic parameters of the instrument are related to the wafer chuck, the probe card, the test head, and the corresponding wiring. Figure 9 As shown, the parasitic parameters related to the probe card 402 and the test head 403 include the capacitance of each test head probe, i.e., the capacitance corresponding to the TH pin, and the capacitance corresponding to the wire. The capacitances on the back of the wafer include the capacitance corresponding to the wafer chuck 41, the capacitance corresponding to the cable, and the capacitance corresponding to the input terminal of the wafer chuck 41, i.e., the TH Chuck input.

[0074] Depend on Figure 9 As shown, the N-type diode capacitor 304 without a DNW structure is mainly a parasitic capacitance formed between the N+ electrode region 306 and the P-type well 302. The P+ electrode region 307, the P-type well 302, and the P-type semiconductor substrate 301 form a leakage path connected to the wafer chuck 401. Therefore, parasitic parameters of the equipment can adversely affect the measurement structure of the N-type diode capacitor 304 without a DNW structure through this path.

[0075] Regarding the P-type diode capacitor 305, since there is a parasitic capacitance between the N-type well 308 and the P-type well 302, there is no conductive path between the N-type well 308 and the P-type semiconductor substrate 301. Therefore, the parasitic parameters of the instrument will not affect the test results of the P-type diode capacitor 305.

[0076] Will Figure 9 The parasitic parameters of each machine in the data can be simplified to obtain Figure 10 The circuit diagram shown is as follows. Figure 10 In the test, the excitation source 404 is applied through a probe, the voltage is measured by voltmeter 405, and the current is measured by ammeter 406. The device under test (DUT) 409 uses the aforementioned N-type diode capacitor 304 without DNW structure, which is affected by the parasitic parameters of the equipment. Figure 10 In the circuit, the device under test 409 includes the actual capacitance Cp and actual resistance Rp of the N-type diode capacitor 304 without DNW structure, as well as multiple parasitic resistances Rs distributed at different locations in the circuit. The capacitor Ct corresponding to label 407 is the parasitic capacitance related to the test head, and the capacitor Cr corresponding to label 408 is the parasitic capacitance related to the wafer chuck of the test instrument.

[0077] right Figure 10 Further simplification can yield Figure 11 , Figure 11 middle, Figure 10 All Rs in the data are unified into one Rs, namely Rs(total); Figure 10The capacitances Ct and Cr in the model are unified to a single Cr, i.e., Cr(total). That is, Figure 11 In this context, Cr represents the sum of parasitic capacitances related to the machine and probe card (primarily Chuck capacitance), and Rs represents the parasitic resistance related to the machine, probe card, and devices. Formulas (1) and (2) can be obtained by analyzing... Figure 11 The circuit was derived through calculation, and the derivation formulas include: I1 = I2 + I3 (3); V1=I1*Rs+I2 / Y2 (4; Y2=1 / Rp+jωCp=(1+jωCpRp) / Rp (5); I3=(I2 / Y2) / (1 / (jωCr)) (6).

[0078] I1, I2, I3 and V1 respectively in Figure 11 Y2 is the admittance of Rp and Cp in parallel, and the reciprocal of the impedance. Substituting it into the formula Zmeas=V1 / I2, we get the formulas (1) and (2) corresponding to the capacitance and conductance measurements Cmeas and Gmeas and Rs, Cr, Cp and Rp.

[0079] In this embodiment of the invention, before performing WAT automatic capacitance testing on the capacitor to be calibrated, which introduces parasitic parameters from the WAT automatic testing machine, a step of obtaining the machine's parasitic parameters is performed. This step involves performing WAT automatic capacitance testing on a calibration capacitor of the same type as the capacitor to be calibrated and then converting the results to obtain the parasitic parameters. Since the capacitor to be calibrated and the calibration capacitor are of the same type, the conversion relationships between their test values, true values, and the machine's parasitic parameters are the same. Therefore, after performing WAT automatic capacitance testing on the capacitor to be calibrated, the true value of the capacitor to be calibrated can be calculated using the machine's parasitic parameters. The true value eliminates the parasitic parameters from the test value, thus achieving good calibration. Furthermore, this embodiment of the invention can obtain the machine's parasitic parameters online. Therefore, this embodiment of the invention can test the machine's parasitic parameters online and thus enable timely calibration of the capacitor to be calibrated.

[0080] Furthermore, the calibration capacitor in this embodiment only needs to be set to the same type as the capacitor to be calibrated. Therefore, this embodiment can be applied to various WAT automatic testing machines and can obtain accurate test results on various WAT automatic testing machines.

[0081] In this embodiment of the invention, each time the parasitic capacitance item is tested, the corresponding device in the calibration wafer is first calibrated before the formal test begins, and the calibrated capacitance test value is obtained, mainly including: During the WAT automated testing process, a “capacitance test reference wafer” is introduced as a calibration wafer and placed in the probe station “wafer table” for later use.

[0082] The calibration devices, i.e., calibration capacitors, on the calibration wafer must correspond one-to-one with the capacitor under test (the capacitor to be calibrated), meaning they must possess the same characteristics as the capacitor under test. For example, a calibration wafer may have an N-type capacitor (Cj) without a DNW structure, used as a calibration device to measure the parameters of capacitors with the same N-type DNW structure.

[0083] The calibration wafer was pre-tested on a B1500+Formfactor CM300F machine to obtain the true value of the calibration capacitor.

[0084] When the WAT automatic test is started, the corresponding device in the calibration wafer is first used for calibration, that is, the values ​​of parasitic parameters Cr and Rs are calculated. Then, the values ​​of Cr and Rs are substituted into the formal test to obtain the calibrated capacitance test value.

[0085] This invention implements a testing method that, during the WAT automatic testing process, introduces a reference wafer with a similar structure and accurate capacitance data, performs online testing on the reference wafer to calculate the parasitic parameters of the testing equipment, and then calibrates the online test capacitance parameters.

[0086] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A test method for online calibration of WAT automatic test capacitor parameters, characterized in that, include: Before performing WAT automatic capacitance testing on the capacitor to be calibrated that will be introduced into the WAT automatic testing machine, the step of obtaining the machine parasitic parameters is performed. The steps for obtaining the parasitic parameters of the machine include: Provide a calibration capacitor of the same type as the capacitor to be calibrated under test; The calibration capacitor has a first real capacitance and a first real resistance obtained in advance; The calibration capacitor is subjected to WAT automatic capacitance test using the WAT automatic testing machine to obtain the first test capacitance and the first test conductance of the calibration capacitor. The parasitic parameters of the machine are obtained by converting the first test capacitor, the first test conductance, the first actual capacitor, and the first actual resistance. After obtaining the parasitic parameters of the machine tool, the WAT automatic capacitance test is performed on the capacitor to be calibrated to obtain the second test capacitance and the second test conductance of the capacitor to be calibrated. The second true capacitance and second true resistance of the capacitor to be calibrated are obtained by converting the second test capacitance, the second test conductance, and the parasitic parameters of the machine tool.

2. The test method for online calibration of WAT automatic test capacitor parameters as described in claim 1, characterized in that: The calibration capacitor is fabricated on the corresponding calibration wafer.

3. The test method for online calibration of WAT automatic test capacitor parameters as described in claim 2, characterized in that: The first real capacitor and the first real resistor were obtained by testing on a semi-automatic testing machine with better machine isolation and higher accuracy than the WAT automatic testing machine.

4. The test method for online calibration of WAT automatic test capacitor parameters as described in claim 3, characterized in that: The WAT automated testing machine has a wafer stage; After obtaining the first real capacitance and the first real resistance, the calibration wafer is placed on the wafer stage, and the first real capacitance and the first real resistance corresponding to the calibration capacitor are entered into the record file of the WAT automatic test machine.

5. The test method for online calibration of WAT automatic test capacitor parameters as described in claim 1, characterized in that: The parasitic parameters of the machine tool include the parasitic capacitance and the parasitic resistance of the machine tool.

6. The test method for online calibration of WAT automatic test capacitor parameters as described in claim 1, characterized in that: The conversion formulas for the parasitic parameters of the machine tool include: （1）； （2）； Wherein, Cmeas represents the test capacitance measured using the WAT automatic testing machine; Gmeas represents the test conductance measured using the WAT automatic testing machine. Rp represents the actual resistance; Cp represents the actual capacitance. Rs represents the parasitic resistance of the machine tool, and Cr represents the parasitic capacitance of the machine tool. ω represents the measured angular frequency; When the parasitic parameters of the machine are obtained by converting the first test capacitor, the first test conductance, the first real capacitor and the first real resistance, Cmeas is taken as the first test capacitor, Gmeas is taken as the first test conductance, Rp is taken as the first real resistance and Cp is taken as the first real capacitor. When calculating the second true capacitance and second true resistance of the capacitor to be calibrated using the second test capacitance, the second test conductance, and the parasitic parameters of the machine, Cmeas is the second test capacitance, Gmeas is the second test conductance, Rp is the second true resistance, and Cp is the second true capacitance.

7. The test method for online calibration of WAT automatic test capacitor parameters as described in claim 1, characterized in that: The types of capacitor devices to be calibrated include N-type diode capacitors without DNW structure. The N-type diode capacitor without DNW structure includes: A P-type well formed on a P-type semiconductor substrate; An N+ electrode region and a P+ electrode region are formed in a selected area of ​​the surface region of the P-type well, with a spacing between the N+ electrode region and the P+ electrode region.

8. The test method for online calibration of WAT automatic test capacitor parameters as described in claim 4, characterized in that: When the test wafer containing the capacitor to be tested begins the WAT automatic capacitance test, the process also includes: Determine whether the capacitor to be tested is the capacitor to be tested that needs to be calibrated. If it is not the capacitor to be tested that needs to be calibrated, then directly perform the WAT automatic capacitance test on the capacitor to be tested. If it is determined that the capacitor device to be tested is the capacitor device to be calibrated, then the calibration wafer with the same type as the calibration capacitor device to be calibrated is selected on the wafer stage, and the parasitic parameters of the machine are obtained.

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