Flash memory controller, control method of flash memory controller and electronic device applied by flash memory controller
By setting a hold memory area in the buffer memory in the flash memory controller, the problem of long ISP code read time in power-saving mode is solved, improving the system's response speed and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN XINXIN SEMICONDUCTOR CO LTD
- Filing Date
- 2024-11-01
- Publication Date
- 2026-05-08
AI Technical Summary
The flash memory controller needs to read the ISP code for a longer time in power-saving mode, which leads to a decrease in system performance.
Before the flash controller enters power-saving mode, a specific area in the buffer memory is set as hold memory to save program code, and after entering power-saving mode, the non-hold memory area is turned off, and the ISP code is loaded directly from the flash module.
This reduces the latency when the flash controller wakes up from power-saving mode, improving system response speed and performance.
Smart Images
Figure CN121996141A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more particularly to a flash memory controller and its control method. Background Technology
[0002] Flash memory is a type of non-volatile solid-state storage, widely used in memory cards and USB flash drives, and in recent years has also been widely used in mobile electronic devices. In use, flash memory typically requires a flash memory controller to manage the data stored in it and to communicate with computers or electronic devices.
[0003] Flash controllers typically enter a power-saving mode when they don't receive access commands from the host device, turning off the power to static random-access memory (SRAM) to conserve power. Because a portion of the SRAM is disabled, some of the in-system programming (ISP) code stored there is lost. Therefore, when the flash controller transitions from power-saving mode to operating mode, it needs to re-read the ISP code from the flash memory modules into SRAM before it can properly receive access commands from the host device and access the flash memory modules. However, because the ISP code is large, the flash controller needs considerable time to read it. This results in a longer time for the flash controller to process access commands from the host device when exiting power-saving mode, thus reducing overall system performance.
[0004] Therefore, providing an electronic device that can improve the above-mentioned problems, including a flash memory controller, a control method for the flash memory controller, and its application, is one of the important current research topics. Summary of the Invention
[0005] To achieve the above objectives, the present invention provides a flash memory controller, a control method for the flash memory controller, and an electronic device for the application of the flash memory controller, which can set a specific area in the buffer memory as a hold memory before the flash memory controller enters a power-saving mode, so as to prevent the program code temporarily stored there from being lost when the power-saving mode is entered under specific conditions.
[0006] This invention provides a flash memory controller for accessing a flash memory module. The flash memory controller includes a buffer memory and a microprocessor. The buffer memory is used to temporarily store internal system program code, and a portion of the buffer memory is used to temporarily store write / read command program code associated with processing write or read operations within the internal system program code. The microprocessor executes the internal system program code to control access to the flash memory module. The microprocessor sets a portion of the buffer memory as retention memory, and upon receiving a start-stop unit (SSU) command representing entry into a sleep mode or a power-off mode, sets a portion of the buffer memory as non-retention memory. Upon receiving a hibernation command, the flash memory controller enters a power-saving mode and disables the non-retention memory.
[0007] In one embodiment, the start / stop unit command is sent by a host device.
[0008] In one embodiment, when the flash controller enters an operating mode from a power-saving mode, the microprocessor reads write / read command program code associated with the write or read operation from the system internal program code in the flash module to a portion of the buffer memory.
[0009] In one embodiment, when the flash memory controller enters the operating mode from the power-saving mode, the microprocessor sets a portion of the buffer memory as either retained memory or non-retained memory depending on whether it receives a start / stop unit command representing entering sleep mode or power-off mode.
[0010] In addition, to achieve the above objectives, the present invention also provides an electronic device comprising a flash memory module and a flash memory controller electrically connected to each other. The flash memory controller is used to access the flash memory module and includes a buffer memory and a microprocessor. The buffer memory is used to temporarily store internal system program code, and a portion of the buffer memory is used to temporarily store write / read command program code associated with processing write or read operations within the internal system program code. The microprocessor is used to execute the internal system program code to control access to the flash memory module. The microprocessor sets a portion of the buffer memory as retained memory, and upon receiving a start / stop unit command representing entering a sleep mode or a power-off mode, sets a portion of the buffer memory as non-retained memory. Upon receiving a hibernation command, the flash memory controller enters a power-saving mode and disables the non-retained memory.
[0011] Furthermore, to achieve the above objectives, the present invention also provides a control method for a flash memory controller, wherein the flash memory controller is used to access a flash memory module. The control method for the flash memory controller includes: setting a portion of a buffer memory used to temporarily store write / read command program code associated with processing write or read commands in the system's internal program code as a holding memory; determining whether a start / stop unit command representing entering a sleep mode or a power-off mode has been received; when a start / stop unit command representing entering a sleep mode or a power-off mode is received, setting a portion of the buffer memory as a non-holding memory; and upon receiving a hibernation command, the flash memory controller enters a power-saving mode and disables the non-holding memory.
[0012] As described above, the flash memory controller, flash memory controller control method, and electronic device thereof disclosed in this invention configure a region in the buffer memory that temporarily stores write / read command program code associated with processing writes or reads as retainable memory, thereby maintaining its operation and preventing it from being shut down. When the flash memory controller receives a start / stop unit command representing entering a sleep mode or a power-off mode, it then configures the region storing the write / read command program code as non-retainable memory and shuts it down after entering a power-saving mode. Accordingly, in the state of being configured as retainable memory, the write / read command program code associated with processing writes or reads will remain in the buffer memory, preventing it from being lost. Attached Figure Description
[0013] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0014] Figure 1 This is a block diagram of an electronic device including a flash memory module and a flash memory controller, which is a preferred embodiment of the present invention.
[0015] Figure 2 This is a flowchart of a control method for a flash memory controller according to a preferred embodiment of the present invention.
[0016] Figure 3 This is a detailed flowchart of the control method for the flash memory controller.
[0017] Figure label:
[0018] 10: Electronic devices
[0019] 100: Memory device
[0020] 110: Flash memory module
[0021] 111: System Area
[0022] 112: Data Area
[0023] 113: Backup Area
[0024] 120: Flash memory controller
[0025] 121: Microprocessor
[0026] 122: Read-only memory
[0027] 122C: Program code
[0028] 123: Memory Interface
[0029] 124: Buffer memory
[0030] 124A: Partial Area
[0031] 124B: Another part of the area
[0032] 125: Host Interface
[0033] 130: Host terminal device
[0034] S01-S04, S11-S17: Steps Detailed Implementation
[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0036] Figure 1 This is a schematic diagram of an electronic device 10 according to a preferred embodiment of the present invention. The electronic device 10 includes a host device 130 and a memory device 100. The memory device 100 includes a flash memory module 110 and a flash memory controller 120, wherein the flash memory controller 120 is used to access the flash memory module 110.
[0037] The flash memory module 110 may include a system zone 111, a data zone 112, and a spare zone 113. The system zone 111 stores internal system program code, which may include write / read command program code associated with processing write or read operations, or error correction code (ECC) associated with processing error verification. Furthermore, the flash memory module 110 includes multiple flash memory chips (not shown), each chip comprising multiple blocks, and the flash memory controller 120 performs data erasure operations on the flash memory module 110 on a block-by-block basis. Additionally, a single block can record a specific number of data pages, and the flash memory controller 120 performs data writing operations on the flash memory module 110 on a page-by-page basis. In this embodiment, the flash memory module 110 is a NAND-type flash memory module, but this is not a limiting factor.
[0038] The flash memory controller 120 includes a microprocessor 121, a read-only memory (ROM) 122, a memory interface 123, a buffer memory 124, and a host interface 125, all electrically connected to each other. The ROM 122 stores program code 122C, which includes at least boot code. The microprocessor 121 executes the program code 122C to control access to the flash memory module 110, for example, loading all or part of the system's internal program code into the buffer memory 124.
[0039] Memory interface 123 serves as the connection interface between flash memory controller 120 and flash memory module 110 for data transmission. Host interface 125 serves as the connection interface between flash memory controller 120 and host device 130 for data transmission. In this embodiment, host interface 125 can receive, for example, start / stop unit commands sent by host device 130. These start / stop unit commands include, for example, Active, Pre-Active, Idle, Sleep, Pre-Sleep, PowerDown, and Pre-PowerDown.
[0040] The buffer memory 124 includes, but is not limited to, static random access memory (SRAM), multiple regions for temporarily storing internal system program code. The microprocessor 121 can, as needed, configure a portion of buffer memory 124A as persistent memory and another portion 124B as non-persistent memory. Persistent memory is memory that will not be closed under certain conditions, thus preserving the program code temporarily stored there.
[0041] In this embodiment, the memory device 100 can be a portable memory device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device 10 that can be connected to the memory device, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the memory device 100 can be a solid-state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded MultiMedia Card (EMMC) specifications, and can be installed in the electronic device 10, such as in a mobile phone, laptop, or desktop computer. In this case, the host device 130 can be a processor of the electronic device 10.
[0042] Next, please refer to Figure 2 And in combination with the above and Figure 1 This invention describes a preferred embodiment of a flash memory controller control method. The control method of the flash memory controller in this embodiment includes steps S01 to S04.
[0043] Step S01 involves setting a portion of the buffer memory as retainable memory. In this embodiment, the microprocessor 121 sets a portion 124A of the buffer memory 124, which is used to temporarily store write / read command program code related to processing write or read operations within the system's internal program code, as retainable memory. It is worth noting that when the flash controller 120 goes into sleep mode, the retainable memory will not be shut down, thus the program code temporarily stored therein will be preserved.
[0044] Step S02 involves determining whether a start / stop unit command representing entering a sleep mode or a power-off mode has been received. In this embodiment, the microprocessor 121 can receive commands from the host device 130 via the host interface 125 and determine whether they are start / stop unit commands representing entering a sleep mode or a power-off mode. The start / stop unit command representing a sleep mode may include "sleep" and "before sleep," while the start / stop unit command representing a power-off mode may include "power off" and "before power off."
[0045] Step S03 involves setting a portion of buffer memory 124A as non-retention memory when a start / stop unit command representing entering sleep mode or power-off mode is received. Since the start / stop unit command is sent by the host device 130, when the command is for entering sleep mode or power-off mode, it indicates an active command from the host device 130, potentially leading to a prolonged hibernation period. Therefore, setting a portion of buffer memory 124A as non-retention memory allows it to be shut down during subsequent hibernation, thus saving energy.
[0046] It is worth mentioning that, depending on the usage scenario, the microprocessor 121 can be configured to set a portion of region 124A as non-retaining memory only when the start / stop unit command is for "sleep" or "power off," while keeping a portion of region 124A as retaining memory when it is for "before sleep" or "before power off." In other words, the judgment condition can be adjusted by the user or by artificial intelligence based on usage experience, without any limitations.
[0047] Step S04 involves the flash memory controller entering power-saving mode and shutting down non-retaining memory after receiving a hibernate command. Simultaneously, program code temporarily stored in the buffer memory 124 belonging to the non-retaining memory area will be deleted until the next start / stop unit command representing "working" is received, at which point the microprocessor 121 loads part or all of the corresponding internal system program code from the flash memory module 110 into the buffer memory 124.
[0048] Please refer to the following: Figure 3 The above description is used to further illustrate the control method of the flash memory controller in a preferred embodiment of the present invention. The control method of the flash memory controller in this embodiment includes steps S11 to S17.
[0049] Step S11 is to set a portion of buffer memory 124A, which is used to temporarily store the write / read command program code associated with the internal program code of the system that handles writing or reading, as holding memory.
[0050] Step S12 is to determine whether a start / stop unit command has been received. If the result is "yes", proceed to step S13; if the result is "no", proceed to step S15.
[0051] Step S13 determines whether the start / stop unit command is "sleep" or "power off". If the result is "yes", proceed to step S14; if the result is "no", return to step S11.
[0052] Step S14 involves setting a portion of buffer memory 124A, which temporarily stores write / read command program code related to writing or reading in the system's internal program code, as non-retaining memory. Then, the process returns to step S12.
[0053] Step S15 determines whether to enter hibernation mode. This step is based on whether the flash memory controller 120 has received a hibernation command. If the result is "yes", the process proceeds to step S16; if the result is "no", the process returns to step S12.
[0054] Step S16 involves entering power-saving mode and disabling non-retaining memory. Simultaneously, program code temporarily stored in the buffer memory 124 that belongs to the non-retaining memory area will be deleted.
[0055] Next, step S17 determines whether to exit hibernation mode. If the result is "yes", the process proceeds to step S12; if the result is "no", it continues to step S17. In this step, it is determined whether a start / stop unit command representing "operation" has been received from the host device 130.
[0056] When a start / stop unit command representing "working" is received, it indicates that the flash memory controller 120 will enter the working mode from the power-saving mode. At this time, the microprocessor 121 will read the internal system program code from the system area 111 of the flash memory module 110 into the buffer memory 124. Then, proceeding to steps S12 and S13, if no start / stop unit command representing entering the sleep mode or power-off mode is received, the portion 124A of the buffer memory 124 used to temporarily store the write / read command program code related to processing write or read in the internal system program code is set as retainable memory. In other words, when the flash memory controller 120 enters the working mode from the power-saving mode, the microprocessor 121 will set the portion 124A of the buffer memory 124 as retainable memory or non-retainable memory depending on whether a start / stop unit command representing entering the sleep mode or power-off mode is received.
[0057] In summary, the flash memory controller, flash memory controller control method, and electronic device thereof disclosed in this invention configure a region in the buffer memory that temporarily stores write / read command program code associated with processing writes or reads as retainable memory, thereby maintaining its operation and preventing it from being shut down. When the flash memory controller receives a start / stop unit command representing entering a sleep mode or a power-off mode, it then configures the region storing the write / read command program code as non-retainable memory and shuts it down after subsequently entering a power-saving mode.
[0058] Therefore, when the flash controller enters power-saving mode not because of a start / stop unit command to enter sleep or power-off mode (e.g., because no start / stop unit command has been received after a preset time), the write / read command program code, which is temporarily stored in a portion of memory set as hold memory, will not be shut down and will be avoided from being lost. In this case, when the flash controller is woken up, it does not need to reread the relevant program code and can respond to the corresponding operation in a timely manner.
[0059] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the methods and techniques disclosed above without departing from the scope of the present invention to create equivalent embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A flash memory controller for accessing a flash memory module, characterized in that, include: A buffer memory is used to temporarily store internal program code of a system, and a portion of the buffer memory is used to temporarily store write / read command program code associated with processing write or read in the internal program code of the system. as well as A microprocessor is used to execute internal system program code to control access to the flash memory module; The microprocessor sets a portion of the buffer memory as a persistent memory, and sets the portion of the buffer memory as a non-persistent memory upon receiving a start / stop unit command representing entering a sleep mode or a power-off mode. Upon receiving a hibernation command, the flash memory controller enters the power-saving mode and shuts down the non-persistent memory.
2. The flash memory controller as described in claim 1, characterized in that, The start / stop unit command is sent by a host terminal device.
3. The flash memory controller as described in claim 1, characterized in that, When the flash memory controller enters a working mode from the power-saving mode, the microprocessor reads the write / read command program code associated with the write or read operation from the internal program code of the system in the flash memory module and writes it to the portion of the buffer memory.
4. The flash memory controller as described in claim 3, characterized in that, When the flash memory controller enters the operating mode from the power saving mode, the microprocessor sets a portion of the buffer memory as the retained memory or the non-retained memory depending on whether it receives a start / stop unit command representing entry into the sleep mode or the shutdown mode.
5. An electronic device, characterized in that, include: One flash memory module; as well as A flash memory controller for accessing the flash memory module, wherein the flash memory controller includes: A buffer memory for temporarily storing internal system program code, and a portion of the buffer memory for temporarily storing write / read command program code within the internal system program code related to processing writes or reads; and A microprocessor is used to execute internal system program code to control access to the flash memory module; The microprocessor sets a portion of the buffer memory as a persistent memory, and sets the portion of the buffer memory as a non-persistent memory upon receiving a start / stop unit command representing entering a sleep mode or a power-off mode. Upon receiving a hibernation command, the flash memory controller enters the power-saving mode and shuts down the non-persistent memory.
6. The electronic device as claimed in claim 5, characterized in that, The start / stop unit command is sent by a host terminal device.
7. The electronic device as claimed in claim 5, characterized in that, When the flash memory controller enters a working mode from the power-saving mode, the microprocessor reads the write / read command program code associated with the write or read operation from the internal program code of the system in the flash memory module and writes it to the portion of the buffer memory.
8. The electronic device as claimed in claim 7, characterized in that, When the flash memory controller enters the operating mode from the power saving mode, the microprocessor sets a portion of the buffer memory as the retained memory or the non-retained memory depending on whether it receives a start / stop unit command representing entry into the sleep mode or the shutdown mode.
9. A control method for a flash memory controller, wherein the flash memory controller is used to access a flash memory module, characterized in that, The control method of the flash memory controller includes: Set a portion of a buffer memory that temporarily stores write / read commands associated with internal system program code for handling write or read operations as a holding memory. Determine whether a start / stop unit command representing entering a sleep mode or a shutdown mode has been received; When a start / stop unit command representing entry into the sleep mode or the shutdown mode is received, the portion of the buffer memory is set to non-retention memory; and Upon receiving a hibernation command, the flash memory controller enters the power-saving mode and shuts down the non-retaining memory.
10. The control method for a flash memory controller as described in claim 9, characterized in that, Also includes: When the flash memory controller enters a working mode from the power-saving mode, the microprocessor reads the write / read command program code associated with the write or read operation from the internal program code of the system in the flash memory module and writes it to the portion of the buffer memory.
11. The control method for a flash memory controller as described in claim 9, characterized in that, Also includes: When the flash memory controller enters the operating mode from the power saving mode, the microprocessor sets a portion of the buffer memory as the retained memory or the non-retained memory depending on whether it receives a start / stop unit command representing entry into the sleep mode or the shutdown mode.