Flash memory controller, control method of flash memory controller and electronic device applied by flash memory controller
By setting a buffer memory area in the flash memory controller to retain the program code based on the number of commands, the problem of long ISP code loading time in power-saving mode is solved, thus improving the system's response speed and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN XINXIN SEMICONDUCTOR CO LTD
- Filing Date
- 2024-11-01
- Publication Date
- 2026-05-08
AI Technical Summary
The flash memory controller takes a long time to reload the ISP code in power-saving mode, which reduces system performance.
Before the flash memory controller enters power-saving mode, a specific area in the buffer memory is set as hold memory. A count value is generated based on the number of write or read commands received by the microprocessor. When the count value reaches a preset value, the area is set as hold memory to prevent the program code from disappearing, and the ISP code is loaded directly when entering the working mode.
This reduces the latency of the flash controller switching from power-saving mode to operating mode, improving system response speed and performance.
Smart Images
Figure CN121996142A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more particularly to a flash memory controller and its control method. Background Technology
[0002] Flash memory is a type of non-volatile solid-state storage, widely used in memory cards and USB flash drives, and in recent years has also been widely used in mobile electronic devices. In use, flash memory typically requires a flash memory controller to manage the data stored in it and to communicate with computers or electronic devices.
[0003] Flash controllers typically enter a power-saving mode when they don't receive access commands from the host device, turning off the power to static random-access memory (SRAM) to conserve power. Because a portion of the SRAM is disabled, some of the in-system programming (ISP) code stored there is lost. Therefore, when the flash controller transitions from power-saving mode to operating mode, it needs to re-read the ISP code from the flash memory modules into SRAM before it can properly receive access commands from the host device and access the flash memory modules. However, because the ISP code is large, the flash controller needs considerable time to read it. This results in a longer time for the flash controller to process access commands from the host device when exiting power-saving mode, thus reducing overall system performance.
[0004] Therefore, providing an electronic device that can improve the above-mentioned problems, including a flash memory controller, a control method for the flash memory controller, and its application, is one of the important current research topics. Summary of the Invention
[0005] To achieve the above objectives, the present invention provides a flash memory controller, a control method for the flash memory controller, and an electronic device for the application of the flash memory controller, which can set a specific area in the buffer memory as a hold memory before the flash memory controller enters the power-saving mode, according to specific conditions, so as to prevent the program code temporarily stored there from being lost after entering the power-saving mode.
[0006] This invention provides a flash memory controller for accessing a flash memory module. The flash memory controller includes a buffer memory, a microprocessor, and a counter. The buffer memory is used to temporarily store internal system program code, and a portion of the buffer memory is used to temporarily store write / read command program code associated with processing write or read operations. The microprocessor executes the internal system program code to control access to the flash memory module. The counter generates a count value in response to the number of consecutive write or read commands received by the microprocessor. The microprocessor sets a portion of the buffer memory as non-retention memory. Upon receiving a sleep command, when the count value is greater than or equal to a pre-designed value, it sets a portion of the buffer memory as retained memory, causing the flash memory controller to enter a power-saving mode and disabling the non-retention memory.
[0007] In one embodiment, the write command or read command is sent by a host device.
[0008] In one embodiment, upon receiving a hibernation command, if the count value is less than a pre-designed value, the flash memory controller is directly put into power-saving mode, and non-retaining memory is shut down. Furthermore, when the flash memory controller transitions from power-saving mode to operating mode, the microprocessor reads the write / read command program code associated with the write or read operations from the system's internal program code within the flash memory module and stores it in a portion of the buffer memory.
[0009] In one embodiment, when the flash memory controller enters the operating mode from the power-saving mode, the microprocessor sets a portion of the buffer memory as non-retaining memory.
[0010] In addition, to achieve the above objectives, the present invention also provides an electronic device comprising a flash memory module and a flash memory controller electrically connected to each other. The flash memory controller is used to access the flash memory module and includes a buffer memory, a microprocessor, and a counter. The buffer memory is used to temporarily store internal system program code, and a portion of the buffer memory is used to temporarily store write / read command program code associated with processing write or read operations within the internal system program code. The microprocessor is used to execute the internal system program code to control access to the flash memory module. The counter generates a count value in response to the number of consecutive write or read commands received by the microprocessor. The microprocessor sets a portion of the buffer memory as non-retaining memory, and upon receiving a sleep command, when the count value is greater than or equal to a preset value, sets a portion of the buffer memory as retaining memory, causing the flash memory controller to enter a power-saving mode and disabling the non-retaining memory.
[0011] Furthermore, to achieve the above objectives, the present invention also provides a control method for a flash memory controller, wherein the flash memory controller is used to access a flash memory module. The control method for the flash memory controller includes: setting a portion of a buffer memory used to temporarily store write / read command program code associated with processing write or read commands in the system's internal program code as non-retention memory; incrementing a counter from 0 based on the number of consecutive write or read commands received by a microprocessor to generate a count value; upon receiving a sleep command, determining whether the count value is greater than or equal to a preset value; and when the count value is greater than or equal to the preset value, setting a portion of the buffer memory as retention memory, causing the flash memory controller to enter a power-saving mode, and disabling the non-retention memory.
[0012] In one embodiment, upon receiving a hibernation command, if the count value is less than a pre-designed value, the flash controller is directly put into a power-saving mode and the non-retaining memory is turned off; and when the flash controller enters a working mode from the power-saving mode, the microprocessor reads the write / read command program code associated with the write or read operation from the internal program code of the flash module to a portion of the buffer memory.
[0013] As described above, the flash memory controller, flash memory controller control method, and electronic device using the present invention determine whether to set a portion of the buffer memory used to temporarily store the write / read command program code associated with processing write or read operations as holding memory based on a count value generated by the number of consecutive write or read commands received by the microprocessor. When the count value is greater than or equal to a preset value, it indicates that the read or write operation is active, and the portion of the memory can be set as holding memory. While the portion of the memory is set as holding memory, the write / read command program code associated with processing write or read operations will remain in the buffer memory, preventing it from being erased. When the read or write operation is not active, the portion of the memory is set as non-holding memory, and therefore can be turned off during sleep to save power. Attached Figure Description
[0014] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0015] Figure 1 This is a block diagram of an electronic device including a flash memory module and a flash memory controller, which is a preferred embodiment of the present invention.
[0016] Figure 2 This is a flowchart of a control method for a flash memory controller according to a preferred embodiment of the present invention.
[0017] Figure 3 This is a detailed flowchart of the control method for the flash memory controller.
[0018] Figure label:
[0019] 10: Electronic devices
[0020] 100: Memory device
[0021] 110: Flash memory module
[0022] 111: System Area
[0023] 112: Data Area
[0024] 113: Backup Area
[0025] 120: Flash memory controller
[0026] 121: Microprocessor
[0027] 122: Read-only memory
[0028] 122C: Program code
[0029] 123: Memory Interface
[0030] 124: Buffer memory
[0031] 124A: Partial Area
[0032] 124B: Another part of the area
[0033] 125: Host Interface
[0034] 126: Counter
[0035] 130: Host terminal device
[0036] S01-S04, S11-S20: Steps Detailed Implementation
[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0038] Figure 1 This is a schematic diagram of an electronic device 10 according to a preferred embodiment of the present invention. The electronic device 10 includes a host device 130 and a memory device 100. The memory device 100 includes a flash memory module 110 and a flash memory controller 120, wherein the flash memory controller 120 is used to access the flash memory module 110.
[0039] The flash memory module 110 may include a system zone 111, a data zone 112, and a spare zone 113. The system zone 111 stores internal system program code, which may include write / read command program code associated with processing write or read operations, or error correction code (ECC) associated with processing error verification. Furthermore, the flash memory module 110 includes multiple flash memory chips (not shown), each chip comprising multiple blocks, and the flash memory controller 120 performs data erasure operations on the flash memory module 110 on a block-by-block basis. Additionally, a single block can record a specific number of data pages, and the flash memory controller 120 performs data writing operations on the flash memory module 110 on a page-by-page basis. In this embodiment, the flash memory module 110 is a NAND-type flash memory module, but this is not a limiting factor.
[0040] The flash memory controller 120 includes a microprocessor 121, a read-only memory (ROM) 122, a memory interface 123, a buffer memory 124, a host interface 125, and a counter 126, all electrically connected to each other. The ROM 122 stores program code 122C, which includes at least boot code. The microprocessor 121 executes the program code 122C to control access to the flash memory module 110, for example, loading all or part of the system's internal program code into the buffer memory 124.
[0041] Memory interface 123 serves as the connection interface between flash memory controller 120 and flash memory module 110 for data transmission. Host interface 125 serves as the connection interface between flash memory controller 120 and host device 130 for data transmission. In this embodiment, host interface 125 can receive commands such as start / stop unit commands, read commands, or write commands sent by host device 130. Start / stop unit commands include, for example, Active, Pre-Active, Idle, Sleep, Pre-Sleep, PowerDown, and Pre-PowerDown.
[0042] The buffer memory 124, such as but not limited to static random access memory (SRAM), includes multiple regions for temporarily storing internal system program code. The microprocessor 121 can, as needed, configure a portion of buffer memory 124A as persistent memory and another portion 124B as non-persistent memory. Persistent memory is memory that is not turned off under certain conditions, thus preserving the program code temporarily stored in that area. These specific conditions include, for example, the flash controller entering sleep or power-saving mode.
[0043] Counter 126 is used to record the number of times an event occurs. It can count based on external or internal signals and can be set to increment or decrement depending on the application requirements. Counter 126 can accumulate counts from 0 or a preset value. The preset value is, for example, any integer, which can be modified by setting. In this invention, counter 126 generates a count value in response to the number of times the microprocessor 121 continuously receives a write command or a read command.
[0044] It is worth mentioning that in this embodiment, the counter 126 is described as a component independent of the microprocessor. In other embodiments, the counter 126 may also be integrated into the microprocessor 121, or implemented by software or firmware, and there is no limitation on this.
[0045] In this embodiment, the memory device 100 can be a portable memory device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device 10 that can be connected to the memory device, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the memory device 100 can be a solid-state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded MultiMedia Card (EMMC) specifications, and can be installed in the electronic device 10, such as in a mobile phone, laptop, or desktop computer. In this case, the host device 130 can be a processor of the electronic device 10.
[0046] Next, please refer to Figure 2 And in combination with the above and Figure 1 This invention describes a preferred embodiment of a flash memory controller control method. The control method of the flash memory controller in this embodiment includes steps S01 to S04.
[0047] After the program starts, step S01 is to set a portion of the buffer memory as non-retaining memory. In this embodiment, the microprocessor 121 sets a portion 124A of the buffer memory 124, which is used to temporarily store write / read command program code related to processing writes or reads in the internal program code of the system, as non-retaining memory.
[0048] Step S02 involves incrementing the counter 126 and generating a count value based on the number of consecutive write or read commands received by the microprocessor 121. In this embodiment, the counter 126 increments from 0, and the microprocessor 121 receives commands from the host device 130 via the host interface 125. When the microprocessor 121 receives a second consecutive write or read command, the counter 126 increments by 1; when a non-write or read command is received, the counter 126 is reset to 0 or returns to a preset value.
[0049] Step S03 is to determine whether the count value is greater than or equal to a pre-designed value after receiving the hibernation command. The default count value is a value set by the user or product developer, such as an integer like 5, 10, 100, etc. There are no restrictions on this value. Furthermore, the pre-designed value can be adjusted by artificial intelligence based on the actual operation process.
[0050] Step S04 involves setting a portion of the buffer memory as hold memory when the count value is greater than or equal to a pre-designed value, causing the flash controller to enter power-saving mode and shutting down the non-hold memory. When the flash controller 120 goes into sleep mode, the hold memory will not be shut down, thus preserving the program code temporarily stored there. Therefore, a count value greater than or equal to the pre-designed value indicates that read or write operations are active. By continuously storing the relevant internal system program code in the buffer memory, additional waiting time can be avoided by reloading the relevant program code after sleep mode.
[0051] Please refer to the following: Figure 3 The above description is used to further illustrate the control method of the flash memory controller in a preferred embodiment of the present invention. The control method of the flash memory controller in this embodiment includes steps S11 to S20.
[0052] Step S11 is to set a portion of buffer memory 124A, which is used to temporarily store the write / read command program code associated with the internal program code of the system that handles writing or reading, as non-retaining memory.
[0053] Step S12 is to reset the counter. In this embodiment, the counter is reset to 0. In other embodiments, the counter may be reset to any preset value.
[0054] Step S13 determines whether any commands have been received. If the result is "yes", proceed to step S14; if the result is "no", proceed to step S16. It's worth noting that commands include read, write, erase, or reset, etc.
[0055] Step S14 determines whether the received command is a write command or a read command. If the result is "yes", proceed to step S15; if the result is "no", return to step S12.
[0056] Step S15 involves incrementing the counter. In this embodiment, this step increments the counter 126 by 1. In other embodiments, the incremented value can be any custom value, including negative values. After step S15 is completed, the process returns to step S13.
[0057] Step S16 determines whether to enter hibernation mode. This step is based on whether the flash memory controller 120 has received a hibernation command. If the result is "yes", the process proceeds to step S17; if the result is "no", the process returns to step S13.
[0058] Step S17 determines whether the count value is greater than or equal to the pre-designed value. In this embodiment, the pre-designed value is 5, but it can be any integer and is not a limiting factor. If the determination result is "yes", the process proceeds to step S18; if the determination result is "no", the process proceeds to step S19.
[0059] Step S18 involves setting a portion of buffer memory 124A, which temporarily stores write / read command program code related to writing or reading in the system's internal program code, as hold memory. Then, the process proceeds to step S19. In this step, since a count value greater than or equal to a pre-designed value indicates a current need for writing or reading, setting a portion of region 124A as hold memory avoids the need to reload the write / read command program code related to writing or reading into buffer memory 124 after a sudden hibernation event.
[0060] Step S19 involves entering power-saving mode and disabling non-retaining memory. Simultaneously, program code temporarily stored in the buffer memory 124 belonging to the non-retaining memory area will be deleted. Then, the process proceeds to step S20.
[0061] Next, step S20 determines whether to exit hibernation mode. If the result is "yes," the process proceeds to step S11; if the result is "no," step S20 continues. In this step, it is determined whether a start / stop unit command representing "working" has been received from the host device 130. When a start / stop unit command representing "working" is received, it indicates that the flash memory controller 120 will enter working mode from power-saving mode, and the necessary steps will be restarted from step S11.
[0062] It is worth mentioning that when the flash memory controller 120 enters the operating mode from the power-saving mode, the microprocessor 121 reads the internal system program code from the system area 111 of the flash memory module 110 into the buffer memory 124. The read internal system program code excludes the portion temporarily stored in the holding memory. In other words, when the write / read command program code associated with processing writes or reads is still temporarily stored in the portion 124A of the buffer memory 124 designated as holding memory, the flash memory controller 120 can immediately execute the read or write command upon entering the operating mode from the power-saving mode, eliminating the waiting time for loading.
[0063] In summary, the flash memory controller, flash memory controller control method, and electronic device disclosed in this invention determine whether to set a portion of the buffer memory used to temporarily store write / read command program code related to the write or read operations based on a count value generated by the number of consecutive write or read commands received by the microprocessor. When the count value is greater than or equal to a preset value, it indicates that the read or write operation is active, and the portion of the memory can be set as hold memory. While the portion of the memory is set as hold memory, the write / read command program code related to the write or read operations will remain in the buffer memory, preventing it from being erased. When the read or write operation is not active, the portion of the memory is set as non-hold memory, and therefore can be turned off during sleep mode to save power.
[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the methods and techniques disclosed above without departing from the scope of the present invention to create equivalent embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A flash memory controller for accessing a flash memory module, characterized in that, include: A buffer memory is used to temporarily store internal program code of a system, and a portion of the buffer memory is used to temporarily store write / read command program code associated with processing write or read in the internal program code of the system. A microprocessor is used to execute internal system program code to control access to the flash memory module; as well as A counter generates a count value in response to the number of times the microprocessor receives a write command or a read command consecutively; The microprocessor sets a portion of the buffer memory as non-retaining memory. Upon receiving a hibernation command, when the count value is greater than or equal to a pre-designed value, it sets the portion of the buffer memory as retaining memory, causing the flash memory controller to enter the power-saving mode and shutting down the non-retaining memory.
2. The flash memory controller as described in claim 1, characterized in that, The write command or the read command is sent by a host device.
3. The flash memory controller as described in claim 1, characterized in that, Also includes: Upon receiving the hibernation command, if the count value is less than the preset value, the flash memory controller is directly put into the power-saving mode, and the non-retention memory is shut down; and When the flash memory controller enters the operating mode from the power-saving mode, the microprocessor reads the write / read command program code associated with the write or read operation from the internal program code of the system in the flash memory module and writes it to the portion of the buffer memory.
4. The flash memory controller as claimed in claim 1, characterized in that, When the flash memory controller switches from the power-saving mode to the operating mode, the microprocessor sets a portion of the buffer memory as the non-retaining memory.
5. An electronic device, characterized in that, include: One flash memory module; as well as A flash memory controller for accessing the flash memory module, wherein the flash memory controller includes: A buffer memory for temporarily storing internal system program code, and a portion of the buffer memory for temporarily storing write / read command program code within the internal system program code related to processing writes or reads; and A microprocessor for executing internal system program code to control access to the flash memory module; and A counter generates a count value in response to the number of times the microprocessor receives a write command or a read command consecutively; The microprocessor sets a portion of the buffer memory as non-retaining memory, and upon receiving a hibernation command, when the count value is greater than or equal to a pre-designed value, sets the portion of the buffer memory as retaining memory, thereby causing the flash memory controller to enter the power-saving mode and shutting down the non-retaining memory.
6. The electronic device as claimed in claim 5, characterized in that, The write command or the read command is sent by a host device.
7. The electronic device as claimed in claim 5, characterized in that, Also includes: Upon receiving the hibernation command, if the count value is less than the preset value, the flash memory controller is directly put into the power-saving mode, and the non-retention memory is shut down; and When the flash memory controller enters the operating mode from the power-saving mode, the microprocessor reads the write / read command program code associated with the write or read operation from the internal program code of the system in the flash memory module and writes it to the portion of the buffer memory.
8. The electronic device as claimed in claim 5, characterized in that, When the flash memory controller switches from the power-saving mode to the operating mode, the microprocessor sets a portion of the buffer memory as the non-retaining memory.
9. A control method for a flash memory controller, wherein the flash memory controller is used to access a flash memory module, characterized in that, The control method of the flash memory controller includes: Set a portion of a buffer memory that temporarily stores write / read commands associated with the internal program code of the system to be non-retained memory; A counter is incremented from 0 based on the number of times a microprocessor receives a write command or a read command consecutively, thus generating a count value. Upon receiving a hibernation command, determine whether the count value is greater than or equal to a pre-designed value; and When the count value is greater than or equal to the pre-designed value, the portion of the buffer memory is set as a hold memory, the flash memory controller enters the power-saving mode, and the non-hold memory is turned off.
10. The control method for a flash memory controller as described in claim 9, characterized in that, Also includes: Upon receiving the hibernation command, if the count value is less than the preset value, the flash memory controller is directly put into the power-saving mode, and the non-retention memory is shut down; and When the flash memory controller enters a working mode from the power-saving mode, the microprocessor reads the write / read command program code associated with the write or read operation from the internal program code of the system in the flash memory module and writes it to the portion of the buffer memory.
11. The control method for a flash memory controller as described in claim 9, characterized in that, Also includes: When the flash memory controller switches from the power-saving mode to the operating mode, the microprocessor sets a portion of the buffer memory as the non-retaining memory.