Compiling method, compiling device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a compiling method, a compiling device, electronic equipment and a storage medium, and belongs to the technical field of computer compiling. The corresponding method comprises the following steps: mapping operator nodes of a predetermined target application to a virtual processing unit; generating a PE array according to the plurality of virtual processing units; wherein the PE array is used for representing the operator nodes executed by the virtual processing unit, a corresponding execution clock period, a hardware function unit supported by the virtual processing unit and a data dependency relationship among a plurality of operator nodes; and generating a hardware description language code of the target application according to the PE array. According to the method, one-time and collaborative global optimization can be carried out on the target software and the bottom-layer reconfigurable hardware architecture, so that a high-performance and high-energy-efficiency customized computing system is efficiently and automatically generated.

Description

Technical Field

[0001] This application belongs to the field of computer technology, specifically relating to a compilation method, a compilation device, an electronic device, and a storage medium. Background Technology

[0002] Currently, the emergence of new applications, the continuous increase in user demand, and the rapid development of technological capabilities have led to increasingly faster software upgrades. Consequently, hardware implementations are unable to adapt to these software changes, resulting in hardware production facing challenges such as excessively short lifecycles and high one-time engineering costs.

[0003] In existing technologies, domain-specific reconfigurable computing architectures (such as coarse-grained reconfigurable arrays, CGRA) have become an important solution to the aforementioned problems. The core design principle of such architectures lies in how to automatically generate a highly energy-efficient and area-optimized hardware structure and its configuration information based on a set of target software applications (kernels). Currently, the mainstream method to achieve this goal is Design Space Exploration (DSE). This process typically involves iterative modification, mapping, and evaluation of the hardware architecture with the assistance of a compiler. However, this "compiler-in-the-loop" iterative method has a fundamental flaw: the direction of hardware architecture exploration is disconnected from the actual mapping results of the software on that architecture. Specifically:

[0004] Inefficient optimization: Every tiny adjustment to hardware parameters requires re-calling the compiler to map the target software to the new architecture and perform performance, power consumption, and area (PPA) evaluations, resulting in huge and unnecessary exploration overhead.

[0005] The optimization objectives are fragmented: the existing DSE process treats "architectural modification" and "software mapping evaluation" as two separate stages. Sudden changes in hardware architecture (such as adding or removing functional units or changing interconnects) are based on "post-hoc" analysis of the previous round of mapping results, rather than "pre-hoc" guidance that is coordinated with the mapping process. This leads to a blind search process and makes it difficult to achieve global optimization.

[0006] The lack of a unified abstraction layer is a significant problem. Existing compiler intermediate representations (IRs) or hardware-oriented descriptions (such as LLVM IR, MLIR, and Architecture Description Graphs (ADGs) are primarily used in single domains: they can only describe software logic and data flow (i.e., the logical flow of data processed by the software), or they can only describe static hardware structures. The absence of a unified intermediate representation that can simultaneously and explicitly express the characteristics of physical hardware resources and the virtual mapping results of software on them makes it difficult to formalize and efficiently solve hardware-software co-optimization problems. Summary of the Invention

[0007] One object of the present invention is to construct a compilation method and apparatus, which aims to solve at least a portion of the above-mentioned technical problems.

[0008] Another object of the present invention is to provide a compilation apparatus. Another object of the present invention is to provide an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program, implements the steps of the above-described compilation method. A further object of the present invention is to provide a readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described compilation method.

[0009] To address the technical problems in the background section of this application, the present invention provides the following technical solutions:

[0010] In a first aspect, the present invention provides a compilation method comprising:

[0011] Map the pre-determined target application's operator nodes to the virtual processing unit;

[0012] A PE array is generated based on the plurality of virtual processing units; wherein the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between the plurality of operator nodes;

[0013] The hardware description language code for the target application is generated based on the PE array.

[0014] In one embodiment of the present invention, generating hardware description language code for the target application based on the PE array includes:

[0015] The first constraint is generated based on the number of hardware functional units required by the PE array and the number of physical connection units between the multiple virtual processing units.

[0016] A first intermediate representation of the target application is generated based on the first constraint and the PE array;

[0017] A second constraint is generated based on the number of registers required by the PE array;

[0018] Generate a second intermediate representation of the target application based on the second constraint and the first intermediate representation;

[0019] The hardware description language code is generated based on the second intermediate representation.

[0020] In one embodiment of the present invention, the first intermediate representation includes: the structure of the PE array, the mapping relationship between the operator nodes and the virtual processing units, and the data dependency relationship between multiple virtual processing units; wherein, the data dependency relationship between the multiple virtual processing units is determined by the data dependency relationship between the multiple operator nodes.

[0021] In some embodiments of the present invention, the second intermediate representation includes: all hardware functional units, the port and source of the input data of the virtual processing unit, and the configuration of the registers.

[0022] In one embodiment of the present invention, a first constraint condition is generated based on the number of hardware functional units required by the PE array and the number of physical connection units between the plurality of virtual processing units, including:

[0023] The first constraint condition is generated by optimizing the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units to a minimum value through a pre-generated integer programming model.

[0024] In one embodiment of the present invention, a second constraint condition is generated based on the number of registers required by the PE array, including:

[0025] The second constraint is generated by merging time-incompatible registers used in the first intermediate representation using a pre-generated graph coloring model.

[0026] The steps for determining the operator nodes of the target application include:

[0027] The data flow graph of the target application is determined based on the execution logic of the target application;

[0028] The operator node is determined based on the data flow graph.

[0029] In a second aspect, the present invention provides a compilation apparatus, the apparatus comprising:

[0030] The node mapping module is used to map the operator nodes of the predetermined target application to the virtual processing unit;

[0031] A PE array generation module is used to generate a PE array based on a plurality of virtual processing units; wherein, the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between the plurality of operator nodes;

[0032] The hardware code generation module is used to generate hardware description language code for the target application based on the PE array.

[0033] In one embodiment of the present invention, the hardware code generation module includes:

[0034] The first condition generation unit is used to generate a first constraint condition based on the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units.

[0035] The first intermediate representation generation unit is configured to generate a first intermediate representation of the target application based on the first constraint condition and the PE array.

[0036] The second condition generation unit is used to generate a second constraint condition based on the number of registers required by the PE array;

[0037] The second intermediate representation generation unit is configured to generate a second intermediate representation of the target application based on the second constraint and the first intermediate representation.

[0038] The hardware code generation unit is used to generate the hardware description language code based on the second intermediate representation.

[0039] In one embodiment of the present invention, the first condition generation unit includes:

[0040] The first condition generation sub-unit is used to optimize the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units to the minimum value through a pre-generated integer programming model, thereby generating the first constraint condition.

[0041] In one embodiment of the present invention, the second condition generation unit includes:

[0042] The second condition generation subunit is used to merge time-incompatible registers used in the first intermediate representation through a pre-generated graph coloring model to generate the second constraint condition.

[0043] In one embodiment of the present invention, a compilation apparatus capable of implementing a compilation method further includes:

[0044] An operator node determination module is used to determine the operator nodes of the target application; the operator node determination module includes:

[0045] A data flow graph determination unit is used to determine the data flow graph of the target application based on the execution logic of the target application;

[0046] The operator node determination unit is used to determine the operator node based on the data flow graph.

[0047] Thirdly, the present invention provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of a compilation method.

[0048] Fourthly, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of a compilation method.

[0049] Fifthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a compilation method.

[0050] As described above, the compilation method and apparatus proposed in this application firstly map the predetermined operator nodes of the target application to virtual processing units; then, a PE array is generated based on multiple virtual processing units; wherein, the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between multiple operator nodes; finally, hardware description language code of the target application is generated based on the PE array.

[0051] This invention provides an intermediate representation of a compiler and a corresponding compilation method, which can perform one-time, collaborative global optimization of the target software and the underlying reconfigurable hardware architecture, thereby efficiently and automatically generating a high-performance, energy-efficient customized computing system. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a flowchart illustrating a compilation method in an embodiment of the present invention;

[0054] Figure 2 This is a flowchart illustrating step 300 of the compilation method in an embodiment of the present invention;

[0055] Figure 3This is a schematic diagram of another compilation method in an embodiment of the present invention;

[0056] Figure 4 This is a flowchart illustrating step 400 of the compilation method in an embodiment of the present invention;

[0057] Figure 5 This is a flowchart illustrating a compilation method according to a specific embodiment of the present invention;

[0058] Figure 6 This is a block diagram of a compilation device according to an embodiment of the present invention;

[0059] Figure 7 This is a block diagram of the hardware code generation module 30 in an embodiment of the present invention;

[0060] Figure 8 This is another block diagram of a compilation device according to an embodiment of the present invention;

[0061] Figure 9 This is a block diagram of the operator node determination module 40 in an embodiment of the present invention;

[0062] Figure 10 This is a schematic diagram of the structure of an electronic device in an embodiment of the present invention. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0065] It should be noted that the terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Without conflict, the embodiments and features in the embodiments of this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0066] The acquisition, storage, use, and processing of data in this application all comply with relevant laws and regulations.

[0067] With the rapid development of digitalization, intelligentization, and automation technologies, the demand for computing power from numerous emerging applications far exceeds previous levels. This development process generates massive amounts of data, originating from vast amounts of sensor data, logistics information, measurement and control information, biological information, and so on. Therefore, big data, cloud computing, artificial intelligence, and bioinformatics have become the most popular development areas. The ability to process and analyze massive amounts of data has become a core capability for adapting to the development of an information society, and providing them with high-efficiency computing power support is the primary driving force for chip development. In the past few decades, advancements in integrated circuit technology have been one of the main measures to improve the computing power of chips.

[0068] However, the pace of manufacturing technology development is slowing significantly. Moore's Law's prediction of transistor integration density has gradually decelerated and will soon reach its physical limits. The Denard scaling law's prediction of energy efficiency improvements has become completely ineffective. Limited by thermal management, continuous performance improvements are becoming increasingly difficult, and shrinking process feature widths no longer provides unconditional performance and energy efficiency gains. For example, the computational workload of Deep Neural Networks (DNNs), the largest neural network model in terms of data volume, has doubled every 3.4 months since 2012. In contrast, Moore's Law predicts that integrated circuit technology will only double every two years, and the recent slowdown has resulted in actual development lagging by as much as 15 times. Therefore, the gap between the growth rate of application demands and the growth rate of integrated circuit technology is widening. Currently, the mainstream approach is to increase computing power by adding processor cores. However, due to the low energy efficiency of general-purpose processors, the severe problem of massive parallel processing is the exponential increase in energy consumption. It is difficult to imagine the inefficiency of training with general-purpose processors today; future demands must be prepared for far greater computing power than today. Therefore, chip designers have had to shift their focus from performance to energy efficiency. At the same time, the flexibility of computing circuits has become an important design consideration.

[0069] In conclusion, the key challenge facing chip technology development to date is how to design chips that balance high energy efficiency and high flexibility.

[0070] To address the aforementioned technical issues, existing technologies primarily focus on two categories: intermediate representations (IR) for hardware design and compiler frameworks that support hardware-software co-design.

[0071] 1) Traditional and domain-specific hardware design IR:

[0072] LLVM IR / MLIR: Primarily used for software compilation optimization and some high-level synthesis (HLS). This method excels at expressing the control flow and data flow of software, but cannot directly describe the physical topology, resource reuse, and configuration state of the hardware.

[0073] Architecture Description Diagram (ADG): Used to describe the hardware structure of a reconfigurable array (such as that used in the DSAGEN framework). It only describes the hardware and does not carry software mapping information; hardware modifications and software mapping evaluation are separate.

[0074] Hardware construction languages ​​(such as Chisel / FIRRTL) are used to generate register transfer language (RTL) code. They provide the ability to parameterize and compose hardware modules, but they also do not include software mapping semantics and usually require manual design.

[0075] Disadvantages: The above-mentioned IR can only characterize one aspect of the problem (pure software or pure hardware), and lacks the ability to model both in a unified way, which means that co-optimization must be achieved through external loop iteration, resulting in low efficiency.

[0076] 2) Compilers / frameworks that support hardware-software co-design:

[0077] DSAGEN, AURORA: Employs metaheuristic search (such as simulated annealing) to iteratively modify the hardware ADG based on the mapping results provided by the compiler and feedback from a fast analysis model. Its drawbacks include strong search randomness and decoupling of hardware modification from mapping.

[0078] REVAMP: This approach uses a systematic method, starting with a homogeneous baseline architecture and gradually introducing heterogeneity under the guidance of the compiler. Its drawback is that the final result heavily depends on the choice of the initial architecture, and the optimization process still follows a separate model of "modify the hardware first, then evaluate the mapping".

[0079] Disadvantages: These frameworks integrate compilers for random or greedy iterative processing, but they still use hardware design IR (such as ADG) internally.

[0080] To address the aforementioned technical problems, embodiments of the present invention provide a specific implementation of a compilation method. See also... Figure 1 The method specifically includes the following:

[0081] Step 100: Map the pre-determined operator nodes of the target application to the virtual processing unit;

[0082] Step 200: Generate a PE array based on the plurality of virtual processing units; wherein the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between the plurality of operator nodes;

[0083] Step 300: Generate the hardware description language code for the target application based on the PE array.

[0084] As described above, the compilation method proposed in this application includes: first, mapping predetermined operator nodes of a target application to virtual processing units; then, generating a PE array based on multiple virtual processing units; wherein the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between multiple operator nodes; finally, generating hardware description language code for the target application based on the PE array.

[0085] Compared with the prior art, this application, for the first time, integrates the mapping result of the target software's data flow graph on virtual reconfigurable hardware and the physical structural characteristics of the virtual hardware itself in the same abstraction layer, thereby providing a novel compiler intermediate representation form of Configurable Architecture IR (CAIR) and an energy-efficiency-oriented co-optimization compilation method based on CAIR.

[0086] The virtual processing element (PE) in step 100 is an abstract logical computing unit. It does not directly correspond to a physical CPU core, but is an execution environment created and managed by the software layer (such as the operating system, hypervisor, or runtime system). The main purpose is to abstract, divide, and reorganize limited physical computing resources (such as CPU cores, ALUs, etc.) to present more and more flexible computing units than the physical ones, thereby more efficiently supporting multitasking, parallel computing, and virtualization.

[0087] In step 200, the PE array records the following information: the operator node executed by each virtual processing unit and the clock cycle for executing the operator node, the data dependency between two (or more) operator nodes being mapped to the virtual interconnect between the two virtual processing units (communication information), and the set of hardware functional units that each virtual processing unit needs to support (hardware capability information).

[0088] For step 300, the PE array is instantiated, and the hardware description language code (SystemVerilog or Verilog HDL code) of the target reconfigurable array is generated through parameterized RTL module templates (such as parameterized PE, connector box, synchronizer).

[0089] In some embodiments of the present invention, see Figure 2 Step 300 includes:

[0090] Step 301: Generate a first constraint condition based on the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units;

[0091] Step 302: Generate a first intermediate representation of the target application based on the first constraint and the PE array;

[0092] Step 303: Generate a second constraint based on the number of registers required by the PE array;

[0093] Step 304: Generate a second intermediate representation of the target application based on the second constraint and the first intermediate representation;

[0094] Step 305: Generate the hardware description language code based on the second intermediate representation.

[0095] As shown in steps 302 and 305, this application performs two optimizations on the PE array using Configurable Architecture IR (CAIR). The first optimization corresponds to steps 301 and 302, and the second optimization corresponds to steps 303 and 304.

[0096] In steps 301 and 302, firstly, an integer programming model constrained by CAIR (e.g., Integer Linear Programming (ILP)) is constructed, the optimization objective of which is to minimize the total number of hardware functional units in all virtual processing units (PEs) (arithmetic and logic unit (ALU) specialization). Next, the actual number of physical interconnections required for multiple virtual processing units in the PE array is minimized (interconnect specialization).

[0097] Finally, by solving the integer programming model, the optimal hardware simplification scheme and the final mapping scheme were determined simultaneously while ensuring that all kernels could be correctly mapped, and the intermediate representation of the reconfigurable architecture after the first optimization was output.

[0098] In steps 303 and 304, based on the first optimization, hardware details are further instantiated and optimized. The optimizations in the second reconfigurable architecture intermediate representation include: the specific number of input ports and the source of input data for each virtual processing unit; the number and depth of registers (synchronizers) recording data synchronization and buffering, and their connection to the ALU input ports; and the final, specialized, and streamlined set of hardware functional units included in the ALU within each virtual processing unit.

[0099] The second intermediate representation is closer to the description of register-transfer level (RTL) and can be directly parameterized and exported as a hardware module.

[0100] In some embodiments of the present invention, the first intermediate representation includes: the structure of the PE array, the mapping relationship between the operator nodes and the virtual processing units, and the data dependency relationship between multiple virtual processing units; wherein, the data dependency relationship between the multiple virtual processing units is determined by the data dependency relationship between the multiple operator nodes.

[0101] In some embodiments of the present invention, the second intermediate representation includes: all hardware functional units, the port and source of the input data of the virtual processing unit, and the configuration of the registers.

[0102] In some embodiments of the present invention, step 301 specifically involves: optimizing the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units to a minimum value by pre-generating an integer programming model, thereby generating the first constraint condition.

[0103] Specifically, the first constraint is to minimize the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units through an integer programming model.

[0104] In some embodiments of the present invention, step 303 specifically involves: merging time-incompatible registers used in the first intermediate representation through a pre-generated graph coloring model to generate a second constraint.

[0105] The execution logic of the second constraint is to combine time-incompatible registers for multiple registers of each virtual processing unit using a graph coloring model, thereby further reducing the total number of registers.

[0106] Step 303, in its implementation, merges time-independent synchronizers to effectively reduce the number of registers and hardware complexity, thereby improving the energy efficiency and area efficiency of the resulting reconfigurable array. Specifically, step 303 includes the following steps:

[0107] First, the problem is modeled. In a processing element (PE), each ALU input port may correspond to a slack synchronizer for buffering data. If the time intervals of multiple synchronizers do not overlap, they can be merged into a single skew synchronizer, thereby reducing the number of registers.

[0108] Next, a conflict graph is constructed: each slack synchronizer corresponds to a node, and the node weight represents the depth of the synchronizer (i.e., the number of registers required). If the time intervals of two synchronizers overlap (i.e., there is a time conflict), an edge is established between them.

[0109] The graph coloring problem is formalized, with each color corresponding to a merged synchronizer. The coloring objective is to assign a color to each node such that there are no edges between nodes of the same color (i.e., no time conflicts). The goal is to minimize the sum of the weights of the nodes with the largest weights across all colors, which is equivalent to minimizing the total number of registers in the merged synchronizer.

[0110] Finally, the solution and optimization are performed using a graph coloring algorithm to obtain the optimal or near-optimal merging scheme. The merged scheme reduces the number of synchronizers and makes register usage more compact, thereby reducing area and power consumption.

[0111] In some embodiments of the present invention, see Figure 3 A compilation method, which also includes:

[0112] Step 400: Determine the operator nodes for the target application; then, see... Figure 4 Step 400 includes:

[0113] Step 401: Determine the data flow graph of the target application based on the execution logic of the target application;

[0114] The execution logic here refers to the steps, rules, and processes that an application follows to complete a specific function. This includes: the order of function calls, conditional statements and loops, calls to different components (such as databases, APIs, and microservices), and the processing, transformation, and transfer of data.

[0115] Step 402: Determine the operator node based on the data flow graph.

[0116] Understandably, processes and data storage / data sources in a data flow diagram are typically implemented as one or more operator nodes. The data flow in the data flow diagram then becomes the data channel between operators. Step 402, in its implementation, specifically involves: First, traversing each component of the data flow diagram to determine its corresponding operator implementation: For each "process," determining its data source and data destination, for example:

[0117] Data source (such as Kafka topic, database change log, file) -> Source operator;

[0118] Data destination (e.g., database, another Kafka topic, dashboard) -> Sink operator;

[0119] Next, operator fusion optimization can lead to inefficient execution by directly mapping each "process" to an independent operator (e.g., high network serialization / deserialization overhead). Therefore, it is necessary to evaluate whether to fuse multiple processes into a single operator node.

[0120] If two operators A and B are connected one-to-one, and B can process every record output by A immediately, then merging them into a single node can avoid network transmission overhead.

[0121] Conversely, when the edges connecting two operators involve operations such as KeyBy and rebalance(), the data needs to be shuffled across the network. In this case, the operators must be split across different nodes. Additionally, if one operator requires a lot of CPU and the other requires a lot of memory, separating them allows for independent scaling.

[0122] Next, define the parallelism of the operators, that is, specify the number of parallel instances for each operator node. This step needs to consider the following factors: operators that process large amounts of data require higher parallelism. Computationally intensive operators also require higher parallelism. Ensure that downstream operators can process the data generated upstream in a timely manner to avoid backpressure. Finally, configure the data exchange strategy, that is, determine how data is transferred between operators (arrows in the data flow diagram).

[0123] In some embodiments of the present invention, step 200 includes: first, determining the optimal number of different types of virtual processing units (such as virtual processing units with storage units and virtual processing units without storage units) in the PE array based on a pre-generated energy efficiency assessment model.

[0124] Next, on the initial PE array, an integer linear programming (ILP) model is used to schedule and map the operator nodes of each data flow graph (DFG) to specific virtual processing units and time periods, generating a first intermediate representation. The goal of this ILP is to minimize the time required for data transfer between multiple operator nodes, laying the foundation for reducing the number of registers in the future.

[0125] As described above, the compilation method proposed in this application includes: first, mapping predetermined operator nodes of a target application to virtual processing units; then, generating a PE array based on multiple virtual processing units; wherein the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between multiple operator nodes; finally, generating hardware description language code for the target application based on the PE array.

[0126] In summary, the compilation method provided in this application enables the decisions on "specialization" (simplifying virtual processing units and interconnecting them according to mapping requirements) and "reuse" (sharing hardware resources across cycles and kernels) of hardware resources to be jointly optimized in the same model as the software mapping scheme.

[0127] For further explanation of the plan, see Figure 5 The present invention also provides a specific implementation of the compilation method, which specifically includes the following contents.

[0128] The application scenarios of the compilation method provided in this application include: automatically generating customized accelerators for computationally intensive and energy-sensitive applications, such as edge AI inference (image recognition, speech processing), acceleration of specific data center loads (recommendation systems, financial analysis), digital signal processing (wireless communication, radar), and scientific computing (fluid dynamics, molecular dynamics simulation).

[0129] S1: Map the operator nodes to the virtual processing unit to generate the PE array.

[0130] The input is an intermediate representation of the computation graph of a set of target kernels, such as a DFG. Next, based on a pre-generated energy efficiency assessment model, the optimal number of different types of virtual processing units (e.g., virtual processing units with and without memory) in the PE array is determined. Finally, on the initial PE array, an integer linear programming (ILP) model is used to schedule and map the operator nodes of each DFG to specific virtual processing units and time periods, generating the first intermediate representation. The goal of this ILP is to minimize the time required for data transfer between multiple operator nodes, laying the foundation for subsequent reduction of register count.

[0131] S2: Generate the first intermediate representation of the target application based on the PE array.

[0132] First, given the PE array, an integer programming model constrained by CAIR is constructed. The optimization objective is to minimize the total number of hardware functional units in all virtual processing units and to minimize the actual number of physical interconnects required between multiple virtual processing units (interconnect specialization). Finally, by solving this model, the optimal hardware simplification scheme and the final mapping scheme are determined simultaneously, ensuring that all cores can be correctly mapped, and the optimized first intermediate representation is output.

[0133] The first intermediate representation includes the following information: the operator node executed by the virtual processing unit and the clock cycle for executing the operator node, the data dependency relationship between two (or more) operator nodes being mapped to the virtual interconnect between the two virtual processing units (communication information), and the set of hardware functional units that each virtual processing unit needs to support (hardware capability information).

[0134] The first intermediate representation is in the form of a graph structure or XML / text format in a specific language, with nodes labeled "(virtual PE, mapping operator)" and edges labeled "(virtual interconnect, mapping data dependency)".

[0135] S3: Generate a second intermediate representation of the target application based on the first intermediate representation.

[0136] Based on the optimized mapping information, the first intermediate representation is converted into a second intermediate representation that includes detailed register connections.

[0137] In addition, for each virtual processing unit's multiple registers, a graph coloring model is used to merge registers that do not conflict in usage time, thereby further reducing the total number of registers.

[0138] Building upon the first intermediate representation, the second intermediate representation further instantiates and optimizes the hardware details. The second intermediate representation includes the following information: the specific number of input ports for each virtual processing unit and the source of the input data; the number and depth of registers (synchronizers) recording data synchronization and buffering, and their connections to the ALU input ports; and the final, specialized, and streamlined set of hardware functional units contained within the ALU of each virtual processing unit.

[0139] The second intermediate representation is closer to the description of register-transfer level (RTL) and can be directly parameterized and exported as a hardware module.

[0140] S4: Generate hardware code based on the second intermediate representation.

[0141] The second intermediate representation is instantiated, and the SystemVerilog or Verilog HDL code of the target reconfigurable array is generated through parameterized RTL module templates (such as parameterized PE, connectors, and synchronizers).

[0142] It should be noted that the entire process from steps S1 to S4 is non-iterative, meaning that the process from inputting the software kernel to outputting the hardware description code involves a single optimization. In other words, this single-step optimization model replaces the traditional iterative "modify-compile-evaluate" cycle, directly generating a near-optimal hardware design and mapping scheme.

[0143] As described above, the compilation method proposed in this application includes: first, mapping predetermined operator nodes of a target application to virtual processing units; then, generating a PE array based on multiple virtual processing units; wherein the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between multiple operator nodes; finally, generating hardware description language code for the target application based on the PE array.

[0144] In summary, the compilation method proposed in this application, through receiving a software IR (such as a Graph IR extracted from C / PyTorch) and passing through a series of non-iterative optimization stages based on a mathematical programming model, directly outputs optimized hardware RTL code and kernel configuration information. Compared with the prior art, this application has the following beneficial effects:

[0145] High design quality: Hardware specialization and software mapping are optimized in synergy. Experiments show that compared with the existing mainstream DSE framework (REVAMP), this application improves energy efficiency by 37.6% and area efficiency by 48.6%.

[0146] High design efficiency: It avoids long iterations using compilers, significantly reduces the exploration space through CAIR and mathematical programming and directly leads to the optimal region, thus significantly shortening the design cycle.

[0147] High degree of automation: Provides end-to-end automatic generation capabilities from software description to hardware RTL and configuration.

[0148] Based on the same inventive concept, this application also provides a compilation apparatus that can be used to implement the methods described in the above embodiments, as shown in the following embodiments. Since the principle by which the compilation apparatus solves the problem is similar to that of the compilation method, the implementation of the compilation apparatus can refer to the implementation of the compilation method, and repeated details will not be elaborated further. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the system described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0149] Embodiments of the present invention provide a specific implementation of a compilation apparatus capable of implementing a compilation method, see below. Figure 6 A compilation device specifically includes the following:

[0150] The node mapping module 10 is used to map the operator nodes of the predetermined target application to the virtual processing unit;

[0151] PE array generation module 20 is used to generate a PE array based on the plurality of virtual processing units; wherein, the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between the plurality of operator nodes;

[0152] The hardware code generation module 30 is used to generate hardware description language code for the target application based on the PE array.

[0153] In one embodiment of the present invention, see Figure 7 The hardware code generation module 30 includes:

[0154] The first condition generation unit 30a is used to generate a first constraint condition based on the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units.

[0155] The first intermediate representation generation unit 30b is used to generate a first intermediate representation of the target application based on the first constraint condition and the PE array.

[0156] The second condition generation unit 30c is used to generate a second constraint condition based on the number of registers required by the PE array;

[0157] The second intermediate representation generation unit 30d is used to generate a second intermediate representation of the target application based on the second constraint condition and the first intermediate representation.

[0158] The hardware code generation unit 30e is used to generate the hardware description language code based on the second intermediate representation.

[0159] In one embodiment of the present invention, the first intermediate representation includes: the structure of the PE array, the mapping relationship between the operator nodes and the virtual processing units, and the data dependency relationship between multiple virtual processing units; wherein, the data dependency relationship between the multiple virtual processing units is determined by the data dependency relationship between the multiple operator nodes.

[0160] In one embodiment of the present invention, the second intermediate representation includes: all hardware functional units, the port and source of the input data of the virtual processing unit, and the configuration of the registers.

[0161] In one embodiment of the present invention, the first condition generation unit 30a includes:

[0162] The first condition generation sub-unit is used to optimize the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units to the minimum value through a pre-generated integer programming model, thereby generating the first constraint condition.

[0163] In one embodiment of the present invention, the second condition generation unit 30d includes:

[0164] The second condition generation subunit is used to merge time-incompatible registers used in the first intermediate representation through a pre-generated graph coloring model to generate the second constraint condition.

[0165] In one embodiment of the present invention, see Figure 8 A compilation device capable of implementing a compilation method further includes:

[0166] Operator node determination module 40 is used to determine the operator nodes of the target application; see also Figure 9 The operator node determination module 40 includes:

[0167] The data flow graph determination unit 40a is used to determine the data flow graph of the target application based on the execution logic of the target application.

[0168] Operator node determination unit 40b is used to determine the operator node based on the data flow graph.

[0169] The embodiments of this application also provide a specific implementation of an electronic device capable of implementing all the steps in the compilation method of the above embodiments, see [link to implementation details]. Figure 10 The electronic devices specifically include the following:

[0170] Processor 1201, memory 1202, communications interface 1203, and bus 1204;

[0171] The processor 1201, memory 1202, and communication interface 1203 communicate with each other via bus 1204; the communication interface 1203 is used to realize information transmission between server-side devices and client-side devices and other related devices.

[0172] The processor 1201 is used to call the computer program in the memory 1202. When the processor executes the computer program, it implements all the steps in the compilation method in the above embodiments. For example, when the processor executes the computer program, it implements the following steps:

[0173] Map the pre-determined target application's operator nodes to the virtual processing unit;

[0174] A PE array is generated based on the plurality of virtual processing units; wherein the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between the plurality of operator nodes;

[0175] The hardware description language code for the target application is generated based on the PE array.

[0176] Embodiments of this application also provide a computer-readable storage medium capable of implementing all steps of the compilation method in the above embodiments. The computer-readable storage medium stores a computer program that, when executed by a processor, implements all steps of the compilation method in the above embodiments. For example, when the processor executes the computer program, it implements the following steps:

[0177] Map the pre-determined target application's operator nodes to the virtual processing unit;

[0178] A PE array is generated based on the plurality of virtual processing units; wherein the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between the plurality of operator nodes;

[0179] The hardware description language code for the target application is generated based on the PE array.

[0180] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, hardware + program embodiments are relatively simple in description because they are fundamentally similar to method embodiments; relevant parts can be referred to the descriptions in the method embodiments.

[0181] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0182] While this application provides method operation steps as shown in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive labor. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual device or client product execution, the method can be executed in the order shown in the embodiments or drawings or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0183] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing the embodiments of this specification, the functions of each module can be implemented in one or more software and / or hardware components, or a module that performs the same function can be implemented by a combination of multiple sub-modules or sub-units. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0184] Those skilled in the art will also know that, besides implementing the controller using purely computer-readable program code, the same functions can be achieved by logically programming the method steps, making the controller function as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers (PLCs), and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the devices within it used to implement various functions can also be considered structures within that hardware component. Alternatively, the devices used to implement various functions can be considered as both software modules implementing the method and structures within a hardware component.

[0185] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0186] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0187] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, system embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments in this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0188] The above description is merely an embodiment of the present specification and is not intended to limit the embodiments of the present specification. For those skilled in the art, various modifications and variations can be made to the embodiments of the present specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the embodiments of the present specification should be included within the scope of the claims of the embodiments of the present specification.

Claims

1. A compilation method, characterized in that, include: Map the pre-determined target application's operator nodes to the virtual processing unit; A PE array is generated based on the plurality of virtual processing units; wherein the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between the plurality of operator nodes; The hardware description language code for the target application is generated based on the PE array.

2. The compilation method according to claim 1, characterized in that, Generating hardware description language code for the target application based on the PE array includes: The first constraint is generated based on the number of hardware functional units required by the PE array and the number of physical connection units between the multiple virtual processing units. A first intermediate representation of the target application is generated based on the first constraint and the PE array; A second constraint is generated based on the number of registers required by the PE array; Generate a second intermediate representation of the target application based on the second constraint and the first intermediate representation; The hardware description language code is generated based on the second intermediate representation.

3. The compilation method according to claim 2, characterized in that, The first intermediate representation includes: the structure of the PE array, the mapping relationship between the operator nodes and the virtual processing units, and the data dependency relationship between multiple virtual processing units; wherein, the data dependency relationship between the multiple virtual processing units is determined by the data dependency relationship between the multiple operator nodes.

4. The compilation method according to claim 2, characterized in that, The second intermediate representation includes: all hardware functional units, the ports and sources of input data for the virtual processing unit, and the configuration of registers.

5. The compilation method according to claim 2, characterized in that, A first constraint is generated based on the number of hardware functional units required by the PE array and the number of physical connection units between the multiple virtual processing units, including: The first constraint condition is generated by optimizing the number of hardware functional units required by the PE array and the number of physical connection units between multiple virtual processing units to a minimum value through a pre-generated integer programming model.

6. The compilation method according to claim 2, characterized in that, A second constraint is generated based on the number of registers required by the PE array, including: The second constraint is generated by merging time-incompatible registers used in the first intermediate representation using a pre-generated graph coloring model. The steps for determining the operator nodes of the target application include: The data flow graph of the target application is determined based on the execution logic of the target application; The operator node is determined based on the data flow graph.

7. A compiler apparatus, characterized in that, include: The node mapping module is used to map the operator nodes of the predetermined target application to the virtual processing unit; A PE array generation module is used to generate a PE array based on a plurality of virtual processing units; wherein, the PE array is used to characterize the operator nodes executed by the virtual processing units, the corresponding execution clock cycles, the hardware functional units supported by the virtual processing units, and the data dependencies between the plurality of operator nodes; The hardware code generation module is used to generate hardware description language code for the target application based on the PE array.

8. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the compilation method according to any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the compilation method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the compilation method according to any one of claims 1 to 6.

Images