RISC-V architecture-oriented matrix multiplication optimization method and system

Abstract

The invention discloses a matrix multiplication optimization method and system oriented to an RISC-V architecture, and the method comprises the steps: detecting the hardware characteristics of a target RISC-V platform, and adaptively configuring optimization parameters according to a detection result; performing memory layout and data rearrangement on the input matrix B to realize memory optimization; a multi-level partitioning strategy is adopted to adapt to a memory hierarchical structure, and multi-level partitioning calculation is achieved; carrying out RVV vectorization core calculation by using RISC-V vector instruction extension to realize data-level parallel optimization; the instruction delay is hidden through loop expansion and a software assembly line, and a data prefetching mechanism is adopted to realize instruction-level parallel optimization; performing multi-core parallel computing by using an OpenMP multi-thread technology to realize thread-level parallel optimization; and calculating residual elements by using a vector register to realize tail processing optimization. According to the method, the cache hit rate and the calculation performance degree are improved, the hardware potential is fully excavated, and the method is suitable for edge devices with high requirements.

Description

Technical Field

[0001] This invention belongs to the field of artificial intelligence and computer hardware and software co-optimization technology, specifically relating to an optimization method and system for matrix multiplication oriented towards RISC-V architecture. Background Technology

[0002] With the rapid development of fields such as artificial intelligence, big data analytics, and scientific computing, matrix multiplication, as the most fundamental and computationally intensive core algorithm, plays a crucial role in key applications such as deep learning inference, image processing, and signal analysis. Especially driven by the trends of edge computing and the intelligentization of IoT devices, an increasing number of intelligent applications require real-time execution of neural network inference and complex numerical calculations on resource-constrained embedded terminal devices.

[0003] The RISC-V (Reduced Instruction Set Computing – V) architecture, with its open-source, customizable, and low-power characteristics, is becoming the mainstream choice for edge intelligent chips. For example, in edge computing scenarios such as smart security, autonomous driving, and industrial IoT, terminal devices using RISC-V processors need to efficiently execute convolutional neural network calculations based on matrix multiplication to achieve intelligent functions such as face recognition, object detection, and voice wake-up.

[0004] However, due to the stringent limitations of edge devices in terms of computing power, memory bandwidth, and power consumption, deploying high-complexity matrix computation libraries designed for the cloud directly faces significant challenges. General Matrix to Matrix Multiplication (GEMM), as the most computationally intensive core operator in neural networks, directly determines the performance and energy efficiency of intelligent applications. Although the RISC-V instruction set provides Vector Extensions (RVV) to support data-parallel computation, the matrix multiplication implementations in existing general-purpose mathematical libraries fail to fully utilize their hardware potential, resulting in significant performance bottlenecks when performing large-scale matrix operations on the RISC-V platform. With the rapid adoption of the RISC-V ecosystem in edge AI, conducting in-depth optimization research on matrix multiplication for the RISC-V architecture is crucial for promoting the practical application of edge intelligence technologies.

[0005] The basic idea for matrix multiplication in RISC-V is as follows: For input matrices A and B, the high-dimensional matrix computation is first decomposed into computational blocks that can be processed in parallel. Then, a multi-level parallelization strategy is designed to perform efficient computation on the matrix blocks. Finally, the results of each computational block are summed to obtain the final output matrix. The optimization goal is to achieve the matrix multiplication implementation with the highest computational efficiency and numerical accuracy.

[0006] For example, Wang Yumu proposed a method to optimize matrix multiplication using the V (vector) instruction set of the RISC-V extended instruction set in the paper "Wang Yumu, Pan Zhiming, Wu Pengfei, et al. YOLOv3 Porting and Optimization of RISC-V Vector Instruction Set [J]. Microcontroller & Embedded System Applications, 2021, 21 (12): 20-25+30.", and adopted two methods: embedded handwritten assembly and inline assembly, and used the data address alignment method. Another example is Ren Ping, who proposed to optimize matrix multiplication through program performance analysis, vectorization, memory access optimization, loop unrolling, and other techniques in the paper "Ren Ping, Xu Xuezheng, Huang Anwen, et al. Optimization of Target Detection Algorithm for RISC-V Architecture [J]. Intelligent Security, 2024, 3(03): 21-33.".

[0007] However, when optimizing matrix multiplication for RISC-V architecture, most existing methods are directly ported from ARM or x86 platforms, ignoring the inherent characteristics of the RISC-V instruction set architecture and the potential for deep collaborative optimization in convolution computation. This results in the following limitations: 1. Neglecting the dynamic configuration capability of RISC-V vector registers, leading to low tail processing efficiency; 2. Not adapting to the memory hierarchy, resulting in insufficient cache hit rate; 3. Lacking multi-core collaborative optimization, failing to fully utilize hardware potential. Based on these issues, existing optimization methods for matrix multiplication in RISC-V architecture struggle to meet the low power consumption and high real-time performance requirements of edge devices. Summary of the Invention

[0008] To address the aforementioned problems in the existing technology, this invention provides an optimization method and system for matrix multiplication in RISC-V architecture. The technical problem to be solved by this invention is achieved through the following technical solution: Firstly, this invention proposes an optimization method for matrix multiplication in RISC-V architecture, comprising: The hardware characteristics of the target RISC-V platform are detected, and optimization parameters are adaptively configured based on the detection results; optimization parameters include block parameters and the number of OpenMP threads. Memory optimization is achieved by performing memory layout and data rearrangement on the input matrix B; Based on the block parameters and memory optimization results, a multi-level block strategy is adopted to adapt to the memory hierarchy and realize multi-level block computation. RVV vectorization core computation is performed using RISC-V vector instruction extensions to achieve data-level parallel optimization; Instruction-level parallel optimization is achieved by using loop unrolling and software pipeline to hide instruction latency, and by employing a data prefetching mechanism. Based on the number of OpenMP threads, OpenMP multithreading technology is used for multi-core parallel computing to achieve thread-level parallel optimization. The remaining elements are computed using a vector register to optimize tail processing.

[0009] Secondly, this invention proposes an optimized system for matrix multiplication in RISC-V architecture, comprising: The detection and configuration module is used to detect the hardware characteristics of the target RISC-V platform and adaptively configure optimization parameters based on the detection results; the optimization parameters include block parameters and the number of OpenMP threads. The memory optimization module is used to perform memory layout and data rearrangement on the input matrix B to achieve memory optimization. The multi-level block computation module is used to adapt to the memory hierarchy structure by adopting a multi-level block strategy based on block parameters and memory optimization results to achieve multi-level block computation. The data-level parallel optimization module is used to perform RVV vectorized core computation using RISC-V vector instruction extensions to achieve data-level parallel optimization. The instruction-level parallel optimization module is used to hide instruction latency through loop unrolling and software pipeline, and to achieve instruction-level parallel optimization by using a data prefetching mechanism. The thread-level parallel optimization module is used to perform multi-core parallel computing based on the number of OpenMP threads and using OpenMP multi-threading technology to achieve thread-level parallel optimization. The tail optimization module is used to perform calculations on the remaining elements using a vector register to optimize tail processing.

[0010] The beneficial effects of this invention are: 1. This invention proposes an optimization method for matrix multiplication in RISC-V architecture. First, hardware detection is performed, and parameters are adaptively configured. Then, based on dynamic parameter configuration, memory optimization, multi-level block computation, data-level parallel optimization, instruction-level parallel optimization, and thread-level parallel optimization are sequentially performed using a multi-level collaborative parallel optimization strategy. Compared with existing general-purpose matrix multiplication methods, this method achieves higher computational efficiency and energy efficiency. Finally, a tail-processing optimization method based on RISC-V vector instructions is adopted, fully utilizing the new features of RISC-V vector registers to further improve computational performance. This method improves cache hit rate and parallelism, fully exploits hardware potential, and is suitable for edge devices with low power consumption and high real-time requirements.

[0011] 2. This invention adopts a more memory-friendly matrix partitioning method. By adapting to the memory hierarchy through a three-level partitioning strategy, it reduces the number of memory accesses, lowers memory bandwidth pressure, and improves memory utilization.

[0012] 3. This invention proposes a multi-threaded technology based on OpenMP for multi-core processors that support vector extension. Compared with the original single-threaded mode, it can better utilize hardware platform resources, improve processing performance, and meet the needs of large-scale matrix operations.

[0013] 4. This invention employs a data prefetching method, which can load the data needed later into the cache in advance. Compared with existing methods, this significantly improves the cache hit rate, reduces data access latency, and thus improves the computational efficiency of matrix multiplication.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] Figure 1 A flowchart illustrating an optimization method for matrix multiplication in RISC-V architecture provided in an embodiment of the present invention; Figure 2 This is a block diagram of an optimized matrix multiplication system for RISC-V architecture provided in an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] The first aspect of this invention provides an optimization method for matrix multiplication in RISC-V architecture. Please refer to... Figure 1 , Figure 1 This is a flowchart illustrating an optimization method for matrix multiplication in a RISC-V architecture, provided as an embodiment of the present invention. The method mainly includes the following steps: Step 1: Detect the hardware characteristics of the target RISC-V platform and adaptively configure optimization parameters based on the detection results; optimization parameters include block parameters and the number of OpenMP threads.

[0018] It is understood that the method proposed in this invention requires a multi-core processor that supports vector extension. Therefore, it is necessary to first detect whether the platform's RISC-V chip supports vector extension, i.e., RISC-V Vector extension (RVV), and if the detection result indicates support, subsequent hardware feature detection and parameter optimization configuration are performed.

[0019] Specifically, the compiler can use the predefined macro __riscv_vector to check whether vector instruction set extensions are supported during the compilation phase.

[0020] Then, the hardware characteristics of the target RISC-V platform are dynamically detected, and adaptive configuration parameters are optimized. Step 1 mainly includes: 1a) Dynamically query the vector register length VLEN and determine the number of floating-point numbers that a single vector can process based on the vector register length VLEN.

[0021] Specifically, based on the characteristic that single-precision floating-point numbers occupy 32 bits, the number of floating-point numbers that a single vector can process is calculated as vector_capacity = VLEN / 32. For example, if the vector register length VLEN is 256 bits, then vector_capacity is 8, meaning that a single vector can process 8 single-precision floating-point numbers.

[0022] 1b) Dynamically detect the size of the RISC-V core cache (L1 / L2) and determine the block parameters based on the size of the RISC-V core cache.

[0023] In this embodiment, the detection of the RISC-V core cache size is mainly used to guide multi-level block partitioning strategies (such as L1 / L2 cache capacity determining block size), and is generally implemented through hardware manuals, device trees, or special registers.

[0024] The core count result is directly used for subsequent block partitioning strategies. The block partitioning parameter (BLOCK_SIZE) can be dynamically adjusted based on the core count and cache size to optimize memory access.

[0025] In this embodiment, the block parameters are calculated using the formula BLOCK_SIZE = sqrt(L1_CACHE_SIZE / 3 / sizeof(float)). Here, BLOCK_SIZE is the block size, sqrt() represents the square root function, L1_CACHE_SIZE represents the size of the L1 cache, and sizeof(float) represents a single-precision floating-point number.

[0026] For example, if L1_CACHE_SIZE is 32KB and sizeof(float) is 4 bytes, then BLOCK_SIZE ≈ 51, meaning that the size of each block is approximately 51 × 51 single-precision floating-point numbers.

[0027] 1c) Dynamically detect the number of CPU cores and configure the number of OpenMP threads based on the number of CPU cores.

[0028] Core count detection is a computer system optimization technique that involves dynamically identifying the number of available computing cores in a processor using software or hardware methods. In parallel computing, the number of cores directly determines the degree of parallelism in task partitioning and is a key parameter for resource scheduling and efficiency improvement. By detecting the number of cores, the system can be helped to allocate threads rationally, avoiding resource idleness or contention.

[0029] Generally speaking, the number of cores can be obtained directly through the operating system interface or programming interface.

[0030] In the multi-core RISC-V chip of this invention, the core count detection result is directly used for subsequent OpenMP multi-threaded startup. The number of OpenMP threads can be dynamically set according to the core count, while providing a foundation for subsequent RVV vectorization and OpenMP multi-threaded computation, forming a multi-layered parallel system.

[0031] In this embodiment, the `omp_set_num_threads(nums_cores)` function is used to set the number of OpenMP threads, where `nums_cores` is the number of detected CPU cores. For example, if 4 CPU cores are detected, the number of threads is set to 4 to enable subsequent multi-threaded parallel computing.

[0032] Step 2: Perform memory layout and data rearrangement on the input matrix B to achieve memory optimization.

[0033] Memory layout and data rearrangement are key steps in optimizing matrix multiplication in the RISC-V architecture in this embodiment. They mainly improve cache utilization and vector loading efficiency by adjusting the storage and access patterns of data in memory.

[0034] First, the input matrix B is transposed to change column-major access to row-major access, thus completing the memory layout.

[0035] Specifically, since the data in the input matrix B is usually accessed row by row during matrix multiplication, this embodiment converts the original column-first storage method to row-first storage method by transposing matrix B. This can improve the locality of data access and reduce the cache miss rate.

[0036] In addition, the transpose operation can make the data blocks accessed by each thread independent in subsequent multi-threaded operations, reduce memory contention between multi-cores, and support OpenMP thread-safe parallelism.

[0037] Then, using a memory alignment allocation mechanism, the data addresses are aligned according to the vector length to complete the data rearrangement.

[0038] Specifically, a memory alignment allocation function is used to allocate memory for matrix data, ensuring that the starting address of the matrix data is aligned according to the alignment method required by the vector loading instruction, thereby improving vector loading efficiency and reducing memory access latency.

[0039] Furthermore, a contiguous and aligned memory layout enables efficient loading and computation of RVV instructions, improving parallelism.

[0040] Step 3: Based on the block parameters and memory optimization results, a multi-level block strategy is adopted to adapt to the memory hierarchy and realize multi-level block computation.

[0041] In matrix multiplication, directly processing large matrices leads to frequent main memory accesses, causing cache thrashing and memory bandwidth bottlenecks. This problem is particularly pronounced in resource-constrained RISC-V edge devices. Therefore, large matrix computations can be decomposed into data blocks of varying granularity, adapting to the processor's memory hierarchy, to reduce memory access latency, improve cache hit rate, and enhance parallel computing efficiency.

[0042] Specifically, this embodiment adopts a three-level block strategy to adapt to the memory hierarchy for multi-level block calculation; the three-level block strategy includes outer block, middle block and inner block.

[0043] First, for the outer layer partitioning, the output matrix C is divided into MB×NB macroblocks to adapt to the L3 cache. MB and NB represent the partition size, where MB is the number of row blocks and NB is the number of column blocks. Their values ​​are determined by the size of the L3 cache. If the L3 cache is large, the macroblocks can be divided into larger blocks to reduce the data exchange overhead between macroblocks; if the L3 cache is small, the macroblocks can be divided into smaller blocks to ensure that the data of each macroblock can be accommodated in the L3 cache as much as possible. For the specific calculation formula, please refer to step 1c).

[0044] For example, if the L3 cache is 4MB and the value is a single-precision floating-point number (4 bytes), then MB ≈ NB ≈ sqrt(4MB / 3 / 4B) ≈ 584, which means the macroblock size is approximately 584×584.

[0045] The data required for computation within a macroblock (corresponding blocks of input matrix A and input matrix B) are loaded into the L3 cache at once to avoid repeated access to main memory.

[0046] Secondly, for the intermediate-level blocks, each macroblock is divided into IB×KB blocks to adapt to the L2 cache; IB and KB represent the partition size, with IB being the number of row blocks and KB being the number of column blocks; their values ​​are determined by the L2 cache size, and the calculation formula is similar to that for the outer-level blocks. Similarly, the block size is adjusted reasonably according to the L2 cache capacity, so that the data in each intermediate-level block can be processed efficiently in the L2 cache, reducing the number of accesses to main memory.

[0047] By residing sub-block data (such as rows IB of input matrix A and columns KB of input matrix B) in the L2 cache, it can be reused for inner-layer computations. Furthermore, during the computation of the current sub-block, subsequent sub-block data is prefetched, hiding memory latency.

[0048] In addition, the middle layer block division provides a continuous data source for the inner layer vectorized computation, avoiding frequent swapping in and out of the L1 cache.

[0049] Finally, for inner-level partitioning, register-level partitioning is performed within the cache block, using the RVV vector register to process 32 elements.

[0050] Specifically, the data within the cache block is further divided into smaller blocks suitable for processing by the vector register, which are then directly processed by the RVV vector register. Each time, a small block of data can be loaded from the cache into the vector register for computation, fully utilizing the parallel computing capability of the vector register. The number of elements processed in a single operation is determined by the vector register length VLEN (see step 1b for the formula). For example, when VLEN = 128 bits, vector_capacity = 4, meaning that one vector instruction processes 4 floating-point numbers.

[0051] This invention employs a more memory-friendly matrix partitioning method. By adapting to the memory hierarchy through a three-level partitioning strategy, the matrix data is transposed and aligned, and then refined level by level according to "macroblock → cache block → register block". This ensures that each level of data block is adapted to the corresponding storage level, reduces the number of memory accesses, reduces memory bandwidth pressure, and improves memory utilization.

[0052] Step 4: Use RISC-V vector instruction extensions to perform RVV vectorized core computation to achieve data-level parallel optimization.

[0053] In this embodiment, the RVV vectorization core computation is mainly implemented through the following four sub-steps 4a)-4d), ensuring optimization of the entire process from data loading to result storage.

[0054] 4a) Setting up vector configuration Specifically, this embodiment uses assembly instructions to dynamically determine the vector length and complete the vector configuration.

[0055] For example, the assembly instruction `vsetvli vl, remainder, e32, m4, ta, ma` can be used to dynamically determine the vector length. Here, `vl` represents the vector length, `remainder` represents the number of remaining elements, `e32` indicates that the element type is 32-bit single-precision floating-point, `m4` indicates the use of four vector register sets, and `ta` and `ma` represent the mantissa processing mode. This instruction allows for dynamic adjustment of the vector length to accommodate calculations of matrix blocks of different sizes.

[0056] 4b) Vector Loading Specifically, in this embodiment, a load instruction is used to load matrix block data in batches from memory into a vector register.

[0057] For example, the vle64.v instruction can be used to load matrix blocks of data into vector registers in batches. For instance, to load eight single-precision floating-point numbers into a vector register, the vle64.v instruction can be used to read 64 bits (8×8 bits) of data from memory into the vector register at once, improving data loading efficiency.

[0058] 4c) Vector multiplication and addition Specifically, in this embodiment, the multiply-accumulate instruction is used to perform vector fusion multiply-accumulate operations to obtain the calculation result.

[0059] For example, the `vfmacc.vv` instruction can be used to perform fused multiplication and addition operations. This instruction can perform vector multiplication and addition operations simultaneously, reducing the number of instructions and computation cycles, and improving computational efficiency. For instance, to perform multiplication and addition operations on data in two vector registers, the `vfmacc.vv` instruction can complete the multiplication and addition operations on all elements at once and store the result in the specified vector register.

[0060] 4d) Vector storage Specifically, in this embodiment, a storage instruction is used to write the calculation result back to memory, thus completing the output of the calculation block.

[0061] For example, the vse64.v instruction can be used to write the calculation results back to memory. Similar to vector loading, the vse64.v instruction can write 64 bits of data from the vector register back to memory at once, improving data storage efficiency.

[0062] This embodiment uses RISC-V vector instruction extensions for RVV vectorized core computation. Through four refined steps—configuration, loading, multiplication-accumulation, and storage—it fully leverages the vector instruction parallelism potential of the RISC-V architecture. Furthermore, as the core of the hybrid parallel architecture, RVV vectorized core computation synergizes with technologies such as block partitioning and multithreading, ensuring low-latency and high-precision matrix multiplication in edge computing scenarios, providing fundamental support for applications such as AI inference.

[0063] Step 5: Implement instruction-level parallel optimization by hiding instruction delays through loop unrolling and software pipeline, and by adopting a data prefetching mechanism.

[0064] Specifically, step 5 can be achieved through the following three sub-steps 5a)-5c).

[0065] 5a) Cyclic expansion Specifically, by unrolling the memory loop multiple times, loop control overhead is reduced, increasing the opportunity for instruction-level parallelism.

[0066] For example, the original loop required multiple checks of the loop condition and control of the loop variable. Expanding the memory loop four times can combine the operations of multiple loops into one, reducing the number of loop checks and variable controls, thereby improving computational efficiency.

[0067] 5b) Software Pipeline Specifically, interleaving dependent instructions, such as data loading, computation, and storage instructions, forms a pipeline that hides execution latency.

[0068] By rationally arranging the execution order of instructions, load, compute, and store instructions can be executed overlappingly in the pipeline, reducing instruction execution wait time and improving instruction execution efficiency. For example, after executing a load instruction, subsequent compute instructions can begin execution without waiting for the load operation to complete, while simultaneously scheduling the next load instruction, enabling the pipeline to run continuously and efficiently.

[0069] 5c) Data prefetching Specifically, data prefetch instructions, such as the prefetch instruction, can be used to load the data needed for subsequent calculations from main memory into the cache in advance, reducing cache miss latency during calculations.

[0070] This invention employs a data prefetching method, which can load the data needed later into the cache in advance. Compared with existing methods, this significantly improves the cache hit rate, reduces data access latency, and thus improves the computational efficiency of matrix multiplication.

[0071] Step 6: Based on the number of OpenMP threads, use OpenMP multithreading technology to perform multi-core parallel computing and achieve thread-level parallel optimization.

[0072] Specifically, in step 1c), the number of CPU cores has been dynamically identified and the number of parallel threads has been configured accordingly. Here, based on the number of OpenMP threads, the compiler's preprocessing directives need to be added before the main loop, such as #pragmaomp parallel for num_threads(num_cores), which can automatically parallelize the multi-level block computation of matrix multiplication.

[0073] This invention proposes a multi-threaded technology based on OpenMP for multi-core processors that support vector extension. Compared with the original single-threaded mode, it can better utilize hardware platform resources, improve processing performance, and meet the needs of large-scale matrix operations.

[0074] Step 7: Calculate the remaining elements using a vector register to optimize tail processing.

[0075] Specifically, tail processing is mainly achieved through two sub-steps: main vector looping and remaining element processing.

[0076] First, the main vector is dynamically determined to process the data in a loop based on the number of floating-point numbers that a single vector can handle, and then the main vector loop processing is performed.

[0077] The main vector loop processes N-(N%vector_capacity) data points.

[0078] Then, the RVV property is used to perform vectorized calculations on the remaining elements, and the actual number of elements processed is dynamically adjusted.

[0079] Specifically, when using the RVV property to perform vectorized calculations on the remaining elements, the actual number of elements processed is calculated as: N % vector_capacity; where N represents the matrix dimension and vector_capacity represents the number of floating-point numbers that a single vector can process.

[0080] This completes the optimization of matrix multiplication for the RISC-V architecture.

[0081] This invention proposes an optimization method for matrix multiplication in RISC-V architecture. First, hardware detection and adaptive parameter configuration are performed. Then, based on dynamic parameter configuration, memory optimization, multi-level block computation, data-level parallel optimization, instruction-level parallel optimization, and thread-level parallel optimization are sequentially implemented through a multi-level collaborative parallel optimization strategy. Compared to existing general-purpose matrix multiplication methods, this method achieves higher computational efficiency and energy efficiency. Finally, a tail-processing optimization method based on RISC-V vector instructions is adopted, fully utilizing the new features of RISC-V vector registers to further improve computational performance. This method improves cache hit rate and parallelism, fully exploits hardware potential, and is suitable for edge devices with low power consumption and high real-time requirements.

[0082] The beneficial effects of the present invention can be further verified and illustrated by the following simulation experiments.

[0083] 1. Experimental conditions This test was conducted on the CanMV-K230 development board. The board's processor has two cores: a large core running at 1 GHz with 32kB of L1 cache and 256kB of L2 cache, supporting RVV version 1.0, and featuring 32 128-bit vector registers; and a small core running at 800MHz, without RVV support. The board is equipped with 512MB of DDR3 memory to meet data processing and storage requirements. The operating system is a K230 Debian Ubuntu system image, based on Ubuntu 23.10, burned to an SD card to boot the development board. The system image uses the riscv64-linux-gnu gcc compiler, version 13.1.0, with O2 optimization options enabled.

[0084] 2. Experiment Content The method proposed in this invention is compared with existing methods, and the existing comparison methods are as follows: Darknet, an open-source neural network framework, implements the GEMM algorithm using the gemm_nn function, which performs matrix multiplication of two untransposed matrices.

[0085] According to a specific embodiment of the present invention, the time consumption of gemm_nn is used as a benchmark for normalization processing, and performance comparison is performed. The results are shown in Table 1.

[0086] Table 1 Efficiency Comparison of GEMM Algorithms

[0087] As shown in Table 1, the optimization method employed in this invention fully leverages the hardware performance of the RISC-V platform, resulting in a significant improvement in algorithm efficiency compared to existing methods. This verifies the advanced nature of this invention.

[0088] Based on the same inventive concept, a second aspect of this invention also provides an optimized system for matrix multiplication in RISC-V architecture. Please see [link to relevant documentation]. Figure 2 , Figure 2 This invention provides a structural block diagram of an optimized matrix multiplication system for RISC-V architecture, which mainly includes the following modules: The detection and configuration module is used to detect the hardware characteristics of the target RISC-V platform and adaptively configure optimization parameters based on the detection results; the optimization parameters include block parameters and the number of OpenMP threads. The memory optimization module is used to perform memory layout and data rearrangement on the input matrix B to achieve memory optimization. The multi-level block computation module is used to adapt to the memory hierarchy structure by adopting a multi-level block strategy based on block parameters and memory optimization results to achieve multi-level block computation. The data-level parallel optimization module is used to perform RVV vectorized core computation using RISC-V vector instruction extensions to achieve data-level parallel optimization. The instruction-level parallel optimization module is used to hide instruction latency through loop unrolling and software pipeline, and to achieve instruction-level parallel optimization by using a data prefetching mechanism. The thread-level parallel optimization module is used to perform multi-core parallel computing based on the number of OpenMP threads and using OpenMP multi-threading technology to achieve thread-level parallel optimization. The tail optimization module is used to perform calculations on the remaining elements using a vector register to optimize tail processing.

[0089] The present invention provides an optimization system for matrix multiplication in RISC-V architecture, which can be used to implement the above-mentioned optimization method. Since it is fundamentally similar to the method embodiment, the description is relatively simple; relevant details can be found in the description of the method embodiment. Therefore, this system also has the same beneficial effects as the method embodiment.

[0090] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An optimization method for matrix multiplication in RISC-V architecture, characterized in that, include: The hardware characteristics of the target RISC-V platform are detected, and the parameters are adaptively configured and optimized based on the detection results. The optimization parameters include block parameters and the number of OpenMP threads; Memory optimization is achieved by performing memory layout and data rearrangement on the input matrix B; Based on the block parameters and memory optimization results, a multi-level block strategy is adopted to adapt to the memory hierarchy and realize multi-level block computation. RVV vectorization core computation is performed using RISC-V vector instruction extensions to achieve data-level parallel optimization; Instruction-level parallel optimization is achieved by using loop unrolling and software pipeline to hide instruction latency, and by employing a data prefetching mechanism. Based on the number of OpenMP threads, multi-core parallel computing is performed using OpenMP multi-threading technology to achieve thread-level parallel optimization. The remaining elements are computed using a vector register to optimize tail processing.

2. The optimization method for matrix multiplication in RISC-V architecture according to claim 1, characterized in that, The detection targets the hardware characteristics of the RISC-V platform and adaptively configures and optimizes parameters based on the detection results, including: The vector register length VLEN is dynamically queried, and the number of floating-point numbers that a single vector can process is determined based on the vector register length VLEN; The size of the RISC-V core cache is dynamically detected, and the block parameters are determined based on the size of the RISC-V core cache. The number of CPU cores is dynamically detected, and the number of OpenMP threads is configured according to the number of CPU cores.

3. The optimization method for matrix multiplication in RISC-V architecture according to claim 1, characterized in that, The memory layout and data rearrangement of the input matrix B to achieve memory optimization includes: Transpose the input matrix B to convert column-major access to row-major access; The memory alignment allocation mechanism is used to align data addresses according to the vector length, thereby completing the data rearrangement.

4. The optimization method for matrix multiplication in RISC-V architecture according to claim 1, characterized in that, Based on the block parameters and memory optimization results, a multi-level block strategy is adopted to adapt to the memory hierarchy, realizing multi-level block computation, including: A three-level block partitioning strategy is adopted to adapt to the memory hierarchy for multi-level block computation; the three-level block partitioning strategy includes outer-level block partitioning, middle-level block partitioning, and inner-level block partitioning; wherein, For outer layer partitioning, the output matrix C is divided into MB×NB macroblocks to adapt to L3 cache; MB is the number of row blocks and NB is the number of column blocks; For mid-level segmentation, each macroblock is divided into IB×KB blocks to adapt to the L2 cache; IB is the number of row blocks and KB is the number of column blocks. For inner-level partitioning, register-level partitioning is performed within the cache block, using the RVV vector register to process 32 elements.

5. The optimization method for matrix multiplication in RISC-V architecture according to claim 1, characterized in that, The use of RISC-V vector instruction extensions for RVV vectorization core computation, achieving data-level parallel optimization, includes: The vector length is dynamically determined using assembly instructions to complete the vector configuration. Use load instructions to load matrix block data in batches from memory into vector registers; Use the multiply-accumulate instruction to perform vector fusion multiply-accumulate operations and obtain the calculation result; Use the store instruction to write the calculation result back to memory, and complete the output of the calculation block.

6. The optimization method for matrix multiplication in RISC-V architecture according to claim 1, characterized in that, The aforementioned instruction-level parallel optimization, achieved through loop unrolling and software pipeline hiding of instruction latency, and the use of a data prefetching mechanism, includes: Unroll the memory loop multiple times to reduce loop control overhead; By interleaving data loading, computation, and storage instructions, a pipeline is formed, hiding execution latency; Use data prefetching instructions to load the data needed for subsequent calculations from main memory into the cache in advance.

7. The optimization method for matrix multiplication in RISC-V architecture according to claim 1, characterized in that, Based on the aforementioned number of OpenMP threads, multi-core parallel computing is performed using OpenMP multi-threading technology to achieve thread-level parallel optimization, including: Based on the number of OpenMP threads, compiler preprocessing instructions are added before the main loop to automatically parallelize the multi-level block computation of matrix multiplication.

8. The optimization method for matrix multiplication in RISC-V architecture according to claim 2, characterized in that, The step of using a vector register to calculate the remaining elements to optimize tail processing includes: The main vector is dynamically determined to process the data in a loop based on the number of floating-point numbers that a single vector can handle. The remaining elements are vectorized using the RVV property, and the actual number of elements processed is dynamically adjusted.

9. An optimization method for matrix multiplication in RISC-V architecture according to claim 8, characterized in that, When using the RVV property to perform vectorized calculations on the remaining elements, the actual number of elements processed is calculated as: N %vector_capacity; where N represents the matrix dimension and vector_capacity represents the number of floating-point numbers that a single vector can process.

10. An optimized system for matrix multiplication in RISC-V architecture, used to implement the method described in any one of claims 1-9, characterized in that, The system includes: The detection and configuration module is used to detect the hardware characteristics of the target RISC-V platform and adaptively configure optimization parameters based on the detection results; the optimization parameters include block parameters and the number of OpenMP threads. The memory optimization module is used to perform memory layout and data rearrangement on the input matrix B to achieve memory optimization. A multi-level block calculation module is used to adapt the memory hierarchy structure by adopting a multi-level block strategy based on the block parameters and memory optimization results to realize multi-level block calculation. The data-level parallel optimization module is used to perform RVV vectorized core computation using RISC-V vector instruction extensions to achieve data-level parallel optimization. The instruction-level parallel optimization module is used to hide instruction latency through loop unrolling and software pipeline, and to achieve instruction-level parallel optimization by using a data prefetching mechanism. The thread-level parallel optimization module is used to perform multi-core parallel computing using OpenMP multi-threading technology based on the number of OpenMP threads, thereby achieving thread-level parallel optimization. The tail optimization module is used to perform calculations on the remaining elements using a vector register to optimize tail processing.

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