Memory device and method for programming

Abstract

A memory device and a method for programming are provided. The memory device may include a plurality of non-volatile memories and a memory controller electrically connected to the plurality of non-volatile memories through a plurality of channels and a plurality of lanes. A plurality of pathways may be included in a group of pathways. The memory controller may be configured to pre-program the input data into the plurality of non-volatile memories through the plurality of lanes, and reprogram the input data into the plurality of non-volatile memories through different ones of the lane groups during periods that do not overlap each other after the pre-programming is completed.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0156184, filed with the Korean Intellectual Property Office on November 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments relate to storage devices and methods for programming. Background Technology

[0004] Storage devices store data under the control of host devices such as computers, smartphones, or tablets. Most storage devices are powered by an external power source. However, storage devices are vulnerable to damage, including data loss, due to external power failures or power outages such as sudden power-offs (SPO).

[0005] To address the aforementioned power-related issues, auxiliary power equipment can be included within storage devices to support data backup (or dumping). However, the power supply used for data backup may depend on the capacity of the auxiliary power equipment. Therefore, it is beneficial to reduce reliance on the capacity of auxiliary power equipment and improve data reliability by reducing the amount of data backed up during power outages. Summary of the Invention

[0006] Example embodiments provide a storage device and a method for programming that can reduce the amount of data backup during a sudden power outage (SPO) event.

[0007] According to some example embodiments, a storage device may include a plurality of non-volatile memories and a storage controller electrically connected to the plurality of non-volatile memories via a plurality of channels and a plurality of ways. The plurality of ways may be included in a group of ways. The storage controller may be configured to preprogram input data into the plurality of non-volatile memories via the plurality of ways, and, after preprogramming is complete, reprogram the input data into the plurality of non-volatile memories via different groups of ways within the group of ways during non-overlapping time periods.

[0008] According to some example embodiments, a method of operating a storage device may include preprogramming input data into multiple non-volatile memories through multiple channels and multiple paths, wherein the multiple paths are included in a path group, and after preprogramming is completed, reprogramming the input data into the multiple non-volatile memories through different path groups in the path group during non-overlapping time periods.

[0009] According to some example embodiments, a storage device may include a plurality of non-volatile memories and a storage controller electrically connected to the plurality of non-volatile memories via a plurality of channels and a plurality of paths. The storage controller may be configured to preprogram input data into the plurality of non-volatile memories via the plurality of paths during a time period, and to reprogram the input data into at least one of the plurality of non-volatile memories via a path in the plurality of paths, wherein the number of the paths is less than a predetermined threshold value. Attached Figure Description

[0010] Figure 1 This is a block diagram of a storage device according to an example embodiment.

[0011] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of an example storage controller.

[0012] Figure 3 This illustrates an example embodiment. Figure 1 A block diagram of an example of non-volatile memory.

[0013] Figure 4 This illustrates an example embodiment. Figure 1 A circuit diagram of an example memory block within a memory cell array.

[0014] Figure 5 This is a diagram illustrating the data state based on pre-programmed operations and reprogrammed operations according to an example embodiment.

[0015] Figure 6 and Figure 7 This is a timing diagram illustrating backup operations during a sudden power outage (SPO) event according to an example embodiment.

[0016] Figure 8 and Figure 9 This is a timing diagram illustrating the scheduling of a reprogramming method according to an example embodiment.

[0017] Figure 10 This is a flowchart illustrating a method of operating a storage device according to an example embodiment.

[0018] Figure 11 This is a flowchart illustrating a backup operation of a storage device according to an example embodiment.

[0019] Figure 12 This is a flowchart illustrating a programming scheduling method for a storage device according to an example embodiment.

[0020] Figure 13 This is a block diagram of a storage device according to an example embodiment. Detailed Implementation

[0021] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0022] Figure 1 This is a block diagram of a storage device according to an example embodiment.

[0023] refer to Figure 1 The storage device 100 according to the example embodiment may include a storage controller 110, a plurality of non-volatile memories 120 and a buffer memory 130.

[0024] The storage controller 110 can be configured to control multiple non-volatile memories 120 and buffer memories 130 in response to commands from or under the control of a host. For example, the storage controller 110 can write data to or read data stored in the multiple non-volatile memories 120 in response to a request from the host.

[0025] The storage controller 110 can be connected to multiple non-volatile memories 120 via multiple channels CH1 to Chi and multiple paths to access the multiple non-volatile memories 120. For example, the multiple channels CH1 to CHi can include i channels. The multiple paths can be connected to the multiple channels CH1 to CHi respectively. In addition, j paths can be provided for each channel, where i and j are the same or different positive integers. For example, multiple paths W11 to W1j can be connected to the first channel CH1, and multiple paths Wi1 to Wij can be connected to the i-th channel CHi.

[0026] A single non-volatile memory can be connected to each of multiple paths. For example, non-volatile memory NVM11 can be connected to path W11, and non-volatile memory NVMij can be connected to path Wij.

[0027] The storage controller 110 can send signals to and receive signals from multiple non-volatile memories 120 via multiple channels CH1 to CHi. For example, the storage controller 110 can send commands, addresses, and data to multiple non-volatile memories 120 via multiple channels CH1 to CHi, or receive data read from multiple non-volatile memories 120 via multiple channels CH1 to CHi.

[0028] The memory controller 110 can send signals to and receive signals from multiple non-volatile memories 120 in parallel through different channels. Furthermore, the memory controller 110 can control each of the multiple non-volatile memories 120 connected to multiple channels CH1 to CHi. For example, the memory controller 110 can send commands and addresses through a single channel and select and control a single non-volatile memory.

[0029] Each of the plurality of non-volatile memories 120 can be connected to one of the plurality of channels CH1 to CHi via a corresponding path. For example, non-volatile memories NVM11 to NVM1j can be connected to the first channel CH1 via paths W11 to W1j, and non-volatile memories NVMi1 to NVMij can be connected to the i-th channel CHi via paths Wi1 to Wij. For example, each of the plurality of non-volatile memories 120 can be implemented as any memory cell capable of operating in response to a separate command from the memory controller 110. For example, each of the plurality of non-volatile memories 120 can be implemented as a chip or a die, but the example embodiment is not limited thereto.

[0030] Buffer memory 130 can be a data buffer for data exchange between storage device 100 and a host connected to storage device 100. Buffer memory 130 can buffer (e.g., temporarily store) data written from the host (i.e., input data) or data read from multiple non-volatile memories 120.

[0031] Upon a write request from the host, buffer memory 130 can buffer write data to be stored (e.g., programmed) in multiple non-volatile memories 120. As another example, upon a read request from the host, when data existing in multiple non-volatile memories 120 is cached, buffer memory 130 can support caching functionality that directly provides the cached data to the host.

[0032] For example, buffer memory 130 can be a volatile memory such as DRAM or SRAM, and can be implemented as synchronous DRAM to provide sufficient buffering performance.

[0033] An example of storage controller 110 will be described in more detail below.

[0034] In an example embodiment, the memory controller 110 may manage or control programming operations on multi-bit cells included in each of a plurality of non-volatile memories 120. For example, a multi-bit cell may include a single-level cell (SLC), a multilevel cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC), and may also include cells that can store more bits than a QLC in a single cell.

[0035] In an example embodiment, the storage controller 110 can program write data, which is multi-bit data, into the non-volatile memory using a reprogramming method. The reprogramming method can be a method of programming the same data N times, where N is a positive integer. For example, N can be a predetermined value.

[0036] The storage controller 110 may store data in the buffer memory 130 before executing the reprogramming method, and retain the data stored in the buffer memory 130 until the reprogramming method is completed (e.g., after N programming operations).

[0037] The reprogramming method can be performed through preprogramming operations and reprogramming operations. Preprogramming and / or reprogramming operations can be performed once or multiple times. The total number of preprogramming and reprogramming operations performed can be a total of N times. The storage controller 110 can preprogram the write data (i.e., input data) into multiple non-volatile memories 120. After the preprogramming operation is completed, the storage controller 110 can reprogram the write data (i.e., input data) into the multiple non-volatile memories 120.

[0038] In an example embodiment, state group data (or summary data) indicating state information of the pre-programmed data can be generated during (or after) the pre-programming operation. State group data can be generated during or after the pre-programming operation.

[0039] When generating state group data, the storage controller 110 according to the example embodiment can back up (or dump) the state group data in the event of a power failure, such as a sudden power outage (SPO) event, that occurs during the period after the pre-programming operation is completed and before the reprogramming operation is performed. The storage controller 110 can recover written data based on the backed-up state group data and can perform a reprogramming operation based on the recovered data. However, when an SPO event occurs during the reprogramming operation, errors may occur in the pre-programmed word lines due to the SPO event. Therefore, errors occurring in the pre-programmed word lines may make data recovery difficult using the state group data.

[0040] According to an example embodiment, the storage controller 110 can limit the number of paths used for reprogramming operations in any given time period. For example, the storage controller 110 can reprogram written data into multiple non-volatile memories 120 using fewer than a predetermined threshold number of paths in any given time period. For example, the predetermined threshold can be less than or equal to the total number of paths. The storage controller 110 can set a threshold to limit the number. In other words, the storage controller 110 can set a predetermined threshold to limit the number of paths used.

[0041] During a reprogramming operation, the storage controller 110 may first preprogram the write data into multiple non-volatile memories 120 via multiple paths based on a write command requested from the host. For example, the initial preprogramming operation may be performed simultaneously via multiple paths.

[0042] After the pre-programming operation is completed, the storage controller 110 can reprogram the written data into multiple non-volatile memories 120 through different path groups included in multiple paths during non-overlapping time periods. A path group represents a path through which the reprogramming operation is performed during any time period within the non-overlapping time periods after the pre-programming operation is completed. For example, each in a path group may include a subset of multiple paths.

[0043] The storage controller 110 can reprogram the written data through different path groups for different time periods. Therefore, reprogramming operations for different path groups may not be redundantly performed within the same time period.

[0044] When reprogramming operations are performed multiple times according to the example embodiment, the storage controller 110 can interleave any k-th reprogramming operation across different path groups over a time period, where k is a positive integer. For example, reprogramming operations of at least the same iteration may not be performed in the same time period. Reprogramming operations of different iterations may be performed across one or more path groups in any time period.

[0045] In an example embodiment, when the storage controller 110 detects an SPO event at any time during the period of performing a reprogramming operation, the storage controller 110 may back up the write data of one or more path groups. When the number of paths used for the reprogramming operation is limited according to the above embodiments, the size of the write data to be backed up (data backup amount or data dump amount) may depend on a finite number of paths, rather than all paths (e.g., multiple paths). For example, the backup amount when an SPO event occurs during a reprogramming operation may be the product of a multi-bit program unit and the number of paths being reprogrammed. The program unit may be the product of the page size, the number of pages, and the number of planes in the non-volatile memory.

[0046] Therefore, the storage controller 110 can limit the number of paths being reprogrammed in any given time period to reduce the size of the write data to be backed up.

[0047] According to the above embodiments, storage device 100 can limit the number of paths used for reprogramming operations based on the occurrence of an SPO event during a reprogramming operation to reduce the amount of data backups. As the amount of backups decreases, the time spent on backups may also decrease.

[0048] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of an example storage controller.

[0049] refer to Figure 2 According to an example embodiment, the storage controller 110 may include a central processing unit (CPU) 111, a power loss protection (PLP) circuit 112, a programming manager 113, a host interface (I / F) 114, a buffer manager 115, and a memory interface (I / F) 116. Each component in the storage controller 110 can be connected via a system bus.

[0050] CPU 111 may include a processing unit such as a microprocessor. CPU 111 can control the overall operation of memory controller 110. CPU 111 can drive firmware for driving memory controller 110. For example, CPU 111 can execute various types of firmware loaded into code memory (not shown).

[0051] In the example embodiment, when the programming manager 113 is provided as a software module, the CPU 111 can execute the software module corresponding to the programming manager 113 to perform operations of the storage controller 110 according to the example embodiment, including programming operations on data. When the programming manager 113 is executed, the CPU 111 can generate various types of control information required to implement reprogramming strategies and interleaved reprogramming operations.

[0052] In an example embodiment, CPU 111 may include multiple cores. Each of the multiple cores may be implemented as a separate processor core. The multiple cores may include host cores, flash translation layer (FTL) cores, and / or NAND cores.

[0053] A host core can be defined as a core within a storage device that performs operations related to the host interface layer (HIL). For example, a host core can handle requests received from the host via host interface 114.

[0054] An FTL core can be defined as a core within a storage device that performs FTL-related operations. For example, an FTL core can control a NAND core, allowing read, write, or erase operations to be performed by the non-volatile memory based on requests received from the host core. As another example, an FTL core can use the FTL to perform address mapping operations that map logical block addresses (LBAs) sent from the host to physical block addresses (PBAs) (the physical locations of the non-volatile memory).

[0055] A NAND core can be defined as a core within a storage device that performs operations related to the flash interface layer (FIL). For example, a NAND core can control memory interface 116 to perform operations on non-volatile memory under the control of an FTL core. For instance, a NAND core can control memory interface 116 based on a queue for controlling the non-volatile memory. Commands for controlling the non-volatile memory can be queued.

[0056] PLP circuit 112 can monitor external power and detect power failure events such as SPO events. When an SPO event occurs, PLP circuit 112 can detect the SPO event, generate a detection signal based on the detection, and provide the detection signal to programming manager 113.

[0057] Programming manager 113 can generate, set, and manage reprogramming strategies. In an example embodiment, the reprogramming strategy can set or indicate the maximum number of pathways (e.g., the number of pathways within a pathway group) that can be activated during a single reprogramming operation (e.g., the k-th reprogramming operation when multiple reprogramming operations should be performed). As another example, the reprogramming strategy can set or indicate the number of pathways included in each of the pathway groups. As another example, the reprogramming strategy can set or indicate the number of pathway groups. For example, the number of pathway groups can be two (2), but the example embodiment is not limited to this.

[0058] Programming manager 113 can statically or dynamically schedule reprogramming operations for a path group or set the number of paths included in each path group based on a reprogramming strategy.

[0059] The programming manager 113 can reprogram the written data through one or more path groups in the path group at any time after the pre-programming operation, based on a reprogramming strategy. When reprogramming operations are performed through multiple path groups, the programming manager 113 can schedule different reprogramming operations through different path groups for any time period.

[0060] In an example embodiment, the programming manager 113 can monitor the programming progress of multiple channels and multiple paths according to a reprogramming strategy. The programming manager 113 can dequeue commands for controlling programming operations on multiple non-volatile memories from a queue. For example, a command can request programming of written data for one or more path groups. Commands can instruct pre-programming or reprogramming operations. When instructed by a command, the programming manager 113 can perform a pre-programming operation.

[0061] As another example, when the command does not indicate a pre-programmed operation, the programming manager 113 can check the number of channels among multiple channels that are currently undergoing a reprogramming operation (e.g., determine the number of channels). When the number of channels is greater than or equal to a predetermined threshold (e.g., the maximum number of channels indicated by the reprogramming strategy), the programming manager 113 can enqueue the command into a pending queue. The programming manager 113 can continuously monitor the programming status. When the number of channels decreases to below the predetermined threshold, the programming manager 113 can again dequeue the command from the pending queue to perform a reprogramming operation.

[0062] When the number of channels is less than the threshold value, the programming manager 113 can immediately perform a reprogramming operation.

[0063] When a detection signal is received from PLP circuit 112, programming manager 113 can pause the ongoing programming operation. Then, programming manager 113 can access the buffer memory (see memory interface 116) via memory interface 116. Figure 1 Data in the buffer memory 130 is backed up to non-volatile memory.

[0064] In an example embodiment, when an SPO event is detected during a reprogramming operation, the programming manager 113 may back up the write data to be reprogrammed into non-volatile memory through the path being reprogrammed (or the path where the reprogramming operation is scheduled). For example, when an SPO event is detected at any time after a preprogramming operation, the programming manager 113 may back up only the write data to be reprogrammed into non-volatile memory through a limited number of paths.

[0065] In an example embodiment, additional commands can be requested from the host via host interface 114. For example, an additional command could be a request to write additional write data. After the reprogramming operation of a single path group within the path group is completed, programming manager 113 can preprogram the additional write data into multiple non-volatile memories via a single path group. For example, programming manager 113 can initiate the preprogramming operation of the additional write data and the reprogramming operation of the write data simultaneously at any time interval within a time period.

[0066] Therefore, pre-programming and reprogramming operations on different pathway groups can be performed in parallel at any time.

[0067] Host interface 114 provides an interface between the host and storage controller 110. The host and storage controller 110 can be connected via a single interface from a variety of standardized interfaces. Standardized interfaces can include various interface schemes such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI-express (PCIe), Universal Serial Bus (USB), IEEE 1394, Universal Flash Storage (UFS), or card interfaces.

[0068] Buffer manager 115 can control the buffer memory (see...) Figure 1 The buffer manager 115 can buffer write and write operations in the buffer memory 130. For example, under the control of the CPU 111 or the programming manager 113, the buffer manager 115 can buffer write data or read data in the buffer memory. When an SPO event occurs, the buffer manager 115 can buffer write data corresponding to the programming operation at the time of the SPO into the buffer memory.

[0069] In an example embodiment, when an SPO event occurs during a preprogramming operation, buffer manager 115 may buffer the write data to be preprogrammed into a buffer memory. In an example embodiment, when an SPO event occurs after the preprogramming operation is complete, buffer manager 115 may buffer state group data into a buffer memory. In an example embodiment, when an SPO event occurs during a reprogramming operation, buffer manager 115 may back up only the write data to be reprogrammed into non-volatile memory via a limited number of paths.

[0070] The memory interface 116 can provide an interface connection between the memory controller 110 and non-volatile memory. For example, data processed by the CPU 111 can be stored in non-volatile memory through the memory interface 116. For example, write data to be backed up can be backed up in non-volatile memory through the memory interface 116.

[0071] According to the above embodiments, the storage device can limit the number of paths used for reprogramming operations based on a reprogramming strategy to reduce the amount of backups and the time spent on backups due to the occurrence of SPO events during reprogramming operations.

[0072] Figure 3 This illustrates an example embodiment. Figure 1 A block diagram of an example of non-volatile memory.

[0073] refer to Figure 3 The non-volatile memory 120a may include a memory cell array 121, a row decoder 122, a page buffer circuit 123, a control logic circuit 124, and a voltage generation circuit 125. Although not explicitly stated... Figure 3 As shown, the non-volatile memory 120a may also include data input / output circuitry, input / output interfaces, etc. The non-volatile memory 120a may also include components such as column logic, a pre-decoder, a temperature sensor, a command decoder, and / or an address decoder. Furthermore, the non-volatile memory 120a may be... Figure 1 One of the multiple non-volatile memories 120 shown.

[0074] The memory cell array 121 may include multiple memory blocks BLK0 to BLKm-1, where m is a positive integer. Each of the multiple memory blocks BLK0 to BLKm-1 may include multiple memory cells. The multiple memory blocks BLK0 to BLKm-1 may be included in a single memory plane, but the example embodiment is not limited thereto. The memory cell array 121 can be connected to the page buffer circuit 123 via bit lines BL, and can be connected to the line decoder 122 via word lines WL, serial select lines SSL, and ground select lines GSL.

[0075] In an example embodiment, the memory cell array 121 may include a three-dimensional (3D) memory cell array 121. The 3D memory cell array 121 may include multiple levels and may have word lines or bit lines shared between levels.

[0076] Row decoder 122 can select a single memory block in the memory cell array 121 in response to row address RADDR. Row decoder 122 can select a single word line in the word line of the selected memory block in response to row address RADDR. Row decoder 122 can transmit a voltage VWL corresponding to the operating mode to the word line of the selected memory block. During programming operations, row decoder 122 can transmit programming voltage and verification voltage to the selected word line and pass voltage to the unselected word line. During read operations, row decoder 122 can transmit read voltage to the selected word line and pass read voltage to the unselected word line.

[0077] Page buffer circuit 123 may include multiple page buffers PB0 to PBn-1. The multiple page buffers PB0 to PBn-1 may each be connected to a memory cell via multiple bit lines BL. Page buffer circuit 123 may select at least one bit line in the bit lines BL in response to the column address CADDR. Page buffer circuit 123 may operate as a write driver or a sense amplifier depending on the operating mode. For example, during a programming operation, page buffer circuit 123 may apply a bit line voltage corresponding to the data (DATA) to be programmed to the selected bit line. During a read operation, page buffer circuit 123 may sense the current or voltage of the selected bit line to detect the data (DATA) stored in the memory cell.

[0078] Control logic circuit 124 can control the overall operation within non-volatile memory 120a. Control logic circuit 124 can respond to control signals CTRL, command CMD, and / or address ADDR to output various control signals for programming, reading, or erasing data stored in memory cell array 121. For example, control logic circuit 124 can output voltage control signal VTG_C, addresses (e.g., row address RADDR and column address CADDR), etc.

[0079] In an example embodiment, the control logic circuit 124 can output control signals for programming multi-bit data based on the received control signal CTRL, command CMD, and / or address ADDR. For example, the control logic circuit 124 can output control signals for pre-programming and reprogramming operations, output control signals for backing up state group data, or output control signals for reading pre-programmed or reprogrammed multi-bit data.

[0080] The voltage generation circuit 125 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal VTG_C. For example, the voltage generation circuit 125 can generate programming voltages, reading voltages, programming verification voltages, etc., as word line voltages VWL. For example, the programming voltage can be generated using an incremental steppulse program (ISPP) scheme.

[0081] In programming operations involving multi-bit data, the voltage generation circuit 125 can generate a pre-programming verification voltage for pre-programming operations and a reprogramming verification voltage for reprogramming operations. The pre-programming verification voltage can be lower than the reprogramming verification voltage.

[0082] Figure 4 This illustrates an example embodiment. Figure 1 A circuit diagram of an example memory block within a memory cell array is provided. For ease of description, an example of a single memory block comprising four strings STR1 to STR4 is given.

[0083] refer to Figure 4 The memory block BLKa may include multiple strings STR1 to STR4 vertically stacked on a substrate. Each of the multiple strings STR1 to STR4 may be positioned in a first direction (X-axis direction) and a second direction (Y-axis direction). For example, the memory block BLKa may be... Figure 3 The example embodiment shows one of the multiple memory blocks BLK0 to BLKm-1, but is not limited to this.

[0084] Strings in the same column from multiple strings STR1 to STR4 can be connected to the same position line. For example, the first string STR1 and the second string STR2 can be connected to the first position line BL1, and the third string STR3 and the fourth string STR4 can be connected to the second position line BL2.

[0085] Each of the multiple strings STR1 through STR4 may include multiple cell transistors. Each of the multiple cell transistors may be a charge-trap flash (CTF) memory cell, but the example embodiment is not limited thereto. The multiple cell transistors may be stacked in a third direction (Z-axis direction).

[0086] Multiple strings STR1 through STR4 can be connected together to a common source line CSL. For example, as shown below. Figure 4As shown, the common source line CSL can be connected to the lower ends of multiple strings STR1 to STR4. However, this is only an example; the common source line CSL only needs to be electrically connected to the lower ends of strings STR1 to STR4, and is not limited to being physically located at the lower ends of strings STR1 to STR4. In the following description, for ease of description, the structure and configuration of the strings will be described based on the first string STR1. The other strings STR2, STR3, and STR4 can have a similar structure to the first string STR1, so detailed descriptions of them will be omitted.

[0087] Multiple unit transistors can be connected in series between the first bit line BL1 and the common source line CSL. For example, the multiple unit transistors may include gate-induced drain leakage (GIDL) transistors GDT1 and GDT2, a string select transistor SST, memory cells MC1 to MC5, a virtual memory cell DMC, and a ground select transistor GST.

[0088] The first GIDL transistor GDT1 can be located at the bottom end of the string STR1. For example, the first GIDL transistor GDT1 can be connected to the common source line CSL at the bottom end of the string STR1. However, this is only an example, and the example embodiment is not limited thereto. The gate of the first GIDL transistor GDT1 can be connected to the first GIDL line GIDL1a.

[0089] The second GIDL transistor GDT2 can be positioned at the upper end of string STR1 and between string select transistor SST and memory cell MC5. For example, the second GIDL transistor GDT2 can be connected to the first bit line BL1 via string select transistor SST. The gate of the second GIDL transistor GDT2 can be connected to the second GIDL line GIDL2a.

[0090] exist Figure 4 In the diagram, GIDL transistors GDT1 and GDT2 are shown positioned at the top and bottom of string STR1, respectively. However, this is merely an example. In some embodiments, GIDL transistors may be positioned only at the top of string STR1 or only at the bottom of string STR1.

[0091] A single string select transistor SST can be positioned at the top of string STR1. The string select transistor SST can be connected to the first line BL1 at the top of string STR1. The gate of the string select transistor SST can be connected to the string select line SSLa. However, this is merely an example. In some embodiments, multiple string select transistors connected in series can be positioned between the first line BL1 and the second GIDL transistor GDT2.

[0092] A single ground selection transistor GST can be disposed between the virtual memory cell DMC and the first GIDL transistor GDT1. The gate of the ground selection transistor GST can be connected to the ground selection line GSLa. However, this is only an example. In some embodiments, multiple ground selection transistors connected in series can be disposed between the virtual memory cell DMC and the first GIDL transistor GDT1.

[0093] The first memory cells MC1 to the fifth memory cells MC5 can be connected in series between the string select transistor SST and the virtual memory cell DMC. The gate of each of the first memory cells MC1 to the fifth memory cells MC5 can be connected to the first word line WL1 to the fifth word line WL5.

[0094] A single virtual memory cell (DMC) can be disposed between the first memory cell (MC1) and the first GIDL transistor (GDT1). The gate of the virtual memory cell (DMC) can be connected to the virtual word line (DWL). However, this is only an example. In some embodiments, multiple virtual memory cells connected in series can be disposed between the first memory cell (MC1) and the first GIDL transistor (GDT1). As another example, an additional virtual memory cell can be disposed between the string select transistor (SST) and the fifth memory cell (MC5). As a further example, an additional virtual memory cell can be disposed between memory cells (MC1 to MC5). As yet another example, a virtual memory cell (DMC) may not be disposed.

[0095] According to an example embodiment, a programming voltage can be applied to the gate of each of the first memory cells MC1 to the fifth memory cells MC5 via the first word line WL1 to the fifth word line WL5, and a pre-programming operation or a reprogramming operation can be performed by applying the programming voltage.

[0096] After the pre-programming operation is completed via word lines WL1 to WL5, an SPO (Special Purpose Error) may occur in the storage device during a reprogramming operation. An SPO event may cause errors in word lines WL1 to WL5, and these errors may make it difficult to recover the pre-programmed data.

[0097] Figure 5 This is a diagram illustrating the data state based on pre-programmed operations and reprogrammed operations according to an example embodiment.

[0098] refer to Figure 5When a programming operation begins, the storage device according to the example embodiment can pre-program (or coarsely program) multiple bits of data in a memory cell of a non-volatile memory. For example, when the multiple bits of data are 4 bits (e.g., when the memory cell is a QLC), the pre-programmed memory cell can have a threshold voltage (Vth) corresponding to a single state among 16 threshold voltage states E0 and P1 to P15, such as... Figure 5 As shown, the 16 threshold voltage states E0 and P1 to P15 can each correspond to one of the 16 values ​​that multi-bit data can have. For example, a pre-programmed memory cell can correspond to one of the 16 threshold voltage states E0 and P1 to P15 based on a multi-bit data value. The threshold voltage of a memory cell may fluctuate due to capacitive coupling between adjacent memory cells, resulting in an increase in the width of the threshold voltage distribution. Therefore, adjacent threshold voltage distributions can overlap with each other.

[0099] The threshold voltage distribution of preprogrammed memory cells can be divided into multiple state groups. For example, the threshold voltage states corresponding to the erase state E0 and the programming states P1 to P15 can be divided into a first state group GR1 and a second state group GR2.

[0100] In an example embodiment, each of the state groups may include a different threshold voltage distribution, and the threshold voltage distributions of each of the state groups may not overlap with each other. For example, the first state group GR1 may include threshold voltage distributions corresponding to the erase state E0, the second programming state P2, the fourth programming state P4, the sixth programming state P6, the eighth programming state P8, the tenth programming state P10, the twelfth programming state P12, and the fourteenth programming state P14. The second state group GR2 may include threshold voltage distributions corresponding to the first programming state P1, the third programming state P3, the fifth programming state P5, the seventh programming state P7, the ninth programming state P9, the eleventh programming state P11, the thirteenth programming state P13, and the fifteenth programming state P15.

[0101] The number of state groups is merely an example, and the example implementation is not limited thereto.

[0102] Each state in a state group can be represented by state group data.

[0103] For example, when the threshold voltage distribution is divided into four state groups, the state group data can be 2 bits. Alternatively, the number of bits in the state group data can be less than the number of bits in a multi-bit data set.

[0104] Pre-programmed multi-bit data can correspond to state group data indicating one of multiple state groups based on data values. For example, multi-bit data corresponding to the erase state E0 can correspond to state group data indicating the first state group GR1, and multi-bit data corresponding to the first programming state P1 can correspond to state group data indicating the second state group GR2.

[0105] When an SPO occurs after the pre-programming operation is completed, the storage device can back up the state group data corresponding to the pre-programmed memory cell in non-volatile memory. For example, when multiple bits of data corresponding to the first programming state P1 are pre-programmed, the storage device can back up the state group data indicating the second state group GR2 corresponding to the pre-programmed memory cell in non-volatile memory.

[0106] When power is restored from the SPO, the storage device can recover multiple bits of data based on the backed-up state group data. For example, the storage device can read multiple bits of data from a pre-programmed memory cell based on the state group data. Figure 5 As shown, even when there are overlapping regions in the threshold voltage distribution of the pre-programmed memory cells, the read operation performed on each state group based on the state group data can determine which threshold voltage distribution the overlapping region belongs to. Therefore, the reliability of the recovered multi-bit data can be improved.

[0107] Storage devices can reprogram (or finely program) multiple bits of data in memory cells based on recovered multiple bits of data. Programming multiple bits of data can be accomplished through a reprogramming operation. For example... Figure 5 As shown, the width of the threshold voltage distribution of a memory cell can be reduced by performing a reprogramming operation.

[0108] The fluctuation range of the programming voltage used for reprogramming operations can be lower than that of the programming voltage used for preprogramming operations. For example, a storage device can perform a reprogramming operation based on applying a programming voltage with a smaller fluctuation range.

[0109] Due to the variation in the programming voltage range, the increase in threshold voltage of a memory cell caused by a reprogramming operation may be less than the increase caused by a preprogramming operation. Therefore, the threshold voltage distribution based on the reprogramming operation may be less affected by coupling, resulting in a narrower threshold voltage distribution of the memory cell and a smaller overlap area according to the reprogramming operation. Consequently, the reliability of multi-bit data can be improved when reading multi-bit data from a reprogrammed memory cell.

[0110] In an example embodiment, the reprogramming verification voltage for the reprogramming operation may be higher than the preprogramming verification voltage for the preprogramming operation. For example, the reprogramming verification voltage applied to any programming state during the reprogramming operation may be higher than the preprogramming verification voltage applied to any programming state during the preprogramming operation. For example, the preprogramming operation may be performed using a preprogramming verification voltage corresponding to a threshold voltage lower than the desired threshold voltage. During the reprogramming operation, memory cells may be programmed to the desired threshold voltage using a reprogramming verification voltage higher than the preprogramming verification voltage.

[0111] although Figure 5 The example shows the threshold voltage state generated from a single reprogramming operation, but the example embodiment is not limited to this. For example, several reprogramming operations can be performed to generate a finer threshold voltage.

[0112] When a SPO occurs during a reprogramming operation, it may be necessary to back up the write data corresponding to the programming state generated from the reprogramming operation. According to the above embodiment, the storage device can limit the number of paths used for reprogramming operations to reduce backup volume and backup time.

[0113] Figure 6 and Figure 7 This is a timing diagram illustrating the backup operation during an SPO event according to an example embodiment.

[0114] refer to Figure 6 In operation S11, the storage device performs a pre-programming operation. For example, when the written data is 4 bits, the memory cell programmed through the pre-programming operation can have 16 threshold voltage states (e.g., Figure 5 The threshold voltage corresponding to a single state in E0 and P1 to P15 generated from the pre-programmed operation.

[0115] In the example embodiment, state group data can be generated through pre-programmed operations.

[0116] After the pre-programming operation in operation S11 is completed, operation S12 can be executed, in which the storage device performs a reprogramming operation. When operation S12 is completed normally, the memory cell programmed through the reprogramming operation can have 16 threshold voltage states (e.g., Figure 5 The threshold voltage is one of the corresponding values ​​from E0 and P1 to P15 generated by the reprogramming operation.

[0117] When an SPO event occurs during operation S12, operation S13 can be performed, in which the storage device performs a backup of the write data to be reprogrammed. When the number of paths that can be reprogrammed is limited according to the example embodiment, the backup in operation S13 can be performed only on the write data to be reprogrammed through a limited number of paths.

[0118] Therefore, compared to the case where all paths in multiple paths are reprogrammed, the backup time (tback) can be further reduced in the case where reprogramming is performed on a limited number of paths according to the example embodiment.

[0119] refer to Figure 7 In operation S21, the storage device performs a pre-programming operation.

[0120] In operation S22, the storage device has a waiting time before performing a reprogramming operation.

[0121] In an example embodiment, when SPO1 occurs during the waiting period (i.e., when the first SPO event SPO1 occurs during the waiting period), operation S23 can be performed, wherein the storage device can back up the state group data generated by operation S21. According to the example embodiment, the storage device can also perform write data recovery based on the backed-up state group data and pre-programmed data.

[0122] In operation S24, the storage device performs a reprogramming operation. When SPO1 has occurred according to the example embodiment, the storage device can perform a reprogramming operation based on the recovered data.

[0123] In the example embodiment, when SPO2 occurs during the reprogramming operation (i.e., when a second SPO event SPO2 occurs during the reprogramming operation), operation S25 can be performed, wherein the storage device performs a backup of the write data to be reprogrammed. According to the above embodiment, the backup according to operation S25 can be performed only on the write data to be reprogrammed via a limited number of paths. Therefore, the backup time (tback) can be further reduced.

[0124] The occurrence of SPO2 during a reprogramming operation may lead to errors in the preprogramming operation. The state group data generated by the preprogramming operation becomes unavailable due to the error, thus potentially requiring backups of the write data to be reprogrammed. However, according to the above embodiment, the amount of backups of the write data to be reprogrammed can be reduced, allowing for faster backups during the reprogramming operation.

[0125] Figure 8 and Figure 9 This is a timing diagram illustrating the scheduling of a reprogramming method according to an example embodiment.

[0126] refer to Figure 8 According to the example embodiment, the storage device can schedule the start time of a reprogramming operation such that the reprogramming operation is performed through different path groups during a first time period TI1 to a seventh time period TI7 that do not overlap with each other. Although in Figure 8 Two pathway groups are shown as examples, but the example embodiments are not limited to these. The programming time tPROG2 of the reprogramming operation can be greater than or equal to the programming time tPROG1 of the preprogramming operation.

[0127] Depending on the scheduling of the start time of the reprogramming operation (Re-PGM), the reprogramming operation for the first pathway group WG1 and the reprogramming operation for the second pathway group WG2 can be performed in different time periods. For example, reprogramming operations for different pathway groups can be performed at different times.

[0128] In the reprogramming operation method according to the example embodiment, write data can be pre-programmed (Pre-PGM) into non-volatile memory via the first path group WG1 and the second path group WG2 during a first time period TI1.

[0129] When the first time period TI1 ends, the written data can be reprogrammed into the non-volatile memory via the first path group WG1 during the second time period TI2. Reprogramming operations on the second path group WG2 can be paused during the second time period TI2.

[0130] When the second time period TI2 ends, a reprogramming operation can be performed in the non-volatile memory via the second path group WG2 during the third time period TI3. ​​When a programming operation for additional write data is requested according to additional commands, a pre-programming operation on the first path group WG1 and a reprogramming operation on the second path group WG2 can be performed. For example, the reprogramming operation for write data via the second path group WG2 and the pre-programming operation for additional write data via the first path group WG1 can start simultaneously during the third time period TI3. ​​For example, during the third time period TI3, the memory controller 110 (see...) Figure 1 and Figure 2 It can simultaneously initiate the reprogramming operation of written data through the second path group WG2 and the preprogramming operation of additional written data through the first path group WG1.

[0131] A delay period DLY may exist when there is a difference between the programming time tPROG2 of the reprogramming operation and the programming time tPROG1 of the preprogramming operation. When the preprogramming operation of the first path group WG1 is completed, the first path group WG1 can wait for the delay period DLY.

[0132] When the third time period TI3 ​​ends, a reprogramming operation is performed through the first path group WG1 during the fourth time period TI4. Simultaneously, a preprogramming operation can be performed through the second path group WG2.

[0133] Then, during the fifth time period TI5 to the seventh time period TI7, a pre-programming operation can be repeatedly performed on one path group and a reprogramming operation can be performed on the other path group. Due to scheduling, during the second time period TI2 to the seventh time period TI7, the reprogramming operations on both the first path group WG1 and the second path group WG2 are not performed simultaneously.

[0134] Therefore, when an SPO event is detected during any of the time periods from the second time period TI2 to the seventh time period TI7, backups can be performed only on the write data to be reprogrammed in any single path group. For example, when an SPO event is detected during the second time period TI2, the storage device can back up the write data to be reprogrammed in the first path group WG1.

[0135] refer to Figure 9 According to the example embodiment, the reprogramming operation can be performed multiple times. Figure 9 In this example, the reprogramming operation is shown as being performed twice in a single reprogramming operation method, but the example embodiment is not limited thereto.

[0136] When multiple reprogramming operations are performed, the storage device according to the example embodiment can schedule the start time of the reprogramming operations so that different iterative reprogramming operations (e.g., a first reprogramming operation (first Re-PGM) and a second reprogramming operation (second Re-PGM)) are performed through different path groups during a first time period TI1 to a sixth time period TI6 that do not overlap with each other. Although in Figure 9 Three pathway groups are shown as examples, but the example embodiments are not limited to these. The programming time tPROG2 of each reprogramming operation can be greater than or equal to the programming time tPROG1 of the preprogramming operation. Furthermore, the programming times of the first and second reprogramming operations are shown to be the same, but in some embodiments they can be different from each other.

[0137] Depending on the scheduling of the start time of the reprogramming operations, the k-th reprogramming operation for the first path group WG1 and the k-th reprogramming operation for the second path group WG2 can be executed within different time periods. For example, reprogramming operations in the same iteration are not executed simultaneously for different path groups. For instance, during the same time period from the first time period TI1 to the sixth time period TI6, the first reprogramming operation is not executed for different path groups from the first path group WG1 to the third path group WG3. In other words, during a given time period from the first time period TI1 to the sixth time period TI6, the first reprogramming operation can be executed only for one path group from the first path group WG1 to the third path group WG3. As another example, during the same time period from the first time period TI1 to the sixth time period TI6, the second reprogramming operation is not executed for different path groups from the first path group WG1 to the third path group WG3.

[0138] In the reprogramming operation method according to the example embodiment, write data can be pre-programmed (Pre-PGM) into non-volatile memory through the first path group WG1 to the third path group WG3 during the first time period TI1.

[0139] When the first time period TI1 ends, the first reprogramming operation can be performed through the first path group WG1 during the second time period TI2. The first reprogramming operation on the second path group WG2 can be paused during the second time period TI2.

[0140] When the second time period TI2 ends, the first reprogramming operation can be performed through the second path group WG2 during the third time period TI3. ​​Simultaneously, the second reprogramming operation can be performed through the first path group WG1. The first reprogramming operation on the third path group WG3 can be paused between the second time period TI2 and the third time period TI3.

[0141] When a request is made to program additional write data based on additional commands, a pre-programming operation on the first path group WG1, a second reprogramming operation on the second path group WG2, and a first reprogramming operation on the third path group WG3 can be performed. For example, the reprogramming operation of write data through the second path group WG2 and the third path group WG3, and the pre-programming operation of additional write data through the first path group WG1, can begin simultaneously during the fourth time period TI4.

[0142] A delay period DLY may exist when there is a difference between the programming time tPROG2 of a reprogramming operation and the programming time tPROG1 of a preprogramming operation. Furthermore, delay periods may exist even between reprogramming operations in different iterations. In this case, the remaining path groups can wait until the longest reprogramming operation completes.

[0143] When the fourth time period TI4 ends, pre-programming operations can be repeated for one pathway group and reprogramming operations of different iterations can be performed for other pathway groups during the fifth time period TI5 to the sixth time period TI6. Due to scheduling, during the second time period TI2 to the sixth time period TI6, the same iteration of reprogramming operations will not be performed simultaneously on the first pathway group WG1 to the third pathway group WG3.

[0144] Therefore, when an SPO event is detected during any of the time periods from the second time period TI2 to the sixth time period TI6, backups can be performed only on the write data to be reprogrammed in some path groups. In this case, the number of backups can be reduced compared to scheduling reprogramming operations for all path groups.

[0145] and Figure 9 Unlike the illustrations, storage devices according to some other example embodiments can schedule programming operations on path groups such that a reprogramming operation is performed only once in any time period after the initial preprogramming operation is completed, regardless of the iteration of the reprogramming operation.

[0146] As another example, the storage device according to the example embodiment can schedule programming operations for a path group such that one or more of the first reprogramming operation to the Kth reprogramming operation are performed at any time period after the initial preprogramming operation is completed, where K is a positive integer.

[0147] Figure 10 This is a flowchart illustrating a method of operating a storage device according to an example embodiment. In some embodiments, a storage controller included in the storage device may be configured to perform... Figure 10 One or more of the operations shown.

[0148] refer to Figure 10 In operation S110, the storage device can preprogram write data into multiple non-volatile memories through multiple channels and multiple paths. For example, the preprogramming operation can start simultaneously on multiple paths.

[0149] After operation S110 is completed, the method proceeds to operation S120, in which the storage device can reprogram written data to multiple non-volatile memories through different path groups included in multiple paths during non-overlapping time periods. The storage device can reprogram the written data through one or more of the path groups at any time period within the time period. For example, when a single reprogramming operation is required, the written data can be reprogrammed through a single path group at any time period.

[0150] For example, when multiple reprogramming operations are required, the k-th reprogramming operation can be performed through a single channel group at any time interval, or different iterations of reprogramming operations can be performed simultaneously through multiple channel groups at any time interval.

[0151] According to the above method, the number of reprogrammed paths is limited, which reduces the amount of backups caused by SPO events.

[0152] Figure 11 This is a flowchart illustrating a backup operation of a storage device according to an example embodiment. In some embodiments, a storage controller included in the storage device may be configured to perform... Figure 11 One or more of the operations shown.

[0153] refer to Figure 11 In operation S210, the storage device can detect SPO events specific to the storage device. For example, the storage device can detect SPO events by monitoring external power. When no SPO event is detected, the SPO detection operation via operation S210 can be repeated.

[0154] When an SPO event is detected at any time during operation S210, operation S220 can be executed, in which the storage device can back up the write data of one or more path groups. These one or more path groups are reprogrammed path groups.

[0155] Based on the above backup operations, the amount of backups can be reduced compared to backing up the write data of all path groups.

[0156] Figure 12 This is a flowchart illustrating a programming scheduling method for a storage device according to an example embodiment. In some embodiments, a storage controller included in the storage device may be configured to perform... Figure 12 One or more of the operations shown.

[0157] refer to Figure 12 In operation S310, the storage device can dequeue commands for controlling multiple non-volatile memories from a queue. For example, commands can be received from the host and can be used to control multiple non-volatile memories.

[0158] In operation S320, the storage device can check whether the dequeued command in operation S310 indicates a pre-programming operation. When the dequeued command indicates a pre-programming operation, the method proceeds to operation S330, where the storage device can perform the pre-programming operation.

[0159] When the dequeue command does not indicate a preprogramming operation, the method proceeds to operation S340, where the storage device checks the number of paths among the multiple paths in which a reprogramming operation is being performed.

[0160] When the number of paths is less than a threshold value (TH), the method proceeds to operation S350, where the storage device performs a reprogramming operation. For example, the threshold value can be a predetermined threshold value.

[0161] When the number of pathways is greater than or equal to a predetermined threshold (TH), the method proceeds to operation S360, in which the storage device enqueues the command into the processing queue.

[0162] According to the above method, when an SPO event occurs during a reprogramming operation, simultaneous reprogramming through more than a limited number of paths can be prevented to reduce the amount of backups.

[0163] Figure 13 This is a block diagram of a storage device according to an example embodiment.

[0164] refer to Figure 13 The storage device 200 according to the example embodiment may include an auxiliary power supply 210, a PLP circuit 220, a storage controller 230, a plurality of non-volatile memories 240 and a buffer memory 250.

[0165] Auxiliary power supply 210 can supply accumulated energy to storage device 200 in the event of a SPO (Special Purpose) where external power is cut off. Storage device 200 can use the energy from auxiliary power supply 210 to complete ongoing operations and perform data backup operations. The more backups required, the more energy may be needed to accumulate in auxiliary power supply 210.

[0166] The PLP circuit 220 can be configured to prevent power loss to the storage device 200. The PLP circuit 220 can be implemented as an integrated circuit (IC), chip, or component. Under normal external power supply conditions, the PLP circuit 220 can supply external power as the power used by the storage device 200. When external power is cut off, the PLP circuit 220 can provide the output of the auxiliary power supply 210 as the power used by the storage device 200.

[0167] PLP circuit 220 can detect SPO events, such as external power interruption or severe voltage drop. When an SPO event is detected, PLP circuit 220 can provide a power failure detection signal DET to storage controller 230. Furthermore, PLP circuit 220 can switch the power source for driving storage device 200 from external power to auxiliary power supply 210.

[0168] The storage controller 230 can be configured to control multiple non-volatile memories 240 and buffer memories 250 according to commands or controls from a host. For example, the storage controller 230 can write data to or read data stored in the multiple non-volatile memories 240 in response to a request from the host. The storage controller 230 can provide commands, addresses, data, and control signals to the multiple non-volatile memories 240 to access them.

[0169] The storage controller 230 can perform programming operations according to the above embodiments via the programming manager 231. For example, the storage controller 230 can generate various types of control information required for reprogramming strategies and the interleaving of reprogramming via the programming manager 231. The storage controller 230 can schedule reprogramming operations so that reprogramming operations are performed through different path groups during different time periods.

[0170] The storage controller 230 can preprogram write data into multiple non-volatile memories 240 via multiple channels CH1 to CHi and multiple paths W11 to Wij. When the preprogramming operation is complete, the storage controller 230 can reprogram the write data into the multiple non-volatile memories 240 via different path groups. The storage controller 230 can schedule programming such that the number of paths activated for reprogramming operations does not exceed the maximum number set by the reprogramming strategy.

[0171] For example, when a command controlling multiple non-volatile memories 240 indicates a reprogramming operation, the memory controller 230 can check whether the number of active paths is greater than a maximum number when a reprogramming operation is performed according to the command. If the number of active paths is greater than the maximum number, the memory controller 230 can suspend the execution of the reprogramming operation according to the command.

[0172] When the PLP circuit 220 detects an SPO event during a reprogramming operation, the storage controller 230 can back up only the write data of the active path to multiple non-volatile memories 240. Then, when the power failure is restored by the auxiliary power supply 210, the storage controller 230 can resume the pre-programming operation and / or the reprogramming operation.

[0173] Multiple non-volatile memories 240 and buffer memories 250 are essentially the same as those described above. Figure 1 The same as those described in [the previous text], therefore further description of them is omitted.

[0174] As described above, according to the example embodiment, a storage device and a method for programming can be provided that can reduce the amount of data backup during a sudden power outage (SPO) event.

[0175] As used herein, the terms “comprising,” “including,” “having,” and any other variations thereof specify the presence of the stated features, steps, operations, elements, components, and / or groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. Furthermore, it will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. Rather, these terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Additionally, as used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0176] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made to this disclosure without departing from the scope of the disclosure as defined by the appended claims.

Claims

1. A storage device, comprising: Multiple non-volatile memories; and The storage controller is electrically connected to the plurality of non-volatile memories via multiple channels and multiple paths, wherein the multiple paths are included in a path group. The storage controller is configured as follows: Input data is pre-programmed into the multiple non-volatile memories through the multiple pathways; and After the pre-programming is completed, the input data is reprogrammed into the plurality of non-volatile memories through different pathway groups in the pathway group during non-overlapping time periods.

2. The storage device of claim 1, further comprising a buffer memory configured to buffer the input data. in, Each of the plurality of non-volatile memories is electrically connected to one of the plurality of channels through a corresponding path in the plurality of paths.

3. The storage device according to claim 1, wherein, The storage controller is configured to reprogram the input data via a first path group in the path group during a period of time in the time period.

4. The storage device according to claim 3, wherein, The storage controller is configured to back up the input data of the first path group in the path group in response to detecting a sudden power outage SPO event during the one of the time periods in the time period.

5. The storage device according to claim 1, wherein, The storage controller is configured to set the number of paths included in each path group.

6. The storage device according to claim 1, wherein, The number of pathway groups is two.

7. The storage device according to claim 1, wherein, The storage controller is configured to preprogram additional input data into at least one of the plurality of nonvolatile memories via one of the path groups after the reprogramming of the input data via one of the path groups is completed.

8. The storage device according to claim 7, wherein, The storage controller is configured to simultaneously initiate the preprogramming of the additional input data through one of the path groups and the reprogramming of the input data through another path group during a period of time in the time period.

9. The storage device according to claim 1, wherein, The storage controller is configured as follows: Dequeue the command from the queue; In response to the command instructing a pre-programming operation, the pre-programming is performed; and In response to the command not indicating a pre-programming operation, the number of the multiple paths in which the reprogramming is being performed is determined.

10. The storage device according to claim 9, wherein, The storage controller is configured as follows: In response to the number of the pathways being greater than or equal to a predetermined threshold, the command is enqueued into a waiting queue. and The reprogramming is performed in response to the number of pathways being less than the predetermined threshold value.

11. The storage device according to claim 1, wherein, The reprogramming verification voltage configured for the reprogramming is higher than the preprogramming verification voltage configured for the preprogramming.

12. A method of operating a storage device, the method comprising: Input data is pre-programmed into multiple non-volatile memories via multiple channels and multiple paths, wherein the multiple paths are included in a path group; and After the pre-programming is completed, the input data is reprogrammed into the plurality of non-volatile memories through different pathway groups in the pathway group during non-overlapping time periods.

13. The method according to claim 12, wherein, The reprogramming is performed during a time period within the time period via the first path group in the path group to reprogram the input data.

14. The method of claim 13, further comprising: Detect sudden power failure (SPO) events for the storage device; and In response to the detection of the SPO event during the one time period of the time period, the input data of the first channel group in the channel group is backed up.

15. The method of claim 12, further comprising setting the number of pathways included in each pathway group.

16. The method of claim 12, further comprising, after the reprogramming of the input data via one of the pathway groups is completed, preprogramming additional input data into at least one of the plurality of nonvolatile memories via the one of the pathway groups.

17. The method of claim 12, further comprising: Dequeue the command from the queue; In response to the command instructing a pre-programming operation, the pre-programming is performed; and In response to the command not indicating a pre-programming operation, the number of the multiple paths in which the reprogramming is being performed is determined.

18. The method of claim 17, further comprising: In response to the number of the pathways being greater than or equal to a predetermined threshold, the command is enqueued into a waiting queue. and The reprogramming is performed in response to the number of pathways being less than the predetermined threshold value.

19. A storage device, comprising: Multiple non-volatile memories; and The storage controller is electrically connected to the plurality of non-volatile memories through multiple channels and multiple paths. The storage controller is configured as follows: Input data is pre-programmed into the multiple non-volatile memories through the multiple pathways; and During a certain period of time, the input data is reprogrammed into at least one of the plurality of non-volatile memories through one of the plurality of paths, wherein the number of the plurality of paths is less than a predetermined threshold value.

20. The storage device according to claim 19, wherein, The storage controller is configured to set the predetermined threshold value, and Wherein, the predetermined threshold value is less than or equal to the total number of the multiple paths.

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