Request processing module, request processing method, electronic equipment and storage medium

Abstract

The invention provides a request processing module, a request processing method, electronic equipment and a storage medium, and relates to the technical field of computers. The request processing module comprises a first-level merging sub-module used for aggregating a plurality of memory access sub-requests into a plurality of first access requests under the condition that a plurality of memory access sub-requests corresponding to a write-in type instruction are received; and the second-level merging sub-module is used for receiving the plurality of first access requests and updating a plurality of pieces of pre-configured address mapping information in the same clock period according to the target address information respectively carried in the plurality of first access requests so as to generate a plurality of second access requests. According to the method and the device, the write-in type memory access requests can be dynamically merged, so that the high throughput requirement of outputting a plurality of merged requests in the same clock period is met.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more specifically, to a request processing module, a request processing method, an electronic device, and a storage medium. Background Technology

[0002] In existing computer architectures, multiple memory access requests issued by the processor or graphics processing unit can typically be aggregated to reduce the number of accesses to downstream caches or memory. Specifically, memory access requests can be merged according to instruction type, increasing the granularity of access and thus improving data transfer efficiency.

[0003] Common instruction types include load instructions, store instructions, atomic operation instructions, and consistency control instructions (flush / fence). These different types of instructions differ in their interface data format and transmission methods. Taking write instructions as an example, this type of instruction needs to transmit not only the access address but also the write data simultaneously. Therefore, the number of sub-requests that can be processed in parallel under the same bandwidth conditions is limited. This is especially true in scenarios with a large number of access requests carrying write data or dense access patterns, where the request processing solutions in related technologies still have certain limitations in terms of data throughput.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a request processing module, request processing method, electronic device, and storage medium that can dynamically merge write-type memory access requests, thereby meeting the high throughput requirement of outputting multiple merged requests in the same clock cycle.

[0006] According to a first aspect of this disclosure, a request processing module is provided, comprising: The first-level merging submodule is used to aggregate the multiple memory access sub-requests into multiple first access requests when multiple memory access sub-requests corresponding to a write class instruction are received. The second-level merging submodule is used to receive the multiple first access requests and, within the same clock cycle, update the pre-configured address mapping information according to the target address information carried in the multiple first access requests, so as to generate multiple second access requests.

[0007] In one exemplary embodiment of this disclosure, the second-level merging submodule includes: Multiple merge buffer units are provided, each of which stores its corresponding address mapping information; wherein, the address mapping information includes memory address information and write operation information corresponding to a preset merging granularity. The memory address comparison unit is used to match the target address information carried in each of the first access requests received with the memory address information in each of the merging buffer units within the same clock cycle to obtain a matching result, so that each of the merging buffer units updates the address mapping information according to the matching result and generates the second access request.

[0008] In one exemplary embodiment of this disclosure, each of the merging buffer units is configured to: During each clock cycle, when it is detected that the target address information carried in each first access request matches the memory address information stored in any of the merge buffer units, the write operation information carried in each first access request is merged with the write operation information stored in the matching merge buffer unit to obtain aggregated request information. And, under the preset triggering conditions, generate the second access request based on the aggregated request information.

[0009] In one exemplary embodiment of this disclosure, the preset triggering condition includes at least one of the following: the matching merge buffer unit is occupied by a new first access request, or the first access request carries an instruction end identifier.

[0010] In one exemplary embodiment of this disclosure, each of the merging buffer units is further configured to: During each clock cycle, if it is detected that the target address information carried in each of the first access requests does not match the memory address information stored in any of the merge buffer units, a second access request is generated based on the memory address information currently stored in the target merge buffer unit and the write operation information. The target merge buffer unit is determined from the merge buffer units that have never performed a requested merge operation.

[0011] In one exemplary embodiment of this disclosure, each of the merging buffer units is further configured to: The target address information and write operation information carried in each of the first access requests are written into the target merge buffer unit to replace the memory address information and write operation information currently stored in the target merge buffer unit.

[0012] In one exemplary embodiment of this disclosure, each of the merging buffer units is further configured to: Within the current clock cycle after the write instruction ends, if it is detected that all valid merge buffers have performed a request merge operation, a second access request corresponding to each valid merge buffer is generated based on the address mapping information stored in each valid merge buffer.

[0013] In one exemplary embodiment of this disclosure, each of the merging buffer units is further configured to: After generating the second access request, the address mapping information stored in each of the merge buffer units is cleared.

[0014] In one exemplary embodiment of this disclosure, the second-level merging submodule further includes a plurality of pipeline buffer units, each corresponding to one of the merging buffer units; Each of the aforementioned pipeline buffer units is configured to: If, during the current clock cycle at the end of a write instruction, any valid merge buffer unit is detected not to have performed a request merge operation, the target address information and write operation information carried in the first access request during the current clock cycle are received, and the second access request is generated in the next clock cycle based on the stored target address information and write operation information.

[0015] In one exemplary embodiment of this disclosure, the second-level merging submodule further includes: An input arbitration unit is used to control the input channel of the first-level merging submodule to be in a receiving state when the pipeline buffer unit is detected to be in the writing process, so that the input channel of the first-level merging submodule can receive the memory access sub-request corresponding to the new write class instruction after the pipeline buffer unit has been written.

[0016] In one exemplary embodiment of this disclosure, the second-level merging submodule further includes a plurality of multiplexers, which are respectively configured to correspond to a plurality of merging buffer units and a plurality of pipeline buffer units; Each of the multiplexers is configured to: Within the same clock cycle, the stored memory address information and write operation information are selected from the corresponding merge buffer unit or pipeline buffer unit, a second access request is generated and sent to the downstream module.

[0017] In one exemplary embodiment of this disclosure, the first-level merging submodule is configured to: Within the same clock cycle, Q memory access sub-requests carrying write data are received. Based on the memory address information carried by each memory access sub-request, address matching and aggregation are performed at a preset merging granularity to obtain N first access requests. The N first access requests are then output to the second-level merging submodule, where N is less than Q.

[0018] In one exemplary embodiment of this disclosure, the request processing module further includes: The first instruction processing module is used to receive M memory access sub-requests corresponding to read-type instructions within the same clock cycle, and perform single-level aggregation processing on the M memory access sub-requests to obtain P target access requests; wherein, P is less than M.

[0019] In one exemplary embodiment of this disclosure, the request processing module further includes: The second instruction processing module is used to receive consistency control instructions and send the target access request corresponding to the consistency control instructions to the downstream module within one clock cycle.

[0020] According to a second aspect of this disclosure, a request processing method is provided, comprising: Receive multiple memory access sub-requests corresponding to write class instructions, and aggregate the multiple memory access sub-requests into multiple first access requests; The system receives the multiple first access requests and updates the pre-configured multiple address mapping information according to the target address information carried in the multiple first access requests within the same clock cycle, so as to generate the corresponding multiple second access requests.

[0021] According to a third aspect of this disclosure, an electronic device is provided, including the request processing module described in the second aspect of this disclosure.

[0022] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processing unit, implements the above-described request processing method.

[0023] The exemplary embodiments disclosed herein may have some or all of the following beneficial effects: The request processing module provided in this exemplary embodiment can dynamically merge write-type memory access requests by constructing a request processing architecture including a first-level merging submodule and a second-level merging submodule. The second-level merging submodule can dynamically update multiple pre-configured address mapping information within itself based on the target address information carried in multiple first access requests, ensuring that different target address information matches different address mapping records. Furthermore, within the same clock cycle, the second-level merging submodule can generate and output multiple second access requests corresponding to each target address information based on the updated address mapping records. Therefore, even in high-density access scenarios carrying write data, continuous and efficient data transmission and request output can still be achieved.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 An architecture diagram of a request processing module according to an embodiment of this disclosure is shown.

[0027] Figure 2 A processing architecture diagram for multiple types of memory access requests is shown in an embodiment of this disclosure.

[0028] Figure 3 An architecture diagram of a request processing module according to an embodiment of this disclosure is shown.

[0029] Figure 4 A flowchart illustrating a request processing method according to an embodiment of this disclosure is shown.

[0030] Figure 5 A schematic diagram of the structure of an electronic device suitable for implementing embodiments of the present disclosure is shown.

[0031] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0033] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0034] In existing computer architectures, upstream modules (such as compute units and load storage) typically send multiple memory access requests to the request processing module through hardware interfaces. These upstream modules can be compute units, load storage units, instruction arbitration units, Direct Memory Access Controller (DMA) units, on-chip interconnect interface units, or other functional units capable of initiating memory access requests. For read instructions such as `load`, the upstream module only needs to transmit multiple memory address information and some auxiliary information through the interface, such as request type and request length. However, for write instructions such as `store` and `atomic`, in addition to memory address information and some auxiliary information, write data also needs to be transmitted simultaneously. Since write data consumes a significant amount of hardware interface resources, interface resources are typically reused, allowing instructions carrying write data and those not carrying write data to be transmitted on the same hardware interface using different transmission formats.

[0035] For example, for instructions that do not carry write data, the memory address information of M memory access sub-requests can be transmitted in the same clock cycle, meaning that the access request of one complete instruction can be received within one clock cycle. However, for instructions that carry write data, only the memory address information of Q memory access sub-requests and the write data can be transmitted in the same clock cycle, where Q is less than M, and M is usually a positive integer multiple of Q.

[0036] To improve resource utilization, for example, to ensure that write instructions can achieve the same aggregation of M sub-requests as read instructions during the merging phase, related technologies typically employ two methods to merge requests carrying write data: one method is to configure a large data buffer to cache the addresses of the M sub-requests within the same instruction and their corresponding write data, performing the merging operation only after all data has been collected; the other method is to use a multi-level merging structure, where the first-level merging module performs pre-merging on the Q sub-requests received in the same clock cycle, and then the subsequent-level merging module further merges the first-level merging results from multiple clock cycles. While the first method can achieve complete aggregation, it requires a large hardware area and cache resources, making it difficult to apply in large-scale, high-frequency systems; the second method, with lower hardware resource overhead and a certain degree of scalability, is more common. However, when the number of write requests is large or the access patterns are dense, the multi-level merging structure in related technologies still has certain limitations in terms of data throughput.

[0037] To address the aforementioned technical issues, this disclosure provides a request processing module that can simultaneously perform address matching and data merging operations on multiple input requests within the same clock cycle. This allows for multiple merged paths to be output to downstream modules while ensuring resource utilization, effectively improving the overall system throughput. Downstream modules include, but are not limited to, caches or memories, which receive merged memory access requests from the request processing module and perform corresponding data write, cache update, or write-back operations, thereby completing closed-loop data interaction of the memory access path.

[0038] refer to Figure 1 The diagram shown illustrates the architecture of a request processing module. Figure 1 In this process, multiple memory access sub-requests corresponding to write-type instructions are input to the request processing module for processing. This request processing module includes a first-level merging submodule and a second-level merging submodule, which are used to perform step-by-step merging and request generation processing on multiple memory access requests triggered by write-type instructions.

[0039] Specifically, multiple memory access sub-requests are first input to the first-level merging submodule for preliminary merging processing to obtain multiple first access requests. By aggregating memory access requests, the number of requests entering subsequent processing stages can be reduced.

[0040] Multiple initial access requests are then fed into the second-level merging submodule. This submodule has multiple pre-configured address mappings, which record the access status corresponding to different target addresses and support the generation of subsequent access requests. For example, the second-level merging submodule can dynamically update its pre-configured address mappings based on the target address information carried in each of the initial access requests, ensuring that the target addresses corresponding to different initial access requests are matched and the corresponding address mappings are updated.

[0041] Within the current clock cycle after the write instruction ends, if it is detected that all valid merge buffer units have completed the request merge operation, the second-level merge submodule generates and outputs multiple second access requests corresponding to the address mapping information based on the updated multiple address mapping information.

[0042] The second-level merging submodule can generate and output multiple second access requests within the same clock cycle, reducing the waiting overhead caused by generating access requests one by one or scheduling them across cycles. Thus, even in high-density access scenarios carrying write data, it can still maintain a relatively stable request output rhythm and achieve efficient data transmission and request processing.

[0043] It should be noted that, in the example implementation of this disclosure, the second-level merging submodule is configured to process multiple received first access requests in parallel within the same clock cycle; perform an address matching operation based on the target address information carried in the multiple first access requests and the pre-configured address mapping information; and update the address mapping information according to the result of the address matching operation to generate multiple second access requests.

[0044] In some specific implementations, the second-level merging submodule may include multiple merging buffer units and a memory address comparison unit. Each merging buffer unit stores corresponding address mapping information. The memory address comparison unit matches the target address information carried in each received first access request with the memory address information in each merging buffer unit within the same clock cycle, and controls each merging buffer unit to update the address mapping information based on the matching result to generate the corresponding second access request. It should be noted that the above structure is only an exemplary implementation. In other implementations, the second-level merging submodule may also adopt different forms of parallel processing and address matching structures to achieve the same or similar functions, such as through a parallel content-addressable storage structure, a hash-based address matching structure, a pipelined address comparison structure, or other module forms that can perform address matching and merging processing on multiple access requests within the same clock cycle to achieve parallel processing and address mapping updates for the first access request.

[0045] By using any of the above implementation methods, it is possible to achieve parallel address matching and merging of multiple access requests without changing the overall request processing flow, thereby generating a corresponding second access request to support the efficient operation of the request processing module in high-concurrency scenarios.

[0046] In some example implementations, references Figure 2 The diagram illustrates a processing architecture for multiple types of memory access requests. Figure 2 In this module, a request processing module is positioned between the upstream and downstream modules to receive and process various types of memory access commands issued by the upstream module. This module includes a distribution interface, a aggregation interface, and multiple request processing paths corresponding to different command types. The distribution interface connects to the output of the upstream module, receiving various types of memory access commands and distributing them according to command type. Each request processing path handles different types of memory access requests, such as read commands, write commands, and consistency control commands. The aggregation interface connects to the input of the downstream module, integrating the output results after each request processing path completes its processing and transmitting them to the downstream module.

[0047] Through this processing architecture, the request processing module can aggregate, merge, or schedule memory access requests based on the characteristics of different instruction types, thereby forming a hierarchical request management process and achieving high parallelism in access processing.

[0048] For write instruction processing paths, a multi-level merging structure is used to aggregate and output multiple write requests step by step. Figure 2 It can be seen that this path includes a first-level merging submodule and a second-level merging submodule. Specifically, the first-level merging submodule is used to aggregate multiple memory access sub-requests into multiple first access requests when multiple memory access sub-requests corresponding to a write instruction are received.

[0049] For example, the first-level merging submodule is configured to receive Q memory access sub-requests carrying write data within the same clock cycle, perform address matching and aggregation based on the memory address information carried by each memory access sub-request at a preset merging granularity, obtain N first access requests, and output the N first access requests to the second-level merging submodule. Here, N is less than Q, meaning the first merging submodule aggregates multiple input memory access sub-requests into a smaller number of merge requests within the same clock cycle. For the Q input memory addresses, under different address distributions, a minimum of 1 target address can be generated, and a maximum of Q target addresses can be generated.

[0050] The preset merging granularity refers to the address division unit used to determine whether different access addresses belong to the same merging range when performing memory access sub-request aggregation. The value of the merging granularity can be determined based on the system bus width, cache line size, or write mask width. For example, the preset merging granularity can be 32 bytes, 64 bytes, or 128 bytes, etc. This disclosure does not limit it.

[0051] Therefore, from a timing perspective, when the first merging submodule processes requests within an input cycle (i.e., Q memory addresses and their corresponding write data), if the merging conditions are sufficiently matched, it can complete the aggregation within a single clock cycle and send the aggregation result to the second-level merging submodule. If the merging conditions are insufficient, it may take Q / N consecutive clock cycles to complete the aggregation and output process. It is important to note that the first merging submodule does not accept new input requests before completing the aggregation operation for the current input cycle's requests, to ensure the integrity and sequential consistency of the same batch of sub-requests.

[0052] Optionally, when performing aggregation operations, the first-level merging submodule can judge and group multiple memory access sub-requests based on merging granularity rules to form a local aggregation result.

[0053] The merging granularity rule is used to limit the merging granularity of executable aggregation operations. When the target addresses of multiple memory access sub-requests are within the same merging granularity range, these sub-requests are determined to be able to access the same target storage unit, allowing the aggregation operation to be performed, thereby ensuring the integrity of data alignment and transmission boundaries.

[0054] For example, when the merging granularity is set to 128 bytes and the access length of a single request is 4 bytes, if the target addresses of two memory access sub-requests are 0x100010 and 0x100020 respectively, then it can be known that the target addresses of these two memory access sub-requests are both within the address range of the same 128-byte cache line, i.e., [0x100000, 0x100080).

[0055] Therefore, when performing a request merging operation, the alignment of the target addresses can be used to identify two memory access sub-requests that are within the same merging granularity alignment range, and the merging operation can be performed on them to generate a corresponding merged access request. Based on this, the efficiency of memory access sub-request aggregation can be improved while ensuring data correctness and access alignment, and the load on subsequent processing modules can be reduced.

[0056] The second-level merging submodule is used to receive multiple first access requests and, within the same clock cycle, update multiple pre-configured address mapping information according to the target address information carried in the multiple first access requests to generate multiple second access requests and output them to the downstream module.

[0057] It should be noted that the address mapping information maintained internally by the second-level merging submodule is used to characterize the correspondence between the first access request currently participating in the merging process and the target memory address. This address mapping information reflects the access status of each target memory address and its associated write data identifier.

[0058] For example, when a new first access request arrives, the second-level merging submodule first determines the correspondence between the target address carried by the request and the existing address mapping information. If the target address already exists in the current record, the corresponding record is updated so that the write data carried by the new request is logically merged with the data associated in the existing record, thereby maintaining the access consistency of the same target address. If the target address does not appear in the existing record, a corresponding entry is added to the address mapping information to record the address and its associated write data status for inclusion in the subsequent merging process.

[0059] The aforementioned update process can be performed across multiple address records to ensure that multiple input requests are processed within the same clock cycle. Through this dynamic update mechanism, the second-level merging submodule can continuously maintain the address validity status during the request merging process, avoiding repeated access to the same target address, and instantly reflecting the latest write data relationships when the access status changes. Therefore, the second-level merging submodule can complete the merging of multiple write requests without adding additional latency.

[0060] This multi-level merging structure enables dynamic merging of high-density access requests carrying write data under limited interface bandwidth conditions, generating multiple merge requests to achieve a high-throughput write request merging process, thereby improving the overall request processing throughput performance and data transmission efficiency.

[0061] For read instruction processing paths, the read merging submodule handles multiple memory access sub-requests corresponding to received read instructions and generates target access requests under a single-level aggregation structure. During execution, by identifying the target address distribution of each memory access sub-request, access requests with duplicate or adjacent addresses are identified and aggregated to achieve batch merging processing. This reduces the number of accesses to downstream modules during the read phase, lowers the concurrent load on the storage access path, and improves the overall data transfer efficiency.

[0062] For the consistency control instruction processing path, the consistency control instruction processing submodule receives the consistency control instructions and directly sends the corresponding memory access sub-requests to the downstream module, thus maintaining data consistency between the upstream and downstream modules. This processing path maintains a single-cycle pass-through characteristic in its structure, thereby avoiding timing interference or latency accumulation caused by consistency control operations to other instruction type paths.

[0063] After each processing path completes its corresponding instruction merging and processing operations, the result requests are aggregated through the aggregation interface and output to downstream modules in a unified format. The aggregation interface can be implemented in hardware using a multiplexer or arbitration logic structure to select and schedule valid requests from different processing paths within the same clock cycle, thereby ensuring the synchronization of output data and bandwidth utilization.

[0064] Through the above structural design, the request processing module can realize the split processing of instruction types and the aggregation and output of result requests, enabling read instructions, write instructions and consistency control instructions to be processed in parallel. In particular, in the write instruction path, a two-level merging mechanism is used to realize a high-throughput access process for multiple request outputs within the same clock cycle, thereby improving the overall system's data processing efficiency and resource utilization.

[0065] Additionally, it should be noted that regarding merging rules, multiple memory access sub-requests within the same instruction can be aggregated into a single merge request, provided that address alignment conditions are met, to achieve data write consolidation within the merging granularity. Memory access sub-requests between different instructions cannot be merged to avoid cross-instruction data write conflicts and storage consistency anomalies. For multiple consecutive write instructions, there is potential for further aggregation at the architectural level, which will not be described in detail in this disclosure.

[0066] To ensure data consistency and instruction boundary synchronization between the two-level merging modules, the first merging submodule passes the instruction end marker carried in the input request to the second-level merging submodule when outputting the merging result. For example, the instruction end marker is end_of_instruction. When end_of_instruction is 1, it indicates that the current transmission is the last piece of data for the corresponding instruction. The second-level merging submodule uses this to determine the end position of the current instruction and maintains the consistency of instruction boundaries when generating the final merging request. This ensures that the two merging levels maintain precise timing and boundary correspondence when processing the same write instruction, thereby achieving continuous control and synchronous output of instruction-level data merging.

[0067] It should be noted that, Figure 2 This is merely a schematic diagram illustrating the basic architectural concept of this disclosure for handling multiple types of memory access requests. The specific structure within this architecture can be further divided into different sub-modules and interface logic according to actual application requirements, and this disclosure does not limit it in this regard.

[0068] In some example implementations, for write instructions, the second-level merging submodule includes multiple merging buffer units and memory address comparison units. Specifically, each merging buffer unit stores its corresponding address mapping information and temporarily stores a merging request that has not yet been output to the downstream module. That is, each merging buffer unit records a set of address mapping information corresponding to the current cached content. The address mapping information includes memory address information and write operation information corresponding to a preset merging granularity. Among them, the memory address information is used to identify the target storage location associated with the merging request, and the write operation information includes write data and a write mask. The write data represents the data content to be written to the cache or storage unit, and the write mask is used to indicate the validity of each data bit in the write data.

[0069] For example, when the second-level merging submodule includes N merging buffer units, the memory address information recorded in each merging buffer unit is as follows: address1, address2, ..., addressN.

[0070] During the module initialization phase, the memory address information stored in each merge buffer unit is empty and in an invalid state. After the module enters the running phase, when the address records in the merge buffer units are in a valid state, the memory address information recorded in different merge buffer units must be different to ensure that each merge buffer unit corresponds to a unique address record, thereby maintaining the uniqueness and correctness of the address mapping relationship.

[0071] The memory address comparison unit is used to perform address matching operations on multiple first access requests from the first-level merging submodule within the same clock cycle. That is, it matches the target address information carried in each received first access request with the memory address information in each merging buffer unit to obtain the matching result, so that each merging buffer unit can update the address mapping information according to the matching result and generate a second access request.

[0072] Specifically, the memory address comparison unit extracts the target address information carried in each first access request and compares it in parallel with the memory address information recorded in each merging buffer unit. For example, for the target address information carried in each first access request, denoted as the input address, the memory address comparison unit compares it with address1, address2, ..., addressN stored in each merging buffer unit.

[0073] When a target address matches a memory address stored in a merge buffer unit, it is determined that they correspond to the same target storage area, and the matching result is then fed back to the corresponding merge buffer unit. Upon receiving the matching result, the merge buffer unit updates its internal address mapping information based on the result, merging the newly arrived write operation information with the existing write operation information in the cache within the merging granularity. Conversely, when the target address does not match the existing memory address, the memory address comparison unit marks the matching result as inconsistent and triggers the merge buffer unit to create a new address record to store the target address information and its corresponding write operation data.

[0074] The memory address comparison unit can compare and update multiple input access requests within the same clock cycle, enabling the second-level merging submodule to continuously maintain a complete and valid address mapping relationship, and generate multiple corresponding second access requests to output to the downstream module.

[0075] In some example implementations, each merge buffer unit is configured to, in each clock cycle, when it detects that the target address information carried in each first access request matches the memory address information stored in any merge buffer unit, merge the write operation information carried in each first access request with the write operation information stored in the matching merge buffer unit to obtain aggregate request information, and generate a second access request based on the aggregate request information if a preset trigger condition is met.

[0076] The aggregation request information refers to the intermediate data structure generated by the second-level merging submodule during the merging process. It includes information such as the target address, the merged write data, and the mask status, and is used to characterize the current merging status. When a preset trigger condition is met, the second-level merging submodule generates a corresponding second access request based on the aggregation request information and outputs it to the downstream module.

[0077] For example, the preset triggering conditions may include at least one of the following: the matching merge buffer unit is occupied by a new first access request, or the first access request is detected to carry an instruction end identifier.

[0078] When a matched merge buffer unit needs to be reallocated for a new first access request, that is, when the merge buffer unit is about to be occupied by new target address information, a second access request can be generated and output based on the existing aggregation request information in the merge buffer unit, thereby completing the submission of the current data before releasing the merge buffer unit.

[0079] When the first access request is detected to carry an instruction end flag (end_of_instruction=1), it is determined that the data transmission of the current instruction has been completed. The second-level merging submodule synchronously generates the corresponding second access request based on the aggregation request information stored in each merging buffer unit, and outputs each request to the downstream module at once to maintain the integrity of the instruction boundary and the timing synchronization of the merging operation.

[0080] In some implementations, the preset triggering conditions may also include system-configured cache refresh instructions or specific timing events, such as periodic refresh signals or software-triggered synchronization commands, which are used to output all valid aggregated request information to downstream modules in a specific scheduling cycle or forced synchronization scenario. This disclosure does not limit the specific form of the preset triggering conditions.

[0081] Specifically, when the memory address comparison unit in the second-level merging submodule determines that the input address matches the record address in a certain merging buffer unit within a preset merging granularity range, a merge operation is performed. For example, the write data and write mask carried in the input request are merged at the data level with the write data and write mask already stored in the merging buffer unit to obtain aggregated request information.

[0082] During the merging process, the update of written data is based on the write mask rules: for positions where the mask in the input request is valid, the write data in the input request replaces the corresponding write data in the merge buffer unit. For positions where the mask is invalid, the original data in the merge buffer unit remains unchanged.

[0083] This method allows for partial data writing byte-by-byte while avoiding overwriting unupdated data segments. After merging, the written data and write mask information in the merge buffer are updated synchronously to record the complete data state after merging, and aggregate request information is generated accordingly.

[0084] It should be noted that the second-level merging submodule receives N input requests within the same clock cycle. Each input request carries a unique target address, ensuring that multiple input addresses will not simultaneously match the address of the same merging buffer unit within the same clock cycle. In other words, each input request matches at most one merging buffer unit, and each merging buffer unit responds to only one input request update operation within the same clock cycle. This guarantees the uniqueness of the merging process and the consistency of data updates, avoiding contention for access or writes caused by address overlap within the same cycle.

[0085] Through the above merging operations, the second-level merging submodule can complete data fusion and mask update without adding extra timing delay, realizing the aggregation of multiple write operations within the same merging granularity, thereby improving the effective throughput of the request processing module in high-concurrency write scenarios.

[0086] Furthermore, each merge buffer unit is also configured to generate a second access request based on the memory address information currently stored in the target merge buffer unit and the write operation information when the target address information carried in each first access request does not match the memory address information stored in any merge buffer unit during each clock cycle.

[0087] The target merge buffer is determined from merge buffers that have not yet performed a merge request and are currently writable. It is used within the current clock cycle to carry the target address information and corresponding write operation information carried by input requests that do not match any valid address record. In other words, the target merge buffer must meet the following conditions: it has not yet participated in this round of address merging, it is not occupied by other input requests, and its internal storage content can be updated. This ensures that new input requests can be correctly accepted and recorded without conflicts.

[0088] To improve the determinism and efficiency of replacement, target merge buffer units can be determined based on selection rules such as fixed order priority, round-robin priority, and Least Recently Used (LRU) strategy. Fixed order priority determines replacement targets using a preset buffer index order. Round-robin priority achieves balanced replacement by periodically selecting each merge buffer unit sequentially. The Least Recently Used strategy tracks the most recent access time of each merge buffer unit, prioritizing the replacement of buffer units that have not been used in the past few clock cycles to improve overall resource utilization.

[0089] For example, when it is detected that the target address information carried in each first access request does not match the memory address information stored in any merge buffer unit, each merge buffer unit performs an address replacement operation. This process maintains the stability of the internal address mapping table of the module while accepting new input addresses and updating old data output, ensuring the continuity of the data path and the integrity of the output request.

[0090] Specifically, in this case, each merge buffer unit is also configured to write the target address information and write operation information carried in each first access request into the target merge buffer unit, so as to replace the memory address information and write operation information currently stored in the target merge buffer unit, and update the corresponding valid status flag, so that the target merge buffer unit becomes the new active address record.

[0091] In other words, when an input address cannot be matched with any valid address record, the input address that cannot be merged, along with its corresponding write data and write mask, will be sequentially written into the target merge buffer unit. Simultaneously, the memory address information and corresponding write data in the replaced target merge buffer unit will form a merged second access request, which will be output to the downstream module within the current clock cycle to complete the data write operation corresponding to that address.

[0092] In this way, the second-level merging submodule can achieve continuous data output and new request acceptance even when address mismatches occur. It can simultaneously release old requests and write new requests within a single clock cycle, thereby maintaining the stable update of the merge buffer unit set and ensuring that the request processing module can still achieve continuous and efficient output response under high concurrency access conditions.

[0093] In addition, to ensure the orderliness of data processing, each merge buffer unit is also configured to generate a second access request corresponding to each valid merge buffer unit based on the address mapping information stored in each valid merge buffer unit, when it is detected that each valid merge buffer unit has performed a request merge operation within the current clock cycle after the end of a write instruction.

[0094] Specifically, when the instruction end flag end_of_instruction=1 is detected, all valid merge buffer units are scanned within the current clock cycle. If it is confirmed that all valid merge buffer units have completed the matching and data merging operation with the input request, a corresponding second access request is generated based on the address mapping information stored internally and output to the downstream module to ensure that all data of this write instruction is committed within the current clock cycle.

[0095] Furthermore, each merge buffer unit is also configured to perform a unified clear operation on each merge buffer unit after the second access request is generated, that is, to clear the address mapping information and write operation data in each merge buffer unit and restore the state of each merge buffer unit to the initial invalid state.

[0096] The clearing operation is automatically triggered after the second-level merging submodule completes the matching, merging, or replacement operation, so that the buffer resources can be in a clean and idle state to receive new input requests in the next clock cycle. This avoids historical data residue from interfering with subsequent address matching or data aggregation, and maintains the stability of the request processing process and the smoothness of the data path.

[0097] In this example implementation, the second-level merging submodule can flexibly replace data and output requests under different address matching states. This ensures both efficient acceptance of unmatched input data and orderly submission of existing records, thereby achieving a balance between temporal continuity, data consistency, and throughput performance, and improving the overall efficiency of the request processing module.

[0098] It is important to note that the replacement behavior can be understood as the target address information of the input request overwriting and updating the memory address information stored in the target merging buffer unit. This means "kicking out" the original address record and re-storing the target address information of the input request and the corresponding write operation information in the target merging buffer unit. The kicked-out target merging buffer unit generates and outputs a second access request within the current clock cycle, which is received by the downstream module and executes the corresponding write or update operation to ensure real-time data submission and path continuity.

[0099] Within the same clock cycle, if only a portion of the N input addresses are valid addresses, the second-level merging submodule only performs matching, merging, or replacement operations on these valid input addresses. For merge buffer units without corresponding valid input addresses in the current clock cycle, the memory address information and data content recorded inside remain unchanged to maintain the continuity and data consistency of the merge buffer unit content.

[0100] For example, when N=4, N represents the number of first access requests that the second-level merging submodule can simultaneously receive and process in the same clock cycle. Assume that in the current clock cycle, only input address 1 and input address 2 are valid inputs out of the N input addresses. Input address 1 matches record address 2 in the merging buffer unit, while input address 2 does not match record addresses 1, 2, 3, or 4 in the merging buffer unit. The following operation is performed: Data is merged between input address 1 and record address 2. The write data and write mask stored in the merge buffer unit corresponding to record address 2 are updated to complete the data fusion within the same target address range.

[0101] Input address 2 performs a replacement operation on record address 1, removing the original memory address information and written data. The replaced record address 1 generates a second access request within the current clock cycle. Simultaneously, record address 1 is updated with the target address information and written data corresponding to input address 2, so that it can participate in subsequent merging operations as a new valid record.

[0102] For record address 3 and record address 4, since there is no corresponding valid input address in the current clock cycle, the memory address information and written data stored inside them remain unchanged to ensure the stability of the buffer state and the continuity of data recording.

[0103] Therefore, the second-level merging submodule can realize the synchronous processing of data merging, address replacement and request output within a single clock cycle, ensuring continuous transmission and efficient response of the data path under different input address combinations, thereby effectively improving the overall throughput performance of the request processing module in high-concurrency write scenarios.

[0104] Furthermore, the merge and kick-out operations can be completed in parallel within the same clock cycle. When all valid addresses in the input request have been matched and data fused, and the data status in the merge buffer unit has been updated, data updates and merge request outputs can be completed simultaneously within the same clock cycle. This enables parallel processing of merging and output within a single clock cycle, improving the overall throughput efficiency and real-time response capability of the request processing module while ensuring the continuity of processing timing.

[0105] However, in some scenarios, if a valid merge buffer unit has not undergone a merge operation in the current clock cycle, and a new input address needs to replace that merge buffer unit, the ejection and update operations cannot be completed within the same clock cycle. In this case, the memory address information and written data in the original merge buffer unit must first be ejected within the current clock cycle, and a corresponding second access request must be generated and sent to the downstream module. In the next clock cycle, the new input address and corresponding write operation data are then written into the released merge buffer unit, thus completing the overall replacement process. Therefore, this replacement operation will be completed sequentially over two consecutive clock cycles.

[0106] It should be noted that, since memory access sub-requests between different instructions cannot be merged across instructions, during cross-cycle replacement, the second-level merging submodule cannot continue receiving new input data from the first-level merging submodule in the second clock cycle. This input pause manifests as a "bubble" phenomenon at the input interface of the second-level merging submodule, that is, a state where there is temporarily no valid input within a certain clock cycle, resulting in a brief pause in instruction processing and a decrease in throughput.

[0107] To address the input pause issue caused by the replacement operation spanning multiple cycles, some example implementations further include multiple pipeline buffers in the second-level merging submodule. Each pipeline buffer is configured to correspond one-to-one with a merging buffer and is used to temporarily store input requests in instruction boundary scenarios.

[0108] When a replacement operation is detected to be executed across clock cycles, the new input address and write operation information will be temporarily written to the corresponding pipeline buffer unit and automatically written back to the released merge buffer unit in the next clock cycle to complete the update and commit process. This avoids input channel blocking during instruction boundary switching and ensures the timing continuity of the request processing process.

[0109] For example, each pipeline buffer unit is configured to receive the target address information and write operation information carried in the first access request in the current clock cycle when it is detected that any valid merge buffer unit has not performed the request merge operation during the current clock cycle after the end of the write-type instruction, and generate a second access request based on the stored target address information and write operation information in the next clock cycle.

[0110] Specifically, when `end_of_instruction=1` is detected, and at least one valid merge buffer unit has not performed a merge operation, while a new input address needs to replace that merge buffer unit, the new input address and write operation information are no longer directly written to the merge buffer unit, but are temporarily stored in the corresponding pipeline buffer unit. When the next clock cycle arrives, the pipeline buffer unit generates the corresponding second access request and outputs it to the downstream module.

[0111] Through this pipeline buffering mechanism, even after all N merge buffer units are released within the current clock cycle, the input interface of the second-level merging submodule can still receive memory access sub-requests corresponding to new write instructions in the next clock cycle without putting back pressure on the upstream module. This effectively avoids the bubble phenomenon during instruction switching, maintaining continuous data flow and efficient transmission.

[0112] In the exemplary implementation of this disclosure, by introducing a pipeline buffer unit, the second-level merging submodule can maintain the smooth flow of the upstream input path even when the replacement operation is executed across cycles, thereby achieving a smooth transition and continuous scheduling of cross-cycle instructions, reducing the generation of input bubbles, and further improving the continuity of the overall data path, throughput stability, and parallel processing efficiency of the module.

[0113] In some example implementations, the second-level merging submodule also includes an input arbitration unit for coordinating the timing relationship and data transmission status between the first-level merging submodule and the second-level merging submodule to ensure the synchronization and stability of the input path and the internal merging path.

[0114] Specifically, when a pipeline buffer unit is detected to be in the process of writing, the input arbitration unit will temporarily lock the input port of the second-level merging submodule to prevent the memory access sub-request corresponding to the new write instruction from directly entering the merging path, thereby avoiding write conflicts or data overlap.

[0115] At the same time, the input arbitration unit sends a control signal to the first-level merging submodule to maintain the receiving state, controlling the input channel of the first-level merging submodule to be in the receiving state. This allows the unit to receive and cache the memory access sub-requests corresponding to new write-type instructions in advance before the pipeline buffer unit completes writing, without immediately transmitting them to the second-level merging submodule.

[0116] After detecting that the pipeline buffer unit has completed the current write operation, the input arbitration unit immediately releases the lock on the input port of the second-level merging submodule and instructs the first-level merging submodule to output the memory access sub-request corresponding to the write instruction in the cache to the second-level merging submodule for processing. Through this control strategy, the first-level merging submodule and the second-level merging submodule can achieve periodic timing alignment, ensuring the continuity of data transmission and the efficient utilization of channel resources.

[0117] In some implementations, the input arbitration unit can also dynamically adjust the input scheduling strategy based on the system bus bandwidth status, the buffer resource occupancy within the second-level merging submodule, and feedback signals from downstream modules. When a downstream module is detected to be busy or the buffer resources of the second-level merging submodule are nearing full load, the input arbitration unit can temporarily reduce the upstream input rate or pause input to avoid data accumulation. Normal input is automatically restored when system resources become available again or the pipeline buffer unit completes its write operation.

[0118] Through a dynamic arbitration mechanism, the input arbitration unit can achieve adaptive timing coordination between the first-level merging submodule and the second-level merging submodule under different load conditions. This not only effectively prevents access conflicts and data writing errors of cross-cycle instructions, but also ensures continuous input and stable throughput in high-concurrency access scenarios, thereby improving the overall operating efficiency of the request processing module under the condition of multiple instructions being executed alternately.

[0119] Optionally, the second-level merging submodule also includes multiple multiplexers, each corresponding to a multiple merging buffer unit and a multiple pipeline buffer unit. Each multiplexer is configured to select stored memory address information and write operation information from the corresponding merging buffer unit or pipeline buffer unit within the same clock cycle, generate a second access request, and send it to the downstream module.

[0120] Specifically, after the second-level merging submodule completes address matching, data updating, and aggregation processing for each merging buffer unit and pipeline buffer unit, multiple units may simultaneously possess aggregation request information available for output. To ensure the orderly scheduling and parallel transmission of output requests, multiple multiplexers receive candidate output data from the corresponding merging buffer unit and pipeline buffer unit, and determine the final output source based on a preset output strategy.

[0121] For example, a priority strategy based on instruction boundaries prioritizes outputting the corresponding aggregation result when an instruction end marker is detected; a priority strategy based on cache validity directly outputs the content of the merge buffer unit when the merge buffer unit is in an active state and the corresponding pipeline buffer unit is empty; and a polling strategy based on time order ensures that each output channel can obtain an output opportunity in turn over multiple clock cycles, thereby maintaining the balance of output port utilization.

[0122] By configuring a multiplexer, the second-level merging submodule can flexibly select the output source based on the current execution state within the same clock cycle, enabling parallel scheduling and sequential output of multiple aggregation results and instruction boundary requests. This design not only ensures the temporal continuity of the output path and the independence between requests, but also maximizes the output bandwidth utilization in high-concurrency write scenarios, thereby improving the overall throughput performance and response speed of the request processing module and ensuring that the system maintains efficient and stable operation under complex access conditions.

[0123] It is understandable that if the input of the second-level merging submodule is N different first access requests sent by the first merging submodule, each first access request includes its own target address and corresponding write data, then the number of second access requests output by the second-level merging submodule after completing the merging and update operation is also N, and the target addresses corresponding to each second access request are independent of each other, and each carries the write data that matches it.

[0124] For example, refer to Figure 3 The diagram shown illustrates the architecture of a request processing module. Figure 3 In this module, the second-level merging submodule is located between the first-level merging submodule and the downstream module. It is used to further aggregate, replace, and control the output of multiple first access requests from the first-level merging submodule to generate multiple second access requests and send them to the downstream module.

[0125] The second-level merging submodule includes N single-layer merging buffer units and a memory address comparison unit. Optionally, the memory address comparison unit can be an N×N memory address comparator, used to compare the N target address information output by the first-level merging submodule with the memory address information stored in the N merging buffer units within the same clock cycle, to determine the matching relationship between each first access request and the address records stored in the multiple merging buffer units, thereby realizing parallel matching operations with multiple inputs and multiple buffers.

[0126] Multiple merge buffer units are used to store the address mapping information currently being processed in the merge process. Figure 3In the diagram, N merge buffer units are used to represent the data, such as "address1+wdata", "address2+wdata", ..., "addressN+wdata". Here, "address" represents the memory address information, and "wdata" represents the write data content corresponding to that address. When a merge buffer unit detects that the target address information of an input request matches an internal record, it performs a merge process on the newly arrived write operation information and the existing data. This completes data fusion and mask updates within the same address granularity, thereby maintaining the consistency and integrity of the write operation.

[0127] also, Figure 3 The request processing module also includes N pipeline buffer units with a depth of one layer. Each pipeline buffer unit is configured one-to-one with a merge buffer unit to temporarily store input requests at instruction boundaries or in scenarios involving cross-cycle replacement. When a merge buffer unit is detected to be in the process of writing or replacing, the new input address and its corresponding write operation information are temporarily stored in the corresponding pipeline buffer unit and automatically written back to the released merge buffer unit in the next clock cycle, thereby achieving non-blocking input across cycles. This design can maintain the continuity of the input path even when the replacement operation is not completed, avoiding input interruptions caused by merging delays or instruction switching.

[0128] exist Figure 3 In the structure shown, the second-level merging submodule also includes multiple aggregation interfaces. Each aggregation interface is connected to the corresponding merging buffer unit and pipeline buffer unit, respectively, to receive output requests from the two types of buffer units and send the final generated second access request to the downstream module.

[0129] In the specific implementation, each aggregation interface can achieve selection control through a multiplexer. That is, within the same clock cycle, the stored memory address information and write operation information are selected from the corresponding merge buffer unit or pipeline buffer unit to generate a second access request and send it to the downstream module.

[0130] Furthermore, the second-level merging submodule can also be integrated with the input arbitration unit ( Figure 3 (Not shown in the image) works in conjunction with the second-level merging submodule to achieve periodic timing coordination with the first-level merging submodule. When the pipeline buffer unit detects that data is being written, the input arbitration unit temporarily locks the input port of the second-level merging submodule to prevent memory access sub-requests corresponding to new write instructions from directly entering the merging path. After the write is completed, the lock is released and normal input is restored, thereby ensuring the continuity and stability of data transmission.

[0131] pass Figure 3The architecture design features a second-level merging submodule capable of parallel matching, dynamic updating, and synchronous output of N input addresses within the same clock cycle. Without adding extra timing latency, it completes the merging and aggregation of multiple write requests, achieving high request throughput and data transmission efficiency. This structure, through the setting of parallel merging and pipeline buffer units, combined with multiplexers and input arbitration control mechanisms, enables the request processing module to possess periodic parallel merging and output capabilities while ensuring data consistency and access order. This allows for high-bandwidth, low-latency request flow and output aggregation in high-concurrency write scenarios, significantly improving the overall system throughput and operating efficiency.

[0132] In one example embodiment, the parameters set in the request processing module are: M=16, Q=4, N=2, and the merging granularity is 128 bytes. Here, M represents the number of memory access sub-requests into which a single write instruction is divided, Q represents the number of memory access sub-requests that the first-level merging submodule can simultaneously receive and process within the same clock cycle, and N represents the number of first access requests that the second-level merging submodule can process in parallel within the same clock cycle. A merging granularity of 128 bytes means that when the target address information of multiple memory access sub-requests is within the same 128-byte aligned address range, they can be considered as the same merging unit for aggregation processing.

[0133] For a single store instruction with a request length of 4 bytes, the memory addresses of the resulting M=16 memory access sub-requests are as follows: First clock cycle: 0x1000, 0x1004, 0x2000, 0x2004, and end_of_instruction=0; Second clock cycle: 0x1008, 0x100C, 0x2008, 0x200C, and end_of_instruction=0; The third clock cycle: 0x1010, 0x1014, 0x3000, 0x3004, and end_of_instruction=0; The 4th clock cycle: 0x4000, 0x4004, 0x5000, 0x5004, and end_of_instruction=1.

[0134] For simplicity, it is assumed that the four input addresses within the same clock cycle can be aggregated pairwise according to alignment rules, meaning that every two adjacent input addresses can be merged into a single merge request at a 128-byte merging granularity. Therefore, the first-level merging submodule can output two first access requests within the same clock cycle and send them to the second-level merging submodule for further processing.

[0135] It should be noted that in practical applications, if the number of addresses output by the first-level merging submodule exceeds N, it needs to be processed over multiple clock cycles. This disclosure will not elaborate on this situation.

[0136] From the perspective of the second-level merging submodule, the target address sequence output by the first-level merging submodule after 128-byte alignment is as follows: First clock cycle: Input address 1 = 0x1000, input address 2 = 0x2000, end_of_instruction = 0; Second clock cycle: Input address 1 = 0x1000, input address 2 = 0x2000, end_of_instruction = 0; The third clock cycle: Input address 1 = 0x1000, input address 2 = 0x3000, end_of_instruction = 0; The fourth clock cycle: Input address 1 = 0x4000, input address 2 = 0x5000, end_of_instruction = 1.

[0137] During the first clock cycle, input address 1 and input address 2 are written to merge buffer unit 1 and merge buffer unit 2 respectively, and the state of the corresponding merge buffer unit changes from invalid to valid. At this time, the two merge buffer units establish address mapping records corresponding to input address 1 (0x1000) and input address 2 (0x2000) respectively, completing the initial address registration and providing a basis for subsequent matching and merging operations.

[0138] During the second clock cycle, input address 1 matches the record address in merge buffer unit 1, and input address 2 matches the record address in merge buffer unit 2. At this time, each matched merge buffer unit performs a write data merging operation, that is, according to the write mask rules, the write data carried in the input request is merged and updated byte by byte with the data content already stored in the merge buffer unit: the positions marked as valid by the mask are replaced by the original content by the input data, and the positions marked as invalid by the mask remain unchanged.

[0139] During the third clock cycle, input address 1 matches the record address in merge buffer unit 1, while input address 2 does not match the record address in merge buffer unit 2. At this point, merge buffer unit 2 is replaced, and its stored record address and corresponding write data content form a second access request with address 0x2000, which is sent to the downstream module to perform the write operation. Subsequently, input address 2 (0x3000) is written to merge buffer unit 2, updating its address record and write data, thus starting a new merging cycle.

[0140] During the fourth clock cycle, both input address 1 and input address 2 do not match the existing record addresses in merge buffer unit 1 and merge buffer unit 2, thus triggering a replacement operation. Merge buffer unit 1 and merge buffer unit 2 respectively output two second access requests with addresses 0x1000 and 0x3000 to the downstream module to complete the final submission of the corresponding data. Simultaneously, since the current clock cycle carries the instruction end flag end_of_instruction=1, input address 1 and input address 2 no longer enter merge buffer unit 1 and merge buffer unit 2, but are temporarily written to pipeline buffer unit 1 and pipeline buffer unit 2 respectively.

[0141] During the fifth clock cycle, both pipeline buffer unit 1 and pipeline buffer unit 2 are in a non-empty state. Each generates two second access requests with addresses 0x4000 and 0x5000 based on the internally stored target address information and write operation data, and sends them to the downstream module. After the request output is completed, the pipeline buffer unit is cleared and restored to the invalid state. The second-level merging submodule re-enters the idle state, and can continue to receive new write-type instruction inputs and perform subsequent merging and output operations in the next clock cycle.

[0142] As can be seen from this embodiment, the second-level merging submodule performs dynamic merging, replacement, and output operations based on the matching relationship between the input address and the merging buffer unit in each cycle. While maintaining high parallelism, it realizes cycle-level request merging and data flow control, thereby maintaining the continuity of the data path and throughput stability in high-frequency write command scenarios carrying write data.

[0143] In the exemplary embodiments of this disclosure, the request processing module further includes a first instruction processing module, corresponding to Figure 2 The read instruction merging submodule shown is used to receive M memory access sub-requests corresponding to read instructions within the same clock cycle, and perform single-level aggregation processing on the M memory access sub-requests to obtain P target access requests. Where P is less than M.

[0144] In this process, the first instruction processing module identifies adjacent or repeatedly accessed addresses belonging to the same read instruction class by detecting the distribution characteristics of each target address in the input sub-request. For the detected adjacent or repeated addresses, they can be aggregated into a single access request, i.e., a target access request, thereby reducing the number of accesses to downstream modules and reducing bandwidth consumption and memory access overhead.

[0145] In other words, memory access requests corresponding to read instructions are mainly used to retrieve data at the target address and do not involve modifying the storage state. The processing of multiple read requests is relatively independent, and request organization and generation can usually be completed through a single-level aggregation method. In contrast, memory access requests corresponding to write instructions not only carry target address information but also the data to be written and will update the storage state. Therefore, for read instructions, only a single-level merging process is needed to integrate and output the access requests, without the need for a multi-level aggregation structure, thus achieving batch optimization processing of read requests. This design can improve access bandwidth utilization and shorten the overall read latency while maintaining the consistency of data read order.

[0146] The request processing module also includes a second instruction processing module, corresponding to Figure 2 The consistency control instruction processing submodule shown is used to receive consistency control instructions and send the target access request corresponding to the consistency control instruction to the downstream module within one clock cycle. It can be seen that the target access request at this time is the instruction itself, requiring neither aggregation nor splitting.

[0147] Consistency control instructions can complete data transmission operations without going through an aggregation process, meaning processing and downstream output are completed within one clock cycle. This direct processing path ensures timing consistency and data synchronization between upstream and downstream modules when performing consistency maintenance operations.

[0148] This disclosure also provides an example implementation of a request processing method capable of meeting high-throughput requirements for write-type instructions with low hardware resource consumption. (See references) Figure 4 As shown, the request processing method may include the following steps S410 and S420: Step S410: Receive multiple memory access sub-requests corresponding to the write class instruction, and aggregate the multiple memory access sub-requests into multiple first access requests.

[0149] Each memory access sub-request includes the access address and the corresponding write data. For multiple received memory access sub-requests, based on their address alignment, these sub-requests are aggregated into multiple first access requests. This aggregation process allows the originally scattered sub-requests to be merged into larger-granularity access requests within the same clock cycle, thereby reducing the number of downstream transmissions.

[0150] Step S420: Receive multiple first access requests, and within the same clock cycle, update multiple pre-configured address mapping information according to the target address information carried in the multiple first access requests, so as to generate multiple second access requests.

[0151] The address mapping information records the valid target address and its corresponding write data status during the current request merging process. By dynamically updating this address mapping information within the same clock cycle, multiple write operations within the same address range can be integrated and output, thereby improving the overall request processing efficiency.

[0152] Exemplary embodiments of this disclosure also provide a computer-readable storage medium having a program product stored thereon capable of implementing the methods described above in this specification. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when run on an electronic device, causes the electronic device to perform the steps described in the "Exemplary Methods" section of this specification according to the various exemplary embodiments of this disclosure. This program product may be a portable compact disc read-only memory (CD-ROM) including program code and may run on an electronic device, such as a personal computer. However, the program product of this disclosure is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0153] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0154] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0155] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0156] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C#, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0157] Exemplary embodiments of this disclosure provide an electronic device that may include the request merging module described in any of the above example embodiments. For example, the electronic device may be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an MCU (Microcontroller Unit), etc., and this disclosure does not limit it to these.

[0158] Exemplary embodiments of this disclosure also provide another electronic device capable of implementing the above-described method. Referring below... Figure 5 To describe an electronic device 500 according to such an exemplary embodiment of the present disclosure. Figure 5 The electronic device 500 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0159] like Figure 5 As shown, the electronic device 500 can be represented in the form of a general-purpose computing device. The components of the electronic device 500 may include, but are not limited to: at least one processing unit 510, at least one storage unit 520, a bus 530 connecting different system components (including storage unit 520 and processing unit 510), and a display unit 540.

[0160] Storage unit 520 stores program code that can be executed by processing unit 510, causing processing unit 510 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, processing unit 510 can perform... Figure 4 The methods and steps in the text.

[0161] Storage unit 520 may include readable media in the form of volatile storage units, such as random access memory (RAM) 521 and / or cache memory (Cache) 522, and may further include read-only memory (ROM) 523.

[0162] Storage unit 520 may also include a program / utility 525 having a set (at least one) program module 524, such program module 524 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0163] Bus 530 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0164] Electronic device 500 can also communicate with one or more external devices 570 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 500, and / or with any device that enables electronic device 500 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 550. Furthermore, electronic device 500 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 560. As shown, network adapter 560 communicates with other modules of electronic device 500 via bus 530. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0165] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the method according to the exemplary embodiments of this disclosure.

[0166] Furthermore, the above figures are merely illustrative representations of the processes included in the methods according to exemplary embodiments of this disclosure, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0167] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0168] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0169] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A request processing module, characterized in that, include: The first-level merging submodule is used to aggregate the multiple memory access sub-requests into multiple first access requests when multiple memory access sub-requests corresponding to a write class instruction are received. The second-level merging submodule is used to receive the multiple first access requests and, within the same clock cycle, update multiple pre-configured address mapping information according to the target address information carried in the multiple first access requests, so as to generate multiple second access requests.

2. The request processing module according to claim 1, characterized in that, The second-level merging submodule includes: Multiple merge buffer units are provided, each of which stores its corresponding address mapping information; wherein, the address mapping information includes memory address information and write operation information corresponding to a preset merging granularity. The memory address comparison unit is used to match the target address information carried in each of the first access requests received with the memory address information in each of the merging buffer units within the same clock cycle to obtain a matching result, so that each of the merging buffer units updates the address mapping information according to the matching result and generates the second access request.

3. The request processing module according to claim 2, characterized in that, Each of the aforementioned merge buffer units is configured to: During each clock cycle, when it is detected that the target address information carried in each first access request matches the memory address information stored in any of the merge buffer units, the write operation information carried in each first access request is merged with the write operation information stored in the matching merge buffer unit to obtain aggregated request information. And, under the preset triggering conditions, generate the second access request based on the aggregated request information.

4. The request processing module according to claim 3, characterized in that, The preset triggering conditions include at least one of the following: the matching merge buffer unit is occupied by a new first access request, or the first access request carries an instruction end identifier.

5. The request processing module according to claim 2, characterized in that, Each of the aforementioned merge buffer units is also configured to: During each clock cycle, if it is detected that the target address information carried in each of the first access requests does not match the memory address information stored in any of the merge buffer units, a second access request is generated based on the memory address information currently stored in the target merge buffer unit and the write operation information. The target merge buffer unit is determined from the merge buffer units that have never performed a requested merge operation.

6. The request processing module according to claim 5, characterized in that, Each of the aforementioned merge buffer units is also configured to: The target address information and write operation information carried in each of the first access requests are written into the target merge buffer unit to replace the memory address information and write operation information currently stored in the target merge buffer unit.

7. The request processing module according to claim 2, characterized in that, Each of the aforementioned merge buffer units is also configured to: Within the current clock cycle after the write instruction ends, if it is detected that all valid merge buffers have performed a request merge operation, a second access request corresponding to each valid merge buffer is generated based on the address mapping information stored in each valid merge buffer.

8. The request processing module of claim 7, wherein, Each of the aforementioned merge buffer units is also configured to: After generating the second access request, the address mapping information stored in each of the merge buffer units is cleared.

9. The request processing module of claim 2, wherein, The second-level merging submodule also includes multiple pipeline buffer units, each corresponding to one of the merging buffer units; Each of the aforementioned pipeline buffer units is configured to: If, during the current clock cycle at the end of a write instruction, any valid merge buffer unit is detected not to have performed a request merge operation, the target address information and write operation information carried in the first access request during the current clock cycle are received, and the second access request is generated in the next clock cycle based on the stored target address information and write operation information.

10. The request processing module of claim 9, wherein, The second-level merging submodule also includes: An input arbitration unit is used to control the input channel of the first-level merging submodule to be in a receiving state when the pipeline buffer unit is detected to be in the writing process, so that the input channel of the first-level merging submodule can receive the memory access sub-request corresponding to the new write class instruction after the pipeline buffer unit has been written.

11. The request processing module according to any one of claims 1 to 10, characterized in that, The second-level merging submodule also includes multiple multiplexers, which are respectively set to correspond to multiple merging buffer units and multiple pipeline buffer units; Each of the multiplexers is configured to: Within the same clock cycle, the stored memory address information and write operation information are selected from the corresponding merge buffer unit or pipeline buffer unit, a second access request is generated and sent to the downstream module.

12. The request processing module of claim 1, wherein, The first-level merging submodule is configured to: Within the same clock cycle, receive Q memory access sub-requests carrying write data, perform address matching and aggregation based on the memory address information carried by each memory access sub-request at a preset merging granularity to obtain N first access requests, and output the N first access requests to the second-level merging submodule; Where N is less than Q.

13. The request processing module of claim 1, wherein, The request processing module also includes: The first instruction processing module is used to receive M memory access sub-requests corresponding to read-type instructions within the same clock cycle, and perform single-level aggregation processing on the M memory access sub-requests to obtain P target access requests; wherein, P is less than M.

14. The request processing module of claim 1, wherein, The request processing module also includes: The second instruction processing module is used to receive consistency control instructions and send the target access request corresponding to the consistency control instructions to the downstream module within one clock cycle.

15. A request processing method characterized by comprising: include: Receive multiple memory access sub-requests corresponding to write class instructions, and aggregate the multiple memory access sub-requests into multiple first access requests; The system receives the multiple first access requests and updates the pre-configured multiple address mapping information according to the target address information carried in the multiple first access requests within the same clock cycle, so as to generate multiple second access requests.

16. An electronic device, comprising: Includes the request processing module as described in any one of claims 1 to 14.

17. A computer readable storage medium having stored thereon a computer program, characterized in that When the computer program is executed by the processing unit, it implements the request processing method as described in claim 15.

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