Receiver circuit with parallel trigger circuitry

Abstract

The embodiment of the invention relates to a receiver circuit with parallel trigger circuitry. For example, a receiver circuit [100] includes first trigger circuitry [102] configured with a first trigger level for a low-to-high transition of an input signal applied to an input node [101] of the receiver circuit [100], and second trigger circuitry [104] configured with a second trigger level for a low-to-high transition of an input signal applied to an output node [101] of the receiver circuit [100]. The second trigger circuitry is arranged at least partially in parallel with the first trigger circuitry [102] and is configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level. Respective inputs of the first trigger circuitry and the second trigger circuitry are coupled to the input node [101] of the receiver circuit [100], and respective outputs of the first trigger circuitry [102] and the second trigger circuitry [104] are coupled to an output node of the receiver circuit [100].

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuits and systems, and more specifically, but not exclusively, to receiver circuits. Background Technology

[0002] Receiver circuits are illustratively used as part of input / output (I / O) circuit systems in integrated circuits and many other applications. In some applications, such receiver circuits receive input signals from other integrated circuits and / or from other external components of the electronic system. Summary of the Invention

[0003] This disclosure describes a receiver circuit with a parallel trigger circuit system, an integrated circuit including such a receiver circuit, and related methods.

[0004] This summary is not an exhaustive overview of the present disclosure. Rather, the purpose of this summary is to present some examples of the disclosure in a simplified form as a prelude to the more detailed description that follows.

[0005] In some instances, a receiver circuit includes a first trigger circuit system and a second trigger circuit system. The first trigger circuit system is configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit. The second trigger circuit system is arranged at least partially in parallel with the first trigger circuit system and is configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level. The corresponding inputs of the first and second trigger circuit systems are coupled to the input node of the receiver circuit, and the corresponding outputs of the first and second trigger circuit systems are coupled to the output node of the receiver circuit.

[0006] In some other examples, an integrated circuit includes a plurality of receiver circuits and an additional circuit system coupled to the plurality of receiver circuits. At least one of the receiver circuits includes a first trigger circuit system and a second trigger circuit system. The first trigger circuit system is configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit. The second trigger circuit system is arranged at least partially in parallel with the first trigger circuit system and is configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level. Respective inputs of the first and second trigger circuit systems are coupled to the input nodes of the receiver circuits, and corresponding outputs of the first and second trigger circuit systems are coupled to the output nodes of the receiver circuits.

[0007] In some additional instances, a method of manufacturing an integrated circuit includes forming a plurality of receiver circuits and forming an additional circuit system, wherein the receiver circuits are coupled to the additional circuit system, and wherein each of the one or more receiver circuits includes: forming a first trigger circuit system configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit; and forming a second trigger circuit system, at least partially arranged in parallel with the first trigger circuit system, and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level. Respective inputs of the first and second trigger circuit systems are coupled to the input nodes of the receiver circuits, and respective outputs of the first and second trigger circuit systems are coupled to the output nodes of the receiver circuits. Attached Figure Description

[0008] Figure 1 A receiver circuit with a parallel trigger circuit system according to an example of this disclosure is shown;

[0009] Figure 2 This is a block diagram of an integrated circuit including multiple receiver circuits and additional circuit systems according to an example of this disclosure;

[0010] Figure 3 This is based on an example of this disclosure. Figure 1 A schematic diagram of the receiver circuit implementation scheme;

[0011] Figure 4 and 5 This is a timing diagram illustrating the operation of a receiver circuit with parallel trigger circuitry according to an example of the present disclosure;

[0012] Figure 6 Another receiver circuit with a parallel trigger circuit system according to an example of the present disclosure is shown, wherein a Schmitt trigger circuit is used in the parallel trigger circuit system.

[0013] Figure 7 This is a flowchart illustrating a method of operating the receiver circuit according to an example of this disclosure; and

[0014] Figure 8 This is a flowchart illustrating a method for manufacturing an integrated circuit including multiple receiver circuits according to an example of this disclosure. Detailed Implementation

[0015] This disclosure is described with reference to the accompanying drawings. The components in the drawings are not drawn to scale. The focus is on clearly illustrating the general features and principles of this disclosure. Examples in the drawings illustrate numerous specific details and relationships to provide an understanding of this disclosure. The drawings and examples are not intended to limit the scope of this disclosure to such examples, and other examples are possible by means of interchange or modification of at least some of the described or shown elements. Furthermore, where elements of this disclosure may be implemented using some or all of known components, certain portions of such components that facilitate an understanding of this disclosure are described, and detailed descriptions of other portions of such components are omitted to avoid obscuring this disclosure.

[0016] As used herein, terms such as “first” and “second” are used to distinguish elements described by such terms. Therefore, these terms in the description and claims are not necessarily intended to indicate a temporal or other priority order of such elements. Furthermore, given the orientations shown in the figures, terms such as “front,” “back,” “top,” “bottom,” “above,” “below,” “vertical,” “horizontal,” “lateral,” “downward,” “upward,” “upper,” and “lower” are used to refer to the relative orientation or position of features in the device. For example, “upper” or “topmost” may refer to a feature positioned closer to the top of the page than other features. The terms thus used are interchangeable where appropriate, allowing examples and descriptions of the techniques described herein to operate, for example, in orientations other than those shown or otherwise described herein. In the following discussion and claims, the terms “including,” “includes,” “having,” “has,” “with,” or variations thereof are intended to be inclusive in a manner similar to the term “comprising,” and should therefore be interpreted as meaning, for example, “including but not limited to.” Furthermore, in some instances, the terms "about," "approximately," or "substantially" preceding a value imply + / - 10% to 20% of that value. Additionally, unless otherwise stated, the order of steps in the specification and claims is not intended to limit the order in which steps are performed, and alternative orderings of steps may be appropriately considered.

[0017] The various structures disclosed herein, such as transistors and other semiconductor-based circuit systems, or portions and combinations thereof, can be formed using semiconductor process technologies. Layers comprising multiple materials can be formed on a substrate (e.g., a semiconductor wafer) using, for example, deposition techniques (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating), thermal processing techniques (e.g., oxidation, nitriding, epitaxy), and / or other suitable techniques. Similarly, portions of the layers can be selectively removed, for example, using etching techniques (e.g., plasma (or dry) etching, wet etching), chemical mechanical planarization, and / or other suitable techniques, some of which can be combined with photolithography steps. The electrical conductivity (or resistivity) of the substrate (or regions of the substrate) can be controlled by doping techniques using various chemical substances (which may also be referred to as dopants, dopant atoms, etc.), including but not limited to boron, gallium, indium, arsenic, phosphorus, or antimony. Doping can be performed during the initial formation or growth of the substrate (or epitaxial layer grown on the substrate) by ion implantation or other suitable doping techniques.

[0018] In some instances, the receiver circuitry includes a parallel trigger circuitry system, as described herein. For example, such receiver circuitry is illustratively configured to operate on an I / O supply voltage (VDDIO) of approximately 1.2 volts (1.2 V) while also being configured to handle 5-volt (5 V) input signals. In such instances, the receiver circuitry provides a 1.2 V compatible trigger level for both low-to-high transition input voltage (VIH) and high-to-low transition input voltage (VIL), with an appropriate amount of hysteresis (e.g., at least 50 mV), while also drawing negligible quiescent current from the 5 V input signal. Thus, some instances provide a receiver circuitry capable of reliably receiving 5 V switching signals while conforming to the 1.2 V VIH / VIL level and meeting the 50 mV hysteresis requirement, all without drawing significant quiescent current. In other instances, other input signal voltages, supply voltages, VIH / VIL trigger levels, and quiescent current characteristics may be utilized.

[0019] These and other examples provide technical solutions to significant problems with alternative methods. For example, one or more of these examples overcome significant challenges that might otherwise arise when attempting to configure receiver circuitry to operate at a relatively low VDDIO supply voltage level (e.g., 1.2 V) while also accommodating a relatively high input signal swing (e.g., 5 V) and providing the desired amount of hysteresis (e.g., 50 mV) at a low quiescent current. While the various examples described may be expected to provide such or similar improvements, this disclosure does not claim a particular result unless expressly stated in the specific claims.

[0020] Now for reference Figure 1Receiver circuit 100 is configured to receive an input signal applied to input pad 101. In this example, input pad 101, also simply referred to herein as PAD, represents the receiver input of receiver circuit 100. The input signal applied to input pad 101 is also referred to herein as receiver input PAD in some instances to refer to the signal applied to input pad 101. Input pad 101 is an example of an element more generally referred to herein as an “input node” of receiver circuit 100. Receiver circuit 100 includes a first trigger circuit system 102 and a second trigger circuit system 104, which are arranged in parallel with each other, as shown. The first trigger circuit system 102 is configured with a first trigger level for a low-to-high transition of the input signal applied to input pad 101 of receiver circuit 100, and the second trigger circuit system 104 is configured with a second trigger level for a high-to-low transition of the input signal applied to input pad 101, wherein the second trigger level is different from the first trigger level (e.g., lower than the first trigger level).

[0021] In some instances, the first trigger level provided by the first trigger circuit system 102 more specifically includes the VIH trigger level for the receiver circuit 100, and the second trigger level provided by the second trigger circuit system 104 more specifically includes the VIL trigger level for the receiver circuit 100, but in other instances, other types and arrangements of trigger levels may be used.

[0022] The corresponding inputs of the first trigger circuit system 102 and the second trigger circuit system 104 are coupled to the input pad 101 of the receiver circuit 100, and the corresponding outputs of the first trigger circuit system 102 and the second trigger circuit system 104 are coupled to the output node of the receiver circuit 100. As shown, the outputs of the first trigger circuit system 102 and the second trigger circuit system 104 are... Figure 1 The common output node OUT is coupled together. The common output node OUT is coupled to the receiver output Y of the receiver circuit 100 via a series arrangement of level shifter circuit 106 and latch circuit 105. Each of the common output node OUT and the receiver output Y is considered an instance of an “output node” of the receiver circuit 100, as the term is used extensively herein. In other instances, other types of input and output nodes may be used, along with at least partially parallel arrangements of the first and second trigger circuit systems.

[0023] In some instances, the first trigger circuit system 102 is configured to drive the output node of the receiver circuit (e.g., receiver output Y) to one of a logic high level and a logic low level in response to a low-to-high transition of the input signal, and the second trigger circuit system 104 is configured to drive the output node of the receiver circuit to the other of a logic high level and a logic low level in response to a high-to-low transition of the input signal. Examples of this operation can be seen in the description below. Figure 4 and 5 The timing diagram.

[0024] In some instances, the first trigger circuit system 102 and the second trigger circuit system 104 include Figure 1 The corresponding first and second inverters, not explicitly shown, each have an input coupled to the input pad 101 of the receiver circuit 100 and an output coupled to the output node OUT of the receiver circuit 100. The following will combine... Figure 3 The schematic diagrams illustrate examples of such first and second inverters in more detail. In some instances, additional or alternative circuitry is included in the first trigger circuitry system 102 and the second trigger circuitry system 104. For further specific illustration, other instances may configure the first trigger circuitry system 102 and the second trigger circuitry system 104 to include corresponding first and second Schmitt trigger circuits, replacing the first and second inverters described above.

[0025] The first trigger circuit system 102 and the second trigger circuit system 104 further include corresponding enable circuit systems 112 and 114. Enable circuit systems 112 and 114 are examples of elements more generally referred to herein as control circuit systems, configured to simultaneously enable the first trigger circuit system 102 and the second trigger circuit system 104 in response to an applied control signal. In this example, the applied control signal is implemented as an enable signal, also represented as a receiver enable (RXEN) signal.

[0026] An enable signal is an example of an element more generally referred to herein as a "control signal." The terminology used extensively herein is intended to encompass any one or more enable signals of a wide variety of different types and arrangements, as well as additional or alternative signals or combinations of signals that can be used to simultaneously activate and deactivate the first trigger circuitry system 102 and the second trigger circuitry system 104 of the receiver circuitry 100. Although in Figure 1In one example, the control circuitry including the enabling circuitry systems 112 and 114 is illustratively shown as being implemented entirely within the respective first triggering circuitry system 102 and second triggering circuitry system 104; however, in other examples, this circuitry may be implemented at least partially outside the first triggering circuitry system 102 and second triggering circuitry system 104.

[0027] The outputs of the first trigger circuit system 102 and the second trigger circuit system 104, coupled together at the common output node OUT, are also coupled to the input of the latch circuit 105. The output of the latch circuit 105 is coupled to the input of the level shifter circuit 106. Therefore, the latch circuit 105 and the level shifter circuit 106 are coupled in series between the outputs of the first trigger circuit system 102 and the second trigger circuit system 104 and the receiver output Y, thereby coupling the common output node OUT to the output node corresponding to the receiver output Y.

[0028] In some instances, latch circuit 105 illustratively includes Figure 1 The series arrangement of multiple inverters (not explicitly shown) involves the input of the first inverter in the plurality of inverters coupled to the output of a corresponding first trigger circuit system 102 and second trigger circuit system 104, the output of the first inverter in the plurality of inverters coupled to the input of another inverter in the plurality of inverters, and the output of the other inverter in the plurality of inverters coupled to the outputs of the first and second trigger circuit systems. In other instances, one or more latch circuits of other types and arrangements may be used. In some of these instances, latch circuit 105 is more specifically implemented as a “weak” latch, additional examples of which will be described below. Figure 3 The diagram is described in more detail.

[0029] In some instances, the level shifter circuit 106 may be an inverting level shifter or a non-inverting level shifter, and may be implemented according to one or more embodiments disclosed in U.S. Patent No. 10,848,156, issued November 24, 2020, entitled “Voltage Level Shifter,” which is jointly assigned to and incorporated herein by reference in its entirety. In other instances, one or more level shifter circuits of other types and arrangements may be used.

[0030] The receiver circuit 100 is illustratively implemented as part of an integrated circuit, which will now be referenced. Figure 2 Examples of the integrated circuit will be described in more detail below. In other examples, the receiver circuit 100 may be implemented in other ways, for example, at least in part as a discrete circuit component.

[0031] Now for reference Figure 2 An example integrated circuit 200 is shown. Integrated circuit 200 includes a plurality of receiver circuits 100-1 to 100-N, each receiver circuit being previously combined... Figure 1 The description is illustrative. The variable N represents a positive integer greater than one, which can vary depending on the specific implementation, and in some instances may take values ​​such as 2, 10, 100, etc. Other types and arrangements of receiver circuitry, including those compatible with... Figure 1 One or more receiver circuits configured in different ways as shown can be included in integrated circuit 200.

[0032] Integrated circuit 200 includes an input / output (I / O) circuit system 202 and an additional circuit system 204 coupled to the I / O circuit system 202. The I / O circuit system 202 further includes a receive path circuit system 210 and a transmit path circuit system 212, wherein receiver circuits 100-1 to 100-N are implemented as part of the receive path circuit system 210. In this example, the additional circuit system 204 includes a power management circuit system 220 and other core circuit systems 230. Besides the receiver circuits 100-1 to 100-N, a wide variety of other types and arrangements of circuit systems can be implemented within integrated circuit 200.

[0033] In some instances, at least a subset of receiver circuits 100-1 to 100-N are from Figure 2 One or more external devices and / or systems (not shown) receive input signals related to the power management functionality of integrated circuit 200 for further processing by power management circuitry system 220. A wide variety of additional or alternative input signals may be received, additionally or alternatively, by at least a portion of receiver circuits 100-1 to 100-N from one or more external devices and / or systems for further processing by other core circuitry system 230. The transmission path circuitry system 212 of I / O circuitry system 202 illustratively includes multiple transmitter circuits (not explicitly shown) for providing output signals generated by processing performed in additional circuitry system 204 from integrated circuit 200 to one or more external devices and / or systems. Many other integrated circuits may be configured to incorporate previously combined... Figure 1 The type of receiver circuit described.

[0034] Figure 3 An example receiver circuit 300 is shown, which illustrates... Figure 1Example implementation of receiver circuit 100. Receiver circuit 300 includes an input node 301, denoted as PAD, and a receiver output, denoted as Y. Receiver circuit 300 further includes a first trigger circuit system 302 and a second trigger circuit system 304. The first trigger circuit system is configured with a first trigger level for a low-to-high transition of an input signal applied to the input node 301 of receiver circuit 300. The second trigger circuit system is arranged at least partially in parallel with the first trigger circuit system 302 and is configured with a second trigger level for a high-to-low transition of the input signal, wherein the second trigger level is different from the first trigger level (e.g., lower than the first trigger level). The respective inputs of the first trigger circuit system 302 and the second trigger circuit system 304 are coupled to the input node 301 of receiver circuit 300, and the respective outputs of the first trigger circuit system 302 and the second trigger circuit system 304 are coupled to the output node of receiver circuit 300, illustratively referred to as a common output node OUT. The common output node OUT is coupled to another output node of the receiver circuit 300, namely the receiver output Y, via latch circuit 305 including inverters IN1 and IN2, inverting level shifter 306 and additional inverter IN3.

[0035] The receiver circuit 300 further includes a protection circuit 307 between the input node 301 and the inputs of the first trigger circuit system 302 and the second trigger circuit system 304. This protection circuit illustratively includes a series arrangement of a first diode D1 and a second diode D2 as shown in the figure. The two diodes D1 and D2 are coupled in series between a lower power terminal and an upper power terminal, illustratively a ground terminal in this example, and an upper power terminal, illustratively a VDDIO power terminal in this example. The anode of the upper diode D1 is coupled to the cathode of the lower diode D2 and to the input node 301, the cathode of the upper diode D1 is coupled to the VDDIO power terminal, and the anode of the lower diode D2 is coupled to the ground terminal. In the event of, for example, an electrostatic discharge (ESD) event at the input node 301, the two diodes D1 and D2 of the protection circuit 307 are used to limit excessive positive and negative voltages at the input node 301 relative to VDDIO and ground, respectively. Such diodes are illustratively implemented as corresponding PN junction diodes with a threshold voltage of approximately 0.7 V, but in other instances, one or more diodes of other types and arrangements, along with other types of protection circuitry, may be used. For example, additional or alternative protection circuitry incorporating various types of Charge Device Model (CDM) protection circuitry may be used in protection circuitry 307.

[0036] The first trigger circuit system 302 and the second trigger circuit system 304 include corresponding first inverters and second inverters, wherein each of the first inverter and the second inverter has an input coupled to the input node 301 of the receiver circuit 300 and an output coupled to the common output node OUT of the receiver circuit 300.

[0037] In this example, the corresponding first inverter and second inverter of the first trigger circuit system 302 and the second trigger circuit system 304 are each implemented using a P-type field-effect transistor (FET) and an N-type FET, respectively, each having a gate terminal, a source terminal, and a drain terminal, and more specifically implemented as P-type and N-type metal-oxide-semiconductor (MOS) FETs, also referred to herein as PMOS devices and NMOS devices, illustratively configured according to a complementary MOS (CMOS) arrangement. In other examples, other types and arrangements of transistors may be used to implement the first inverter and the second inverter.

[0038] The first inverter of the first trigger circuit system 302 includes a PMOS device MP1 and an NMOS device MN1. The output of the first inverter is denoted as OUT1. The first trigger circuit system 302 further includes an enable circuit system implemented by the NMOS device MN2.

[0039] Similarly, the second inverter of the second trigger circuit system 304 includes a PMOS device MP2 and an NMOS device MN3. The output of the second inverter is denoted as OUT2. The second trigger circuit system 304 further includes an enable circuit system implemented by the NMOS device MN4.

[0040] The gate terminals of MP1 and MN1 of the first inverter in the first trigger circuit system 302 are coupled to the input node 301 of the receiver circuit 300. The source terminal of MP1 is coupled to the upper power supply terminal of the receiver circuit 300, illustratively speaking, the VDDIO power supply terminal in this example. The drain terminal of MP1 is coupled to the drain terminal of MN1, and the source terminal of MN1 is coupled to the lower power supply terminal of the receiver circuit 300 via the enable circuit system of the first trigger circuit system 302, illustratively speaking, the ground terminal in this example. More specifically, in the enable circuit system of the first trigger circuit system 302, the gate terminal of MN2 is coupled to the enable signal RXEN, the drain terminal of MN2 is coupled to the source terminal of MN1, and the source terminal of MN2 is coupled to the ground terminal.

[0041] Similarly, the gate terminals of MP2 and MN3 of the second inverter in the second trigger circuit system 304 are coupled to the input node 301 of the receiver circuit 300, the source terminal of MP2 is coupled to the VDDIO power supply terminal, the drain terminal of MP2 is coupled to the drain terminal of MN3, and the source terminal of MN3 is coupled to the ground terminal via the enable circuit system of the second trigger circuit system 304. More specifically, in the enable circuit system of the second trigger circuit system 304, the gate terminal of MN4 is coupled to the enable signal RXEN, the drain terminal of MN4 is coupled to the source terminal of MN3, and the source terminal of MN4 is coupled to the ground terminal.

[0042] The first trigger circuit system 302 further includes an additional PMOS device MP3, which has a gate terminal coupled to the respective drain terminals of MP1 and MN1 of the first inverter at the output OUT1, a source terminal coupled to the VDDIO power supply terminal, and a drain terminal coupled to the common output node OUT of the receiver circuit 300.

[0043] Similarly, the second trigger circuit system 304 further includes an additional NMOS device MN5 having a gate terminal coupled to the respective drain terminals of MP2 and MN3 of the second inverter at the output OUT2, a source terminal coupled to the ground terminal, and a drain terminal coupled to the common output node OUT of the receiver circuit 300.

[0044] The enabling circuit system, including MN2 in the first trigger circuit system 302 and MN4 in the second trigger circuit system 304, is an example of an element of the “control circuit system” more generally referred to herein as the receiver circuit 300. This control circuit system is typically configured to simultaneously enable the first trigger circuit system 302 and the second trigger circuit system 304 in response to an applied control signal, illustratively referred to in this example as the enable signal RXEN. In other examples, other types and arrangements of control circuit systems may be used to enable the first trigger circuit system 302 and the second trigger circuit system 304, possibly in response to other types of control signals. As indicated above, in typical operation of some examples, both the first trigger circuit system 302 and the second trigger circuit system 304 are enabled together; however, in other examples, other operating modes are possible.

[0045] When enabled, the first trigger circuit system 302 is configured to drive the output node of the receiver circuit 300 to one of a logic high level and a logic low level in response to a low-to-high transition of the input signal applied to the input node 301, and the second trigger circuit system 304 is configured to drive the output node of the receiver circuit 300 to the other of a logic high level and a logic low level in response to a high-to-low transition of the input signal applied to the input node 301. More specifically, in this example, the first trigger circuit system 302 is configured to drive the common output node OUT and thereby the receiver output Y to a logic high level in response to a low-to-high transition of the input signal applied to the input node 301, and the second trigger circuit system 304 is configured to drive the common output node OUT and thereby the receiver output Y to a logic low level in response to a high-to-low transition of the input signal applied to the input node 301.

[0046] In some instances, the channel sizes of the corresponding PMOS devices MP1 and NMOS devices MN2 of the first inverter in the first trigger circuit system 302 are configured with a first ratio that at least partially sets the first trigger level, and the channel sizes of the corresponding PMOS devices MP2 and NMOS devices MN3 of the second inverter are configured with a second ratio that at least partially sets the second trigger level, the second ratio being different from the first ratio. For example, the first ratio may be approximately 5:1, and the second ratio may be approximately 1:1, such that the PMOS:NMOS channel size ratio of the first inverter is MP1:MN1 = 5:1, and the PMOS:NMOS channel size ratio of the second inverter is MP2:MN3 = 1:1; however, in other instances, many other ratio values ​​may be used.

[0047] Regarding the aforementioned size design of the inverter transistors in the first trigger circuit system 302 and the second trigger circuit system 304, relative adjustments in the channel size design can be achieved by changing the relative channel width and / or channel length of the PMOS and NMOS devices in each inverter. Some examples utilize a fixed channel length and adjust the channel width. For example, for a given fixed channel length, such as 0.7 micrometers (µm), different ratios can be achieved by adjusting the channel width, illustratively using width / length values ​​and PMOS:NMOS channel size ratios of MP1:MN1=(5 / 0.7):(1 / 0.7) and MP2:MN3=(1.8 / 0.7):(1.8 / 0.7). In other examples, many other types of adjustments to the channel width and / or channel length can be used to set the first trigger level and the second trigger level provided by the respective first trigger circuit system 302 and second trigger circuit system 304.

[0048] In some instances, sizing the corresponding PMOS and NMOS devices of the inverter at a ratio of 2:1 or 3:1 will produce a trigger level at approximately 50% of the supply voltage, and adjustments in the channel size design relative to such a baseline will achieve a trigger level of approximately 66% of the supply voltage for the first trigger circuit system 302 and approximately 33% of the supply voltage for the second trigger circuit system 304. Other examples of channel size ratios that can be used to achieve these or similar trigger levels include an MP1:MN1 ratio of 4:1 or 6:1, and an MP2:MN3 ratio of 1.2:1 or 0.8:1, where the latter example ratio of 0.8:1 indicates that the relative channel size design makes the NMOS device relatively stronger than the PMOS device.

[0049] In some instances, the channel size designs of the first and second inverters in the corresponding first trigger circuit system 302 and second trigger circuit system 304, as described above, are used to set the corresponding first trigger level VIH and second trigger level VIL. For example, for a VDDIO supply voltage of approximately 1.2 V, the first trigger level VIH and the second trigger level VIH can be set to approximately 0.8 V and approximately 0.4 V, respectively. The trigger level VIH is set by the relative channel size design of MP1 and MN1, and the trigger level VIL is set by the relative channel size design of MP2 and MN3. The hysteresis in such instances is typically given by the difference between the first trigger level VIH and the second trigger level VIL. In other instances, other trigger levels and associated hysteresis amounts can be established. For example, the trigger level VIH can be set to a value less than 0.8 V, and the trigger level VIL can be set to a value greater than 0.4 V, while VIH remains higher than VIL to provide the desired hysteresis amount given by VIH-VIL, such as a hysteresis of at least 50 mV.

[0050] The additional PMOS device MP3 of the first trigger circuit system 302 and the additional NMOS device MN5 of the second trigger circuit system 304 illustratively have their respective channel sizes configured in a 2:1 ratio, because such size design in these additional PMOS and NMOS devices does not significantly affect the trigger level. However, in some instances, the relative channel size design of these devices can be adjusted to allow for other adjustments in the receiver output Y of the receiver circuit 300, such as duty cycle adjustment.

[0051] like Figure 3As shown, the substrate connections of the PMOS and NMOS devices in the first and second trigger circuit systems are illustrated as being coupled to the VDDIO power supply terminal or the ground terminal, respectively. Other types of substrate connections may be used in other examples, and such variations can be used to adjust the threshold voltages of the PMOS and NMOS devices.

[0052] Receiver circuitry 300 is configured to operate using input signals up to 5 V, such as input signals with voltage levels varying between approximately zero volts (logo low) and approximately 5 V (logo high). Because input node 301, where the input signal is applied, can swing between zero volts and 5 V in this example, MP1, MN1, MP2, and MN3 are all configured as 5V MOS devices. In other examples, other input signal levels and associated PMOS and NMOS devices may be used.

[0053] As previously indicated, latch circuit 305 includes inverters, denoted as IN1 and IN2, arranged in series at a common output node OUT. The input of inverter IN2 is coupled at the common output node OUT to the outputs of the respective first trigger circuit system 302 and second trigger circuit system 304. The output of inverter IN2 is coupled to the input of inverter IN1, and the output of inverter IN1 is coupled at the common output node OUT to the outputs of the first trigger circuit system 302 and second trigger circuit system 304. This example arrangement provides an element referred to herein as a “weak” latch, configured to hold the common output node OUT at a specific logic level under floating conditions, whereby the additional PMOS device MP3 of the first trigger circuit system 302 is turned off before the additional NMOS device MN5 of the second trigger circuit system 304 is turned on, and vice versa. In the inverters IN1 and IN2 of latch circuit 305, the channel lengths of the PMOS and NMOS devices are approximately 3µm, and the ratio of the corresponding PMOS and NMOS channel sizes in these inverters is approximately (1 / 3):(3 / 3) in inverter IN1 and approximately (3 / 3):(1 / 3) in inverter IN2, depending on both width and length. This makes IN2 a weak inverter relative to inverter IN1, and the channel size variation is achieved by adjusting the channel width for a fixed channel length. In other instances, other types and arrangements of inverters or other latch circuit systems may be used in latch circuit 305.

[0054] The output of latch circuit 305 is coupled to the input of inverting level shifter 306. Inverting level shifter 306 is configured to adjust the receiver output signal value from a level associated with the VDDIO power supply to a level associated with a core voltage power supply, denoted as VCORE. In some instances, the core voltage power supply may be approximately 1.8 V, but in other instances, other core voltage power supply values ​​may be used. Inverting level shifter 306 is illustratively implemented as a cross-coupled level shifter, utilizing techniques such as those disclosed in U.S. Patent No. 10,848,156 cited above. Because inverting level shifter 306 is used in this example, an additional inverter IN3 is included at the output of inverting level shifter 306 to maintain the desired logic level at receiver output Y. In other instances, other types and arrangements of level shifter circuits may be used. For example, a non-inverting level shifter may be used instead of inverting level shifter 306, in which case the additional output inverter IN3 can be eliminated.

[0055] Now refer to Figure 3 as well as Figure 4 and 5 Example timing diagrams to describe Figure 3 Additional aspects of the operation of the receiver circuit 300.

[0056] Now for reference Figure 4 The example timing diagram illustrates the receiver input PAD, the output OUT1 of the upper inverters including MP1 and MN1 in the first trigger circuit system 302, the output OUT2 of the lower inverters including MP2 and MN3 in the second trigger circuit system 304, the common output node OUT, and the corresponding signals for the receiver output Y. In this example, it is assumed that the VDDIO power supply is 1.2 V, and the first trigger level VIH and the second trigger level VIL are 0.8 V and 0.4 V, respectively. It is further assumed that the receiver input PAD changes from a logic low level of approximately zero volts to a logic high level of approximately 5 V.

[0057] When the receiver input PAD transitions from a low-to-high logic level of approximately 0V to a high-to-low logic level of approximately 5V, the receiver input PAD crosses 0.4V. At this point, the output OUT2 of the second inverter switches to a low logic level, thus turning off MN5. Once PAD crosses the VIH trigger level of 0.8V, the output OUT1 of the first inverter switches to a low logic level, thus turning on MP3 and ultimately driving the receiver output Y to a high logic level via latch circuit 305, inverting level shifter 306, and output inverter IN3. Therefore, once PAD crosses the VIH trigger level of 0.8V, the receiver output Y of receiver circuit 300 switches from a low logic level to a high logic level.

[0058] When the receiver input PAD transitions from a logic high of approximately 5V to a logic low of approximately 0V, the receiver input PAD crosses 0.8V. At this point, the output OUT1 of the first inverter switches to a logic high level, thus turning off MP3. Once PAD crosses the VIL trigger level of 0.4V, the output OUT2 of the first inverter switches to a logic high level, thereby turning on MN5 and ultimately driving the receiver output Y to a logic low level via latch circuit 305, inverting level shifter 306, and output inverter IN3. Therefore, once PAD crosses the VIL trigger level of 0.4V, the receiver output Y of receiver circuit 300 switches from a logic high level to a logic low level.

[0059] As previously indicated, latch circuit 305 is illustratively configured to hold the common output node OUT at a specific logic level under floating conditions, in which MP3 is turned off before MN5, and vice versa. As previously indicated, IN2 is a weak inverter, and the channel sizes of IN1 and IN2 are illustratively configured to ensure that when the output OUT1 of the first inverter drops below VDDIO to reach the PMOS device threshold voltage to turn on MP3, the current through MP3 is much larger than the pull-down current of IN1. Similarly, when the output OUT2 of the second inverter reaches the NMOS device threshold voltage to turn on MN5, the current through MN5 is much larger than the pull-up current of IN1.

[0060] In this example, the channel size ratio of MP1:MN1 in the first inverter is illustratively about 5:1 to set the VIH trigger level to about 0.8 V, and the channel size ratio of MP2:MN3 in the second inverter is illustratively about 1:1 to set the VIL trigger level to about 0.4 V. Similarly, other ratios can be used in other examples. For example, the channel size ratio can be adjusted such that the VIH trigger level is greater than about 0.5 * VDDIO, and the VIL trigger level is less than about 0.5 * VDDIO, wherein the desired hysteresis (e.g., at least 50 mV) is provided by the difference between VIH and VIL.

[0061] Now for reference Figure 5The example timing diagram shows the receiver input signal 501 applied to the input node 301 of the receiver circuit 300, with the corresponding receiver output signal 502 superimposed on the receiver input signal 501 to more clearly illustrate the first trigger level VIH and the second trigger level VIL established by the corresponding first trigger circuit system 302 and second trigger circuit system 304. The receiver input signal 501 and the receiver output signal 502 are also represented as input PAD and output Y. In this example, it is assumed that the specification values ​​of VIH_Spec and VIL are 800 mV (0.8 V) and 400 mV (0.4 V), respectively, as in... Figure 5 The horizontal dashed lines 504 and 506 indicate this. For example, the corresponding specification of receiver circuit 300 may indicate that the receiver circuit provides a VIH trigger level less than about VIH_Spec = 0.8 V and a VIL trigger level greater than about VIL_Spec = 0.4 V, with at least a minimum hysteresis (e.g., 50 mV) for a VDDIO supply voltage of about 1.2 V and for a receiver input signal with a voltage magnitude of up to about 5 V. In this example, the actual value of the VIH trigger level is less than the VIH specification value VIH_Spec value 514 (e.g., about 704 mV), and the actual value of the VIL trigger level is greater than the VIL specification value VIL_Spec value 516 (e.g., about 533 mV), for Figure 5 The approximately 2 V input PAD logic high level shown has a hysteresis (e.g., approximately 171 mV) given by the difference between values ​​514 and 516.

[0062] As indicated above, other types and arrangements of first and second trigger circuit systems can be used to implement the receiver circuits disclosed herein. For example, a first Schmitt trigger circuit and a second Schmitt trigger circuit can be used instead of the first inverters and second inverters of the corresponding first and second trigger circuit systems used to set the corresponding first and second trigger levels of the receiver circuit, as will now be referred to. Figure 6 The examples are described in more detail.

[0063] Figure 6 A receiver circuit 600 with parallel trigger circuitry systems is shown, including a first trigger circuitry system 602 and a second trigger circuitry system 604. In addition to the first trigger circuitry system 602 and the second trigger circuitry system 604, the receiver circuit 600 may further include input pads, an enable circuitry system, latch circuitry, and a level shifter circuitry, wherein these additional components are combined as previously described. Figure 1 The receiver circuit 100 is arranged as described, but for the sake of simplicity and clarity, from... Figure 6 Such additional components are omitted. The operation of the receiver circuit 600 is also the same as previously described. Figure 1 The operation of the receiver circuit 100 is generally the same, but in this example, the first trigger circuit system 602 and the second trigger circuit system 604 more specifically include corresponding different examples of Schmitt trigger circuits. The respective Schmitt trigger circuits of the first trigger circuit system 602 and the second trigger circuit system 604 are used to set a corresponding first trigger level (e.g., VIH level) for a low-to-high transition of the input signal applied to the input pads of the receiver circuit 600 and a second trigger level (e.g., VIL level) for a high-to-low transition of the input signal applied to the input pads.

[0064] like Figure 6 As shown, the first trigger circuit system 602 includes a first Schmitt trigger circuit 605, and the second trigger circuit system 604 includes a second Schmitt trigger circuit 610. The second Schmitt trigger circuit 610 more specifically includes a second example of the first Schmitt trigger circuit 605, but with different MOS channel size designs of one or more MOS devices to provide a trigger level different from the trigger level provided by the first example of the Schmitt trigger circuit 605 in the first trigger circuit system 602. Therefore, in this example, independent and different examples of the Schmitt trigger circuit 605 are illustratively implemented in each of the first trigger circuit system 602 and the second trigger circuit system 604. Each such example of the Schmitt trigger circuit 605 includes, as... Figure 6 The figure shows the arrangement of input nodes IN, output nodes OUT, PMOS devices P1, P2, and P3, and NMOS devices N1, N2, and N3, wherein the PMOS and NMOS devices are arranged between the VDDIO power supply terminal and the ground terminal, as shown. A first example of the Schmitt trigger circuit 605 in the first trigger circuit system 602 is configured with a first trigger level for a low-to-high transition of the input signal applied to the input pad of the receiver circuit 600, and a second example of the Schmitt trigger circuit 605 in the second trigger circuit system 604 is configured with a second trigger level for a high-to-low transition of the input signal applied to the input pad of the receiver circuit 600.

[0065] In some instances, two different examples of the Schmitt trigger circuit 605 are adapted to achieve a trigger level of approximately 66% of the VDDIO supply voltage for the first trigger circuit system 602 and approximately 33% of the VDDIO supply voltage for the second trigger circuit system 604, relative to a baseline configuration that provides a trigger level at approximately 50% of the VDDIO supply voltage. For example, the trigger level of the first example of the Schmitt trigger circuit 605 in the first trigger circuit system 602 is established by increasing the channel size ratio of P1 and P2 relative to N1 and N2 and / or by using a relatively large channel size for N3. Similarly, the trigger level of the second example of the Schmitt trigger circuit 605 in the second trigger circuit system 604 is established by decreasing the channel size ratio of P1 and P2 relative to N1 and N2 and / or by using a relatively small channel size for N3, compared to the baseline configuration presented above. The relative channel size design will vary depending on factors such as the manufacturing technology used, the power supply voltage, the specific VIH trigger level and VIL trigger level, and the amount of hysteresis required in a given implementation.

[0066] The examples described herein provide receiver circuits configured with independent first and second trigger circuit systems, which are arranged at least partially in parallel with each other to provide corresponding VIH and VIL trigger levels. Such receiver circuits can advantageously operate using I / O supply voltages (e.g., 1.2 V) significantly smaller than the maximum input signal voltage swing (e.g., 5 V), while also providing suitable hysteresis and sinking negligible quiescent current. As previously indicated, such examples provide a technical solution to the apparent problems of alternative approaches by overcoming the challenges that might arise when attempting to configure receiver circuits to operate at relatively low VDDIO supply voltage levels while also accommodating relatively high input signal swings and providing the desired hysteresis at low quiescent current.

[0067] Now for reference Figure 7 This illustrates a method for operating receiver circuitry. The method includes illustrative references. Figure 1 The receiver circuit 100 performs steps 700, 702, 704, and 706, but the same or similar steps may be performed relative to other receiver circuits described herein (including...). Figure 3 The receiver circuit 300) is executed.

[0068] In step 700, the first trigger circuit system of the receiver circuit is configured with a first trigger level for the low-to-high transition of the input signal applied to the input node of the receiver circuit.

[0069] In step 702, a second triggering circuit system, at least partially arranged in parallel with the first triggering circuit system, is configured with a second triggering level for a high-to-low transition of the input signal, the second triggering level being different from the first triggering level.

[0070] The terms “configured” and “configuring” used in this context and other similar contexts herein are intended to be understood broadly and should not be construed as implying or requiring any type of user selection or other user-based control over the trigger level of the trigger circuit system. For example, the specific trigger level described herein can be illustratively configured for the trigger circuit system by generating the described trigger circuit system, obtaining the described trigger circuit system, and / or activating the described trigger circuit system at least in part by applying an appropriate supply voltage to the trigger circuit system.

[0071] In some instances, the configuration of steps 700 and 702 may be performed at least in part by generating, obtaining, and / or activating receiver circuitry 100 having a first trigger circuitry system 102 and a second trigger circuitry system 104 that implement the corresponding VIH and VIL trigger levels described previously.

[0072] In step 704, in response to the applied control signal, both the first and second trigger circuit systems are simultaneously enabled. For example, this can be achieved by setting an appropriate logic level (e.g., at...). Figure 3 In the case of receiver circuit 300 (which is at a logic high level), the receiver enable signal RXEN described above is applied to the enable circuit of each of the first and second trigger circuit systems of the receiver circuit to simultaneously enable the first and second trigger circuit systems.

[0073] In step 706, the input signal applied to the input node of the receiver circuit is processed in the receiver circuit to generate a corresponding output signal. For example, the receiver input signal PAD is illustratively processed to generate the receiver output signal Y, such as... Figure 4 and 5 As shown in the timing diagram.

[0074] Although shown in serial order, Figure 7 The steps of the methods and other methods described herein need not be performed in the specific order shown. For example, some steps may be performed at least partially in parallel with each other, and additional or alternative steps may be used in other instances.

[0075] Now for reference Figure 8 This paper illustrates a method for manufacturing an integrated circuit comprising multiple receiver circuits. The method includes illustrative references. Figure 2At least one example of integrated circuit 200 performs steps 800, 802 and 804, but the same or similar steps may be performed relative to other integrated circuits described herein.

[0076] In step 800, a receiver circuit is formed on the semiconductor substrate of the integrated circuit. Each of one or more receiver circuits includes a first trigger circuit system and a second trigger circuit system. The first trigger circuit system is configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit. The second trigger circuit system is arranged at least partially in parallel with the first trigger circuit system and is configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level.

[0077] For example, forming a first trigger circuit system illustratively includes corresponding P-type field-effect transistors and N-type field-effect transistors forming a first inverter of a first trigger circuit system 102, the corresponding P-type field-effect transistors and N-type field-effect transistors having channel sizes at least partially setting a first trigger level, and forming a second trigger circuit system includes corresponding P-type field-effect transistors and N-type field-effect transistors forming a second inverter of a second trigger circuit system 104, the corresponding P-type field-effect transistors and N-type field-effect transistors having channel sizes at least partially setting a second trigger level, the second ratio being different from the first ratio.

[0078] In step 802, an additional circuit system is formed on the semiconductor substrate of the integrated circuit, to which multiple receiver circuits are coupled. For example, the additional circuit system may include... Figure 2 The power management circuit system 220 and / or other core circuit system 230 shown are illustrated.

[0079] Such additional circuitry can be formed at least partially concurrently with the formation of the receiver circuitry in step 800. These formation steps illustratively utilize semiconductor process techniques of the type previously described herein.

[0080] In step 804, the integrated circuit, which includes multiple receiver circuits and additional circuitry, is packaged. For example, in the case of multiple integrated circuits formed on a semiconductor wafer, individual integrated circuits are diced from the wafer. Each individual integrated circuit then undergoes additional operations such as leadframe attachment, wire bonding, and encapsulation, and is subsequently packaged in an appropriate package, such as a single in-line package (SIP), a dual in-line package (DIP), a quad flat no-lead (QFN) package, a double-sided flat no-lead (DFN) package, a chip-on-lead (COL) package, etc.

[0081] Similarly, although shown in serial order, Figure 8 The steps of the method need not be performed in the specific order shown. For example, some steps, such as steps 800 and 802 that form the corresponding receiver circuit and additional circuit system, may be performed at least partially in parallel with each other, and additional or alternative steps may be used in other instances.

[0082] Furthermore, although various features or components have been shown to have a particular arrangement or configuration according to the illustrated embodiments, other arrangements and configurations are also possible. Moreover, aspects of the inventive technology described in the context of the exemplary embodiments may be combined or eliminated in other embodiments. Therefore, the breadth and scope of the description are not limited to any of the embodiments described above.

Claims

1. A receiver circuit, comprising: A first trigger circuit system is configured with a first trigger level for a low-to-high transition of an input signal applied to the input node of the receiver circuit; as well as A second trigger circuit system, which is at least partially arranged in parallel with the first trigger circuit system, and is configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level; The corresponding inputs of the first trigger circuit system and the second trigger circuit system are coupled to the input node of the receiver circuit, and the corresponding outputs of the first trigger circuit system and the second trigger circuit system are coupled to the output node of the receiver circuit.

2. The receiver circuit of claim 1, further comprising a control circuit system configured to simultaneously enable the first trigger circuit system and the second trigger circuit system in response to an applied control signal.

3. The receiver circuit of claim 1, wherein the first trigger circuit system is configured to drive the output node of the receiver circuit to one of a logic high level and a logic low level in response to the low-to-high transition of the input signal, and the second trigger circuit system is configured to drive the output node of the receiver circuit to the other of the logic high level and the logic low level in response to the high-to-low transition of the input signal.

4. The receiver circuit of claim 1, wherein the first trigger circuit system and the second trigger circuit system comprise respective first inverters and second inverters, each of the first inverters and the second inverters having an input coupled to the input node of the receiver circuit and an output coupled to the output node of the receiver circuit.

5. The receiver circuit of claim 4, wherein each of the first inverter and the second inverter includes a first P-type field-effect transistor and a first N-type field-effect transistor, each field-effect transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal being coupled to the input node of the receiver circuit, the source terminal of the first P-type field-effect transistor being coupled to an upper power supply terminal of the receiver circuit, the drain terminal of the first P-type field-effect transistor being coupled to the drain terminal of the first N-type field-effect transistor, and the source terminal of the first N-type field-effect transistor being coupled to a lower power supply terminal of the receiver circuit.

6. The receiver circuit of claim 5, wherein the first trigger circuit system further includes an additional P-type field-effect transistor having a gate terminal coupled to the respective drain terminals of the first P-type field-effect transistor and the first N-type field-effect transistor of the first inverter, a source terminal coupled to the upper power supply terminal, and a drain terminal coupled to the output node of the receiver circuit.

7. The receiver circuit of claim 5, wherein the second trigger circuit system further includes an additional N-type field-effect transistor having a gate terminal coupled to the respective drain terminals of the first P-type field-effect transistor and the first N-type field-effect transistor of the second inverter, a source terminal coupled to the lower power supply terminal, and a drain terminal coupled to the output node of the receiver circuit.

8. The receiver circuit of claim 4, wherein the channel sizes of the respective P-type field-effect transistors and N-type field-effect transistors of the first inverter are configured with a first ratio that at least partially sets the first trigger level, and the channel sizes of the respective P-type field-effect transistors and N-type field-effect transistors of the second inverter are configured with a second ratio that at least partially sets the second trigger level, the second ratio being different from the first ratio.

9. The receiver circuit of claim 8, wherein the first ratio is between approximately 4:1 and approximately 6:1, and the second ratio is between approximately 0.8:1 and approximately 1.2:

1.

10. The receiver circuit of claim 1, wherein the first trigger circuit system and the second trigger circuit system comprise respective first Schmitt trigger circuits and second Schmitt trigger circuits, wherein the respective first trigger level and second trigger level are configured at least in part based on the utilization of different channel sizes for respective corresponding field-effect transistors in the first Schmitt trigger circuit and the second Schmitt trigger circuit.

11. The receiver circuit of claim 1, further comprising a level shifter coupled between the outputs of the respective first and second trigger circuit systems and the output node of the receiver circuit.

12. The receiver circuit of claim 1, further comprising a latch circuit coupled between the output of the respective first trigger circuit system and the second trigger circuit system and the output node of the receiver circuit.

13. The receiver circuit of claim 12, wherein the latch circuit comprises a plurality of inverters arranged in series, wherein the input of a first inverter of the plurality of inverters is coupled to the output of a corresponding first trigger circuit system and a second trigger circuit system, the output of the first inverter of the plurality of inverters is coupled to the input of another inverter of the plurality of inverters, and the output of the other inverter of the plurality of inverters is coupled to the output of the first trigger circuit system and the second trigger circuit system.

14. The receiver circuit of claim 12, wherein the output of the latch circuit is coupled to the input of the level shifter circuit, and the output of the level shifter circuit is coupled to the output node of the receiver circuit.

15. An integrated circuit, comprising: Multiple receiver circuits; as well as Additional circuitry system coupled to the plurality of receiver circuits; At least one of the receiver circuits said to include: A first trigger circuit system is configured with a first trigger level for a low-to-high transition of an input signal applied to the input node of the receiver circuit; and A second trigger circuit system, which is at least partially arranged in parallel with the first trigger circuit system, and is configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level; The corresponding inputs of the first trigger circuit system and the second trigger circuit system are coupled to the input node of the receiver circuit, and the corresponding outputs of the first trigger circuit system and the second trigger circuit system are coupled to the output node of the receiver circuit.

16. The integrated circuit of claim 15, wherein the first trigger circuit system is configured to drive the output node of the corresponding receiver circuit to one of a logic high level and a logic low level in response to the low-to-high transition of the input signal, and the second trigger circuit system is configured to drive the output node of the corresponding receiver circuit to the other of the logic high level and the logic low level in response to the high-to-low transition of the input signal.

17. The integrated circuit of claim 15, wherein the first trigger circuit system and the second trigger circuit system comprise respective first inverters and second inverters, each of the first inverters and the second inverters having an input coupled to the input node of the corresponding receiver circuit and an output coupled to the output node of the corresponding receiver circuit.

18. The integrated circuit of claim 17, wherein the channel sizes of the respective P-type field-effect transistors and N-type field-effect transistors of the first inverter are configured with a first ratio that at least partially sets the first trigger level, and the channel sizes of the respective P-type field-effect transistors and N-type field-effect transistors of the second inverter are configured with a second ratio that at least partially sets the second trigger level, the second ratio being different from the first ratio.

19. A method for manufacturing an integrated circuit, comprising: Multiple receiver circuits are formed; as well as Forming an additional circuit system; The receiver circuitry is coupled to the additional circuitry system. and Each of the one or more receiver circuits forming the receiver circuit includes: A first trigger circuit system is formed, which is configured with a first trigger level for a low-to-high transition of an input signal applied to the input node of the receiver circuit; A second trigger circuit system is formed, which is arranged in parallel with the first trigger circuit system at least in part, and is configured with a second trigger level for the high-to-low transition of the input signal, the second trigger level being different from the first trigger level; The corresponding inputs of the first trigger circuit system and the second trigger circuit system are coupled to the input node of the receiver circuit, and the corresponding outputs of the first trigger circuit system and the second trigger circuit system are coupled to the output node of the receiver circuit.

20. The method of claim 19, wherein forming the first trigger circuit system includes corresponding P-type field-effect transistors and N-type field-effect transistors forming the first inverter of the first trigger circuit system, the corresponding P-type field-effect transistors and N-type field-effect transistors having channel sizes at least partially setting the first trigger level, and forming the second trigger circuit system includes corresponding P-type field-effect transistors and N-type field-effect transistors forming the second inverter of the second trigger circuit system, the corresponding P-type field-effect transistors and N-type field-effect transistors having channel sizes at least partially setting the second trigger level, the second ratio being different from the first ratio.

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