Resistance and inductance parameter extraction method and device, computer equipment and storage medium

Abstract

The invention discloses a resistance and inductance parameter extraction method and device, computer equipment and a storage medium, and the method is based on a generalized centroid basis function conversion method, supports a global non-conformal grid of a triangle and a bilinear surface, and is compatible with rapid algorithm configuration and preprocessing. According to the method, mass center basis function conversion is generalized, vector bit integral calculation of a non-conformal surface grid can be converted into scalar bit integral calculation of a monopole mode, and current direction information is extracted into a sparse matrix at a time. By applying the method provided by the invention, the obtained linear system core matrix can be directly used for fast algorithm configuration and is adaptive to a global non-conformal grid at the same time.

Description

Technical Field

[0001] This application relates to a method, apparatus, computer device, and storage medium for extracting resistance and inductance parameters that supports global non-conformal meshes, and belongs to the field of algorithm optimization for parasitic parameter extraction. Background Technology

[0002] In power integrity analysis of advanced package structures (such as interposers), their wiring layers typically contain a globally distributed array of vias. If traditional conformal meshing techniques are used for electromagnetic simulation, these dense vias fragment the continuous metal layer structure, resulting in a large number of low-quality fine meshes in the vicinity of the vias. This not only drastically increases the dimensionality of the system matrix but also severely degrades its behavior, significantly reducing the convergence speed of solving linear systems and even causing solution failure.

[0003] To address the challenges of non-conformal meshes, existing technologies primarily employ schemes combining them with the Domain Decomposition Method (DDM) to achieve localized non-conformal meshes. Common methods include: (1) Discontinuous Galerkin method: This method requires setting a penalty term on the interface of different subdomains to control the solution accuracy. Its effect depends heavily on the selection of the penalty factor, which increases the complexity and uncertainty of the algorithm.

[0004] (2) Multi-branch RWG basis function method: The basis function construction process of this method is extremely complex, difficult to implement, and has high computational overhead.

[0005] However, a common limitation of the two methods mentioned above is that their non-conformal meshes can only appear at the interfaces between pre-divided subdomains, thus belonging to local non-conformal meshing. For the special structure of advanced packaging where via arrays are distributed globally, it is impossible to use the domain decomposition method to effectively divide the simulation region into multiple independent subdomains. Therefore, existing DDM-based local non-conformal meshing techniques are no longer applicable to such problems.

[0006] Against this backdrop, global non-conformal meshing technology, capable of freely applying non-conformal meshes throughout the entire simulation domain, has become an essential requirement. The method proposed in this application is currently the only resistance and inductance parameter extraction technique that supports global non-conformal meshing, perfectly solving the mesh generation problem in advanced packaging structure simulation. Summary of the Invention

[0007] In view of this, this application provides a method, apparatus, computer device and storage medium for extracting resistance and inductance parameters. The linear system core matrix obtained in the embodiments of this application can be directly used for fast algorithm configuration and is also compatible with global non-conformal meshes.

[0008] The first aspect of this application discloses a method for extracting resistance and inductance parameters, the method comprising: The conductor surface is divided into surface elements, which are mixed surface elements of triangles and bilinear surfaces; Construct a sparse mapping matrix from the loop to the surface element; Discrete conductor surface current based on centroid basis functions; The current of the loop is mapped onto the surface element based on the sparse mapping matrix; Construct the precondition matrix; Accelerate matrix-vector multiplication based on the aforementioned face element configuration FMM algorithm; Post-processing yields the resistance and inductance parameters.

[0009] The subdivision forms a non-conformal mesh; the mapping of the current of the loop onto the surface element based on the sparse mapping matrix includes: Based on the sparse mapping matrix, the loop current is mapped to the surface element, and the current directionality is extracted to the matrix element at once during the mapping process, so that the vector potential integral of the non-conformal mesh is transformed into the scalar potential integral of the monopole mode.

[0010] A second aspect of this application discloses a resistance and inductance parameter extraction device, the device comprising: A partitioning module is used to partition the conductor surface into facets, wherein the facets are a mixture of triangular and bilinear surface facets; The first construction module is used to construct a sparse mapping matrix from the loop to the surface element; Discrete module for discretizing conductor surface currents based on centroid basis functions; A mapping module is used to map the current of the loop onto the surface element based on the sparse mapping matrix; The second building module is used to build the precondition matrix; The configuration module is used to accelerate matrix-vector multiplication using the FMM algorithm based on the surface element configuration. The post-processing module is used to obtain resistance and inductance parameters through post-processing.

[0011] The subdivision forms a non-conformal mesh; the mapping of the current of the loop onto the surface element based on the sparse mapping matrix includes: Based on the sparse mapping matrix, the loop current is mapped to the surface element, and the current directionality is extracted to the matrix element at once during the mapping process, so that the vector potential integral of the non-conformal mesh is transformed into the scalar potential integral of the monopole mode.

[0012] A third aspect of this application discloses a computer-readable storage medium comprising a stored program, wherein the program, when running, controls the execution of the resistance and inductance parameter extraction method of the above embodiments in a processor of the device.

[0013] A fourth aspect of this application discloses a computer device, the computer device including a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed by the above-described method for extracting resistance and inductance parameters.

[0014] Compared with the prior art, the embodiments of this application have the following beneficial effects: This application provides a revolutionary resistance and inductance parameter extraction scheme, whose core advantage lies in its first-ever effective support for globally non-conformal meshes. Compared to existing techniques that rely on domain decomposition and can only handle local non-conformal meshes (such as the discontinuous Galerkin method or the multi-branch RWG basis function method), this technique breaks through the limitations of subdomain partitioning and can directly handle complex scenarios such as advanced packaging structures with via arrays distributed globally.

[0015] Specifically, this application employs an innovative mesh processing and current mapping mechanism: 1) Breakthrough mesh adaptability: This method allows the conductor surface to be discretized into a non-conformal mesh combination of triangles and bilinear quadrilaterals without ensuring that the mesh nodes are aligned globally, thus avoiding mesh fragmentation and quality degradation caused by global vias.

[0016] 2) Efficient computation process: Through a generalized basis function transformation technique, the complex vector bit integral calculation is simplified into a more efficient monopole mode scalar bit integral calculation. This transformation makes the core matrix of the system free of directional information, resulting in higher compressibility.

[0017] 3) Natural compatibility with fast algorithms: The integral format of the obtained system matrix is ​​naturally compatible with fast algorithms such as the Fast Multipole Model (FMM), allowing for direct configuration and acceleration without complex vector decomposition operations, significantly improving computational efficiency. In preconditioning and other stages, computation time can be reduced by several to tens of times compared to traditional methods.

[0018] In summary, the global non-conformal mesh technology provided in this application is the optimal solution for efficient and accurate electromagnetic simulation of multi-scale, highly complex structures in current and future advanced integrated circuit packaging. (See attached figures.) To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a method for extracting resistance and inductance parameters provided in an embodiment of this application.

[0020] Figure 2 This is a schematic diagram of an algorithm for generating three mapping matrices provided in an embodiment of this application.

[0021] Figure 3 This is a structural diagram of a resistance and inductance parameter extraction device provided in an embodiment of this application. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] Example 1: Figure 1 This is a flowchart illustrating a method for extracting resistance and inductance parameters provided in an embodiment of this application. Figure 1 As shown, the method includes: S101. Divide the conductor surface into surface elements, wherein the surface elements are a mixture of triangular and bilinear surface elements.

[0025] In this step, such as Figure 2 As shown, the surface is divided into triangular and bilinear surface hybrid elements, wherein the number of elements is... The number of edges is The number of loop currents is The red arrows in the diagram indicate the direction of the local current base. A bilinear surface can be constructed by piecing together any quadrilateral (rectangle, parallelogram, or general quadrilateral).

[0026] S102. Construct a sparse mapping matrix from the loop to the surface element.

[0027] In this step, the construction of the sparse mapping matrix from the loop to the surface element includes: S1021 obtained the faceplate. All current vectors , k It is a face element The index above, i It is the index of the face element.

[0028] S1022 If the circuit l Sweep the edge k 1 and k 2, and the current vector The direction is the same as the direction of the loop current, and the current vector... If the direction of the current is opposite to the direction of the loop current, then the three sparse matrices are represented as: , , .in, x, y, z Representing the current vector x - ，y - ，z - Components.

[0029] S103. Discrete conductor surface current based on centroid basis function.

[0030] S104. Map the current of the loop onto the surface element based on the sparse mapping matrix.

[0031] In this step, a non-conformal mesh is formed by partitioning; the step of mapping the current of the loop onto the surface element based on the sparse mapping matrix includes: Based on the sparse mapping matrix, the loop current is mapped to the surface element, and the current directionality is extracted to the matrix element at once during the mapping process, so that the vector potential integral of the non-conformal mesh is transformed into the scalar potential integral of the monopole mode.

[0032] Specifically, the linear equations for solving the resistance and inductance parameters using loop current analysis are transformed into: ; Where P represents a scalar bit integral matrix based on surface elements. Represents the equivalent surface impedance. Indicates the loop current. Indicates the circuit voltage. T Represents the transpose of a matrix; ; in, , , .

[0033] S105. Construct the precondition matrix.

[0034] In this step, the preconditioning matrix is ​​constructed using only the diagonal elements of the P matrix, which can save 9-16 times the computation time compared to the traditional edge-based preconditioning matrix.

[0035] S106. Accelerate matrix-vector multiplication using the FMM algorithm based on the surface element configuration.

[0036] In this step, the FMM algorithm is a mature and classic algorithm, which will not be elaborated here. The following are the advantages of calling the FMM algorithm in this embodiment: (1) Direct call, no need for internal decomposition of edge current. (2) Processing surface elements, saving 1.5-2 times the calculation time compared with the existing technology. (3) The near-field integral calculation of FMM, converting the vector potential integral to the scalar potential integral can save 9-16 times the calculation time.

[0037] It is worth noting that, through the transformation in step S104 above, only the Fast Multipole Algorithm is used to accelerate matrix-vector multiplication. Taking triangulation as an example, the number of edges is 1.5 times the number of face elements. This operation reduces the number of operations in the Fast Multipole algorithm by 1.5 times. Furthermore, the Fast Multipole algorithm itself is designed for impulse functions, and the new formula in S104 directly uses the Fast Multipole algorithm without any vector decomposition. In addition, the direct solution complexity of the Fast Multipole algorithm is reduced, and the integral calculation is further accelerated by converting it to scalar bitwise integration.

[0038] It should be noted that scalar bit integrals are 9-16 times faster than vector bit integrals (vector bit integrals require searching the edges of each of the two facets; if they are two triangular facets, the number of edge combinations is 9, and if they are rectangular facets, the number of edge combinations is 16). The number of edges is generally 1.5-2 times the number of facets.

[0039] S107. Post-processing yields resistance and inductance parameters.

[0040] This embodiment applies a generalized centroid basis function transformation, supporting globally non-conformal meshes for the first time. Furthermore, the core matrix is ​​generated by impulse basis functions, resulting in higher matrix compressibility, and the integral format of the matrix elements is naturally adapted to the Fast Multipole Algorithm.

[0041] Example 2: Figure 3 This is a structural diagram of a resistance and inductance parameter extraction device provided in an embodiment of this application. Figure 3 As shown, the device includes: The partitioning module 301 is used to partition the conductor surface into surface elements, wherein the surface elements are a mixture of triangular and bilinear surface elements.

[0042] The first construction module 302 is used to construct a sparse mapping matrix from the loop to the surface element.

[0043] Discrete module 303 is used to discrete conductor surface current based on centroid basis functions.

[0044] The mapping module 304 is used to map the current of the loop onto the surface element based on the sparse mapping matrix.

[0045] The second building module 305 is used to build the precondition matrix.

[0046] Configuration module 306 is used to accelerate matrix-vector multiplication based on the FMM algorithm configured for the surface element.

[0047] The post-processing module 307 is used to obtain the resistance and inductance parameters through post-processing.

[0048] Example 3: Embodiments of this application also provide a computer device, including: a memory storing an executable program; and a processor for running the program, wherein the program executes the methods in various embodiments of the present invention during runtime.

[0049] The aforementioned memory can refer to devices inside a computer used to store data and programs, including RAM, hard disks, etc. RAM can be used to temporarily store running programs and data, while hard disks can be used to store programs and data long-term. Memory enables the computer to read and write data and execute programs. The aforementioned processor is responsible for executing instructions in computer programs and performing data processing. It can also be responsible for controlling and executing various operations, including arithmetic operations, logical operations, and data transmission.

[0050] Example 4: Embodiments of this application also provide a computer-readable storage medium including a stored executable program, wherein, when the executable program is running, it controls the device where the computer-readable storage medium is located to perform the methods of various embodiments of the present invention.

[0051] The aforementioned computer storage media can refer to the media used in computer memory to store certain discontinuous physical quantities. Computer storage media mainly include semiconductors, magnetic cores, magnetic drums, magnetic tapes, laser discs, etc. Computer-readable storage media include stored programs, which can be a set of instructions that a computer can recognize and execute, running on an electronic computer to meet certain information needs.

[0052] Example 5: Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the methods of various embodiments of the present invention.

[0053] The aforementioned computer program products can refer to software programs that have been written, tested, and released, and can run on computers or other devices. Computer program products can include application programs, operating systems, utility software, etc., used to achieve specific functions or solve specific problems.

[0054] Example 6: Embodiments of this application also provide a computer program product, including a non-volatile computer-readable storage medium for storing a computer program that, when executed by a processor, implements the methods in various embodiments of the present invention.

[0055] The aforementioned non-volatile computer-readable storage medium can refer to a medium for storing data. Non-volatile computer-readable storage media can retain data without loss when power is off and can be used to store long-term data, such as operating systems, applications, and user files. Non-volatile storage media can include hard disk drives, solid-state drives, optical disks, and flash memory storage devices, etc.

[0056] Example 7: Embodiments of this application also provide a computer program that, when executed by a processor, implements the methods described in the various embodiments of the present invention.

[0057] The aforementioned computer program can refer to a set of instructions used to tell the computer to perform specific tasks or operations. Computer programs can be written by programmers using specific programming languages ​​and can include algorithms, data structures, logic, and control flow. Computer programs can be used for a variety of purposes, including application software, operating systems, etc.

[0058] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0059] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0060] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0061] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0062] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0063] In summary, this application provides a method for extracting resistance and inductance parameters using a globally non-conformal grid. This method involves discretizing the conductor surface into a non-conformal combination of triangular and bilinear quadrilateral elements. Through generalized centroid basis function transformation, while discretizing the surface current using impulse basis functions, the current continuity between non-conformal grids is ensured. The resulting system matrix does not contain directional information, exhibits higher compressibility, and its integral scheme is naturally adapted to the fast multipole method.

[0064] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for extracting resistance and inductance parameters, characterized in that, include: The conductor surface is divided into surface elements, which are mixed surface elements of triangles and bilinear surfaces; Construct a sparse mapping matrix from the loop to the surface element; Discrete conductor surface current based on centroid basis functions; The current of the loop is mapped onto the surface element based on the sparse mapping matrix; Construct the precondition matrix; Accelerate matrix-vector multiplication based on the aforementioned face element configuration FMM algorithm; Post-processing yields the resistance and inductance parameters.

2. The method for extracting resistance and inductance parameters according to claim 1, characterized in that, The sparse mapping matrix from the constructed loop to the surface element includes: Obtain face value All current vectors , k It is a face element The index above, i It is the index of the face element; If the loop l Sweep the edge k 1 and k 2, and the current vector The direction is the same as the direction of the loop current, and the current vector... If the direction of the current is opposite to the direction of the loop current, then the three sparse matrices are represented as: , , ; in, x, y, z Representing the current vector x - ，y - ，z - Components.

3. The method for extracting resistance and inductance parameters according to claim 2, characterized in that, The step of mapping the current of the loop onto the surface element based on the sparse mapping matrix includes: The linear equations for solving the resistance and inductance parameters using loop current analysis are transformed into: ； Where P represents a scalar bit integral matrix based on surface elements. Represents the equivalent surface impedance. Indicates the loop current. Indicates the circuit voltage. T Represents the transpose of a matrix; ； in, , , .

4. The method for extracting resistance and inductance parameters according to claim 1, characterized in that, The subdivision forms a non-conformal mesh; the mapping of the current of the loop onto the surface element based on the sparse mapping matrix includes: Based on the sparse mapping matrix, the loop current is mapped to the surface element, and the current directionality is extracted to the matrix element at once during the mapping process, so that the vector potential integral of the non-conformal mesh is transformed into the scalar potential integral of the monopole mode.

5. The method for extracting resistance and inductance parameters according to any one of claims 1-4, characterized in that, The sparse mapping matrix The dimension is , Indicates the number of loop currents. Indicates the number of face cells.

6. The method for extracting resistance and inductance parameters according to any one of claims 1-4, characterized in that, The conductor surface is discretized by triangular and bilinear surfaces, and non-conformal meshes are allowed between the facets.

7. The method for extracting resistance and inductance parameters according to any one of claims 1-4, characterized in that, The sparse mapping matrix Includes non-zero elements, wherein the row index of the non-zero element corresponds to the loop current number and the column index corresponds to the surface element edge number; When the loop sweeps across two edges of a surface element, let the local current base on one edge... The direction is the same as the loop current direction, and the local current base on the other side The direction is opposite to the direction of the loop current; The non-zero element is of x , y , z Quantity.

8. A device for extracting resistance and inductance parameters, characterized in that, include: A partitioning module is used to partition the conductor surface into facets, wherein the facets are a mixture of triangular and bilinear surface facets; The first construction module is used to construct a sparse mapping matrix from the loop to the surface element; Discrete module for discretizing conductor surface currents based on centroid basis functions; A mapping module is used to map the current of the loop onto the surface element based on the sparse mapping matrix; The second building module is used to build the precondition matrix; The configuration module is used to accelerate matrix-vector multiplication using the FMM algorithm based on the surface element configuration. The post-processing module is used to obtain resistance and inductance parameters through post-processing.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the resistance and inductance parameter extraction method as described in any one of claims 1-7.

10. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the resistance and inductance parameter extraction method as described in any one of claims 1-7.

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