Method, device and equipment for measuring performance reliability of power semiconductor device and medium

Abstract

The invention provides a power semiconductor device performance reliability measurement method, device and equipment and a medium, and the method comprises the steps: carrying out the experimental design based on a uniform design method, and employing a design table enabling the centralization deviation to be minimum as a uniform design table; determining a performance response agent model of the target power semiconductor device according to a least square method; determining an uncertain limit state function of the target power semiconductor device through a stress-strength interference model; determining the uncertainty measure of the target power semiconductor device according to the uncertainty limit state function and the design variable distribution function, obtaining a performance reliability measurement model according to the uncertainty measure, and solving the model to obtain a performance reliability measurement result of the target power semiconductor device. The method has the beneficial effect that the measurement precision of the performance reliability of the power semiconductor device in the forward design stage is improved.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor reliability design and evaluation technology, and in particular to a method, apparatus, device and medium for measuring the performance reliability of power semiconductor devices. Background Technology

[0002] Reliability assessment is a critical quality characteristic in the forward design process of IGBT (Insulated Gate Bipolar Transistor) power devices, and performance reliability assessment requires consideration of design variables that affect the key performance parameters of power semiconductor devices. During the design phase, the lack of sufficient experimental statistical data often results in insufficient sample data for design variables. How to accurately quantify reliability under different sample size conditions and guide iterative optimization of product design is a pressing reliability engineering challenge that needs to be addressed.

[0003] For reliability analysis of power semiconductor devices, if there is sufficient sample data of design variables, the classical probabilistic reliability analysis theory based on mathematical statistics can accurately characterize the performance reliability of the product. However, if there is insufficient sample data of design variables, especially for power semiconductor devices in the forward design stage, there are many unavoidable epistemic uncertainties in terms of material properties, power loss, external load, structural dimensions, and application conditions. In this case, reliability cannot be accurately measured by probabilistic measures. Summary of the Invention

[0004] The main objective of this invention is to provide a method, apparatus, device, and medium for measuring the performance reliability of power semiconductor devices, thereby improving the accuracy of performance evaluation of power semiconductor devices.

[0005] One aspect of the present invention provides a method for measuring the performance reliability of power semiconductor devices, comprising:

[0006] Experimental design was conducted based on the uniform design method, and multiple alternative uniform design tables were generated according to the number of design variables and the number of levels.

[0007] Based on the uniformity of the hyperrectangle measured by the centering deviation, the design table with the smallest centering deviation value is selected from the candidate design table as the uniform design table for the target power semiconductor device.

[0008] Physical experiments or simulation analyses are conducted based on the uniform design table to obtain design variables and performance response sample values. The performance response proxy model of the target power semiconductor device is determined based on the least squares method, where the uncertain variables are used to characterize the design variables that affect key performance parameters.

[0009] Based on the performance response proxy model and performance response threshold, the uncertainty limit state function of the target power semiconductor device is determined by the stress-intensity interference model;

[0010] Based on the uncertain limit state function and the design variable distribution function, the uncertainty measure of the target power semiconductor device is determined, and a performance reliability measurement model is obtained based on the uncertainty measure.

[0011] The performance reliability measurement model is solved by using equivalent analytical model calculation method and numerical simulation calculation method to obtain the performance reliability measurement results of the target power semiconductor device.

[0012] According to the aforementioned power semiconductor device performance reliability measurement method, the experimental design is based on a uniform design method, generating multiple candidate uniform design tables based on the number of design variables and levels; the uniformity of the hyperrectangle is measured by the centering deviation, and the design table with the smallest centering deviation value is selected as the uniform design table for the target power semiconductor device, including:

[0013] The uniform design table is obtained using the uniform design method, and the uniform design table is represented as U. s (s n ) or Where U represents a uniform design, s represents the number of experiments, n represents the number of input factors, and * represents a design table with smaller bias and better uniformity.

[0014] In each experiment, the values ​​of each design variable do not restrict each other. The experimental region where the values ​​do not restrict each other is called a hyperrectangle, denoted as . Where the number of input factors n is equal to the number of design variables;

[0015] Using the centering deviation CD as a uniformity measure for the hyperrectangle C n The uniformity is measured, where the squared value of the centering deviation CD is obtained. 2 for

[0016]

[0017] Where ξ=(ξ1,ξ2,…,ξ) n ) T To design a vector of variables, It is by C n The experimental sample point set ξ composed of s trials i , that is ξ i =(ξ ij )∈C n .

[0018] According to the aforementioned method for measuring the performance reliability of power semiconductor devices, physical experiments or simulation analyses are conducted based on a uniform design table to obtain design variables and performance response sample values. A proxy model for the performance response of the target power semiconductor device is then determined based on the least squares method, including:

[0019] Experimental sample points for design variables and performance response are generated through multiple physical experiments or simulation analyses. Using the design variables (quadratic polynomials excluding cross terms) as uncertain variables, the performance response surrogate model of the target power semiconductor device is determined using the uniform design method and the least squares method:

[0020]

[0021] Where ξ=(ξ1,ξ2,…,ξ) n ) T Let b be a vector of n-dimensional uncertain random variables, determined by sampling from a uniform design table, where b = (b0, b1, ..., b...). 2n ) T It is a vector of 2n+1 undetermined coefficients in the performance response proxy model.

[0022] According to the aforementioned power semiconductor device performance reliability measurement method, the uncertainty limit state function of the target power semiconductor device is determined through a stress-intensity interference model based on the performance response proxy model and the performance response threshold, including:

[0023] Based on the stress-intensity interference model, the uncertain limit state function is constructed as G(ξ):

[0024] G(ξ)=f(ξ1,=2,…,ξ n ) = S threshold -S(ξ1,ξ2,…,ξ n )

[0025] Based on the least squares method, b = (a T a) -1 a T y, where a is an m×(2n+1) order regression coefficient vector, y=(g(ξ1),g(ξ2),…,g(ξ)). m )) T , which is a vector consisting of the performance responses corresponding to the key performance parameters;

[0026] The uncertain limit state function is updated using the least squares method and the stress-intensity interference model, resulting in:

[0027]

[0028] Where S threshold This is the performance response threshold. This is a performance response proxy model.

[0029] According to the aforementioned power semiconductor device performance reliability measurement method, the uncertainty measure of the target power semiconductor device is determined based on the uncertainty limit state function and the design variable distribution function, and a performance reliability measurement model is obtained based on the uncertainty measure, including:

[0030] Obtain the design variables, and determine the confidence level of the event based on the distribution function of the design variables and the uncertainty limit state function, where the confidence level of the event is represented as {G(ξ)>0};

[0031] Determine the measure of uncertainty based on the reliability of the event. Constructing an uncertain space as a triple Where Γ is a set including events, Let be a σ-algebra within Γ, where the uncertain space satisfies normality, duality, subadditivity, and the product axiom;

[0032] A performance reliability measurement model based on uncertainty space and uncertainty measure. for:

[0033]

[0034] According to the aforementioned power semiconductor device performance reliability measurement method, the equivalent analytical model calculation method includes:

[0035] Through the uncertain limit state function G(ξ=f(ξ1,ξ2,…,ξ) n ) and uncertain variables ξ1,ξ2,…,ξ n The canonical uncertain distribution function is determined as follows:

[0036] Φ1(ξ1),Φ2(ξ2),…,Φ n (ξ n )

[0037] If the limiting state function is uncertain for ξ1, ξ2, ..., ξ m Strictly monotonically increasing, while for ξ m+1 ,ξ m+2 ,…,ξ n If the signal is strictly monotonically decreasing, where 1 < m < n, then the failure confidence of the target power semiconductor device is:

[0038]

[0039] The performance reliability metric model is determined based on the failure confidence level of the target power semiconductor device.

[0040]

[0041] Based on the limit state function and the uncertain inverse distribution function, the equivalent analytical model for the performance reliability measurement model is determined as follows:

[0042]

[0043] Where α is the root of the equivalent analytical model.

[0044] According to the aforementioned method for measuring the reliability of power semiconductor devices, the numerical simulation calculation includes:

[0045] In an uncertain space, a set of uncertain variables ξ are generated through an uncertain inverse distribution function. k for:

[0046]

[0047] Where k = 1, ..., N;

[0048] The uncertain variable ξ k Sort by size and get

[0049] Following the order from k=1 to k=N, if G(ξ) k If ) > 0, then m1(i) = m1(i) + 1. If G(ξ) k If )≤0, then m2(i)=m2(i)+1,

[0050] If m1 > 0 and m2 > 0, for i = 1, 2, ..., n,

[0051] have

[0052] If m1 > 0, then M = 1; if m2 > 0, then M = 0.

[0053] If A (i) <0.5, then If B (i) <0.5 otherwise

[0054] like Then M = A; if Then M = 1 - B; otherwise, M = 0.5.

[0055] Obtain the reliability estimate of the performance reliability measurement model.

[0056] Another aspect of the present invention provides a power semiconductor device performance reliability measurement device, comprising:

[0057] The first module is used for experimental design based on the uniform design method, generating multiple alternative uniform design tables according to the number of design variables and the number of levels.

[0058] The second module is used to select the design table with the smallest centering deviation value from the candidate uniform design tables as the uniform design table for the target power semiconductor device based on the uniformity of the super rectangle according to the centering deviation metric.

[0059] The third module is used to conduct physical experiments or simulation analysis based on the uniform design table, obtain design variables and performance response sample values, and determine the performance response proxy model of the target power semiconductor device based on the least squares method. The uncertain variables are used to characterize the design variables that affect key performance parameters.

[0060] The fourth module is used to determine the uncertainty limit state function of the target power semiconductor device through a stress-intensity interference model based on the performance response proxy model and the performance response threshold.

[0061] The fifth module is used to determine the uncertainty measure of the target power semiconductor device based on the uncertainty limit state function and the design variable distribution function, and to obtain a performance reliability measurement model based on the uncertainty measure.

[0062] The sixth module is used to solve the performance reliability measurement model using equivalent analytical model calculation method and numerical simulation calculation method to obtain the performance reliability measurement results of the target power semiconductor device.

[0063] Another aspect of the present invention provides an electronic device, including a processor and a memory;

[0064] The memory is used to store programs;

[0065] The processor executes the program to implement the method as described above.

[0066] This invention also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the methods described above.

[0067] The beneficial effects of this invention are as follows: For situations where sample data of design variables affecting key performance parameters is insufficient, the reliability analysis model for power semiconductor devices based on uncertainty measures can effectively compensate for the limitations of traditional probabilistic reliability analysis models. For the established reliability analysis model for power semiconductor devices based on uncertainty measures, two analysis methods are proposed: an equivalent analytical model calculation method and a numerical simulation calculation method. If the monotonicity of the limit state function corresponding to the key performance parameters is unclear, the numerical simulation calculation method is more reasonable. If the monotonicity of the limit state function corresponding to the key performance parameters is clear and the number of design variables is small, then the equivalent analytical model is more efficient. The method proposed in this invention is more practical than the classical probabilistic reliability assessment method, improving the accuracy of performance reliability measurement for power semiconductor devices in the forward design stage. Attached Figure Description

[0068] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0069] Figure 1 This is a schematic diagram of the power semiconductor device performance reliability measurement process according to an embodiment of the present invention.

[0070] Figure 2 This is a schematic diagram of the numerical simulation solution algorithm according to an embodiment of the present invention.

[0071] Figure 3 This is a top view of the finite element model of the IGBT power device according to an embodiment of the present invention.

[0072] Figure 4 This is a side view of the finite element model of the IGBT power device according to an embodiment of the present invention.

[0073] Figure 5 This is a schematic diagram comparing the reliability estimation results of UMBR in an embodiment of the present invention.

[0074] Figure 6 This is a schematic diagram of a power semiconductor device performance reliability measurement device according to an embodiment of the present invention. Detailed Implementation

[0075] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings. Throughout the description, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. In the following description, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no inherent meaning. Therefore, "module," "part," or "unit" can be used interchangeably. In this subsequent description, the consecutive reference numerals for method steps are for ease of review and understanding. Adjusting the order of implementation of the steps, considering the overall technical solution of the present invention and the logical relationships between the steps, will not affect the technical effects achieved by the present invention. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0076] refer to Figure 1 , Figure 1 This is a schematic diagram of the power semiconductor device performance reliability measurement process according to an embodiment of the present invention. It includes, but is not limited to, steps S100 to S600:

[0077] S100 uses the uniform design method to design experiments, generating multiple alternative uniform design tables based on the number of design variables and the number of levels.

[0078] In some embodiments, multiple uniform design tables are pre-generated based on the number of design variables and experiments involved in the power semiconductor device.

[0079] S200: Based on the uniformity of the super rectangle measured by the centering deviation, select the design table with the smallest centering deviation value from the candidate uniform design tables as the uniform design table for the target power semiconductor device.

[0080] In some embodiments, a uniform design table is obtained using the uniform design method, and the uniform design table is represented as U. s (s n ) or Where U represents a uniform design, s represents the number of experiments, n represents the number of input factors, and * represents a design table with smaller bias and better uniformity.

[0081] In each experiment, the values ​​of each design variable do not restrict each other; therefore, this experimental region is called a hyperrectangle, which can be denoted as […]. The number of input factors, n, is equal to the number of design variables.

[0082] Using the centering deviation CD as a uniformity measure for the hyperrectangle C n The uniformity is measured, where the squared value of the centering deviation CD is obtained. 2 for

[0083]

[0084] Where ξ=(ξ1,ξ2,…,ξ) n ) T To design a vector of variables, It is by C n The experimental sample point set ξ composed of s trials i , that is ξ i =(ξ ij )∈C n .

[0085] S300 performs physical experiments or simulation analysis based on a uniform design table to obtain design variables and performance response sample values. It then determines the performance response proxy model of the target power semiconductor device based on the least squares method, where uncertain variables are used to characterize design variables that affect key performance parameters.

[0086] In some embodiments, the design variables of a quadratic polynomial excluding cross terms are used as uncertain variables, and the performance response proxy model of the target power semiconductor device is determined by the uniform design method and the least squares method as follows:

[0087]

[0088] Where ξ=(ξ1,ξ2,…,ξ) n ) T Let b be a vector of n-dimensional uncertain random variables, determined by sampling from a uniform design table, where b = (b0, b1, ..., b...). 2n ) T It is a vector of 2n+1 undetermined coefficients in the performance response proxy model.

[0089] Based on the least squares method, b = (a T a) -1 a T y, where a is an m×(2n+1) order regression coefficient vector, y=(g(ξ1),g(ξ2),…,g(ξ)). m )) T , which is a vector consisting of the performance responses corresponding to the key performance parameters;

[0090] S400 determines the uncertainty limit state function of the target power semiconductor device through a stress-intensity interference model based on the performance response proxy model and performance response threshold.

[0091] In some embodiments, the performance of power semiconductor devices is typically affected by various stresses, such as mechanical stress, thermal stress, electrical stress, electromagnetic stress, and moisture stress. A state parameter describing a particular stress can be defined as a critical performance parameter. Performance reliability assessment presupposes the construction of the limit state function corresponding to the critical performance parameter. Since all design variables affecting a critical performance parameter of a power semiconductor device exhibit cognitive uncertainty, this uncertainty is addressed through the uncertainty vector ξ=(ξ1,ξ2,…,ξ…). n ) T All design variables are uniformly represented, where ξ1, ξ2, ..., ξ n There are n design variables, such as material properties, power loss, external load, structural dimensions, and application conditions, etc.

[0092] In some embodiments, the generalized stress (performance response) affecting a key performance parameter of a power semiconductor device is S(ξ1,ξ2,…,ξ). n The generalized strength (performance response threshold) is S. threshold Then, based on the stress-intensity interference model, the Uncertainty Limit State Function (ULSF) can be determined:

[0093] G(ξ)=f(ξ1,ξ2,…,ξ n ) = S threshold -S(ξ1,ξ2,…,ξ n )

[0094] The uncertain limit state function is updated using the least squares method and the stress-intensity interference model, resulting in:

[0095]

[0096] Where S threshold This is the performance response threshold. This is a performance response proxy model.

[0097] S500 determines the uncertainty measure of the target power semiconductor device based on the uncertainty limit state function and the design variable distribution function, and obtains a performance reliability measurement model based on the uncertainty measure.

[0098] In some embodiments, the confidence level of an event is determined by design variables based on the distribution function of the design variables and the uncertainty limit state function, wherein the confidence level of an event is represented as {G(ξ)>0};

[0099] In some embodiments, the uncertainty measure is determined based on the reliability of the event. Constructing an uncertain space as a triple Where Γ is a set including events, Let be a σ-algebra within Γ, where the uncertain space satisfies normality, duality, subadditivity, and the product axiom;

[0100] A performance reliability measurement model based on uncertainty space and uncertainty measure. for:

[0101]

[0102] In some embodiments, the performance reliability of a power semiconductor device under a certain stress can be measured by an uncertainty measure. Quantified as the confidence level of a reliable event {G(ξ)>0}, then in the uncertainty space Construct an Uncertain Measure Based Reliability (UMBR) metric model based on uncertainty measures, as shown above.

[0103] Understandably, the reliability metric UMBR differs from probabilistic reliability. Since all design variables are subject to cognitive uncertainty, performance reliability cannot be quantified using probabilistic measures. UMBR, on the other hand, can reasonably measure performance reliability under conditions of cognitive uncertainty.

[0104] For uncertain measures, the following conditions must be met:

[0105] Wherein, (uncertainty measure) if Γ is a nonempty set, Let Γ be a σ-algebra. Each element Λ in the set represents an event. If the set function... If the following four axioms are satisfied, it is defined as an uncertain measure:

[0106] Axiom 1 (Normative): For the universal set Γ, the following holds true.

[0107] Axiom 2 (Dualism) For any event Λ, the following holds:

[0108] Axiom 3 (Subadditivity) For any countable sequence of events Λ1, Λ2, ..., it satisfies:

[0109]

[0110] Axiom 4 (Product Axiom) If For a series of uncertain spaces, Λ k For any from If an event is selected, k = 1, 2, ..., then the product of uncertain measures is still an uncertain measure, and satisfies the following equation:

[0111]

[0112] In an uncertain space, if Γ is a non-empty set, Let Γ be a σ-algebra. If it is an uncertain measure, then the triplet consisting of the above elements It is an uncertain space.

[0113] Uncertain variables, uncertain distributions, normally uncertain distributions, and the product of uncertain measures must each satisfy the following definitions:

[0114] (1) Uncertain variable, the uncertain variable ξ is from the uncertain space A measurable function of the real number set, i.e., {ξ∈B} is an event of any real number Borel set B.

[0115] Assume ξ1, ξ2, ..., ξ n Let f be a set of uncertain variables, and f be a real-valued measurable function, then ξ = f(ξ1, ξ2, ..., ξ). n Similarly, ξ(τ) is an uncertain variable, meaning that for any τ∈Γ, ξ(τ) can be expressed as follows:

[0116] ξ(τ)=f(ξ1(τ),ξ2(τ),…,ξ n (τ))

[0117] (2) Uncertain distribution: If ξ is an uncertain variable, then the uncertain distribution Φ(x) of ξ with respect to any real number x can be defined as follows:

[0118]

[0119] (3) Normal uncertainty distribution: If the uncertain variable ξ has the following normal uncertainty distribution, then it is defined as a normal uncertain variable:

[0120]

[0121] It is represented as Where m and σ are the uncertain expectation and uncertain variance, respectively.

[0122] (4) The Uncertainty Measure Product Theorem, assuming For a series of uncertain spaces, and Λ k It is a σ-algebra Given any series of events, the following formula can be used to calculate the value of any event. Uncertainty measure:

[0123]

[0124] S600 uses the equivalent analytical model calculation method and numerical simulation calculation method to solve the performance reliability measurement model of the previous step, and obtains the performance reliability measurement results of the target power semiconductor device.

[0125] In some embodiments, the equivalent analytical model calculation method for solving the performance reliability measurement model includes:

[0126] For a certain key performance parameter, the uncertain limit state function is G(ξ)=f(ξ1,ξ2,…,ξ). n ), whose uncertain variables are ξ1,ξ2,…,ξ n They are mutually independent and can be expressed by the regular uncertainty distribution function Φ1(ξ1),Φ2(ξ2),…,Φ n (ξ n Description. If the limit state function is uncertain for ξ1,ξ2,…,ξ… m Strictly monotonically increasing, while for ξ m+1 ,ξ m+2 ,…,ξ n Strictly monotonically decreasing, at which point the failure confidence level of the power semiconductor device is... Therefore, UMBR can be calculated as follows: Based on the limit state function and the uncertain inverse distribution function, an equivalent analytical solution model for the UMBR metric model is constructed:

[0127]

[0128] In the formula, α is the root of the above equation.

[0129] In some embodiments, reference Figure 2 The diagram shown illustrates the processing flow of the numerical simulation calculation method, where the solution to the performance reliability metric model includes:

[0130] Figure 2 middle,

[0131] (1) Set m1(i) = 0, m2(i) = 0, i = 1, 2, ..., n;

[0132] (2) In the uncertain space, through the uncertain inverse distribution function respectively Generate a set of uncertain variables

[0133] (3) The generated uncertain variables Rearrange from smallest to largest

[0134] (4) From k=1 to k=N, if G(ξ) k If ) > 0, then m1(i) = m1(i) + 1. If G(ξ) k If )≤0, then m2(i)=m2(i)+1,

[0135] (5) If m1 > 0 and m2 > 0, for i = 1, 2, ..., n,

[0136] have

[0137]

[0138] If m1 > 0, then M = 1; if m2 > 0, then M = 0.

[0139] (6) If A (i) <0.5, then If B (i) <0.5 otherwise

[0140] (7) If Then M = A; if Then M = 1 - B; otherwise, M = 0.5.

[0141] (8) The final reliability estimate of UMBR is obtained.

[0142] In some embodiments, reference Figure 3 The diagram shows a top view of the IGBT power device. Figure 4 The side view of the IGBT power device shown is shown. Figure 3 and Figure 4 Finite element analysis model for a 6500V / 750A IGBT device.

[0143] The packaging of IGBT power devices serves multiple functions, including power transmission, signal transmission, mechanical support, heat dissipation, and protection. The packaging effect directly impacts the electrical, thermal, and mechanical properties of the power device. Removing the plastic casing and silicone, the main physical model of an IGBT consists of seven layers: from bottom to top, substrate, base solder layer, lower copper layer, ceramic layer, upper copper layer, chip solder layer, and the chip itself. The decisive factor affecting power device packaging failure is thermal stress. Junction temperature fluctuations are a major cause of power device aging. Under power cycling, the heat transfer mechanism of IGBT power devices mainly consists of internal heat conduction (primarily internal) and external substrate heat dissipation (primarily external substrate heat dissipation) via convection.

[0144] The highest internal temperature T of the power semiconductor device maxFor key performance parameters, a thermal performance reliability measurement and analysis is conducted based on a finite element thermal simulation model. (Construction) Figure 3 and Figure 4 The IGBT power device shown is an ANSYS finite element model. In the model, the chip is the only heat source. The applied loads and boundary conditions are as follows: the average power consumption of each IGBT chip is 150W, and the power consumption of the FRD chip is 0W. The chip volumetric heat generation rate is used as the loading condition. The substrate is in contact with the heat sink via thermal grease, and its heat dissipation is equivalent to convection heat transfer, with an average convection heat transfer coefficient of 1500W / (m²). 2 The substrate has four sides exposed to air via natural convection heat transfer (°C), with an average convection heat transfer coefficient of 10 W / (m²). 2 The temperature of the radiator T0 during the test was 35℃~60℃. During the simulation, the applied load was smoothed by a first-order inertial function to simulate a cyclic experiment (on-off).

[0145] Simulation results show that the highest internal temperature of the IGBT device is located on the IGBT chip, and the spacing between the chips hinders the lateral heat transfer. Based on the controlled variable method and finite element simulation analysis, the design variables affecting the highest internal temperature of the device include substrate thermal conductivity / thermal conductivity coefficient, substrate specific heat capacity, substrate density, substrate bottom heat transfer coefficient, IGBT chip losses, and heat sink temperature. The values ​​of the relevant distribution parameters of these sensitive design variables are shown in Table 1.

[0146] Table 1 Distribution parameters of sensitive design variables

[0147] Design variables Physical meaning mean Standard deviation λ[W / (m.℃)] substrate thermal conductivity / thermal conductivity coefficient 200 8 c[J / kg.℃] Substrate specific heat capacity 760 20 <![CDATA[ρ(kg / m 3 )]]> Substrate density 2960 200 <![CDATA[H[W / (m 2 ·℃)]]]> heat transfer coefficient at the bottom of the substrate 1500 40 L(W) IGBT chip loss 150 5

[0148] Introduce a uniform design table containing 6 factors and 25 levels. To design DOE experiments, the minimum squared value of the centering bias CD is used. 2 (P) = 0.2130. Considering the radiator temperature T0 falls within the interval [35, 59℃], this interval is diffused into 25 equally spaced sample points. The sample values ​​for other design variables are x. i =μ i ±fσ i / 4, f = 0, 1, 2, ..., 12; i = 1, 2, ..., n, where μ i and σ i These represent the mean and standard deviation of the design variables, respectively. The maximum stress value for each experiment was obtained based on finite element simulation, and then a response function was fitted to the maximum stress value. Table 2 lists the detailed results of the 25 simulation experiments.

[0149] Table 2 shows the simulation results of the highest temperature based on the uniform design table.

[0150]

[0151]

[0152] The response function of the IGBT chip at its highest temperature was fitted based on the simulation data listed in Table 2, and the coefficient of determination R was calculated. 2 =0.993297, which is close to 1. Therefore, the response function for the highest chip temperature obtained based on the experimental design of this invention meets the accuracy requirements, that is, the response function can effectively replace the finite element model to estimate the highest temperature value. According to the allowable temperature threshold S of the IGBT chip... threshold =150℃, the following limit state function for thermal stress failure of power semiconductor devices can be established:

[0153]

[0154] In the formula, ξ=(T0,λ,,c,ρ,H,L) T It is a vector of design variables, b = (b0, b1, ..., b 12 ) T It is a coefficient vector.

[0155] Next, a reliability measurement analysis under thermal stress is performed. Since the sample data for obtaining the probability density function of the design variables is very limited, reliability quantification based on uncertainty theory is more reasonable. In this case, the substrate thermal conductivity / thermal conductivity coefficient, substrate specific heat capacity, substrate density, substrate bottom heat transfer coefficient, and IGBT chip loss can be described by uncertain variables that follow a normal uncertain distribution, i.e.

[0156] Taking the partial derivative of the uncertain limit state function G(ξ) reveals that it is strictly monotonically increasing with respect to λ, c, ρ, and H, and strictly monotonically decreasing with respect to L. Since all design variables follow a canonical uncertain distribution function, the reliability can be assessed using an equivalent analytical model. To verify the accuracy of the numerical simulation method, it is also applied to the reliability assessment of this power device. This is done when all design variables are assumed to be random variables, i.e., following a normal probability distribution. In this case, the classic probability measure-based method is used for comparative analysis, where the probability measure-based reliability (PMBR) is estimated using the first-order second moment (FORM) method. Figure 5 The results of reliability analysis of power semiconductor devices under thermal stress based on the above three methods are presented when the heat sink temperature T0 is in the range [60, 90℃].

[0157] according to Figure 5 It can be seen that the overall trend of reliability indices based on uncertainty measures is basically consistent with that of probabilistic reliability indices. That is, the reliability of both UMBR and PMBR decreases as the heat sink temperature increases, and the reliability of power semiconductor devices continuously decreases. If the reliability value is in the range of [0, 0.5], the reliability of UMBR based on uncertainty measures is greater than that of the traditional PMBR based on probabilistic measures. If the reliability value is in the range of [0.5, 1], the reliability of UMBR is lower than that of PMBR. This indicates that at a high reliability level, the reliability of UMBR is more conservative and reasonable, effectively reflecting the impact of cognitive uncertainty and ensuring product safety to a greater extent. In addition, the UMBR reliability value estimated by the numerical simulation calculation method is basically consistent with that estimated by the numerical simulation calculation method. Therefore, the numerical simulation solution algorithm for UMBR reliability based on the uncertainty simulation idea proposed in this invention meets the accuracy requirements.

[0158] In summary, regarding the reliability problem of power devices under cognitive uncertainty, assuming the uncertain variables are random variables and using probability theory for analysis ignores the impact of cognitive uncertainty, leading to overly optimistic calculation results. On the one hand, when there is insufficient information about the design variables and the specific probability distribution function cannot be obtained, the UMBR metric model based on uncertainty measures is suitable for analysis. On the other hand, when there is sufficient statistical information about the design variables, probability theory is more appropriate. Furthermore, when facing high-dimensional nonlinearity and uncertain limit state functions that do not change strictly monotonically with respect to the design variables, equivalent analytical model methods cannot be used for performance reliability measurement; that is, numerical simulation methods are more practical for engineering applications.

[0159] Figure 6 This is a diagram of a power semiconductor device performance reliability measurement and analysis device according to an embodiment of the present invention. The device includes a first module 610, a second module 620, a third module 630, a fourth module 640, a fifth module 650, and a sixth module 660.

[0160] The system comprises six modules: First, a uniform design method is used to design experiments, generating multiple candidate uniform design tables based on the number of design variables and levels. Second, a uniform design table with the smallest centering deviation value is selected from the candidate uniform design tables as the target power semiconductor device's uniform design table, based on the uniformity of the hyperrectangle using the centering deviation metric. Third, physical experiments or simulations are conducted based on the uniform design table to obtain design variables and performance response sample values, and a performance response surrogate model for the target power semiconductor device is determined using the least squares method, where uncertain variables characterize design variables affecting key performance parameters. Fourth, the performance response surrogate model and performance response threshold are used to determine the uncertainty limit state function of the target power semiconductor device using a stress-intensity interference model. Fifth, the uncertainty measure of the target power semiconductor device is determined based on the uncertainty limit state function and the design variable distribution function, and a performance reliability measurement model is obtained based on the uncertainty measure. Sixth, the performance reliability measurement model is solved using equivalent analytical model calculation methods and numerical simulation calculation methods to obtain the performance reliability measurement results of the target power semiconductor device.

[0161] For example, with the cooperation of the first, second, third, fourth, fifth, and sixth modules in the device, the embodiment device can implement any of the aforementioned power semiconductor device performance reliability measurement methods, namely, conducting experimental design based on the uniform design method, generating multiple candidate uniform design tables according to the number of design variables and the number of levels; selecting the design table with the smallest centering deviation value from the candidate uniform design tables as the uniform design table of the target power semiconductor device based on the uniformity of the centering deviation metric hyperrectangle; conducting physical experiments or simulation analysis based on the uniform design table to obtain design variables and performance response sample values, determining the performance response proxy model of the target power semiconductor device based on the least squares method, wherein the uncertain variables are used to characterize the design variables affecting key performance parameters; determining the uncertainty limit state function of the target power semiconductor device through the stress-intensity interference model based on the performance response proxy model and the performance response threshold; determining the uncertainty measure of the target power semiconductor device based on the uncertainty limit state function and the design variable distribution function, obtaining the performance reliability measurement model based on the uncertainty measure; and solving the performance reliability measurement model using the equivalent analytical model calculation method and the numerical simulation calculation method to obtain the performance reliability measurement result of the target power semiconductor device. The beneficial effects of this invention are as follows: For situations where sample data of design variables affecting key performance parameters is insufficient, the reliability analysis model for power semiconductor devices based on uncertainty measures can effectively compensate for the limitations of traditional probabilistic reliability analysis models. For the established reliability analysis model for power semiconductor devices based on uncertainty measures, two analysis methods are proposed: an equivalent analytical model calculation method and a numerical simulation calculation method. If the monotonicity of the limit state function corresponding to the key performance parameters is unclear, the numerical simulation calculation method is more reasonable. If the monotonicity of the limit state function corresponding to the key performance parameters is clear and the number of design variables is small, then the equivalent analytical model is more efficient. The method proposed in this invention is more practical than the classical probabilistic reliability assessment method, improving the accuracy of performance reliability measurement for power semiconductor devices in the forward design stage.

[0162] This invention also provides an electronic device, which includes a processor and a memory;

[0163] The memory stores the program;

[0164] The processor executes a program to perform the aforementioned power semiconductor device performance reliability measurement method; the electronic device has the function of carrying and running a software system for measuring the power semiconductor device performance reliability provided in the embodiments of the present invention, such as a personal computer, minicomputer, mainframe, workstation, network or distributed computing environment, standalone or integrated computer platform, or communicating with charged particle tools or other imaging devices, etc.

[0165] This invention also provides a computer-readable storage medium storing a program that is executed by a processor to implement the power semiconductor device performance reliability measurement method as described above.

[0166] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0167] This invention also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the aforementioned power semiconductor device performance reliability measurement method.

[0168] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0169] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0170] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0171] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0172] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0173] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0174] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0175] The above is a detailed description of the preferred embodiments of the present invention, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A method for measuring the reliability of power semiconductor devices, characterized in that, include: Experimental design was conducted based on the uniform design method, and multiple alternative uniform design tables were generated according to the number of design variables and the number of levels. Based on the uniformity of the hyperrectangle measured by the centering deviation, the design table with the smallest centering deviation value is selected from the candidate uniform design tables as the uniform design table for the target power semiconductor device. Physical experiments or simulation analyses are performed based on the uniform design table to obtain design variables and performance response sample values. The performance response proxy model of the target power semiconductor device is determined based on the least squares method, where the uncertain variables are used to characterize the design variables that affect key performance parameters. Based on the performance response proxy model and performance response threshold, the uncertainty limit state function of the target power semiconductor device is determined by the stress-intensity interference model; Based on the uncertain limit state function and the design variable distribution function, the uncertainty measure of the target power semiconductor device is determined, and a performance reliability measurement model is obtained based on the uncertainty measure. The performance reliability measurement model is solved by using equivalent analytical model calculation method and numerical simulation calculation method to obtain the performance reliability measurement results of the target power semiconductor device.

2. The method for measuring the performance reliability of power semiconductor devices according to claim 1, characterized in that, Experimental design was conducted based on the uniform design method, and multiple alternative uniform design tables were generated according to the number of design variables and the number of levels. Based on the uniformity of the hyperrectangle measured by the centering deviation, the design table with the smallest centering deviation value is selected as the uniform design table for the target power semiconductor device, including: The uniform design table is obtained using the uniform design method, and the uniform design table is represented as U. s (s n ) or Where U represents a uniform design, s represents the number of experiments, n represents the number of input factors, and * represents a design table with smaller bias and better uniformity. In each experiment, the values ​​of each design variable do not restrict each other. The experimental region where the values ​​do not restrict each other is called a hyperrectangle, denoted as . Where the number of input factors n is equal to the number of design variables; Using the centering deviation CD as a uniformity measure for the hyperrectangle C n The uniformity is measured, where the squared value of the centering deviation CD is obtained. 2 for Where ξ=(ξ1,ξ2,…,ξ) n ) T To design a vector of variables, It is by C n The experimental sample point set ξ composed of s trials i , that is ξ i =(ξ ij )∈C n .

3. The method for measuring the performance reliability of power semiconductor devices according to claim 1, characterized in that, Based on the uniform design table, physical experiments or simulation analyses are conducted to obtain design variables and performance response sample values. A proxy model for the performance response of the target power semiconductor device is determined using the least squares method, including: Experimental sample points for design variables and performance response are generated through multiple physical experiments or simulation analyses. Using the design variables (quadratic polynomials excluding cross terms) as uncertain variables, the performance response surrogate model of the target power semiconductor device is determined using the uniform design method and the least squares method: Where ξ=(ξ1,ξ2,…,ξ) n ) T Let b be a vector of n-dimensional uncertain random variables, determined by sampling from a uniform design table, where b = (b0, b1, ..., b...). 2n ) T It is a vector of 2n+1 undetermined coefficients in the performance response proxy model.

4. The method for measuring the performance reliability of power semiconductor devices according to claim 3, characterized in that, The step of determining the uncertainty limit state function of the target power semiconductor device using a stress-intensity interference model based on the performance response proxy model and performance response threshold includes: Based on the stress-intensity interference model, the uncertain limit state function is constructed as G(ξ): G(ξ)=f(ξ1,ξ2,…,ξ n )=S threshold -S(ξ1,ξ2,…,ξ n ) Based on the least squares method, b = (a T a) -1 a T y, where a is an m×(2n+1) order regression coefficient vector, y=(g(ξ1),g(ξ2),…,g(ξ)). m )) T , which is a vector consisting of the performance responses corresponding to the key performance parameters; The uncertain limit state function is updated using the least squares method and the stress-intensity interference model, resulting in: Where S threshold This is the performance response threshold. This is a performance response proxy model.

5. The method for measuring the performance reliability of power semiconductor devices according to claim 4, characterized in that, The step of determining the uncertainty measure of the target power semiconductor device based on the uncertain limit state function and design variables, and obtaining a performance reliability metric model based on the uncertainty measure, includes: Obtain the design variables, and determine the confidence level of the event based on the design variables and the uncertain limit state function, where the confidence level of the event is represented as {G(ξ)>0}; Determine the measure of uncertainty based on the reliability of the event. Constructing an uncertain space as a triple Where Γ is a set including events, Let be a σ-algebra within Γ, where the uncertain space satisfies normality, duality, subadditivity, and the product axiom; A performance reliability measurement model based on uncertainty space and uncertainty measure. for:

6. The method for measuring the performance reliability of power semiconductor devices according to claim 5, characterized in that, The method for calculating the equivalent analytical model includes: Through the uncertain limit state function G(ξ=f(ξ1,ξ2,…,ξ) n ) and uncertain variables ξ1,ξ2,…,ξ n The canonical uncertain distribution function is determined as follows: Φ1(ξ1),Φ2(ξ2),…,Φ n (x) n ) If the limiting state function is uncertain for ξ1, ξ2, ..., ξ m Strictly monotonically increasing, while for ξ m+1 ,ξ m+2 ,…,ξ n If the signal is strictly monotonically decreasing, where 1 < m < n, then the failure confidence level of the target semiconductor is: The performance reliability metric model is determined based on the target semiconductor failure confidence level as follows: Based on the limit state function and the uncertain inverse distribution function, the equivalent analytical model of the performance reliability measurement model is determined as follows: Where α is the root of the equivalent analytical model.

7. The method for measuring the reliability of power semiconductor devices according to claim 5, characterized in that, The numerical simulation calculations include: In an uncertain space, a set of uncertain variables ξ are generated through an uncertain inverse distribution function. k for: Where k = 1, ..., N; The uncertain variable ξ k Sort by size and get Following the order from k=1 to k=N, if G(ξ) k If ) > 0, then m1(i) = m1(i) + 1. If G(ξ) k If )≤0, then m2(i)=m2(i)+1, If m1 > 0 and m2 > 0, for i = 1, 2, ..., n, have If m1 > 0, then M = 1; if m2 > 0, then M = 0. If A (i) <0.5, then If B (i) <0.5 otherwise like Then M = A; if Then M = 1 - B; otherwise, M = 0.

5. Obtain the reliability estimate of the performance reliability measurement model.

8. A device for measuring the performance reliability of power semiconductor devices, characterized in that, include: The first module is used for experimental design based on the uniform design method, generating multiple alternative uniform design tables according to the number of design variables and the number of levels. The second module is used to select the design table with the smallest centering deviation value from the candidate uniform design tables as the uniform design table for the target power semiconductor device based on the uniformity of the super rectangle according to the centering deviation metric. The third module is used to conduct physical experiments or simulation analysis based on the uniform design table, obtain design variables and performance response sample values, and determine the performance response proxy model of the target power semiconductor device based on the least squares method. The uncertain variables are used to characterize the design variables that affect key performance parameters. The fourth module is used to determine the uncertainty limit state function of the target power semiconductor device through a stress-intensity interference model based on the performance response proxy model and the performance response threshold. The fifth module is used to determine the uncertainty measure of the target power semiconductor device based on the uncertainty limit state function and the design variable distribution function, and to obtain a performance reliability measurement model based on the uncertainty measure. The sixth module is used to solve the performance reliability measurement model using equivalent analytical model calculation method and numerical simulation calculation method to obtain the performance reliability measurement results of the target power semiconductor device.

9. An electronic device, characterized in that, Including the processor and memory; The memory is used to store programs; The processor executes the program to implement the power semiconductor device performance reliability measurement method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a program that is executed by a processor to implement the power semiconductor device performance reliability measurement method as described in any one of claims 1-7.

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