Derivation method of common-ground converter topology

Abstract

The invention discloses a common-ground converter topology derivation method, and belongs to the technical field of converters. Comprising the following steps: determining a node number na and a switch number nb of a common-ground converter topology; according to the double-grounding characteristic circuit, the negative electrode of the input power supply and the negative electrode of the output end are common-grounded; constructing an adjacent matrix according to the node number and the switch number; and inserting capacitors and inductors into the adjacent matrix to obtain all topologies, performing isomorphic screening and feasibility screening on the obtained topologies, and rejecting topologies of unneeded categories according to the required categories. The common-ground converter topology derivation method provided by the invention is completely based on adjacent matrix modeling, so that automatic generation and analysis can be conveniently realized through programming software; the method is high in systematicness and clear in rule, can effectively eliminate invalid or redundant structures, and remarkably improves the topology derivation efficiency and integrity.

Description

Technical Field

[0001] This invention relates to the field of converter technology, and in particular to a method for deriving the topology of a common-ground converter. Background Technology

[0002] Non-isolated converters are widely used due to their advantages of simple structure, low cost, low energy loss, and high overall efficiency. However, due to the lack of isolation, the capacitance between the photovoltaic panel and ground will generate common-mode leakage current, which will lead to conducted noise and harmonic current interference, and even threaten personal safety.

[0003] Domestic and international experts and scholars have conducted a series of fruitful studies on how to suppress common-mode leakage current in non-isolated converters. Commonly used methods for suppressing common-mode leakage current include improving modulation techniques, adding switching devices, adding filters, and improving control methods. However, these methods are easily affected by the parasitic capacitance of the input power supply to ground and changes in circuit parameters. To completely eliminate common-mode leakage current, some scholars have proposed a double-grounded topology. This structure short-circuits the negative terminal of the DC input with the neutral point of the AC output, directly short-circuiting the parasitic capacitance of the photovoltaic module to ground, thereby completely eliminating common-mode leakage current. However, its theoretical reasoning model is complex and inefficient, easily leading to invalid circuits, and cannot automatically derive all circuit topologies through a program. Therefore, it is necessary to study a method for automatically deriving all common-ground converters using a computer. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method for deriving common-ground converter topologies, aiming to solve the problem that common-ground converter topologies cannot be automatically derived by computer, thereby enabling the derivation of all common-ground converter topologies.

[0005] To achieve the above objectives, the present invention provides a method for deriving a common-ground converter topology, comprising the following steps: (1) Determine the number of nodes na and the number of switches nb of the common-ground converter topology, which should be at least 3 nodes and 2 switches; (2) According to the double-grounded characteristic circuit, let the negative terminal of the input power supply and the negative terminal of the output terminal share the same ground, and define it as node 0; (3) Based on the number of nodes and the number of switches, construct an adjacency matrix to ensure that a loop is formed with the input power supply and the output terminal, and insert switches between the interconnected nodes; (4) Given the number of capacitors N1; insert capacitors into the adjacency matrix, wherein the capacitors are allowed to be placed between any two nodes; (5) Given the number of inductors N2; insert inductors into the adjacency matrix by introducing new nodes at the branch where inductors need to be inserted through node splitting, move the original branch elements to the new node between one original node of the original branch, connect the inductor between the new node and another original node of the original branch, and set the elements between the two nodes of the original branch in the adjacency matrix to 0. (6) Traverse all combinations of steps (4) and (5) until all topologies are obtained. Perform isomorphism screening and feasibility screening on the obtained topologies to obtain legal topologies. (7) Based on Boolean logic, legal switch combinations of legal topologies are automatically enumerated and depth-first search (DFS) is used to traverse the loop. The voltage gain, capacitance and voltage across the switch are calculated using the volt-second balance principle and Kirchhoff's voltage law. Then, the topology is classified as "DC" or "inverter". Based on the required category, topologies that do not need to be classified are eliminated.

[0006] Furthermore, the adjacency matrix is ​​an N-order symmetric matrix used to mathematically represent the topological connection relationships between nodes in the circuit.

[0007] Furthermore, in step (4), when inserting capacitors into the adjacency matrix, the number of capacitors is independent of the number of nodes and the number of switches, and different capacitors can exist between two nodes simultaneously.

[0008] Furthermore, in step (4), when inserting a capacitor into the adjacency matrix, if it is an independent structure, one of the capacitors is connected to the parallel branch of the output load; if it is a grid-connected structure, the output terminal is directly connected to the power grid.

[0009] Furthermore, step (5) specifically involves: (5.1) Check if there is a loop consisting only of an input source or a capacitor and a switch. If the loop does not exist, proceed directly to step (5.3). Otherwise, insert an inductor into one of the branches of all the branches of the node contained in the loop. In this case, the loop is a parallel branch for the node. Update the adjacency matrix in the following cases: (a) If the inductor is inserted into the independent branch of the node, that is, the branch is not a parallel branch, the element between the two original nodes of the branch in the adjacency matrix is ​​set to 0, the original branch element is moved to the new node and the other original node of the original branch, and the inductor is connected between the new node and the node where the inductor needs to be inserted. (b) If an inductor is inserted into one of the parallel branches, the original elements of the parallel branches in the adjacency matrix should be split, the elements between the two nodes of the original parallel branch should be rewritten as all the branch elements without the inductor, the original elements of the branch with the inductor should be moved to the new node and the other original node of the original branch, and the inductor should be connected between the new node and the node where the inductor needs to be inserted. (c) If an inductor is inserted into both an independent branch and a parallel branch at the same time, the adjacency matrix is ​​first updated according to (a) for the independent branch, and then updated according to (b) for the parallel branch. (5.2) In the topology corresponding to the updated adjacency matrix, check again whether there is a loop consisting of an input source or capacitor and switch. If such a loop exists, update the adjacency matrix according to step (5.1) until there is no such loop or the number of inserted inductors is equal to the number of given inductors. (5.3) If the number of inductors currently inserted is equal to the given number of inductors, then the insertion of inductors ends; otherwise, randomly select a node branch with non-zero elements in the adjacency matrix from any node and insert an inductor. Introduce a new node at the branch where the inductor needs to be inserted by splitting the node. Set the elements between the two original nodes in the adjacency matrix of the branch to 0. Move the original branch element to the new node and one of the original nodes of the original branch. Connect the inductor between the new node and the other original node of the original branch. (5.4) Repeat step (5.3) until the number of inductors currently inserted is equal to the number of given inductors.

[0010] Furthermore, step (6) specifically involves: The isomorphic filtering is as follows: if the adjacency matrices of two topologies can be made completely identical by renumbering, then they are determined to be isomorphic, and one of the two topologies is eliminated. The feasibility screening is as follows: if the topology contains only input sources or capacitors and switches directly connected in parallel, or switches and inductors are connected in series in one branch; or three branches of the same node contain three inductors or two inductors and one switch respectively, then the topology is determined to be infeasible and needs to be eliminated. All remaining topologies after removing the above topologies are valid topologies.

[0011] Furthermore, step (7) specifically includes: (7.1) Establish Boolean rules for each topology, determine all legal switch operating modes, and obtain legal switch combinations; In a circuit consisting only of an input power source, a capacitor, and switches, when the number of switches is greater than or equal to 2, all switches cannot be turned on simultaneously. The Boolean expression for this rule is: (S1 ∧ S2 ∧ S3 …); where S1, S2, and S3 represent switches. Based on these two Boolean expressions, determine all legal switch operating modes. After obtaining the legal operating modes of the switch, all legal operating modes are combined in pairs to form the switching logic of the converter. (7.2) Based on depth-first search (DFS), all loops in the topology are traversed to obtain the loop voltage equations; Each loop must start from a node and return to that node, and the row number of the previous matrix element must be equal to the column number of the next matrix element; for each loop, the voltage equation is obtained according to Kirchhoff's voltage law, and the loop equation is for loops with on switches; loops with off switches are not calculated. (7.3) In all the loops obtained in step (7.2), find the unique independent loop in which each inductor is located, that is, the loop only includes this inductor and does not include other inductors. Taking advantage of the characteristic that the volt-second integral of the inductor is zero in steady state, establish a volt-second balance equation system for each inductor. Solve the equations of all inductors to form a linear equation system about the unknown capacitor voltage and the output voltage. Solve the linear equation system to obtain the voltage gain and the voltage across the capacitor. (7.4) Among all the loops obtained in step (7.2), find the effective loop that includes each switch and energy storage element, substitute all the known voltages obtained in step (7.3) into Kirchhoff's voltage law equation, and solve analytically for the voltage expression across the switch. (7.5) Based on the voltage gain obtained in step (7.3), determine whether the topology is a "DC" or "inverter" topology; (7.6) Repeat steps (7.1)-(7.5) to complete the category determination of all legal topologies; (7.7) If the requirement is a DC topology, then all inverter topologies are eliminated from all valid topologies. If the requirement is an inverter topology, then all DC topologies are eliminated from all valid topologies.

[0012] The beneficial effects of this invention are: The common-ground converter topology derivation method provided in this invention is entirely based on adjacency matrix modeling, which facilitates automated generation and analysis through programming software. It is not only highly systematic and rule-based, but also effectively eliminates invalid or redundant structures, significantly improving the efficiency and completeness of topology derivation. Compared to traditional graph theory methods, this method supports automatic switching logic selection, voltage gain analysis, and inverter capability discrimination, and can efficiently generate a large number of novel and functionally effective common-ground converter topologies, providing rich circuit design solutions for non-isolated applications such as photovoltaics. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the common-ground converter topology derivation method according to an embodiment of the present invention.

[0014] Figure 2This is a schematic diagram of the four-node, four-switch adjacency matrix structure of an embodiment of the present invention.

[0015] Figure 3 This is a schematic diagram of the capacitor insertion position in the four-node, four-switch adjacency matrix structure of an embodiment of the present invention.

[0016] Figure 4 This is a schematic diagram of the inverter topology with four nodes, four switches, two capacitors, and two inductors according to an embodiment of the present invention.

[0017] Figure 5 This is a schematic diagram of traversing a loop in a circuit using depth-first search (DFS) according to an embodiment of the present invention.

[0018] Figure 6 This is a schematic diagram of the inductor insertion position in an adjacency matrix structure where the node to which the inductor needs to be inserted has parallel branches, according to an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on the invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0020] In the following description, references to "some embodiments" or "one or more embodiments" describe a subset of all possible embodiments. However, it is understood that "some embodiments" or "one or more embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] In the following description, the terms "first" and "second" are used only for similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of the invention described herein can be implemented in an order other than that shown in the illustrations or description.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0023] like Figure 1 As shown, this embodiment of the invention provides a method for deriving a common-ground converter topology, including the following steps: S101. Determine the number of nodes na and the number of switches nb of the common-ground converter topology, with a minimum of 3 nodes and 2 switches.

[0024] The number of nodes and switches in the common-ground converter topology to be derived needs to be determined, among which, , This embodiment of the invention takes a 4-node, 4-switch structure 6 as an example.

[0025] S102. According to the double-grounded characteristic circuit, let the negative terminal of the input power supply and the negative terminal of the output terminal share the same ground, and define it as node 0.

[0026] To ensure that it is a double-grounded inverter circuit, the negative terminal of the input power supply and the negative terminal of the output terminal need to be grounded together, so that they are on the same node, which is the common ground node 0.

[0027] S103. Based on the number of nodes and the number of switches, construct an adjacency matrix to ensure that a loop is formed with the input power supply and the output terminal, and insert switches between the interconnected nodes.

[0028] The adjacency matrix is ​​an N-order symmetric matrix used to mathematically represent the topological connections between nodes in a circuit.

[0029] Connect the input power source (Uin) between node 0 and node 1, and connect the output port (load / grid) between node 0 and node N-1. This ensures that the input and output share a common ground (i.e., "double ground"), thereby eliminating common-mode leakage current.

[0030] The diagonal elements in the adjacency matrix correspond to self-loops, which have no physical meaning in the circuit topology because all switches, capacitors, and inductors must be connected between two different nodes. Therefore, the components must be placed in the off-diagonal positions of the adjacency matrix.

[0031] The adjacency matrix of this embodiment consists of four nodes and four switches, including: node 0, node 1, node 2, node 3, first switch S1, second switch S2, third switch S3, and fourth switch S4. Figure 2 One example is given: First switch S1 is between node 1 and node 0. Second switch S2 is between node 1 and node 2. Third switch S3 is between node 3 and node 2. Fourth switch S4 is between node 2 and node 0. The input power supply is between node 1 and node 0, and the output is between node 3 and node 0. Node 0 is a common ground node.

[0032] S104. Given the number of capacitors N1; insert capacitors into the adjacency matrix, wherein the capacitors are allowed to be placed between any two nodes.

[0033] There are two types of capacitors in a circuit: one type is connected in parallel between any two nodes, and the other type is connected in parallel across the output terminals in an independent structure to filter the output voltage. In a grid-connected structure, the output terminal is directly connected to the power grid, and there is no need to add a capacitor to filter the output voltage.

[0034] The number of capacitors is independent of the number of nodes and switches, and different capacitors can be connected to the same two nodes simultaneously.

[0035] In this embodiment of the invention, the given number of capacitors is two, one of which needs to be connected in parallel between any two nodes, resulting in six possibilities (between node 1 and node 0, between node 2 and node 0, between node 3 and node 0, between node 1 and node 2, between node 1 and node 3, and between node 2 and node 3). This embodiment uses an independent structure, therefore the other capacitor is connected in parallel across switch S4 (e.g., ...). Figure 3 (As shown).

[0036] S105. Given the number of inductors N2; insert inductors into the adjacency matrix by introducing new nodes at the branches where inductors need to be inserted through node splitting, moving the original branch elements to the new node between the new node and one of the original nodes of the original branch, and connecting the inductor between the new node and another original node of the original branch.

[0037] (1) Check if there is a loop consisting only of an input source or a capacitor and a switch. If there is no such loop, proceed directly to step (3). Otherwise, insert an inductor into one of the branches of all the branches of the node contained in the loop. In this case, the loop is a parallel branch for the node. The adjacency matrix is ​​updated in the following ways: (a) If the inductor is inserted into an independent branch of the node, i.e., the branch is not a parallel branch, then the elements between the original two nodes of the branch in the adjacency matrix are set to 0, the original branch elements are moved to the new node and the other original node of the original branch, and the inductor is connected between the new node and the node where the inductor needs to be inserted, such as... Figure 6 As shown in (a) to (c) (where A, B, C, and D represent the components in each branch).

[0038] (b) If an inductor is inserted into one of the parallel branches, the original elements of the parallel branch in the adjacency matrix should be split. The elements between the two nodes of the original parallel branch are rewritten as all branch elements without the inductor. The original elements of the branch with the inductor are moved to the new node and the other original node of the original branch. The inductor is connected between the new node and the node where the inductor needs to be inserted, such as... Figure 6 As shown in (d) to (e).

[0039] (c) If an inductor is inserted into both an independent branch and a parallel branch, the adjacency matrix is ​​first updated according to (a) for the independent branch, and then updated according to (b) for the parallel branch, as follows. Figure 6 As shown in (f) to (i).

[0040] (2) In the updated adjacency matrix, check again whether there is a loop consisting of an input source or a capacitor and a switch. If such a loop exists, update the adjacency matrix according to step (1) until there is no such loop or the number of inserted inductors is equal to the number of given inductors.

[0041] (3) If the number of inductors currently inserted is equal to the number of given inductors, then the insertion of inductors ends; otherwise, randomly select a node branch with non-zero elements in the adjacency matrix from any node and insert an inductor. Introduce a new node at the branch where the inductor needs to be inserted by splitting the node. Set the elements between the two original nodes in the adjacency matrix of the branch to 0. Move the original branch element to the new node and one of the original nodes of the original branch. Connect the inductor between the new node and the other original node of the original branch.

[0042] (4) Repeat step (3) until the number of inductors currently inserted is equal to the number of given inductors.

[0043] In this embodiment of the invention, the adjacency matrix inserts capacitors first and then inductors. Compared with the method of inserting inductors first and then capacitors, this reduces the complexity and uncertainty caused by split nodes, making the derivation process more convenient and simple, and improving the efficiency of common-ground converter topology derivation. This embodiment provides an example of inductor insertion; the inductor is inserted accordingly based on the capacitor insertion position, and the result is as follows: Figure 4 As shown.

[0044] S106. Traverse all combinations of steps S104 and S105 until all topologies are obtained. Perform isomorphic screening and feasibility screening on the obtained topologies to obtain legal topologies.

[0045] The isomorphism screening is as follows: if the adjacency matrices of two topologies can be made completely identical by renumbering, then they are determined to be isomorphic, and one of the two topologies is eliminated.

[0046] Specifically, for two topologies, while keeping node 0 (the common node) unchanged, for one of the adjacency matrices, enumerate all possible renumbering methods (i.e. all permutations) of the remaining nodes {1, 2, ..., N-1}. By comparing the entire matrix, if there is a certain renumbering that makes the two matrices completely identical, it is determined to be isomorphic, and one of them is removed.

[0047] The feasibility screening is as follows: if the topology contains only input sources or capacitors and switches directly connected in parallel, or switches and inductors are connected in series in one branch; or three branches of the same node contain three inductors or two inductors and one switch respectively, then the topology is deemed infeasible and needs to be eliminated.

[0048] All remaining topologies after removing the above topologies are valid topologies.

[0049] S107. Based on Boolean logic, automatically enumerate the legal switch combinations of the legal topology, and combine depth-first search (DFS) to traverse the loop. Calculate the voltage gain, capacitance and voltage across the switch using the volt-second balance principle and Kirchhoff's voltage law. Then, determine whether the topology is "DC" or "inverter". Based on the required category, remove the topologies that do not need the category.

[0050] (1) Establish Boolean rules for each topology to determine all legal switch operating modes.

[0051] In a circuit consisting only of an input power supply, a capacitor, and switches, when the number of switches is greater than or equal to 2, all switches cannot be turned on simultaneously. The Boolean expression for this rule is: (S1 ∧ S2 ∧ S3 …); where S1, S2, and S3 represent switches. Based on the two Boolean expressions, all legal switch operating modes are determined. After obtaining the legal operating modes of the switches, all legal operating modes are combined in pairs to form the switching logic of the converter.

[0052] (2) Based on depth-first search (DFS), all loops in the topology are traversed to obtain the loop voltage equations.

[0053] Each loop must start from a node and return to that node, and the row number of the previous matrix element must be equal to the column number of the next matrix element; for each loop, the voltage equation is obtained according to Kirchhoff's voltage law, and the loop equation is for loops with the switch on; loops with the switch off are not calculated.

[0054] like Figure 5 As shown, each loop must start from a node and return to that node, and the row number of the previous matrix element must be equal to the column number of the next matrix element. For example, Adj(a, b) — Adj(b, c) — Adj(c, d) — Adj(d,a) can construct a loop (abcda). For each loop, the voltage equation is obtained according to Kirchhoff's Voltage Law (KVL), for example: Uab + Ubc + Ucd + Uda = 0. It should be noted that if the switch is open, the voltage across the switch is zero, so only the loop voltage equation containing the open switch needs to be listed (the switch's on and off states are obtained through the switch logic described above).

[0055] (3) In all the loops obtained in step (2), find the unique independent loop where each inductor is located (ensure that the loop contains only this inductor and no other inductors). That is, the loop contains only this inductor and no other inductors. Using the characteristic that the volt-second integral of the inductor is zero in steady state, establish a volt-second balance equation set for each inductor. Solve the equations of all inductors to form a linear equation set about the unknown capacitor voltage and the output voltage. Solve the linear equation set to obtain the voltage gain (expression about the duty cycle) and the expression of the voltage across the capacitor about the input voltage Uin.

[0056] (4) In all the loops obtained in step (2), find the effective loop that includes each switch and energy storage element, substitute all the known voltages obtained in step (3) into Kirchhoff's voltage law equation, and solve analytically for the voltage expression across the switch.

[0057] (5) Based on the voltage gain obtained in step (3), determine whether the topology is a "DC" or "inverter" topology.

[0058] Based on the voltage gain expression obtained above, determine whether the gain corresponding to its duty cycle D in the interval (0, 1) has the ability to output continuous positive and negative values ​​(i.e., positive and negative voltages). If it has the ability to output continuous positive and negative values, the topology is determined to have inverter function; if it has the ability to output a constant non-negative or constant non-positive voltage, it is determined to only support DC function.

[0059] (6) Repeat steps (1)-(5) until all legal topologies are classified.

[0060] (7) If the requirement is a DC topology, then all inverter topologies are eliminated from all legal topologies. If the requirement is an inverter topology, then all DC topologies are eliminated from all legal topologies.

[0061] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the invention. Therefore, the embodiments of the invention are not to be limited to the embodiments shown herein, but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for deriving the topology of a common-ground converter, characterized in that, Includes the following steps: (1) Determine the number of nodes na and the number of switches nb of the common-ground converter topology, which should be at least 3 nodes and 2 switches; (2) According to the double-grounded characteristic circuit, let the negative terminal of the input power supply and the negative terminal of the output terminal share the same ground, and define it as node 0; (3) Based on the number of nodes and the number of switches, construct an adjacency matrix to ensure that a loop is formed with the input power supply and the output terminal, and insert switches between the interconnected nodes; (4) Given the number of capacitors N1; insert capacitors into the adjacency matrix, wherein the capacitors are allowed to be placed between any two nodes; (5) Given the number of inductors N2; insert inductors into the adjacency matrix by introducing new nodes at the branch where inductors need to be inserted through node splitting, move the original branch elements to the new node between one original node of the original branch, connect the inductor between the new node and another original node of the original branch, and set the elements between the two nodes of the original branch in the adjacency matrix to 0. (6) Traverse all combinations of steps (4) and (5) until all topologies are obtained. Perform isomorphism screening and feasibility screening on the obtained topologies to obtain legal topologies. (7) Based on Boolean logic, legal switch combinations of legal topologies are automatically enumerated, and depth-first search (DFS) is used to traverse the loop. The voltage gain, capacitance and voltage across the switch are calculated using the volt-second balance principle and Kirchhoff's voltage law. Then, the topology is classified as "DC" or "inverter". Based on the required category, topologies that do not need to be classified are eliminated.

2. The method for deriving the topology of a common-ground converter according to claim 1, characterized in that: The adjacency matrix is ​​an N-order symmetric matrix used to mathematically represent the topological connections between nodes in the circuit.

3. The method for deriving the topology of a common-ground converter according to claim 1, characterized in that: In step (4), when inserting capacitors into the adjacency matrix, the number of capacitors is independent of the number of nodes and the number of switches, and different capacitors can exist between two nodes at the same time.

4. The method for deriving the topology of a common-ground converter according to claim 1, characterized in that: In step (4), when inserting a capacitor into the adjacency matrix, if it is an independent structure, one of the capacitors is connected to the parallel branch of the output load; if it is a grid-connected structure, the output terminal is directly connected to the power grid.

5. The method for deriving the topology of a common-ground converter according to claim 1, characterized in that, Step (5) specifically involves: (5.1) Check if there is a loop consisting only of an input source or a capacitor and a switch. If the loop does not exist, proceed directly to step (5.3). Otherwise, insert an inductor into one of the branches of all the branches of the node contained in the loop. In this case, the loop is a parallel branch for the node. Update the adjacency matrix in the following cases: (a) If the inductor is inserted into the independent branch of the node, that is, the branch is not a parallel branch, the element between the two original nodes of the branch in the adjacency matrix is ​​set to 0, the original branch element is moved to the new node and the other original node of the original branch, and the inductor is connected between the new node and the node where the inductor needs to be inserted. (b) If an inductor is inserted into one of the parallel branches, the original elements of the parallel branches in the adjacency matrix should be split, the elements between the two nodes of the original parallel branch should be rewritten as all the branch elements without the inductor, the original elements of the branch with the inductor should be moved to the new node and the other original node of the original branch, and the inductor should be connected between the new node and the node where the inductor needs to be inserted. (c) If an inductor is inserted into both an independent branch and a parallel branch at the same time, the adjacency matrix is ​​first updated according to (a) for the independent branch, and then updated according to (b) for the parallel branch. (5.2) In the topology corresponding to the updated adjacency matrix, check again whether there is a loop consisting of an input source or capacitor and switch. If such a loop exists, update the adjacency matrix according to step (5.1) until there is no such loop or the number of inserted inductors is equal to the number of given inductors. (5.3) If the number of inductors currently inserted is equal to the given number of inductors, then the insertion of inductors ends; otherwise, randomly select a node branch with non-zero elements in the adjacency matrix from any node and insert an inductor. Introduce a new node at the branch where the inductor needs to be inserted by splitting the node. Set the elements between the two original nodes in the adjacency matrix of the branch to 0. Move the original branch element to the new node and one of the original nodes of the original branch. Connect the inductor between the new node and the other original node of the original branch. (5.4) Repeat step (5.3) until the number of inductors currently inserted is equal to the number of given inductors.

6. The method for deriving the topology of a common-ground converter according to claim 1, characterized in that, The specific steps (6) are as follows: The isomorphic filtering is as follows: if the adjacency matrices of two topologies can be made completely identical by renumbering, then they are determined to be isomorphic, and one of the two topologies is eliminated. The feasibility screening is as follows: if the topology contains only input sources or capacitors and switches directly connected in parallel, or switches and inductors are connected in series in one branch; or three branches of the same node contain three inductors or two inductors and one switch respectively, then the topology is determined to be infeasible and needs to be eliminated. All remaining topologies after removing the above topologies are valid topologies.

7. The method for deriving the topology of a common-ground converter according to claim 1, characterized in that, The specific steps (7) are as follows: (7.1) Establish Boolean rules for each topology, determine all legal switch operating modes, and obtain legal switch combinations; In a circuit consisting only of an input power source, a capacitor, and switches, when the number of switches is greater than or equal to 2, all switches cannot be turned on simultaneously. The Boolean expression for this rule is: (S1 ∧ S2 ∧ S3 …); where S1, S2, and S3 represent switches. Based on these two Boolean expressions, determine all legal switch operating modes. After obtaining the legal operating modes of the switch, all legal operating modes are combined in pairs to form the switching logic of the converter. (7.2) Based on depth-first search (DFS), all loops in the topology are traversed to obtain the loop voltage equations; Each loop must start from a node and return to that node, and the row number of the previous matrix element must be equal to the column number of the next matrix element; for each loop, the voltage equation is obtained according to Kirchhoff's voltage law, and the loop equation is for loops with on switches; loops with off switches are not calculated. (7.3) In all the loops obtained in step (7.2), find the unique independent loop in which each inductor is located, that is, the loop only includes this inductor and does not include other inductors. Taking advantage of the characteristic that the volt-second integral of the inductor is zero in steady state, establish a volt-second balance equation system for each inductor. Solve the equations of all inductors to form a linear equation system about the unknown capacitor voltage and the output voltage. Solve the linear equation system to obtain the voltage gain and the voltage across the capacitor. (7.4) Among all the loops obtained in step (7.2), find the effective loop that includes each switch and energy storage element, substitute all the known voltages obtained in step (7.3) into Kirchhoff's voltage law equation, and solve analytically for the voltage expression across the switch. (7.5) Based on the voltage gain obtained in step (7.3), determine whether the topology is a "DC" or "inverter" topology; (7.6) Repeat steps (7.1)-(7.5) to complete the category determination of all legal topologies; (7.7) If the requirement is a DC topology, then all inverter topologies are eliminated from all valid topologies. If the requirement is an inverter topology, then all DC topologies are eliminated from all valid topologies.

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