Data verification system and verification method

Abstract

The invention provides a data verification system and method, and the method comprises a verification module which is used for generating a target signal in a first signal format, transmitting the target signal to a transmission module, and receiving a simulation operation result generated based on the target signal through the transmission module, comparing the simulation operation result with a real operation result of the target signal to obtain a verification result; the transmission module is used for receiving the target signal in the first signal format at the input end and converting the target signal into a second signal format for transmission, and converting the target signal in the second signal format back to the first signal format at the output end and outputting the target signal, and the precision loss of the transmission module for transmitting the signal in the second signal format is smaller than that of the transmission module for transmitting the signal in the first signal format; and the circuit simulation module is used for receiving the target signal in the first signal format through the transmission module for operation, and sending a generated simulation operation result to the verification module through the transmission module for verification.

Description

Technical Field

[0001] This disclosure relates to the fields of data processing and data transmission technology, and in particular to a data verification system and verification method. Background Technology

[0002] In mixed-signal systems, digital and analog circuits interact closely. Verifying the digital or analog components in isolation cannot cover issues such as interface compatibility and timing matching. Furthermore, mixed-signal circuits can lead to protocol errors or abnormal signal conversion at the digital-analog interface, resulting in reduced computational efficiency and accuracy loss. Summary of the Invention

[0003] In view of this, this disclosure provides a data verification system and verification method.

[0004] One aspect of this disclosure provides a data verification system, comprising: a verification module, configured to generate a target signal in a first signal format and send it to a transmission module, and to receive, through the transmission module, a simulated calculation result generated based on the target signal, and to compare the simulated calculation result with the actual calculation result of the target signal to obtain a verification result; a transmission module, configured to receive the target signal in the first signal format at an input end and convert it into a second signal format for transmission, and to convert the target signal in the second signal format back to the first signal format at an output end and output it, wherein the transmission module transmits the signal in the second signal format with less precision loss than the signal in the first signal format; and a circuit simulation module, configured to receive the target signal in the first signal format through the transmission module, perform calculations, and send the generated simulated calculation result to the verification module through the transmission module for verification.

[0005] According to an embodiment of this disclosure, the circuit simulation module includes: a first analog unit connected to the transmission module, used to receive a target signal and perform gain and analog-to-digital conversion processing to obtain a first intermediate signal in a second signal format; a digital filtering unit connected to the first analog unit, used to filter the first intermediate signal to obtain a second intermediate signal; and a second analog unit connected to the digital filtering unit, used to perform digital-to-analog conversion and filtering processing on the second intermediate signal in the second signal format to obtain and output the analog calculation result in the first signal format.

[0006] According to an embodiment of this disclosure, the first analog unit includes: an amplification subunit, configured to acquire a target signal in a first signal format and perform gain processing to obtain a gain signal; a first sub-transmission unit, connected to the amplification subunit, configured to receive the gain signal from the amplification subunit and convert it into a second signal format for transmission, convert the gain signal in the second signal format back to the first signal format at the output end and output it, and transmit it to an analog-to-digital conversion subunit; and an analog-to-digital conversion subunit, connected to the first sub-transmission unit, configured to quantize the gain signal in the first signal format to obtain a first intermediate signal in the second signal format, and output it to a digital filtering unit.

[0007] According to an embodiment of this disclosure, the second analog unit includes: a digital-to-analog conversion subunit, used to receive a second intermediate signal sent by a digital filtering unit and perform digital-to-analog conversion to obtain a converted analog signal in a first signal format; a second sub-transmission unit, connected to the digital-to-analog conversion subunit, used to convert the analog signal in the first signal format into a second signal format for transmission, and at the output end to convert the analog signal in the second signal format back to the first signal format and transmit it to the low-pass filtering subunit; and a low-pass filtering subunit, used to receive the analog signal sent by the second sub-transmission unit and perform low-pass filtering processing to obtain an analog calculation result, so that the transmission module can send the analog calculation result to the verification module for verification.

[0008] According to embodiments of this disclosure, the transmission module, the first sub-transmission unit, and the second sub-transmission unit all include a data transmission component. The data transmission component includes: an input sub-component for encoding a received signal in a first signal format to obtain a transmission signal in a second signal format; a transmission channel connected to the input sub-component for transmitting the transmission signal in the second signal format, wherein the transmission channel experiences less precision loss when transmitting the second signal format signal than when transmitting the first signal format signal, the first signal format including analog signal format, and the second signal format including digital signal format; and an output sub-component connected to the transmission channel for receiving the second signal format transmission signal, performing data conversion to obtain a signal in the first signal format, and outputting it.

[0009] According to an embodiment of this disclosure, the input sub-component is configured to: convert a signal of a first signal format into a signal of a second signal format with a first preset number of bits; and add a start code of a second preset number of bits before the signal of the second signal format to obtain a transmission signal of the second signal format.

[0010] According to an embodiment of this disclosure, the output sub-component is configured to: generate a data valid signal when receiving a transmission signal; obtain a signal to be processed in a second signal format based on the indication of the data valid signal, wherein the signal to be processed in the second signal format is obtained by shifting the transmission signal to remove the start code; determine the valid data range of the signal to be processed by performing data valid detection on the signal to be processed; and obtain a target signal in a first signal format by performing data conversion on the signal in the valid data range.

[0011] According to embodiments of this disclosure, the valid data signal is generated in the following manner: in response to detecting a start code, the output subcomponent controls the valid data signal to a first level; in response to the completion of start code reception, the output subcomponent controls the valid data signal to a second level until the reception of a signal with a first preset number of bits is completed.

[0012] According to embodiments of this disclosure, the input subcomponent receives a signal of a first signal format including exponential data of a fourth preset number of bits, and the output subcomponent performs data validity detection on the signal to be processed in the following manner: extracting data to be detected from the signal to be processed within a preset interval, the length of the preset interval being equal to the fourth preset number of bits; and determining the valid data interval of the signal to be processed based on the preset interval in response to the data to be detected conforming to the numerical range of the exponential data.

[0013] Another aspect of this disclosure provides a verification method, comprising: generating a target signal in a first signal format using a verification module and sending it to a transmission module; receiving the target signal in the first signal format using a circuit simulation module through the transmission module and performing calculations to obtain a simulation calculation result generated based on the target signal; receiving the simulation calculation result generated based on the target signal using the verification module through the transmission module; and comparing the simulation calculation result with the actual calculation result of the target signal using the verification module to obtain a verification result.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0015] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 A schematic block diagram of a data verification system according to an embodiment of the present disclosure is shown.

[0017] Figure 2 A schematic diagram illustrating the structure of a data transmission component according to an embodiment of the present disclosure is shown.

[0018] Figure 3 A schematic diagram illustrating the structure of a data verification system according to an embodiment of the present disclosure is shown.

[0019] Figure 4 This illustration schematically shows a data transmission diagram of a data transmission component according to an embodiment of the present disclosure;

[0020] Figure 5 A timing diagram of the data valid signal according to an embodiment of the present disclosure is schematically shown; and

[0021] Figure 6 A flowchart illustrating a verification method according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0022] The embodiments of this disclosure will now be described with reference to the accompanying drawings. Various details of the embodiments of this disclosure are included to aid understanding and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0023] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision, disclosure, and application of data (including but not limited to user personal information) comply with the provisions of relevant laws and regulations, necessary confidentiality measures have been taken, and they do not violate public order and good morals.

[0024] In mixed-signal processing systems, digital and analog circuits interact closely. Verifying the digital or analog circuitry in isolation can fail to cover issues such as interface compatibility and timing mismatch. Failures in mixed-signal circuits often stem from protocol errors or abnormal signal conversion at the digital-to-analog interface. For example, the control logic of a digital circuit may experience timing errors due to delays in the analog circuit, while the output of an analog circuit may be distorted by noise interference from the digital circuit. Mixed-signal verification comprehensively detects potential defects in the interaction between the digital and analog domains, ensuring that the analog-to-digital signal conversion conforms to design specifications.

[0025] In mixed-signal systems of digital and analog circuits, simulation verification methods include SPICE (Simulation Program With Integrated Circuit Emphasis), Verilog-AMS co-simulation, and behavioral model simulation. SPICE simulation technology enables precise analysis of transistor-level circuits with high accuracy; however, this significantly reduces simulation speed, making it unsuitable for verifying system-level analog circuits. Verilog-AMS co-simulation introduces analog and mixed-signal modeling capabilities to specify the behavior of analog and mixed-signal circuits. Verilog-AMS simulation improves simulation speed to some extent, but accuracy is somewhat reduced. Behavioral model simulation describes circuit functionality through mathematical equations or abstract algorithms. It uses behavioral language to model analog circuits, while digital circuits are modeled using register-transfer level modeling, significantly improving simulation speed. It enables system-level simulation on digital verification platforms, ensuring the uniformity of the simulation toolchain and achieving rapid verification of system-level functionality.

[0026] With increasing chip complexity and rapid project iteration, behavioral-level models are widely used in the early stages of system-level verification to quickly verify the functionality of analog circuits on digital verification platforms. During behavioral-level modeling, the interaction between the digital and analog domains impacts system-level behavior. If data conversion in analog circuits is not properly quantized—for example, mapping continuous voltage values ​​to a finite-bit digital signal—truncation errors may be introduced. Therefore, ensuring accurate and lossless data transmission within the verification platform and analog domain is a fundamental and necessary condition for achieving functional correctness verification.

[0027] Based on this, this disclosure proposes a data verification system that aims to connect digital and analog circuits using a transmission module without changing the signal format in the digital and analog domains, thereby ensuring accurate and efficient signal transmission and avoiding signal sampling misalignment.

[0028] Figure 1 A schematic block diagram of a data verification system according to an embodiment of the present disclosure is shown.

[0029] like Figure 1 As shown, the digital verification system 100 of this embodiment includes a verification module 110, a transmission module 120, and a circuit simulation module 130.

[0030] The verification module 110 is used to generate a target signal in a first signal format and send it to the transmission module, and to receive the simulation calculation results generated based on the target signal through the transmission module, and to compare the simulation calculation results with the actual calculation results of the target signal to obtain the verification results.

[0031] The verification module 110 can be a platform for generating simulated signals and performing operations such as parsing, comparing, and recording the collected data. The first signal format can refer to an analog signal format. The target signal can refer to a continuous analog signal generated by the verification module 110. The actual calculation result can be the result obtained by the verification module 110 based on the target signal. The verification result is obtained by parsing and comparing the collected simulated calculation result with the actual calculation result.

[0032] The transmission module 120 is used to receive a target signal in a first signal format at the input end and convert it into a second signal format for transmission, and at the output end to convert the target signal in the second signal format back to the first signal format and output it. The transmission module has less precision loss when transmitting a signal in the second signal format than when transmitting a signal in the first signal format.

[0033] The transmission module 120 can convert the received target signal in the first signal format into the second signal format for transmission. Before output, it deserializes the target signal in the second signal format, reconstructs the original target signal in the first signal format, and then outputs it.

[0034] In embodiments of this disclosure, the transmission module 120 transmits the target signal in a second signal format, but maintains the data type characteristics of the first signal format at the output.

[0035] The circuit simulation module 130 is used to receive the target signal in the first signal format through the transmission module, perform calculations, and send the generated simulation results to the verification module for verification through the transmission module.

[0036] The circuit simulation module 130 can be a behavioral model of an analog circuit. It can consist of multiple processing modules, implemented internally using a hardware description language. It performs calculations on the first signal format (analog signal) while preserving the physical characteristics of the real circuit. The circuit simulation module 130 performs calculations based on the received target signal of the first signal format, obtains the simulation result, and outputs it.

[0037] According to embodiments of this disclosure, a transmission module connects signal domains of different formats, enabling bidirectional conversion between the two signal formats. This ensures high-precision data calculation in the analog domain while avoiding precision loss during analog signal transmission, thereby improving the verification efficiency of the data verification system.

[0038] Figure 2A schematic diagram of the structure of a data transmission component according to an embodiment of the present disclosure is shown.

[0039] like Figure 2 As shown, the transmission module may include a data transmission component. In this embodiment, the data transmission component 220 includes an input sub-component 221, a transmission channel 222, and an output sub-component 223.

[0040] According to an embodiment of this disclosure, the input sub-component 221 is used to encode the received signal in a first signal format to obtain a transmission signal in a second signal format.

[0041] In embodiments of this disclosure, the input sub-component 221 can convert a signal in a first signal format into a signal in a second signal format based on the signal encoding function, and convert the real number field signal generated by the verification module into a single-bit wide serial data stream for transmission.

[0042] The transmission channel 222 is connected to the input sub-component 221 and is used to transmit a transmission signal in a second signal format. The transmission channel transmits a signal in the second signal format with less accuracy loss than it transmits a signal in the first signal format. The first signal format includes analog signal format and the second signal format includes digital signal format.

[0043] Transmission channel 222 is used to transmit signals with a single bit width to avoid loss of precision during signal transmission.

[0044] The output sub-component 223 is connected to the transmission channel and is used to receive the transmission signal in the second signal format, perform data conversion, obtain the signal in the first signal format, and output it.

[0045] The output sub-component 223 parses the transmitted signal in the second signal format and deserializes the transmitted signal into the original first signal format, so that the circuit simulation module or verification module can perform simulation calculations and analysis based on the signal output by the output sub-component 223.

[0046] According to embodiments of this disclosure, the data transmission component constructs a data conversion bridge between the analog circuit behavioral model and the verification platform, executes the verification process to complete the functional verification of the analog circuit, realizes rapid simulation and verification of the verification platform, and improves the efficiency of system-level functional verification.

[0047] Figure 3 A schematic diagram of the structure of a data verification system according to an embodiment of the present disclosure is shown.

[0048] like Figure 3As shown, the data verification system 300 of this embodiment includes a verification module 310, a transmission module, and a circuit simulation module 330. The transmission module includes a first transmission module 321 and a second transmission module 322. The first transmission module 321 is used to send the target signal in the first signal format generated by the verification module 310 to the circuit simulation module 330, and the second transmission module 322 is used to send the simulation calculation result of the circuit simulation module 330 to the verification module 310.

[0049] According to embodiments of this disclosure, the circuit simulation module 330 includes a first analog unit, a digital filtering unit, and a second analog unit. The first analog unit and the second analog unit are two signal processing paths within the circuit simulation module 330.

[0050] The first analog unit is connected to the first transmission module 321 and is used to receive the target signal, perform gain and analog-to-digital conversion processing to obtain the first intermediate signal in the second signal format.

[0051] The first analog unit is a signal processing path that performs gain and analog-to-digital conversion on the target signal. It obtains the target signal in a first signal format from the driver submodule 311 of the verification module 310 through the first transmission module 321, and converts the target signal into a first intermediate signal in a second signal format for subsequent processing.

[0052] The digital filtering unit may include a first digital filtering unit 3321 and a second digital filtering unit 3322. The first digital filtering unit 3321 is connected to the first analog unit and is used to filter the first intermediate signal and perform other processing based on actual needs. The second digital filtering unit 3322 is connected to the second analog unit and is used to filter the first intermediate signal after other processing to obtain a second intermediate signal.

[0053] The second analog unit, connected to the second digital filtering unit 3322, is used to perform digital-to-analog conversion and filtering on the second intermediate signal in the second signal format to obtain and output the analog calculation result in the first signal format.

[0054] The second analog unit is a signal processing path that performs digital-to-analog conversion and filtering on the second intermediate signal. After processing the second intermediate signal output by the second digital filtering unit 3322, it obtains the analog calculation result in the first signal format and sends the analog calculation result to the detection submodule 312 of the verification module 310 through the second transmission module 322.

[0055] According to embodiments of this disclosure, the first analog unit includes an amplification subunit 3311, a first sub-transmission unit 3312, and an analog-to-digital conversion subunit 3313. The first sub-transmission unit 3312 includes the data transmission component 200 described in the above embodiments.

[0056] In the embodiments of this disclosure, the first analog unit may be composed of an amplification subunit 3311 and an analog-to-digital conversion subunit 3313 in a cascaded structure, and the amplification subunit 3311 and the analog-to-digital conversion subunit 3313 are interconnected through a data transmission component in the first sub-transmission unit 3312.

[0057] The amplification subunit 3311 is used to acquire the target signal in the first signal format and perform gain processing to obtain the gain signal.

[0058] The amplification subunit 3311 acquires a target signal in a first signal format through the first transmission module 321. This target signal in the first signal format can be an analog audio excitation signal generated by the driving submodule of the verification module 310. The amplification subunit 3311 performs gain processing on the received target signal to obtain the amplified audio data, i.e., the gain signal.

[0059] The first sub-transmission unit 3312 is connected to the amplification sub-unit 3311. The first sub-transmission unit is used to receive the gain signal from the amplification sub-unit and convert it into a second signal format for transmission. At the output end, it converts the gain signal of the second signal format back to the first signal format and outputs it, and transmits it to the analog-to-digital conversion sub-unit.

[0060] The first sub-transmission unit 3312 is used to encode the gain signal output by the amplification sub-unit 3311, transmit it in a second signal format, and parse it into a gain signal in a first signal format after transmission for subsequent processing.

[0061] The analog-to-digital conversion subunit 3313 is connected to the first sub-transmission unit. The analog-to-digital conversion unit is used to quantize the gain signal of the first signal format to obtain the first intermediate signal of the second signal format, and output it to the digital filtering unit.

[0062] For example, the target signal in the first signal format generated by the verification platform driver can be a real-number analog audio excitation signal. First, the first sub-transmission unit 3312 converts the real-number analog audio excitation signal into a single-bit serial data stream and transmits it to the first analog unit. Then, it is converted back into a real-number signal at the output. Gain processing is performed by the amplification sub-unit 3311, and the signal is transmitted in the second signal format by the first sub-transmission unit 3312. Subsequently, when it is sent to the analog-to-digital conversion sub-unit 3313, it is re-encoded to obtain real-number gained audio data. The analog-to-digital conversion sub-unit 3313 performs analog-to-digital conversion on the gained audio signal to obtain the first intermediate signal in the quantized second signal format, which is then output to the first digital filtering unit 3321.

[0063] According to embodiments of this disclosure, the second analog unit includes a digital-to-analog conversion subunit 3331, a second sub-transmission unit 3332, and a low-pass filter subunit 3333. The second sub-transmission unit 3332 includes the data transmission component 200 described in the above embodiments. The signal transmission path of the second analog unit is opposite to that of the first analog unit.

[0064] In the embodiments of this disclosure, the second analog unit may be composed of a digital-to-analog conversion subunit 3331 and a low-pass filter subunit 3333 through a cascaded structure, and the digital-to-analog conversion subunit 3331 and the low-pass filter subunit 3333 are interconnected through a data transmission component in the second sub-transmission unit 3332.

[0065] The digital-to-analog conversion subunit 3331 is used to receive the second intermediate signal sent by the second digital filtering unit 3322 and perform digital-to-analog conversion to obtain an analog signal in the first signal format after conversion.

[0066] The second intermediate signal in the second signal format output by the second digital filtering unit 3322 is converted into an analog signal in the digital-to-analog conversion subunit 3331 to obtain an analog signal in the first signal format.

[0067] The second sub-transmission unit 3332 is connected to the digital-to-analog conversion sub-unit 3331. The second sub-transmission unit 3332 is used to convert the analog signal in the first signal format into the second signal format for transmission. At the output end, it converts the analog signal in the second signal format back into the first signal format and transmits it to the low-pass filter sub-unit 3333.

[0068] The second sub-transmission unit 3332 is used to encode the analog signal output by the digital-to-analog conversion sub-unit 3331, transmit it in a second signal format, and parse it into an analog signal in a first signal format after transmission for subsequent processing.

[0069] The low-pass filtering subunit 3333 is used to receive the analog signal sent by the second sub-transmission unit 3332 and perform low-pass filtering to obtain the analog calculation result, so that the transmission module can send the analog calculation result to the verification module 310 for verification.

[0070] According to embodiments of this disclosure, digital signal transmission between analog circuits and verification platforms is achieved through a data transmission component. It also enables data format conversion and transmission between modules within the analog circuit, ensuring the compatibility of the entire data verification environment and improving verification efficiency and accuracy.

[0071] Figure 4 A schematic diagram of data transmission of a data transmission component according to an embodiment of the present disclosure is shown.

[0072] like Figure 4As shown, the data transmission component of this embodiment includes an input subcomponent 421 and an output subcomponent 423.

[0073] According to an embodiment of the present disclosure, the input sub-component 421 is configured to: convert a signal 401 of a first signal format into a signal 402 of a second signal format with a first preset number of bits; and add a start code of a second preset number of bits before the signal 402 of the second signal format to obtain a transmission signal 403 of the second signal format.

[0074] In the embodiments of this disclosure, IEEE 754 double-precision floating-point numbers can be selected as the standard, and the first preset bit width can be 64 bits. After converting the signal 401 in the first signal format into the signal 402 in the second signal format with the first preset bit width, the total width of the binary format of the signal 402 in the second signal format is 64 bits, including a 1-bit sign bit, an 11-bit exponent width, and a 52-bit mantissa width. The signal 401 in the first signal format can be a real-valued voltage data of a sine wave.

[0075] The data processing flow of the input subcomponent 421 may include the following steps: First, the real2i conversion function is called to complete the binary conversion from real numbers to 64-bit wire data, resulting in signal 402 in the second signal format. After completing the 64-bit data binary conversion, according to the component transmission protocol requirements, a 4-bit binary start code (4'b0101) is appended before the most significant bit of the data as a frame synchronization identifier. Therefore, the resulting transmission signal 403 in the second signal format includes a 4-bit start code segment and a 64-bit valid data segment, meaning the frame structure of the transmission signal 403 in the second signal format is 68 bits.

[0076] According to an embodiment of this disclosure, the output sub-component 423 is configured to: generate a data valid signal upon receiving a transmission signal 403 of a second signal format; acquire a signal to be processed 404 of a second signal format based on the indication of the data valid signal, wherein the signal to be processed 404 of the second signal format is obtained by shifting the transmission signal 403 to remove the start code; perform data valid detection on the signal to be processed 403 based on a redundancy mechanism to determine the valid data range of the signal to be processed 403; and obtain the original signal 401 of the first signal format by performing data conversion on the signal of the valid data range.

[0077] In the embodiments of this disclosure, to ensure timing data alignment and avoid signal sampling misalignment, the output sub-component 423 is configured with a 2-bit redundancy mechanism. When receiving the transmission signal 403 of the second signal format through the transmission channel and performing left shift processing, two redundant bits are added to the transmission signal of the second signal format, and the 4-bit start code is removed to obtain the signal to be processed 404 of the second signal format. The frame structure bits of the signal to be processed in the second signal format are 66 bits, namely a 64-bit valid data segment and 2 bits of redundant bits randomly added before and after the valid data segment.

[0078] According to an embodiment of the present disclosure, the input subcomponent 421 receives a signal in a first signal format including exponential data of a fourth preset number of bits, and the output subcomponent 423 performs data validity detection on the signal to be processed in the following manner: extracting data to be detected in a preset interval from the signal to be processed 404 in a second signal format, wherein the length of the preset interval is equal to the fourth preset number of bits; and determining the valid data interval of the signal to be processed based on the preset interval in response to the data to be detected conforming to the numerical range of the exponential data.

[0079] In the embodiments of this disclosure, based on the consideration of offset, the output sub-component 421 may experience signal offset when receiving the transmission signal 403 of the second signal format. By detecting the possible regions of the exponential data, the signal offset can be determined, thereby determining the effective data range from the signal to be processed 404 of the second signal format containing the redundancy code, and thus determining the original signal 401 of the first signal format.

[0080] For example, offset can be 0, 1, or 2. When offset=0, the signal offset is 0, and the effective data range of the second signal format signal 404 to be processed should be [63:0], with a redundancy code of [65:64]. Therefore, the data to be detected in the preset range corresponding to offset=0 is exponential data of [62:52]. When offset=1, the signal offset is 1, and the effective data range of the second signal format signal 404 to be processed should be [64:1], with redundancy codes at bits 65 and 0. Therefore, the data to be detected in the preset range corresponding to offset=1 is exponential data of [63:53]. When offset=2, the signal offset is 2, and the effective data range of the second signal format signal 404 to be processed should be [65:2], with a redundancy code of [0:1]. Therefore, the data to be detected in the preset range corresponding to offset=2 is exponential data of [64:54].

[0081] In the embodiments of this disclosure, preset intervals can be set as [62:52], [63:53] and [64:54], respectively. By detecting whether the data to be detected in multiple preset intervals conforms to the numerical range of the exponential data, the signal offset and the corresponding effective data interval can be determined.

[0082] For example, the range of real numbers in the data to be detected corresponding to the valid data interval is (-2). 30 , -2 -100 ] ⋃[2 -100 , 2 30 The numerical range of the exponential data of the data to be detected can be determined as [-100+1023, (30-1)+1023], i.e. [923, 1052]. By detecting whether the data to be detected in the preset interval conforms to the numerical range of the exponential data, the valid data interval is determined, thereby extracting the valid signal from the valid data interval of the signal to be processed 404 in the second signal format, and converting the 64-bit valid data to the real data type through the i2real function to obtain the signal 401 in the first signal format.

[0083] According to embodiments of this disclosure, lossless data transmission between the analog circuit behavioral model and the digital verification platform is achieved based on the design of the data transmission component. Through a serialized data stream transmission mechanism between modules, the high-precision characteristics of the data in the analog circuit behavioral model are strictly maintained. All data interactions are completed based on a serial protocol with a start code, effectively avoiding cross-domain timing conflicts while ensuring the scalability of the digital system-level verification.

[0084] According to embodiments of this disclosure, the valid data signal is generated in the following manner: in response to detecting a start code, the output subcomponent controls the valid data signal to a first level; in response to the completion of start code reception, the output subcomponent controls the valid data signal to a second level until the reception of a signal with a first preset number of bits is completed.

[0085] Next, combined Figure 5 The generation of valid data signals in this disclosure will be further explained.

[0086] Figure 5 A timing diagram of a data valid signal according to an embodiment of the present disclosure is illustrated schematically.

[0087] like Figure 5As shown, the valid data signal can be determined based on the input signal received by the data transmission component. When the data transmission component detects the start code, the valid data signal is at a first level, which can be low; when the start code reception ends, the valid data signal changes to a second level, which can be high. The valid data signal continues to receive a signal of a second preset number of bits, and returns to the first level when reception is complete.

[0088] In the embodiments of this disclosure, the data transmission component transmits a set of signal data in a first signal format within a preset period T. Before and after receiving the signal data, the valid signal remains at the first level.

[0089] For example, the preset period T can be set to 1 nanosecond, and the data transmission component completes one data transmission within 1 nanosecond. Based on the IEEE 754 double-precision floating-point standard, the data transmission component needs to transmit data once every 0.70 nanoseconds within 1 nanosecond. That is, the valid signal remains low before and after data transmission and during the reception of the start code within 1 nanosecond.

[0090] According to embodiments of this disclosure, a frame structure for serialized data streams ensures strict timing alignment during data transmission between components. This mechanism delivers signals with high data density, ensuring that each signal transmission cycle is fully consistent with the analog circuit behavior-level model. While maintaining high simulation speed, the combination of timing synchronization and high-density sampling provides reliable data fidelity for mixed-signal interactions, ultimately supporting the accuracy of system-level verification results.

[0091] Figure 6 A flowchart illustrating a verification method according to an embodiment of the present disclosure is shown schematically.

[0092] like Figure 6 As shown, the verification method 600 of this embodiment includes operations S610-S640.

[0093] When operating S610, the verification module generates a target signal in the first signal format and sends it to the transmission module.

[0094] When operating S620, the circuit simulation module receives the target signal in the first signal format through the transmission module and performs calculations to obtain the simulation calculation result generated based on the target signal.

[0095] When operating the S630, the verification module receives the simulation results generated based on the target signal through the transmission module.

[0096] When operating the S640, the verification module compares the simulated calculation results with the actual calculation results of the target signal to obtain the verification results.

[0097] In the embodiments of this disclosure, the verification method may specifically include two processes: input stimulus generation and output response monitoring. The input stimulus generation stage may include operations S610-S620, where the verification module generates a continuous analog signal (e.g., a sine wave), encodes it using the input sub-component in the transmission module, and transmits it to the circuit simulation module. The output sub-component in the circuit simulation module then parses the signal into a real number type, and subsequently performs calculations based on the real number signal. The output response monitoring stage may include operations S630-S640, where the calculation result generated by the circuit simulation module is encoded by the input sub-component of the transmission module and transmitted in a first signal format. After being sent to the verification platform, the output sub-component performs conversion, and the converted real number data is collected and analyzed, thereby performing data comparison, recording, and other operations.

[0098] It should be noted that the collection, storage, use, processing, transmission, provision, disclosure, and application of user personal information in this disclosed technical solution comply with relevant laws and regulations, necessary confidentiality measures have been taken, and it does not violate public order and good morals. In this disclosed technical solution, user authorization or consent has been obtained before acquiring or collecting user personal information.

[0099] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on a user's computing device, partially on a user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0101] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0102] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A data verification system, comprising: The verification module is used to generate a target signal in a first signal format and send it to the transmission module, and to receive the simulation calculation result generated based on the target signal through the transmission module, and to compare the simulation calculation result with the actual calculation result of the target signal to obtain the verification result; The transmission module is used to receive the target signal in the first signal format at the input end and convert it into the second signal format for transmission, and to convert the target signal in the second signal format back to the first signal format at the output end and output it. The transmission module has less precision loss when transmitting the signal in the second signal format than when transmitting the signal in the first signal format. The circuit simulation module is used to receive the target signal of the first signal format through the transmission module, perform calculations, and send the generated simulation results to the verification module for verification through the transmission module.

2. The data verification system according to claim 2, characterized in that, The circuit simulation module includes: The first analog unit, connected to the transmission module, is used to receive the target signal and perform gain and analog-to-digital conversion processing to obtain a first intermediate signal in a second signal format; A digital filtering unit, connected to the first analog unit, is used to filter the first intermediate signal to obtain a second intermediate signal; The second analog unit, connected to the digital filtering unit, is used to perform digital-to-analog conversion and filtering on the second intermediate signal in the second signal format to obtain and output the analog calculation result in the first signal format.

3. The data verification system according to claim 2, characterized in that, The first simulation unit includes: An amplification subunit is used to acquire the target signal in the first signal format and perform gain processing to obtain a gain signal; The first sub-transmission unit is connected to the amplification sub-unit. The first sub-transmission unit is used to receive the gain signal from the amplification sub-unit and convert it into a second signal format for transmission. At the output end, the gain signal in the second signal format is converted back to the first signal format and output, and then transmitted to the analog-to-digital conversion sub-unit. An analog-to-digital conversion subunit is connected to the first sub-transmission unit. The analog-to-digital conversion unit is used to quantize the gain signal of the first signal format to obtain the first intermediate signal of the second signal format, and output it to the digital filtering unit.

4. The data verification system according to claim 2, characterized in that, The second simulation unit includes: The digital-to-analog conversion subunit is used to receive the second intermediate signal sent by the digital filtering unit, perform digital-to-analog conversion, and obtain an analog signal in the first signal format after conversion. The second sub-transmission unit is connected to the digital-to-analog conversion sub-unit. The second sub-transmission unit is used to convert the analog signal in the first signal format into the second signal format for transmission, and at the output end, convert the analog signal in the second signal format back to the first signal format and transmit it to the low-pass filter sub-unit. The low-pass filtering subunit is used to receive the analog signal sent by the second sub-transmission unit and perform low-pass filtering to obtain the analog calculation result, so that the transmission module can send the analog calculation result to the verification module for verification.

5. The data verification system according to claims 1-4, characterized in that, The transmission module, the first sub-transmission unit, and the second sub-transmission unit all include a data transmission component, which includes: The input sub-component is used to encode the received signal in the first signal format to obtain the transmission signal in the second signal format. A transmission channel, connected to the input sub-component, is used to transmit the transmission signal in a second signal format. The transmission channel transmits the signal in the second signal format with less loss of accuracy than it transmits the signal in the first signal format. The first signal format includes an analog signal format, and the second signal format includes a digital signal format. The output sub-component, connected to the transmission channel, is used to receive the transmission signal in the second signal format, perform data conversion, obtain the signal in the first signal format, and output it.

6. The data verification system according to claim 5, characterized in that, The input subcomponent is configured as follows: Convert the signal in the first signal format into a signal of the second signal format with a first preset number of bits; A second preset number of start codes is added before the signal in the second signal format to obtain the transmission signal in the second signal format.

7. The data verification system according to claim 5, characterized in that, The output sub-component is configured as follows: Upon receiving the transmitted signal, a data valid signal is generated; Based on the indication of the data valid signal, a signal to be processed in a second signal format is obtained, wherein the signal to be processed in the second signal format is obtained by shifting the transmitted signal to remove the start code; Based on a redundancy mechanism, the signal to be processed is subjected to valid data detection to determine the valid data range of the signal to be processed. The target signal in the first signal format is obtained by performing data conversion on the signal in the effective data range.

8. The data verification system according to claim 7, characterized in that, The valid data signal is generated in the following manner: In response to detecting that the start code has been received, the output subcomponent controls the data valid signal to a first level; In response to the completion of the start code reception, the output sub-component controls the data valid signal to the second level until the signal reception of the first preset number of bits is completed.

9. The data verification system according to claim 7, characterized in that, The input subcomponent receives a signal in a first signal format including exponential data of a fourth preset bit length, and the output subcomponent performs data validity detection on the signal to be processed in the following manner: Extract the detection data of the preset interval from the signal to be processed, wherein the length of the preset interval is equal to the fourth preset number of bits; In response to the detection data conforming to the numerical range of the exponential data, the effective data range of the signal to be processed is determined according to the preset range.

10. A verification method applied to a data verification system as described in any one of claims 1-9, the method comprising: The verification module generates a target signal in the first signal format and sends it to the transmission module. The circuit simulation module receives the target signal of the first signal format through the transmission module and performs calculations to obtain the simulation calculation result generated based on the target signal. The verification module receives the simulation results generated based on the target signal through the transmission module. The verification module compares the simulated calculation results with the actual calculation results of the target signal to obtain the verification results.

Images