Signal quality optimization method and device and medium
By embedding capacitors at the power vias and connecting them to the ground plane, the problem of limited signal return paths in the BGA area is solved, improving signal quality and circuit performance. In particular, in densely packaged areas, it provides local low-impedance paths to enhance signal integrity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INSPUR (SHANDONG) COMPUTER TECH CO LTD
- Filing Date
- 2026-01-29
- Publication Date
- 2026-05-08
AI Technical Summary
In densely packaged areas such as BGA, the return path of high-speed signals cannot be improved through ground vias, resulting in a decline in signal quality. This manifests as oscillations in the impedance curve of differential vias and increased return loss, affecting the performance and reliability of the circuit system.
In a printed circuit board, locate the signal pins whose signal quality needs to be improved, and bring out power vias from the power pins around them. Through the blind vias, the power is transmitted to the ground plane, where a capacitor is embedded. The second end of the capacitor is connected to the ground via, forming a local low-impedance return path.
By connecting the ground plane with a capacitor, the signal return path is shortened, the continuity of the signal impedance is improved, the signal quality is enhanced, power supply noise is filtered out, and the regional signal quality is optimized.
Smart Images
Figure CN121997877A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit design technology, and in particular to a signal quality optimization method, apparatus, and medium. Background Technology
[0002] In high-speed circuit design, the signal return path has a crucial impact on signal quality. Typically, the optimal return path for a signal is ground (GND). For traces, it is desirable to reference the GND plane to ensure signal transmission stability; for signal pins, a GND pin is required to provide a good return path; for high-speed signal fan-out vias in Ball Grid Array (BGA) packages, it is desirable for them to be surrounded by adjacent ground vias to reduce signal reflection and crosstalk.
[0003] However, in practical circuit design, some unavoidable situations often arise. For example, in the BGA area, multiple power pins may be distributed around high-speed differential signal pins, leaving no space for ground vias. Furthermore, due to design constraints or other reasons, these power pins cannot be replaced with GND pins, making it difficult to directly improve the return path through ground vias. This layout can lead to interference with the return path of high-speed signals, resulting in signal quality degradation. Specifically, this manifests as oscillations in the impedance curve of differential vias, increased return loss, and other problems, ultimately affecting the performance and reliability of the entire circuit system.
[0004] Therefore, those skilled in the art urgently need a signal quality optimization method to solve the problem that the return path cannot be improved through ground vias in densely packaged areas such as BGA. Summary of the Invention
[0005] The purpose of this invention is to provide a signal quality optimization method, apparatus, and medium to solve the problem that the return path cannot be improved through ground vias in densely packaged areas such as BGA.
[0006] To address the aforementioned technical problems, this invention provides a signal quality optimization method, comprising:
[0007] Locate the signal pins on the printed circuit board that require improved signal quality, and identify the power supply pins surrounding the signal pins as target pins;
[0008] Power vias corresponding to the target pins are led out from the surface layer of the printed circuit board, and the power vias are made to penetrate to the ground layer below the power layer where the power pins are located through blind vias.
[0009] A capacitor is embedded in the grounding layer, and the first end of the capacitor is connected to the power via.
[0010] A ground hole is made connecting the ground layer to the bottom layer, and the second end of the capacitor is connected to the ground hole.
[0011] In one alternative embodiment, the capacitor is a decoupling capacitor for the power supply pin.
[0012] In one alternative embodiment, the number of capacitors is multiple, and the capacitors are connected in parallel.
[0013] In one alternative embodiment, the capacitance values of each capacitor are different, and the capacitance value of each capacitor is determined according to the frequency of the power supply noise corresponding to the power supply pin.
[0014] In one alternative embodiment, the distance between the first end of the capacitor and the power via, and the distance between the second end of the capacitor and the ground via, are both less than 0.5 mm.
[0015] In one alternative embodiment, the width of the trace between the first end of the capacitor and the power via, and the width of the trace between the second end of the capacitor and the ground via, are greater than or equal to 0.2 mm.
[0016] In one alternative embodiment, the trace between the first end of the capacitor and the power via, and the trace between the second end of the capacitor and the ground via, are straight segments, or a combination of straight segments and 45° angled broken lines or arc segments.
[0017] To address the aforementioned technical problems, the present invention also provides a signal quality optimization device, comprising:
[0018] The positioning module is used to locate the signal pins on the printed circuit board that require improved signal quality and to identify the power supply pins around the signal pins as target pins.
[0019] The via module is used to bring out the power via corresponding to the target pin on the surface layer of the printed circuit board, and to allow the power via to penetrate to the ground layer under the power layer where the power pin is located through a blind via.
[0020] An embedded capacitor module is used to embed a capacitor in the grounding layer, and the first end of the capacitor is connected to the power via.
[0021] A grounding module is used to create a ground hole from the grounding layer to the bottom layer, and the second end of the capacitor is connected to the ground hole.
[0022] To address the aforementioned technical problems, the present invention also provides a signal quality optimization device, comprising:
[0023] Memory, used to store computer programs;
[0024] A processor is used to implement the signal quality optimization method described above when executing the computer program.
[0025] To address the aforementioned technical problems, the present invention also provides a non-volatile storage medium storing a computer program, which, when executed by a processor, implements the steps of the signal quality optimization method described above.
[0026] This invention provides a signal quality optimization method by adding a capacitor at a power via to connect to the ground plane. This allows the signal return path to directly reach the ground plane via the power via and capacitor, thereby shortening the signal return path, improving signal impedance integrity, and enhancing signal quality. Furthermore, this capacitor can also filter power supply noise within the power via. In addition, the capacitor in this method is embedded. The capacitor is embedded in the ground plane below the power layer where the power via is located; the power via penetrates to the ground plane through a blind via and connects to the first end of the capacitor; the second end of the capacitor connects to a ground via, which is a via penetrating from the ground plane to the bottom layer of the printed circuit board. Based on this configuration, the embedded capacitor does not occupy space on the effective surface and signal layers, and allows signal pins below the ground plane to also utilize this capacitor to filter power supply noise and use the ground via as a reference return path, achieving further optimization of regional signal quality in space-constrained scenarios.
[0027] The signal quality optimization device and non-volatile storage medium provided by this invention correspond to the above-described method and have the same effect. Attached Figure Description
[0028] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of a BGA region circuit layout provided in an embodiment of the present invention;
[0030] Figure 2 A flowchart of a signal quality optimization method provided in an embodiment of the present invention;
[0031] Figure 3 A schematic diagram of another BGA region circuit layout provided in an embodiment of the present invention;
[0032] Figure 4 Impedance comparison diagram of a 3 / 4 power via layout provided in an embodiment of the present invention;
[0033] Figure 5A comparison diagram of return loss for a 3 / 4 power via layout provided in an embodiment of the present invention;
[0034] Figure 6 This is a schematic diagram of a circuit layout after embedding a capacitor, provided in an embodiment of the present invention;
[0035] Figure 7 An impedance comparison diagram before and after optimization using this method is provided for a 3-power via layout according to an embodiment of the present invention.
[0036] Figure 8 A comparison diagram of return loss before and after optimization of a 3 / 4 power via layout provided in an embodiment of the present invention using this method;
[0037] Figure 9 This is a structural diagram of a signal quality optimization device provided in an embodiment of the present invention;
[0038] Figure 10 This is a structural diagram of another signal quality optimization device provided in an embodiment of the present invention. Detailed Implementation
[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.
[0040] The core of this invention is to provide a signal quality optimization method, apparatus, and medium.
[0041] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0042] In high-speed circuit design, the signal return path has a crucial impact on signal quality. Typically, the optimal return path for a signal is ground (GND). Therefore, traditional circuit design methods involve placing ground vias near high-speed signal traces to create a good return path. However, in practical circuit design, some unavoidable situations often arise. For example, in densely packaged areas such as ball grid array (BGA) packages, wiring space limitations prevent the placement of ground vias near every signal pin. In such cases, if adjacent pins are power supply pins, it is difficult to directly improve the return path using ground vias.
[0043] For example, a scenario where a BGA area signal pin is surrounded by power pins is as follows: Figure 1As shown, the red circles indicate power vias, the yellow areas represent electrical component packages, and the purple, pink, green, and white (with grid-like stripes) areas represent different layers of the printed circuit board (PCB). This layout can cause interference to the return path of high-speed signals, resulting in a degraded signal quality. Specifically, this manifests as oscillations in the impedance curves of differential vias, increased return loss, and other problems, ultimately affecting the performance and reliability of the entire circuit system.
[0044] To address the above problems, this invention provides a signal quality optimization method, such as... Figure 2 As shown, it includes:
[0045] S1: Locate the signal pin on the printed circuit board that requires improved signal quality, and identify the power supply pins around the signal pin as the target pin.
[0046] S2: Lead out the power via corresponding to the target pin on the surface layer of the printed circuit board, and make the power via penetrate to the ground layer under the power layer where the power pin is located through a blind via.
[0047] S3: Embed a capacitor in the grounding layer, with the first end of the capacitor connected to the power via.
[0048] S4: Create a ground hole from the ground layer to the bottom layer, and connect the second end of the capacitor to the ground hole.
[0049] The location of the target pin in step S1 can be achieved through simulation testing. For example, let's take... Figure 1 Taking the BGA region shown as an example: Figure 1 The circular holes within the white, grid-patterned oval area are a pair of differential signal vias; the signal holes surrounded by red circles are power vias; the rest are ground vias. In other words, Figure 1 There are four power vias surrounding one set of differential signal vias. For comparison, we also consider... Figure 1 The layout is the same as in the previous example, but this group of differential signal holes is surrounded by three power vias (the power vias are also signal holes circled in red). Figure 3 As shown.
[0050] Regarding the above, Figure 1 and Figure 3 Simulations were performed on high-speed signals under the two PCB layouts shown, and the impact of the number of power supply pins on the quality of high-speed signals was compared. The simulation results are as follows: Figure 4 and Figure 5 As shown. Among them, Figure 4 This is a simulation result of the impedance of a 100G KR signal (G, Gbps, is the unit of communication rate; KR is the backplane Ethernet standard) in scenarios with 4 power vias (4PWR via) and 3 power vias (3 PWR via). Figure 5This image shows simulation results of return loss (RL) for a 100G KR signal under 4-power-via and 3-power-via scenarios. The image clearly shows that the impedance and return loss are significantly better in the 3-power-via scenario than in the 4-power-via scenario. Impedance and return loss are important indicators of signal impedance continuity. For a 100G KR signal, the design impedance is 100 ohms. Figure 4 As can be seen, the impedance fluctuation of four power supply vias is higher than that of three power supply vias. From... Figure 5 As can be seen, in the frequency band below 12.9GHz, the maximum return loss is -17.5dB with 4 power vias and -21.9dB with 3 power vias. This demonstrates that the number of power vias (or ground vias) surrounding a signal via significantly affects its return loss and impedance continuity. Therefore, by conducting simulation tests on the signal vias, and based on the simulation results and the requirements for return loss and impedance continuity in actual circuit design, the signal pins that need signal quality optimization using this method can be determined.
[0051] Furthermore, after identifying the signal pin requiring signal quality optimization in step S1, the power supply pins "surrounding" it are selected as the "surrounding" target pins. This can be defined by a preset distance threshold. That is, power supply pins whose distance from the signal pin is less than or equal to this distance threshold can be used as the target pins corresponding to that signal pin. Conversely, power supply pins whose distance is greater than this distance threshold are not considered target pins. This embodiment does not impose a limitation on this distance threshold; it can be determined based on actual circuit design requirements and the magnitude of the influence of power supply pins on signal pins at different distances.
[0052] Steps S2 to S4 are the core steps of this method. This method provides a localized low-impedance path for high-speed signals in BGA areas where space is limited and a GND pin cannot be placed, by adding a capacitor at the target pin (power supply pin). This allows the return current of the high-speed signal to quickly return to the ground plane through the capacitor, thereby improving the impedance continuity of the signal path and enhancing signal integrity.
[0053] Furthermore, due to the limited space in the BGA area and the inability to modify the pin distribution, especially on the surface layer, there is no space to add capacitors. Therefore, this method uses embedded capacitors to add capacitors. A capacitor is embedded in the ground layer (GND layer) below the power layer (PWR layer) where the target pin is located. A blind via is used to connect the target pin to the surface layer (TOP layer) and this GND layer, allowing the high-frequency signal (signal pin), power signal (target pin), and the embedded capacitor (first terminal) to be interconnected. Then, grounding the second terminal of this embedded capacitor in the GND layer provides a return path for the high-frequency signal. This method further involves drilling another ground via in the GND layer where the embedded capacitor is located, extending from the GND layer directly to the bottom layer of the PCB (BOT layer). This allows the signal vias below the embedded capacitor's GND layer to use this ground via as a reference for return current, further optimizing the signal quality of each layer of the PCB within the BGA area.
[0054] To better understand this method, the following explanation uses a common PCB design with multiple layers as an example: Assume a 14-layer PCB design, from top to bottom: TOP layer, L2 to L13 layers, and BOT layer. Among these, TOP, L6, L8, L10, L12, and BOT layers are signal layers; L3 and L4 layers are PWR layers; and L2, L5, L7, L9, L11, and L13 layers are GND layers.
[0055] When embedding the capacitor, any GND layer below the PWR layer (L3 or L4, hereinafter assumed to be L3) where the target pin is located can be selected as the ground layer for embedding the capacitor. However, to further improve signal quality, the length of the return path should be shortened as much as possible, that is, the length of the signal via should be shortened as much as possible. Therefore, the GND layer for embedding the capacitor should be the GND layer closest to the PWR layer where the target pin is located, corresponding to the L5 layer in the example above. That is, in this example, the capacitor is embedded in the L5 layer; the first end of the capacitor corresponds to the via, which connects the TOP layer to the L5 layer, so that the capacitor can be connected to the target pin in the L3 layer and the signal pin in the TOP layer; the second end of the capacitor corresponds to the ground via, which connects the L5 layer to the BOT layer. On the one hand, it grounds the capacitor, providing a return path for the signal pin in the TOP layer; on the other hand, the ground via can also provide a reference ground for the signal vias in the L6, L8, L10, L12 and BOT layers, that is, return through the ground via. Therefore, this method can make greater use of space to optimize local signal quality even when space is limited.
[0056] One possible layout after embedding capacitors is as follows: Figure 6 As shown. In Figure 6In the diagram, the yellow holes are power vias with embedded capacitors; the thick yellow lines represent the capacitor packages; the gray holes represent ground holes; and the rest of the PCB is not covered in this method and will not be described further.
[0057] by Figure 3 Taking the 3 PWR via layout shown as an example, when capacitors are added to the 3 power vias using this method, the result is as follows: Figure 7 The impedance simulation results are shown. Furthermore... Figure 8 China also Figure 1 The 4 PWR via layout shown is simulated with return loss before and after optimization using this method to compare signal quality. Figure 7 and Figure 8 It is easy to see that by adding a capacitor using this method, the oscillation of the differential via impedance curve is significantly reduced, and the return loss is also significantly reduced.
[0058] It should also be noted that this invention does not limit the number of capacitors embedded. Considering that this method targets scenarios with limited space, generally only one capacitor needs to be embedded to reduce the area occupied by the capacitor. However, if circuit space allows, or if combining multiple capacitors (such as in parallel) can actually reduce the footprint, then multiple capacitors can be embedded; this invention does not limit this. A corresponding optional embodiment is also provided: multiple capacitors are connected in parallel. This embodiment uses multiple parallel capacitors to form a capacitor network, expanding the range of capacitor selection and making the application of this method more flexible. Furthermore, connecting multiple capacitors in parallel can increase the capacitance and reduce the equivalent series inductance (ESL), further improving the signal quality optimization effect.
[0059] In summary, the signal quality optimization method provided by this invention offers a localized low-impedance path for high-speed signals in the BGA region at high frequencies by adding a capacitor. This allows the return current of the high-speed signal to return to the ground plane more quickly through the capacitor, thereby improving the impedance continuity of the signal path and enhancing signal integrity. It provides a solution for scenarios where the BGA region is constrained by the package structure, and the presence of power pins around the signal pins leads to poor signal quality, thus addressing a current industry pain point in circuit design for high-speed signals within limited space.
[0060] On the other hand, the capacitor embedded in the above embodiment can be a newly added capacitor. However, this embodiment also provides another optional embodiment: the capacitor is a decoupling capacitor for the power supply pin.
[0061] It is readily known that in conventional circuit design, decoupling capacitors are typically placed on power supply pins to filter noise in power signals and achieve power decoupling. Therefore, this embodiment reuses this decoupling capacitor as the aforementioned capacitor, eliminating the need for additional capacitors. However, it should be noted that existing decoupling capacitors are not necessarily embedded in the GND layer below the PWR layer of the target pin as described in step S2 above. If the design allows, the placement of the decoupling capacitor can be modified using the steps described above. If the design does not allow, this decoupling capacitor can also be combined with the capacitor embedded in this method to provide a return path for the signal, further improving signal quality.
[0062] Furthermore, the capacitance value of the decoupling capacitor is generally determined based on the frequency of the noise being filtered. For example, assuming the operating frequency of this circuit is 0~67GHz, the capacitance values of the decoupling capacitors for the four common high-speed signal scenarios are 0.1nF, 1nF, and 10nF. In addition, assuming the signal pin whose signal quality needs to be improved operates near 12.9GHz, a 1nF capacitor has the best return loss effect; a 0.1nF capacitor is not effective due to its high high-frequency impedance; and a 10nF capacitor also fails to achieve its best performance due to its large parasitic inductance.
[0063] That is, when multiplexing decoupling capacitors to provide signal return paths, the capacitance value can be further selected based on the need to filter noise. Furthermore, when there are multiple different frequencies of noise in the power signal, this embodiment provides a further embodiment based on the above embodiment of multiple capacitors connected in parallel: each capacitor has a different capacitance value, and the capacitance value of each capacitor is determined according to the frequency of the power noise corresponding to the power supply pin.
[0064] Using the example above, in addition to the 1nF capacitor, 0.1nF and 10nF capacitors can be connected in parallel to form a multi-stage decoupling network. The 0.1nF capacitor is mainly used to filter out high-frequency noise, while the 10nF capacitor is used to filter out low-frequency noise (the aforementioned high and low frequencies are relative to the noise frequency band targeted by the 1nF capacitor), further improving signal quality.
[0065] On the other hand, besides the selection of capacitor value, the placement of the capacitor is equally important for improving signal quality. Based on the general requirements for operating frequency and signal quality in current high-speed signal circuit design scenarios, this embodiment provides an optional implementation: the distance between the first end of the capacitor and the power supply via, and the distance between the second end of the capacitor and the ground via, are both less than 0.5 mm.
[0066] It should be noted that the 0.5mm distance value provided in this embodiment is only one option. Other distance settings can be adopted in practical applications, depending on the actual operating frequency and signal quality requirements. Furthermore, if the layout allows, the capacitor should be as close to the power pin as possible. The closer the capacitor is to the target pin, the shorter the trace length between them, i.e., the shorter the return current path, and the better the signal quality optimization effect. In addition, the distance between the two ends of the capacitor should also be as short as possible to further shorten the return current path length.
[0067] As can be seen from the above embodiments, the distance between the capacitor and the power supply pin directly affects the trace length, so the closer the capacitor is to the power supply pin, the better. Furthermore, this embodiment also provides an optional embodiment in another aspect: the width of the trace between the first end of the capacitor and the power supply via, and the width of the trace between the second end of the capacitor and the ground via, are greater than or equal to 0.2mm. That is, combining this embodiment and the previous embodiment, the capacitor trace should be as short and wide as possible to reduce trace resistance and inductance, thereby improving the optimization effect on signal quality.
[0068] On the other hand, apart from the limitations on distance and trace width in the above embodiments, this embodiment also provides an optional embodiment for the trace method between capacitor and power via and ground via: the trace between the first end of the capacitor and the power via, and the trace between the second end of the capacitor and the ground via, are straight segments, or a combination of straight segments and 45° angled broken line segments or arc segments.
[0069] As described in this embodiment, when routing capacitor traces, right-angle or acute-angle bends should be avoided. 45° angles or rounded bends can be used to reduce signal reflection and loss. Simultaneously, care should be taken to ensure that capacitor traces do not cross or run parallel to other signal lines to avoid crosstalk. Furthermore, for high-frequency signals, a ground plane can be laid under the capacitor to further reduce its equivalent inductance and improve decoupling.
[0070] In addition to the signal quality optimization method embodiment provided in the above embodiments, the present invention also provides an embodiment corresponding to a computer program product. A computer program product includes a computer program / instructions, which, when executed by a processor, can implement the steps of the signal quality optimization method as described in any of the above embodiments.
[0071] Since the embodiments of the computer program product portion correspond to the embodiments of the method portion, please refer to the description of the embodiments of the method portion for the embodiments of the computer program product portion, which will not be repeated here.
[0072] In the above embodiments, a signal quality optimization method has been described in detail. The present invention also provides an embodiment corresponding to a signal quality optimization device. It should be noted that the present invention describes the device embodiment from two perspectives: one based on functional modules, and the other based on hardware.
[0073] From the perspective of functional modules, such as Figure 9 As shown, this embodiment provides a signal quality optimization device, including:
[0074] The positioning module 11 is used to locate the signal pins on the printed circuit board that require improved signal quality, and to determine the power supply pins around the signal pins as target pins.
[0075] The via module 12 is used to lead out the power via corresponding to the target pin on the surface layer of the printed circuit board, and to allow the power via to penetrate to the ground layer under the power layer where the power pin is located through a blind via.
[0076] Embedded capacitor module 13 is used to embed a capacitor in the grounding layer, and the first end of the capacitor is connected to the power supply via.
[0077] Grounding module 14 is used to create a ground hole from the grounding layer to the bottom layer, and the second end of the capacitor is connected to the ground hole.
[0078] Since the embodiments of the device section correspond to the embodiments of the method section, please refer to the description of the embodiments of the method section for the embodiments of the device section, and they will not be repeated here. This embodiment provides a signal quality optimization device that provides a local low-impedance path for high-speed signals in the BGA region at high frequencies by adding a capacitor. This allows the return current of the high-speed signal to return to the ground plane more quickly through the capacitor, thereby improving the impedance continuity of the signal path and enhancing signal integrity. It provides a solution for scenarios where the BGA region is constrained by the package structure, and the distribution of power pins around the signal pins leads to poor signal quality, thus addressing the current industry pain point in circuit design for high-speed signals in limited space.
[0079] Figure 10 A structural diagram of a signal quality optimization device provided in another embodiment of the present invention is shown below. Figure 10 As shown, a signal quality optimization device includes: a memory 20 for storing computer programs;
[0080] The processor 21 is used to implement the steps of a signal quality optimization method as described in the above embodiment when executing a computer program.
[0081] The signal quality optimization device provided in this embodiment may include, but is not limited to, mobile terminals, personal computers, workstations, etc.
[0082] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array. The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.
[0083] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of a signal quality optimization method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, a signal quality optimization method.
[0084] In some embodiments, a signal quality optimization device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
[0085] Those skilled in the art will understand that Figure 10 The structure shown does not constitute a limitation on a signal quality optimization device and may include more or fewer components than shown.
[0086] This invention provides a signal quality optimization device, including a memory and a processor. When the processor executes a program stored in the memory, it can implement a signal quality optimization method. The signal quality optimization device provided in this embodiment can implement the aforementioned signal quality optimization method. Specifically, by adding a capacitor, a local low-impedance path is provided for high-speed signals in the BGA region at high frequencies. This allows the return current of the high-speed signal to return to the ground plane more quickly through the capacitor, thereby improving the impedance continuity of the signal path and enhancing signal integrity. This provides a solution for scenarios where the BGA region is limited by the package structure, and the distribution of power pins around the signal pins leads to poor signal quality, solving a current industry pain point in circuit design for high-speed signals in limited space.
[0087] Finally, the present invention also provides an embodiment corresponding to a non-volatile storage medium. A computer program is stored on the non-volatile storage medium, and when executed by a processor, the computer program implements the steps described in the above method embodiments.
[0088] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0089] This embodiment provides a non-volatile storage medium storing the signal quality optimization method provided in the above embodiment. When the stored signal quality optimization method is executed, it can provide a local low-impedance path for high-speed signals in the BGA region at high frequencies by adding a capacitor. This allows the return current of the high-speed signal to return to the ground plane more quickly through the capacitor, thereby improving the impedance continuity of the signal path and enhancing signal integrity. This provides a solution for scenarios where the BGA region is constrained by the package structure, and the distribution of power pins around the signal pins leads to poor signal quality, thus addressing a current industry pain point in circuit design for high-speed signals within limited space.
[0090] The signal quality optimization method, apparatus, and medium provided by the present invention have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the present invention.
[0091] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
Claims
1. A signal quality optimization method, characterized in that, include: Locate the signal pins on the printed circuit board that require improved signal quality, and identify the power supply pins surrounding the signal pins as target pins; Power vias corresponding to the target pins are led out from the surface layer of the printed circuit board, and the power vias are made to penetrate to the ground layer below the power layer where the power pins are located through blind vias. A capacitor is embedded in the grounding layer, and the first end of the capacitor is connected to the power via. A ground hole is made connecting the ground layer to the bottom layer, and the second end of the capacitor is connected to the ground hole.
2. The signal quality optimization method according to claim 1, characterized in that, The capacitor is the decoupling capacitor for the power supply pin.
3. The signal quality optimization method according to claim 1 or 2, characterized in that, The number of capacitors is multiple, and the capacitors are connected in parallel.
4. The signal quality optimization method according to claim 3, characterized in that, The capacitance values of each capacitor are different, and the capacitance value of each capacitor is determined according to the frequency of the power supply noise corresponding to the power supply pin.
5. The signal quality optimization method according to claim 1, characterized in that, The distance between the first end of the capacitor and the power via, and the distance between the second end of the capacitor and the ground via, are both less than 0.5 mm.
6. The signal quality optimization method according to claim 1, characterized in that, The width of the trace between the first end of the capacitor and the power via, and the width of the trace between the second end of the capacitor and the ground via, are greater than or equal to 0.2 mm.
7. The signal quality optimization method according to claim 1, characterized in that, The trace between the first end of the capacitor and the power via, and the trace between the second end of the capacitor and the ground via, are straight segments, or a combination of straight segments and 45° angled broken lines or arc segments.
8. A signal quality optimization device, characterized in that, include: The positioning module is used to locate the signal pins on the printed circuit board that require improved signal quality and to identify the power supply pins around the signal pins as target pins. The via module is used to bring out the power via corresponding to the target pin on the surface layer of the printed circuit board, and to allow the power via to penetrate to the ground layer under the power layer where the power pin is located through a blind via. An embedded capacitor module is used to embed a capacitor in the grounding layer, and the first end of the capacitor is connected to the power via. A grounding module is used to create a ground hole from the grounding layer to the bottom layer, and the second end of the capacitor is connected to the ground hole.
9. A signal quality optimization device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the signal quality optimization method as described in any one of claims 1 to 7 when executing the computer program.
10. A non-volatile storage medium, characterized in that, The non-volatile storage medium stores a computer program, which, when executed by a processor, implements the steps of the signal quality optimization method as described in any one of claims 1 to 7.