Neuron circuit, activation and preparation method, neural network and signal processing system

Abstract

The invention provides a neuron circuit. The neuron circuit comprises n input tubes, an integrating capacitor, an inverted output unit and a reset unit, the input tube is selectively gated based on an input voltage and a control voltage; the integrating capacitor accumulates charges and then releases the charges; the inverted output unit generates an output voltage; the reset unit resets the potential of the integrating capacitor. The invention further provides an activation method of the neuron circuit, and the neuron circuit is activated by controlling the integrating capacitor to accumulate charges and then discharge. The invention further provides a preparation method of the field effect transistor. The source electrode structure, the drain electrode structure and the grid electrode structure are formed on the provided substrate. The invention further provides a neural network which comprises an input layer and an output layer, and the output end of a single neuron circuit of the input layer is connected with the input ends of all or part of neuron circuits of the output layer. The signal processing system comprises an electric signal input device, a reading device and a neural network, the electric signal input device provides input data; the readout device reads the output data.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor devices, integrated circuits and neuromorphic computing, and in particular to a neuron circuit, activation and fabrication method, neural network and signal processing system. Background Technology

[0002] With the rapid development of edge computing scenarios such as the Internet of Things, autonomous driving, and mobile robots, there is an urgent need for localized smart hardware capable of real-time and efficient information processing. Traditional von Neumann computing architectures often face memory wall bottlenecks and high power consumption challenges when dealing with such tasks. In contrast, neuromorphic computing, inspired by the human brain, demonstrates extremely high energy efficiency and parallel processing potential by simulating the pulse information processing mechanism of biological neurons and synapses.

[0003] The core of constructing neuromorphic hardware lies in realizing artificial neurons and synapses with functions similar to biological neurons. Current research mostly focuses on the realization of devices based on synaptic plasticity (such as long-term enhancement and pulse time-dependent plasticity). However, relying on only one regulatory mechanism to regulate neuronal circuits has the drawback of limited neuronal modulation parameters.

[0004] On the other hand, in computer vision processing, existing neural networks need to first convert between photoelectric signals and then process the electrical signals based on the neural network, which also has some room for improvement.

[0005] Therefore, how to provide a neuron circuit, activation and preparation method, neural network and signal processing system that can simultaneously realize intrinsic plasticity modulation, photo-sensing and computing integration and pulse integrated firing has become one of the technical problems that urgently need to be solved by those skilled in the art.

[0006] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a neuron circuit, activation and preparation method, neural network and signal processing system to solve the problems of limited neuron modulation parameters, large computational load in visual processing and high power consumption in signal transmission in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a neuron circuit, which includes at least: n input transistors, an integrating capacitor, an inverting output unit, and a reset unit, where n is a natural number greater than or equal to 1; the input terminals of the n input transistors are connected to n input voltages one-to-one, the control terminals are connected to n control voltages one-to-one, and the output terminals of all transistors are connected to the first plate of the integrating capacitor; the second plate of the integrating capacitor is grounded; the input terminal of the inverting output unit is connected to the first plate of the integrating capacitor, and the power supply terminal is connected to an external voltage; the control terminal of the reset unit is controlled by the output terminal of the inverting output unit, the input terminal is connected to a reset voltage, and the output terminal is connected to the first plate of the integrating capacitor.

[0009] Optionally, the inverting output unit includes a first transistor and a second transistor; the input terminal of the first transistor is connected to an external voltage, and the output terminal is connected to the input terminal of the second transistor; the input terminal of the second transistor serves as the output terminal of the inverting output unit, and the output terminal is grounded; the control terminal of the first transistor is connected to the external voltage, and the control terminal of the second transistor is connected to the first plate of the integrating capacitor; or, the control terminal of the first transistor is connected to the first plate of the integrating capacitor, and the control terminal of the second transistor is grounded.

[0010] Optionally, the reset unit includes a trigger and a reset control transistor; the control terminal of the trigger is controlled by the output terminal of the inverting output unit, and the output terminal is connected to the control terminal of the reset control transistor; the input terminal of the reset control transistor is connected to the reset voltage, and the output terminal is connected to the first plate of the integrating capacitor.

[0011] Optionally, the neuron circuit further includes m shaping elements, where m is a natural number greater than or equal to 1; the m shaping elements are connected in series after the output terminal of the inverting output unit.

[0012] Alternatively, the control terminal of the reset unit can be connected to the output terminal of any shaping element.

[0013] To achieve the above and other related objectives, the present invention also provides a method for activating a neuron circuit, based on the aforementioned neuron circuit. The method for activating the neuron circuit includes at least the following steps: S1: Selecting an input transistor based on an input voltage and a control voltage, and accumulating charge in an integrating capacitor; S2: Controlling the control voltage to disconnect the input transistor, and discharging the integrating capacitor; when the integrating capacitor discharges until the output voltage at the output terminal of the inverting output unit flips to a high level, the neuron circuit is activated.

[0014] To achieve the above and other related objectives, the present invention also provides a method for activating a neuron circuit, based on the aforementioned neuron circuit. The method for activating the neuron circuit includes at least the following steps: S1: providing a light source, the light source selectively illuminating an input transistor, the input transistor being turned on based on the input voltage and a control voltage, and the integrating capacitor accumulating charge; S2: controlling the control voltage to disconnect the input transistor, the integrating capacitor discharging; when the integrating capacitor discharges until the output voltage at the output terminal of the inverting output unit flips to a high level, the neuron circuit is activated.

[0015] Optionally, in step S1, when the neuron circuit is used for image processing, the control voltage or the input voltage is adjusted based on the brightness value of stray ambient light.

[0016] To achieve the above and other related objectives, the present invention also provides a method for fabricating a field-effect transistor (FET), at least for fabricating an input transistor in the aforementioned neuron circuit. The method for fabricating the FET includes at least the following steps: S1: providing a substrate and forming a two-dimensional semiconductor material layer on the substrate; S2: patterning the two-dimensional semiconductor material layer and forming a source structure, a drain structure, and a gate structure on the two-dimensional semiconductor material layer to form the FET.

[0017] Optionally, in step S1, the two-dimensional semiconductor material layer is prepared using a transition metal chalcogenide.

[0018] To achieve the above and other related objectives, the present invention also provides a neural network, which includes at least an input layer and an output layer; the input layer includes u neuron circuits, where u is a natural number greater than or equal to 1; the output layer includes v neuron circuits, where v is a natural number greater than or equal to 1; the output terminal of a single neuron circuit in the input layer is connected to the input terminals of all neuron circuits in the output layer or to the input terminals of some neuron circuits in the output layer; wherein, the input terminals of the neuron circuits are uniformly set as the input terminals of an input transistor, and the weight terminals are uniformly set as the control terminals of the input transistor; or, the input terminals of the neuron circuits are uniformly set as the control terminals of an input transistor, and the weight terminals are uniformly set as the input terminals of the input transistor; the output terminals of the neuron circuits are uniformly set as the output terminals of an inverting output unit.

[0019] Optionally, when the neuron circuit further includes one or more shaping elements, the output terminal of the neuron circuit is uniformly set as the output terminal of the shaping element.

[0020] Optionally, the neural network further includes one or more intermediate layers, each intermediate layer including one or more of the neuron circuits; the intermediate layers are sequentially disposed between the input layer and the output layer, and the output terminal of a single neuron circuit in the upper layer in any adjacent layer is connected to the input terminals of all neuron circuits in the lower layer or connected to the input terminals of some neuron circuits in the lower layer.

[0021] To achieve the above and other related objectives, the present invention also provides a signal processing system, which includes at least: an electrical signal input device, a readout device, and the neural network; the electrical signal input device is connected to the input terminals of each neuron circuit in the input layer; and the readout device is connected to the output terminals of each neuron circuit in the output layer.

[0022] Optionally, the signal processing system further includes a light source; the light source illuminates the gated input tubes of each neuron circuit in the input layer.

[0023] As described above, the neuron circuit, activation and preparation method, neural network, and signal processing system of the present invention have the following beneficial effects:

[0024] 1. This invention expands the modulation parameters of a neuron circuit by setting the activation weight of the neuron circuit to the input voltage or control voltage.

[0025] 2. This invention uses two-dimensional semiconductor materials to fabricate the input tube, enabling the input tube to have the ability of integrating photo-sensing and computing, which helps reduce the computational overhead of data transfer in the visual learning of neural networks; and because the source and drain current of the input tube are controlled extremely precisely, the output voltage of the neuron circuit can become very sparse, which helps to reduce the power consumption of the device.

[0026] 4. The circuit structure of the present invention is simple and the device fabrication process is compatible with standard processes, which facilitates large-scale integration and construction of wafer-scale neuromorphic systems. Attached Figure Description

[0027] Figure 1 The diagram shown is a schematic diagram of the first structure of the neuron circuit of the present invention.

[0028] Figure 2 The diagram shown is a signal schematic of the neuron circuit of the present invention.

[0029] Figure 3 The diagram shown is a second structural schematic of the neuron circuit of the present invention.

[0030] Figure 4 This is shown as another signal schematic diagram in the neuron circuit of the present invention.

[0031] Figure 5 The diagram shows the discharge variation of the integrating capacitor of the present invention under different input voltages.

[0032] Figure 6 The diagram shows the discharge variation of the integrating capacitor of the present invention under different control voltages.

[0033] Figure 7 The diagram shown is a first flowchart illustrating the activation method of the neuron circuit of the present invention.

[0034] Figure 8 The diagram shown is a second flowchart illustrating the activation method of the neuron circuit of the present invention.

[0035] Figure 9 The diagram shown illustrates the receiving of optical signals by the neuron circuit of this invention.

[0036] Figure 10 This is shown as another signal schematic diagram in the neuron circuit of the present invention.

[0037] Figure 11 The diagram shows the variation of activation time of the neuron circuit of the present invention under different light intensities.

[0038] Figure 12 The diagram shows the discharge variation of the integrating capacitor of the present invention under different light intensities.

[0039] Figure 13 The diagram shows a modulation schematic of the neuron circuit of the present invention based on input voltage and light intensity.

[0040] Figure 14 The diagram shown is a flowchart illustrating the fabrication method of the field-effect transistor of the present invention.

[0041] Figure 15 The diagram shown is a schematic diagram of the first structure of the neural network of the present invention.

[0042] Figure 16 The diagram shown is a second structural schematic of the neural network of the present invention.

[0043] Figure 17 The diagram shown is a schematic diagram of the connection of neuron circuits in adjacent layers of the neural network of the present invention.

[0044] Figure 18 This diagram illustrates another connection of neuron circuits in adjacent layers of the neural network according to the present invention.

[0045] Figure 19 The diagram shown is a third structural representation of the neural network of this invention.

[0046] Figure 20The diagram shows the adjustment of the integration time of the neuron circuit of the present invention in a bright environment.

[0047] Figure 21 The diagram shows the adjustment of the integration time of the neuron circuit of the present invention in a dim environment.

[0048] Figure 22 The diagram shown is a first structural schematic of the signal processing system of the present invention.

[0049] Figure 23 The diagram shown is a second structural schematic of the signal processing system of the present invention.

[0050] Component designation explanation

[0051] 1 neuron circuit

[0052] Input tubes T, T1, and T2

[0053] Input voltages Vw, Vw1, Vw2

[0054] Vs, Vs1, Vs2 control voltage

[0055] C Integrating capacitor

[0056] Vc integrating capacitor voltage

[0057] 1a Inverting Output Unit

[0058] VDD external voltage

[0059] Q1 first transistor

[0060] Q2 second transistor

[0061] Vout inverting output unit output voltage

[0062] 1b Reset Unit

[0063] 11 triggers

[0064] The clock voltage of the Vclk flip-flop

[0065] The output voltage of the VQ flip-flop

[0066] Q3 reset control transistor

[0067] Vreset reset voltage

[0068] 1c pulse shaping unit

[0069] 12 shaping elements

[0070] The output voltage of the inverting output unit after the first shaping of Vout1

[0071] The output voltage of the inverting output unit after the second shaping of Vout2

[0072] 2 Neural Networks Detailed Implementation

[0073] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0074] Please see Figures 1-23 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0075] The complex functions of the biological nervous system rely on the synergy of multiple plasticity mechanisms. Besides synaptic plasticity, intrinsic neuronal plasticity also plays a crucial role. Intrinsic plasticity influences the neuronal circuitry's response to input signals by regulating the neuron's own excitability (e.g., altering resting membrane potential and action potential threshold), and is essential for neural network stability, learning, and memory. By extending the modulation parameters of neuronal circuits to include intrinsic neuronal plasticity, both the signal modulation precision and modulation range of the neuronal circuitry can be improved.

[0076] In addition, by utilizing two-dimensional semiconductor tubes that can both sense light and process electrical signals, neural circuits can achieve integrated light sensing and computing based on two-dimensional semiconductor tubes, reducing the complex computational load of neural networks. Furthermore, based on the advantage of the extremely precise control of source and drain currents of two-dimensional semiconductor tubes, neural circuits can also achieve pulse integration and firing, thus realizing low power consumption of neural circuits.

[0077] Furthermore, in the processing of computer vision, by drawing on the biological visual system, visual information can be pre-encoded (such as brightness adaptation), and then the encoded pulse signals can be used as input signals to the neural network for processing, which can significantly reduce the amount of data and complexity of back-end processing.

[0078] Therefore, this invention provides a neuron circuit, activation and preparation method, neural network, and signal processing system, the specific technical solution of which is as follows:

[0079] Example 1

[0080] like Figure 1 As shown, this embodiment provides a neuron circuit 1, including: n input transistors T, an integrating capacitor C, an inverting output unit 1a and a reset unit 1b, where n is a natural number greater than or equal to 1.

[0081] like Figure 1 As shown, the input terminals of the n input transistors T are connected to the n input voltages Vw one by one, the control terminals are connected to the n control voltages Vs one by one, and the output terminals are all connected to the first plate of the integrating capacitor C.

[0082] Specifically, in this embodiment, by providing n input voltages Vw (Vw1, Vw2, ..., Vwn) and n control voltages Vs (Vs1, Vs2, ..., Vsn), one of the n input transistors T (T1, T2, ..., Tn) is selectively turned on. Since the n input voltages Vw and the n control voltages Vs are independent of each other, this embodiment can achieve parallel reception and processing of n signals, improving the processing efficiency of the neuron circuit 1. Further, as... Figure 1 As shown, the input transistor T is a field-effect transistor made of two-dimensional semiconductor material. The current between the source and drain can be controlled with extreme precision. Furthermore, the input transistor T can be either an NMOS transistor or a PMOS transistor. In practical applications, the specific type of the input transistor T can be set as needed, and is not limited to this embodiment.

[0083] like Figure 1 As shown, the second plate of the integrating capacitor C is grounded.

[0084] Specifically, in this embodiment, a selected input transistor T is used, and the charge of the input voltage Vw is injected into the first plate of the integrating capacitor C, such as... Figure 2 As shown, the voltage Vc of the integrating capacitor C rises to the value of the input voltage Vw, meaning the resting membrane potential of neuron circuit 1 is determined by the input voltage Vw. Further, by controlling the control voltage Vs, the selected input transistor T operates in the subthreshold region, and the charge on the integrating capacitor C is slowly discharged through the source and drain of the input transistor T, as... Figure 2 As shown, the voltage Vc of the integrating capacitor C also decreases slowly, a process that simulates the integration process of a biological neuron.

[0085] like Figure 1 As shown, the input terminal of the inverting output unit 1a is connected to the first plate of the integrating capacitor C, and the power supply terminal is connected to the external voltage VDD.

[0086] Specifically, in this embodiment, when the input transistor T is turned on, the receiving voltage of the inverting output unit 1a is high and the output voltage is low. When the input transistor T is in a subthreshold state and the first plate of the integrating capacitor C drops to a certain value, the receiving voltage of the inverting output unit 1a is low and the output voltage is high, simulating the activation process of a biological neuron after slow integration. Furthermore, since the current flowing through the input transistor T can be controlled extremely precisely, the output voltage Vout of the inverting output unit 1a can exhibit a very sparse signal form, which helps to achieve low-power circuit performance. Even further, as... Figure 1 and Figure 3 As shown, the inverting output unit 1a includes a first transistor Q1 and a second transistor Q2. The input terminal of the first transistor Q1 is connected to an external voltage VDD, and its output terminal is connected to the input terminal of the second transistor Q2. The input terminal of the second transistor Q2 serves as the output terminal of the inverting output unit 1a, and its output terminal is grounded. The control terminal of the first transistor Q1 is connected to the external voltage VDD, and the control terminal of the second transistor Q2 is connected to the first plate of the integrating capacitor C; alternatively, the control terminal of the first transistor Q1 is connected to the first plate of the integrating capacitor C, and the control terminal of the second transistor Q2 is grounded. As an example, the first transistor Q1 and the second transistor Q2 can both be NMOS transistors or both be PMOS transistors. In practical applications, the specific types of the first transistor Q1 and the second transistor Q2 are determined according to need, and this embodiment is not the limitation.

[0087] like Figure 1 As shown, the control terminal of the reset unit 1b is controlled by the output terminal of the inverting output unit 1a, the input terminal is connected to the reset voltage Vreset, and the output terminal is connected to the first plate of the integrating capacitor C.

[0088] Specifically, in this embodiment, when the output voltage Vout of the inverting output unit 1a is high, the neuron circuit 1 can output Vout, and simultaneously the reset unit 1b is triggered. After the reset unit 1b is triggered, the potential of the integrating capacitor C enters the resting state of Vreset. Further, as... Figure 1 and Figure 3 As shown, the reset unit 1b includes a flip-flop 11 and a reset control transistor Q3. The control terminal of the flip-flop 11 is controlled by the output terminal of the inverting output unit 1a, and the output terminal is connected to the control terminal of the reset control transistor Q3. The input terminal of the reset control transistor Q3 is connected to the reset voltage Vreset, and the output terminal is connected to the first plate of the integrating capacitor C. As an example, the flip-flop 11 can be a D flip-flop, and the reset control transistor Q3 can be an NMOS transistor or a PMOS transistor (the output voltage Vout of the flip-flop 11 can be inverted according to actual needs). Figure 4As shown, the clock input of the D flip-flop is connected to Vclk, and the output is VQ. When the control input of the D flip-flop receives a high-level signal and is triggered, the D flip-flop turns on the reset control transistor Q3, and the integrating capacitor C quickly charges to the reset voltage Vreset. The neuron circuit 1 enters a resting state and will not respond to new inputs during this process. In practical applications, the specific types of flip-flop 11 and reset control transistor Q3 are required and are not limited to this embodiment.

[0089] Specifically, in this embodiment, such as Figure 3 As shown, the neuron circuit 1 also includes m shaping elements 12, where m is a natural number greater than or equal to 1, meaning the neuron circuit 1 also includes a pulse shaping unit 1c. The m shaping elements 12 are connected in series with the output terminal of the inverting output unit 1a to receive and shape the voltage Vout at the output terminal of the inverting output unit 1a. Furthermore, when the neuron circuit 1 includes shaping elements 12, the control terminal of the reset unit 1b can be connected to the output terminal of any one of the shaping elements 12, allowing for reset based on a voltage with superior performance. As an example, the shaping element 12 can be an inverter or an operational amplifier, such as... Figure 4 As shown, the voltage Vout output by neuron circuit 1 can be shaped twice to obtain Vout1 and Vout2. Obviously, Vout1 has better time-domain and frequency-domain characteristics than Vout, and Vout2 has better time-domain and frequency-domain characteristics than Vout1. In practical applications, the specific type of shaping element 12 can be set as needed, and is not limited to this embodiment.

[0090] It should be noted that in neuron circuit 1, y = f(x) + b, where y represents the output value of neuron circuit 1, x represents the input value of neuron circuit 1, f(·) represents the training weight value of neuron circuit 1, and b represents the external bias value connected to neuron circuit 1. Further, as... Figure 5 and Figure 6 As shown, by providing different input voltages Vw and control voltages Vs, different discharge times of the integrating capacitor C can be obtained, meaning that neuron circuit 1 is activated at different times. Therefore, both the input voltage Vw and the control voltage Vs can affect the output voltage Vout of neuron circuit 1. Furthermore, the input terminal of input transistor T can be selected as the input terminal of neuron circuit 1, and the control terminal of input transistor T can be selected as the weight terminal of neuron circuit 1 to simulate the intrinsic plasticity of biological neurons. Furthermore, the control terminal of input transistor T can be selected as the input terminal of neuron circuit 1, and the input terminal of input transistor T can be selected as the weight terminal of neuron circuit 1 to simulate the synaptic plasticity of biological neurons. In summary, the neuron circuit 1 of this embodiment can possess both intrinsic and synaptic regulatory capabilities, providing a foundation for constructing more complex and realistic neural networks.

[0091] Example 2

[0092] like Figure 7 As shown, this embodiment provides a method for activating a neuron circuit 1, including the following steps:

[0093] like Figure 7 As shown, in step S1, based on the input voltage Vw and the control voltage Vs, one of the input transistors T is selected, and the integrating capacitor C accumulates charge.

[0094] Specifically, in this embodiment, based on a certain input voltage Vw and a certain control voltage Vs, one of the input transistors T is selectively turned on, and the voltage Vc of the integrating capacitor C quickly reaches the potential of the input voltage Vw, that is, the integrating capacitor C accumulates charge. Furthermore, when the neuron circuit 1 is used for image processing, based on the brightness value of stray ambient light, the control voltage Vs or the input voltage Vw is adjusted to control the discharge rate or initial discharge potential of the integrating capacitor C, resulting in different activation times for the neuron circuit 1. This is beneficial for the neuron circuit 1 to adapt to brightness during visual processing.

[0095] like Figure 7 As shown, in step S2, the control voltage Vs is controlled to disconnect the input transistor T and the integrating capacitor C discharges; when the integrating capacitor C discharges to the point that the output voltage Vout at the output terminal of the inverting output unit 1a is high, the neuron circuit 1 is activated.

[0096] Specifically, in this embodiment, by controlling the control voltage Vs, the input transistor T is disconnected (including the case where the input transistor T is completely disconnected and enters the subthreshold region), and the integrating capacitor C begins to discharge slowly. When the input terminal of the inverting output unit 1a drops from a high level to a low level, the output terminal of the inverting output unit 1a flips to a high level, at which time the neuron circuit 1 is activated.

[0097] It should be noted that this embodiment can be implemented based on the neuron circuit 1 of Embodiment 1, or it can be implemented based on other neuron circuits 1 that are the same as or similar to the present invention.

[0098] Example 3

[0099] like Figure 8 and Figure 9 As shown, this embodiment provides a method for activating a neuron circuit 1, including the following steps:

[0100] like Figure 8 and Figure 9 As shown, in step S1, a light source is provided, and the light source selectively illuminates the input tube T. Based on the input voltage Vw and the control voltage Vs, the input tube T is turned on, and the integrating capacitor C accumulates charge.

[0101] Specifically, in this embodiment, such as Figure 10 As shown, a light source provides a light signal of a certain intensity, selectively illuminating the input transistor T. This alters the carrier concentration within the input transistor T, significantly increasing the current in the subthreshold state of the input transistor T. Based on the input voltage Vw and the control voltage Vs, the illuminated input transistor T conducts, and the voltage Vc of the integrating capacitor C rapidly reaches the potential of the input voltage Vw, meaning that the integrating capacitor C accumulates charge. Furthermore, when the neuron circuit 1 is used for image processing, based on the brightness value of stray ambient light, the control voltage Vs or the input voltage Vw is adjusted to control the discharge rate or initial discharge potential of the integrating capacitor C, resulting in different activation times for the neuron circuit 1. This facilitates brightness adaptation of the neuron circuit 1 during visual processing.

[0102] like Figure 8 and Figure 9 As shown, in step S2, the control voltage Vs is controlled to disconnect the input transistor T, and the integrating capacitor C discharges; when the integrating capacitor C discharges to the output terminal of the inverting output unit 1a at a high level, the neuron circuit 1 is activated.

[0103] Specifically, in this embodiment, such as Figure 10 As shown, by controlling the control voltage Vs, the input transistor T is disconnected (including the case where the input transistor T is completely disconnected and enters the subthreshold region), the integrating capacitor C begins to discharge slowly, and when the input voltage of the inverting output unit 1a is low, the output voltage Vout flips to high, that is, the neuron circuit 1 is activated.

[0104] It should be noted that, as Figure 11 and Figure 12 As shown, by providing different light intensities, different discharge times of the integrating capacitor C can be obtained, meaning that neuron circuit 1 is activated at different times. Therefore, the light source intensity can also affect the output voltage Vout of neuron circuit 1, such as... Figure 13 As shown, by combining the light source intensity, the neuron circuit 1 can be modulated over a wider range, demonstrating the advantage of this embodiment in terms of encoding dynamic range.

[0105] It should be further noted that this embodiment can be implemented based on the neuron circuit 1 of Embodiment 1, or it can be implemented based on other neuron circuits 1 that are the same as or similar to the present invention.

[0106] Example 4

[0107] like Figure 14 As shown, this embodiment provides a method for fabricating a field-effect transistor, including the following steps:

[0108] like Figure 14 As shown, in step S1, a substrate is provided, and a two-dimensional semiconductor material layer is formed on the substrate.

[0109] Specifically, in this embodiment, the substrate can be any one of silicon, silicon oxide, sapphire, polyimide, or quartz. In practical applications, the specific material of the substrate is selected as needed, and is not limited to this embodiment. Furthermore, the two-dimensional semiconductor material layer is prepared using a transition metal chalcogenide, which includes, but is not limited to, molybdenum disulfide, molybdenum diselenide, tungsten disulfide, and tungsten diselenide. In practical applications, the specific material of the two-dimensional semiconductor material layer is selected as needed, and is not limited to this embodiment.

[0110] like Figure 14 As shown, in step S2, the two-dimensional semiconductor material layer is patterned, and a source structure, a drain structure, and a gate structure are formed on the two-dimensional semiconductor material layer to form a field-effect transistor.

[0111] Specifically, in this embodiment, the field-effect transistor (FET) fabricated from two-dimensional semiconductor materials exhibits highly precise control over source and drain currents. Therefore, it can be used to fabricate the input transistor T in Embodiment 1, as well as the reset control transistor Q3, the first transistor Q1, and the second transistor Q2 in Embodiment 1. As an example, after patterning, the two-dimensional semiconductor material layer forms the channel of the FET, and then the source and drain structures are formed. Based on this, a gate dielectric layer is formed, and the gate dielectric layer is patterned to form the gate structure, thus forming the FET.

[0112] It should be noted that the neuron circuit 1 in Embodiment 1 can be combined with the process of this embodiment to form a two-dimensional semiconductor circuit. The specific process flow is set according to the actual situation and will not be described in detail here.

[0113] Example 5

[0114] like Figure 15 As shown, this embodiment provides a neural network 2, including an input layer and an output layer.

[0115] like Figure 15 As shown, the input layer includes u neuron circuits 1, where u is a natural number greater than or equal to 1; the output layer includes v neuron circuits 1, where v is a natural number greater than or equal to 1; the output terminal of a single neuron circuit 1 in the input layer is connected to the input terminals of all neuron circuits 1 in the output layer or to the input terminals of some neuron circuits 1 in the output layer.

[0116] Specifically, in this embodiment, such as Figure 15 and Figure 16 As shown, the output of a single neuron circuit 1 in the input layer can be connected to the input of all neuron circuits 1 in the output layer, or it can be connected to the input of only some neuron circuits 1 in the output layer. Further, as... Figure 17 (Some neuronal connections are marked for illustration) and Figure 18(As shown in the diagram, some neuron connections are marked for illustration.) In neural network 2, the input terminals of each neuron circuit 1 are uniformly set to the input terminals of the input tube T, and the weight terminals are uniformly set to the control terminals of the input tube T; or, the input terminals of each neuron circuit 1 in neural network 2 are uniformly set to the control terminals of the input tube T, and the weight terminals are uniformly set to the input terminals of the input tube T. This is to ensure the training consistency of each neuron circuit 1 in neural network 2. Furthermore, the output of neuron circuit 1 is uniformly set to the output terminal of the inverting output unit 1a; when neuron circuit 1 also includes one or more shaping elements 12, the output terminals of neuron circuit 1 are uniformly set to the output terminals of the shaping elements 12, and can all be set to the output terminals of the o-th shaping element 12, where o is a natural number greater than or equal to 1 and less than or equal to m.

[0117] Specifically, in this embodiment, such as Figure 19 As shown, the neural network 2 also includes one or more intermediate layers, each comprising one or more neuron circuits 1; wherein, the intermediate layers are sequentially arranged between the input layer and the output layer. Further, the output of a single neuron circuit 1 in the upper layer of any adjacent layer can be connected to the input of all neuron circuits 1 in the lower layer, or it can be connected to the input of some neuron circuits 1 in the lower layer.

[0118] Specifically, in this embodiment, when the neural network 2 is used for image processing, based on the brightness value of stray ambient light, the control voltage Vs or input voltage Vw connected to the weight terminal of the neuron circuit 1 in the input layer is adjusted to obtain different discharge times of the integrating capacitor C, which is beneficial for the neural network 2 to adapt to brightness during visual processing. As an example, such as Figure 20 As shown, when neural network 2 is in a strong light environment, the background brightness values ​​at points P1, P2, P3, and P4 are relatively high. If the neuron sensitivity is too high, all pixels will fire prematurely, resulting in overexposure and loss of detail in the image. Adjusting the control voltage Vs connected to the neuron circuit 1 in the input layer to a smaller negative value reduces the neuron sensitivity, thereby enabling the resolution of image details. As another example, such as... Figure 21 As shown, when the neural network 2 is in a low-light environment, the background brightness values ​​at points P1, P2, P3, and P4 are relatively low. If the sensitivity of the neurons is too low, they may not be able to fire within the effective time to form an image. Adjusting the control voltage Vs connected to the neuron circuit 1 in the input layer to a larger negative value improves the sensitivity, enabling the neurons to respond to weak light signals and form a recognizable image. In practical applications, the specific values ​​of the control voltage Vs or input voltage Vw used as weights for each neuron circuit 1 in the input layer can be set according to actual needs, and are not limited to this embodiment.

[0119] Specifically, in this embodiment, an unsupervised learning algorithm derived from the STDP rule (Spike-Timing-Dependent Plasticity) can be used to train the neural network 2, and the neural network 2 in this embodiment exhibits excellent learning ability.

[0120] It should be noted that this embodiment may include the neuron circuit 1 of Embodiment 1, or any neuron circuit 1 that is the same as or similar to the present invention.

[0121] Example 6

[0122] like Figure 22 As shown, this embodiment provides a signal processing system, including: an electrical signal input device, a readout device, and a neural network 2.

[0123] like Figure 22 As shown, the electrical signal input device is connected to the input terminal of each neuron circuit 1 in the input layer; the readout device is connected to the output terminal of each neuron circuit 1 in the output layer.

[0124] Specifically, in this embodiment, the electrical signal input device is connected to the input terminals of each neuron circuit 1 in the input layer, and is used to provide input data to the neural network 2; the readout device is connected to the output terminals of each neuron circuit 1 in the output layer, and is used to receive the output data of the neural network 2. As an example, when used for visual learning, the electrical signal input device can be a photodetector, used to transmit the input data converted into electrical signals to the neural network 2, and the readout device can be a time-to-digital converter, used to directly read the activation time of the neuron circuit 1 as output data, which helps to further simplify the system. In practical applications, the specific types of electrical signal input devices and readout devices can be set as needed, and are not limited to this embodiment.

[0125] Specifically, in this embodiment, such as Figure 23 As shown, the signal processing system also includes a light source that illuminates the gating input transistors T of each neuron circuit 1 in the input layer, providing input data in the form of optical signals to the neural network 2. Furthermore, when used for image processing, the light source directly transmits the signal light to the input layer of the neural network 2, eliminating the need for additional photoelectric conversion and significantly reducing data transfer overhead.

[0126] It should be noted that this embodiment may include the neural network 2 of Embodiment 5, or any neural network 2 that is the same as or similar to the present invention.

[0127] In summary, the neuron circuit of the present invention includes: n input transistors, an integrating capacitor, an inverting output unit, and a reset unit; the n input transistors are connected one-to-one with n input voltages and n control voltages, and one is selected for each; the first plate of the integrating capacitor is connected to the output terminal of the input transistor, and the second plate is grounded; the input terminal of the inverting output unit is connected to the first plate of the integrating capacitor; the control terminal of the reset unit is controlled by the output terminal of the inverting output unit, the input terminal is connected to the reset voltage, and the output terminal is connected to the first plate of the integrating capacitor. The activation method of the neuron circuit of the present invention activates the neuron circuit by controlling the integrating capacitor to accumulate charge and then discharge, causing the output voltage of the inverting output unit to flip to a high level. The fabrication method of the field-effect transistor of the present invention forms a field-effect transistor by forming a source structure, a drain structure, and a gate structure on a substrate. The neural network of the present invention includes: an input layer and an output layer, wherein the output terminal of a single neuron circuit in the input layer is connected to the input terminals of all neuron circuits in the output layer or to the input terminals of some neuron circuits in the output layer. The signal processing system of this invention includes: an electrical signal input device, a readout device, and a neural network; the electrical signal input device is connected to the input terminals of each neuron circuit in the input layer; the readout device is connected to the output terminals of each neuron circuit in the output layer. Therefore, this invention realizes a neuron circuit integrating pulse integrated firing, intrinsic plasticity modulation, and photo-sensing computation, and thereby constructs a highly efficient bio-inspired neural network. Furthermore, this invention has the advantages of high functional integration, strong bio-inspiredness, significant energy efficiency, and good scalability. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0128] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A neuron circuit, characterized in that, The neuron circuit includes at least: n input transistors, an integrating capacitor, an inverting output unit, and a reset unit, where n is a natural number greater than or equal to 1; The input terminals of the n input transistors are connected to the n input voltages one by one, the control terminals are connected to the n control voltages one by one, and the output terminals are all connected to the first plate of the integrating capacitor. The second plate of the integrating capacitor is grounded. The input terminal of the inverting output unit is connected to the first plate of the integrating capacitor, and the power supply terminal is connected to an external voltage. The control terminal of the reset unit is controlled by the output terminal of the inverting output unit, the input terminal is connected to the reset voltage, and the output terminal is connected to the first plate of the integrating capacitor.

2. The neuron circuit according to claim 1, characterized in that: The inverting output unit includes a first transistor and a second transistor; The input terminal of the first transistor is connected to an external voltage, and the output terminal is connected to the input terminal of the second transistor; the input terminal of the second transistor serves as the output terminal of the inverting output unit, and the output terminal is grounded. The control terminal of the first transistor is connected to the external voltage, and the control terminal of the second transistor is connected to the first plate of the integrating capacitor. Alternatively, the control terminal of the first transistor is connected to the first plate of the integrating capacitor, and the control terminal of the second transistor is grounded.

3. The neuron circuit according to claim 1, characterized in that: The reset unit includes a trigger and a reset control transistor; The control terminal of the trigger is controlled by the output terminal of the inverting output unit, and the output terminal is connected to the control terminal of the reset control transistor. The input terminal of the reset control transistor is connected to the reset voltage, and the output terminal is connected to the first plate of the integrating capacitor.

4. The neuron circuit according to any one of claims 1-3, characterized in that: The neuron circuit also includes m shaping elements, where m is a natural number greater than or equal to 1; the m shaping elements are connected in series after the output terminal of the inverting output unit.

5. The neuron circuit according to claim 4, characterized in that: The control terminal of the reset unit is connected to the output terminal of any shaping element.

6. A method for activating a neuron circuit, implemented based on the neuron circuit according to any one of claims 1-5, characterized in that, The activation method of the neuron circuit includes at least the following steps: S1: Based on the input voltage and control voltage, select one of the input transistors and accumulate charge in the integrating capacitor; S2: Control the control voltage to disconnect the input transistor, and the integrating capacitor discharges; when the integrating capacitor discharges until the output voltage at the output terminal of the inverting output unit flips to a high level, the neuron circuit is activated.

7. A method for activating a neuron circuit, implemented based on the neuron circuit according to any one of claims 1-5, characterized in that, The activation method of the neuron circuit includes at least the following steps: S1: Provide a light source, which selectively illuminates an input tube. Based on the input voltage and control voltage, the input tube is turned on, and the integrating capacitor accumulates charge. S2: Control the control voltage to disconnect the input transistor, and the integrating capacitor discharges; when the integrating capacitor discharges until the output voltage at the output terminal of the inverting output unit flips to a high level, the neuron circuit is activated.

8. The method for activating a neuronal circuit according to claim 6 or 7, characterized in that: In step S1, when the neuron circuit is used for image processing, the control voltage or the input voltage is adjusted based on the brightness value of stray ambient light.

9. A method for fabricating a field-effect transistor, at least for fabricating the input transistor in the neuron circuit according to any one of claims 1-5, characterized in that, The method for fabricating the field-effect transistor includes at least the following steps: S1: Provide a substrate on which a two-dimensional semiconductor material layer is formed; S2: The two-dimensional semiconductor material layer is patterned, and a source structure, a drain structure, and a gate structure are formed on the two-dimensional semiconductor material layer to form the field-effect transistor.

10. The method for fabricating a field-effect transistor according to claim 9, characterized in that: In step S1, the two-dimensional semiconductor material layer is prepared using a transition metal chalcogenide.

11. A neural network, characterized in that, The neural network includes at least: an input layer and an output layer; The input layer includes u neuronal circuits as described in any one of claims 1-5, where u is a natural number greater than or equal to 1; The output layer includes v neuron circuits, where v is a natural number greater than or equal to 1; the output terminal of a single neuron circuit in the input layer is connected to the input terminals of all neuron circuits in the output layer or to the input terminals of some neuron circuits in the output layer. Wherein, the input terminal of the neuron circuit is uniformly set as the input terminal of the input tube, and the weight terminal is uniformly set as the control terminal of the input tube; or, the input terminal of the neuron circuit is uniformly set as the control terminal of the input tube, and the weight terminal is uniformly set as the input terminal of the input tube; the output terminal of the neuron circuit is uniformly set as the output terminal of the inverting output unit.

12. The neural network according to claim 11, characterized in that: When the neuron circuit further includes one or more shaping elements, the output terminal of the neuron circuit is uniformly set as the output terminal of the shaping element.

13. The neural network according to claim 11 or 12, characterized in that: The neural network further includes one or more intermediate layers, each of which includes one or more of the neuron circuits. The intermediate layer is sequentially disposed between the input layer and the output layer, and the output terminal of a single neuron circuit in the upper layer in any adjacent layer is connected to the input terminal of all neuron circuits in the lower layer or to the input terminal of some neuron circuits in the lower layer.

14. A signal processing system, characterized in that, The signal processing system includes at least: an electrical signal input device, a readout device, and a neural network as described in any one of claims 11-13; The electrical signal input device is connected to the input terminal of each neuron circuit in the input layer; the readout device is connected to the output terminal of each neuron circuit in the output layer.

15. The signal processing system according to claim 14, characterized in that: The signal processing system also includes a light source; the light source illuminates the gated input tubes of each neuron circuit in the input layer.

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