Data storage device with auxiliary pulse trains in servo sectors

Abstract

The invention relates to a data storage device with auxiliary pulse trains in servo sectors. Various illustrative aspects relate to a data storage device, a method, and one or more processing devices configured to open a servo gate in a selected head during a read operation, the first servo pulse train, the synchronization mark and the second servo pulse train in one of the servo sectors are read; and determining a position error signal of the selected head based on reading the first servo pulse train and the second servo pulse train.

Description

Background Technology

[0001] Data storage devices such as disk drives include a disk and a read / write head attached to the distal end of an actuator arm that rotates about a pivot via a voice coil motor (VCM) to radially position the head above the disk. The disk includes multiple radially spaced concentric tracks for recording user data sectors and servo wedges or servo sectors. The servo sectors include head positioning information (e.g., track addresses) that is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.

[0002] Figure 1 The existing disk format 2 is shown as including servo wedge regions 60-6 consisting of circumferential records surrounding each servo track. N A plurality of radially spaced concentric servo tracks 4 are defined. A plurality of concentric data tracks are defined relative to the servo tracks 4, wherein the data tracks may have the same or different radial density (e.g., tracks per inch (TPI)) as the servo tracks 4. Each servo wedge 6 i This includes a preamble 8 for storing periodic patterns (which allows for appropriate gain adjustment and timing synchronization of the read signals) and a synchronization flag 10 for storing a special pattern for symbol synchronization to the servo data field 12. The servo data field 12 stores coarse head positioning information, such as the servo track address, for positioning the head over the target data track during seek operations. Each servo wedge (e.g., servo wedge 64) also includes multiple sets of phase-based servo pulse trains 14 (e.g., N-servo pulse trains and Q-servo pulse trains), which are recorded with a predetermined phase relative to each other and relative to the servo track centerline.

[0003] Coarse head position information is processed to position the head above the target data track during seek operations, and servo pulse train 14 provides fine head position information for centerline tracking when accessing the data track during write / read operations. A position error signal (PES) is generated by reading servo pulse train 14, where PES represents the measured position of the head relative to the centerline of the target servo track. The servo controller processes the PES to generate control signals applied to one or more head actuators to radially actuate the head above the disk along the direction that decreases the PES. In some examples, the one or more head actuators may include a voice coil motor and one or more fine-controlled actuators (such as milli-actuators or micro-actuators). Summary of the Invention

[0004] The various examples disclosed herein provide data storage devices (such as hard disk drives) with control circuitry configured to perform novel and inventive position error signal determination using values ​​obtained by reading corresponding first and second servo pulses in a servo sector lacking a preamble. In various examples, the servo sector includes a first servo pulse in the longitudinal direction of the track containing the servo sector, followed by a synchronization marker, and then a second servo pulse. In some embodiments, since the servo sector does not include a preamble, the first servo pulse may be written at the start area of ​​the servo sector, where the preamble is typically written. In embodiments, the first servo pulse written in that area of ​​the servo sector provides an additional servo pulse for the servo sector compared to a servo sector that includes a preamble at that area. In embodiments, this additional servo pulse increases the amount of servo pulse information that can be used to determine the PES, which advantageously reduces the repeatable yaw (RRO) component of the PES associated with the read operation.

[0005] Various exemplary aspects relate to a data storage device comprising: one or more disks, each disk including a plurality of servo sectors defining a plurality of data tracks, wherein each servo sector includes a first servo pulse train, followed by a synchronization marker, followed by a second servo pulse train; an actuator mechanism configured to position a selected head of one or more read / write heads adjacent to a corresponding disk surface of a corresponding disk of the one or more disks; and one or more processing devices. The one or more processing devices are individually or in combination configured to: during a read operation, open a servo gate in the selected head to read the first servo pulse train, the synchronization marker, and the second servo pulse train from one of the servo sectors; and determine a position error signal of the selected head based on the reading of the first servo pulse train and the second servo pulse train.

[0006] Various exemplary aspects relate to a method comprising: during a read operation, opening a servo gate in a selected head to read a first servo pulse train, followed by a second servo pulse train, in a servo sector lacking a preamble; determining a position error signal of the selected head based on reading the first and second servo pulse trains; and using the position error signal to control the position of the selected head, wherein opening the servo gate, determining the position error signal, and controlling the position of the selected head are performed individually or in combination by one or more processing devices.

[0007] Various exemplary aspects relate to one or more processing devices, which include: means for opening a servo gate in a selected head during a read operation to read repeatable yaw (RRO) correction data, followed by a synchronization marker, and then a servo pulse train in a servo sector; means for generating a control signal for the selected head based on reading the RRO correction data and the servo pulse train; and means for using the control signal to control the position of the selected head.

[0008] Various other aspects are depicted in the accompanying drawings and described below, and will become even more apparent from them. Attached Figure Description

[0009] Various features and advantages of the technology disclosed herein will become apparent from the following description of specific examples of those technologies and from those illustrated in the accompanying drawings. The drawings are not necessarily to scale; rather, the emphasis is on illustrating the principles of the technical concepts. In the drawings, the same reference numerals may refer to the same parts in different views. The drawings depict only illustrative examples of the present disclosure and are not intended to limit its scope.

[0010] Figure 1 The existing disk format is illustrated as comprising a plurality of radially spaced concentric servo tracks defined by servo wedge regions of circumferential recording around each servo track.

[0011] Figure 2A and Figure 2B Conceptual block diagrams illustrating top and side views of a data storage device in the form of a disk drive according to various aspects of this disclosure are shown.

[0012] Figure 2C A flowchart depicts an example method in which the control circuitry of a disk drive according to various aspects of this disclosure can be executed or implemented in controlling the operation of the disk drive.

[0013] Figures 3A to 3E Exemplary servo sectors according to various aspects of this disclosure are depicted.

[0014] Figures 4A to 4E The present disclosure describes the control of servo gates relative to servo sectors.

[0015] Figures 5A to 5B Exemplary specific implementations of a first servo burst and a second servo burst in a servo sector according to various aspects of this disclosure are shown.

[0016] Figure 6 A flowchart depicts an example method in which the control circuitry of a disk drive according to various aspects of this disclosure can be executed or implemented in controlling the operation of the disk drive.

[0017] Figure 7A flowchart depicts an example method in which the control circuitry of a disk drive according to various aspects of this disclosure can be executed or implemented in controlling the operation of the disk drive. Detailed Implementation

[0018] Figure 2A and Figure 2B Conceptual block diagrams illustrating top and side views of a data storage device in the form of a disk drive 15 according to various aspects of the present disclosure are shown. The disk drive 15 includes control circuitry 22, actuator arm assembly 19, and a plurality of hard disks 16A, 16B, 16C, 16D (“Hard Disk 16”). Figure 2C A flowchart depicts an example method 80 in which a servo controller 24 of a control circuit 22 according to various aspects of the present disclosure may be executed or implemented in the operation of a control disk drive 15, including determining a position error signal of a read / write head according to various aspects of the present disclosure.

[0019] Actuator arm assembly 19 includes a main actuator 20 (e.g., a voice coil motor (“VCM”)) and multiple actuator arms 40 (e.g., the topmost actuator arm 40A, such as...). Figure 2A and Figure 2B (As shown in the perspective view). Each actuator arm in the actuator arm 40 includes a suspension assembly 42 at its distal end (e.g., in...). Figure 2A and Figure 2B In the view, the topmost actuator arm 40A includes an example of the topmost suspension assembly 42A. In some examples, each suspension assembly 42 may include one or more additional fine actuators.

[0020] Each actuator arm in the actuator arms 40 is configured to suspend the read / write head 18 adjacently above the corresponding disk surface 17 (e.g., the topmost actuator arm 40A suspends the read / write head 18A above the topmost corresponding disk surface 17A, and the bottommost actuator arm 40H suspends the read / write head 18H above the bottommost corresponding disk surface 17H). For example, except... Figure 2A and Figure 2B In addition to one actuator arm assembly 19 and one actuator in the form of a VCM in the example, other examples may include a variety of other numbers of hard disks and disk surfaces, as well as any of the other numbers of actuator arm assemblies, main actuators, and fine actuators.

[0021] In various examples, the disk drive 15 can be considered to perform or implement such functions, tasks, processes, methods, and / or techniques (including aspects of example method 80) with respect to the control circuitry 22 performing or implementing such functions, tasks, processes, methods, and / or techniques. In various examples, the control circuitry 22 may include and / or take the form of one or more drive devices and / or one or more other processing devices of any type, and may implement or perform functions, tasks, processes, methods, or techniques on a hardware structure configured to execute software code or firmware code by executing computer-readable instructions of such software code or firmware code. In various examples, the control circuitry 22 may also implement or perform such functions, tasks, processes, methods, or techniques through its hardware circuitry that implements or performs functions, tasks, processes, methods, or techniques through the hardware structure itself without any operation of software. In various examples, the control circuitry 22 may be operatively communicable and / or controllably connected or coupled to a host 44, which may include any external processing, computing, and / or data management entity, such as computing devices, storage area networks, data centers, any kind of cloud computing resources, and / or any other kind of host.

[0022] Control circuitry 22 may include one or more processing devices and one or more modules constituting a device driver specifically configured to drive and operate certain devices. Such device drivers may include one or more head drivers configured to drive and operate head 18. In various examples, the device driver may be configured as one or more integrated components of one or more larger-scale circuits, such as one or more power large-scale integrated circuit (PLSI) chips or circuits, and / or configured as part of control circuitry 22. In various examples, the device driver may also be configured as one or more components in other large-scale integrated circuits, such as system-on-a-chip (SoC) circuits, or as more or fewer separate circuits operatively coupled to other components of control circuitry 22.

[0023] The master actuator 20 can perform master macro actuation of a plurality of actuator arms 40, each of which can suspend one of the heads 18 above and close to the corresponding disk surface 17 of the disk 16. Figure 2A The location of the read / write heads 18 (e.g., heads 18A and 18H) is indicated, but heads 18 are typically positioned very close to the disk surface, and if... Figure 2A and Figure 2B If depicted to scale, it would be too small to be seen.

[0024] Figure 2A and Figure 2BThe example disk drive 15 includes four hard disks 16. Other examples may include any number of disks, such as only one disk, two disks, three disks, or five or more disks, or ten or eleven or more disks. Hard disks 16 may also be referred to as platters, and their disk surfaces may also be referred to as media or media surfaces. In this exemplary example, the four hard disks 16 include eight disk surfaces 17A, 17B, 17C, 17D, 17E, 17F, 17G, and 17H (“disk surfaces 17”), with one disk surface 17 on each side of each hard disk 16. The actuator assembly 19 suspends and approaches the read / write head 18 of each actuator arm 40 over and from the corresponding disk surface 17, thereby enabling each head of the head 18 to write control features and data to and read control features and data from its corresponding approaching disk surface 17. In this sense, each head 18 of each actuator arm 40 interacts with the corresponding disk surface 17. As used in this article, with respect to its defined local reference frame, head 18 can be said to operate "above" the corresponding disk surface 17.

[0025] The term "disk surface" is understood to have a general meaning to those skilled in the art. It can be understood to include both the very outer surface layer of the disk and the volume of the disk material beneath that outer surface layer, which can be considered in terms of atomic depth or (in a simplified model) the number of atoms deep within the atomic surface layer where the material is susceptible to physical interaction with the read / write head. The term "disk surface" can include portions of the disk material susceptible to interaction with the read / write head during disk drive operations (such as control write operations, control read operations, data write operations, and data read operations).

[0026] exist Figure 2A and Figure 2B In the implementation scheme, each disk surface (e.g., as Figure 2A The disk surface 17A shown includes multiple control features. These control features include servo wedge regions 321-32 that define multiple servo tracks 34. N The data tracks are defined relative to the servo tracks 34 and may be at the same or different radial densities. Control circuitry 22 includes a servo controller 24 that processes head signals 36 (e.g., one or more read signals) from a corresponding head (e.g., head 18A) for reading from the disk surface 17A, thereby demodulating the servo wedges 321-32. NIt generates a position error signal (PES) representing the error between the actual position of the read / write head and the target position relative to the target track. In various examples, the servo controller 24 in control circuit 22 uses a suitable compensation filter to filter the PES from the servo wedge region to generate a control signal 38 applied to actuator arm assembly 19, including a control signal 38 applied to master actuator 20, which acts as a control actuator and rotates actuator arm assembly 19 about an axial pivot to perform master actuation of the corresponding read / write head 18 radially above disk surface 17 in the direction of reducing PES, and to control any fine actuators. In various examples, control circuit 22 may also apply control signals to any component of read / write head 18 and / or disk drive 15 and receive sensor signals from any component of read / write head and / or disk drive.

[0027] exist Figure 2A and Figure 2B In one example, actuator arm assembly 19 rotates actuator arm 40 about a common pivot. In another example, a first actuator arm assembly and / or VCM and a second actuator arm assembly and / or VCM, or other types of master actuators, may each be configured to actuate a corresponding actuator arm assembly or multiple sets of multi-actuator arms about a separate pivot (e.g., mounted at different circumferential positions around the disk). In some examples, each of the two actuator arm assemblies controls half of the read / write head and writes to and reads from half of the disk surface. In some examples, each actuator arm assembly may be addressable by host 44 as a separate logical data storage unit. Other examples may employ more than two actuator arm assemblies or master actuators or multi-actuators that may be actuated about a common pivot, or they may be included in multiple multi-actuators mounted at different circumferential positions around the disk. In various examples, actuator arm assembly 19 and / or any other example in these other examples may thus constitute and / or include actuator mechanisms. Actuator mechanisms such as actuator arm assembly 19 may thus be configured to position read / write heads 18 (including selected heads among one or more read / write heads 18) adjacent to corresponding disk surfaces 17 in one or more disks 16.

[0028] In execution Figure 2CIn example method 80 (the aspects of which will also be further explained below with reference to additional figures), control circuitry 22 may issue one or more commands to other components of disk drive 15, receive information from one or more other components of disk drive 15, and / or perform one or more internal operations, such as generating one or more drive currents for output to system components of disk drive 15. In a particular example, servo controller 24 of control circuitry 22 may open a servo gate in a selected head during a read operation to read a first servo pulse train, followed by a synchronization marker, followed by a second servo pulse train (82) in a servo sector. Servo controller 24 may also determine a position error signal (84) of the selected head based on the reading of the first and second servo pulse trains. Servo controller 24 may also use the position error signal to control the position of the selected head (86). According to the various aspects further described herein, control circuitry 22, including servo controller 24, may also perform additional actions, methods, and techniques.

[0029] As used herein, the term "servo controller 24" may refer to any hardware, firmware, software, and / or combination thereof included in the control circuitry 22 of the disk drive 15, which implements, embodies, or participates in any structure or function of the structure or function attributable to servo controller 24 or any other novel and inventive aspect of this disclosure. Servo controller 24 may constitute any hardware, firmware, software, and / or any other element of control circuitry 22 for determining the position error signal of the selected head based on reading a first servo pulse train and a second servo pulse train, and performing other techniques and methods described herein.

[0030] Figure 3A An exemplary servo sector 300 according to various aspects of this disclosure is depicted. The servo sector 300 may represent a sector included in... Figure 2A A servo sector is one of a plurality of corresponding servo sectors on a corresponding track on a corresponding disk 16 in disk drive 15. In an embodiment, servo sector 300 includes a first servo burst 305, Gray code 310, synchronization marker 315, and a second servo burst 320 arranged sequentially (i.e., one after another) in the longitudinal direction of the track containing servo sector 300. Gray code 310 may include the track address (also referred to as track ID or TID) and the address of servo sector 300 in the track. For example, as per [reference to...] Figure 1As described, the synchronization marker 315 may include a pattern for symbol synchronization to the servo data field, such as a servo address marker (SAM) or a servo index marker (SIM). In an embodiment, the first servo pulse train 305 and the second servo pulse train 320 each include a corresponding set of phase-based servo pulse trains (e.g., a periodic sequence of magnetic transitions) that are recorded at a predetermined phase relative to each other and relative to the centerline of the track containing the servo sector 300.

[0031] Continue to refer to Figure 3A Based on all aspects of this disclosure, and Figure 1 Compared to the servo sector format shown, servo sector 300 is written to the disk without a preamble. In this way, servo sector 300 lacks (i.e., does not include) a preamble. In an implementation, writing servo sectors without a preamble improves disk formatting efficiency by reserving more space for user data. In one implementation, writing servo sectors without a preamble means that gain control and timing synchronization can be implemented without the benefit of reading a preamble at the beginning of each servo sector. Because servo sector 300 does not include a preamble, the first servo pulse train 305 can be written at the beginning area of ​​the servo sector, where the preamble would typically be written.

[0032] According to various aspects of this disclosure, during a read operation, the servo controller 24 determines the PES of the read head based on corresponding readings from each of the first servo pulse train 305 and the second servo pulse train 320. In an embodiment, with Figure 1 Compared to the servo sector format shown, the first servo pulse train 305 provides an additional servo pulse train for the servo sector 300. In the implementation scheme, compared with Figure 1 Compared to the servo sector format shown, these additional servo bursts increase the amount of servo burst information that can be used to determine the PES. In the implementation, compared to using Figure 1 Compared to when the servo sector format shown is used to determine the PES, this increase in servo burst information reduces the repeatable yaw (RRO) component of the PES associated with read operations. Reducing the RRO component of the PES in this way advantageously reduces the amount of RRO correction data used with the disk, which advantageously reduces the amount of time spent determining the RRO correction data and the amount of memory used to store it.

[0033] Figure 3BAn embodiment of a servo sector 300' including RRO data 325 and preamble 330 is shown. In various embodiments, RRO data 325 includes RRO correction data for correcting the RRO component of the PES associated with read operations. Such data may be determined during the manufacture and testing of the disk drive and servo-written onto the disk in servo sector 300'. In embodiments, the RRO correction data may advantageously be stored in servo sector 300' rather than in a separate memory (such as NAND flash or dynamic random access memory (DRAM)) due to the reduced amount of RRO correction data resulting from the use of additional servo bursts. According to aspects of this disclosure, the RRO data 325 in servo sector 300' precedes Gray code 310 and synchronization mark 315. In one example, the RRO data 325 precedes the first servo burst 305 to accommodate write transients associated with the RRO data 325. In one example, RRO data 325, first servo pulse train 305, preamble 310, synchronization marker 315, Gray code 310 and second servo pulse train 320 are arranged sequentially (i.e., one after another) in the longitudinal direction of the track containing servo sector 300'.

[0034] Assuming the write head is located a few micrometers behind the read head in the downtrack direction, and the read head is configured to see at least a second servo burst 320 before stopping writing user data in write mode, keeping the Gray code 310 and synchronization marker 315 as short as possible (as described in U.S. Patent 11,417,362 entitled "DATA STORAGE DEVICE ELIMINATING PREAMBLE FROMSERVO SECTORS"), more space is left in the servo sector between the user data and the rest of the servo mode for fields such as the first servo burst 305 and RRO data 325. Therefore, while the lack of a preamble is not ideal for some implementations (e.g., Figure 3B and Figure 3E The prerequisite for ), but some other implementation schemes (e.g., Figure 3A and Figure 3D This does indeed eliminate the preamble to free up more space in the servo sector for fields such as the first servo burst 305 and / or RRO data 325, thus enabling these implementations to more effectively reduce RRO in user data read mode servo operations. Some implementations may utilize a partitioned servo mode layout, in which each partition has a shorter outer diameter side for the first servo burst 305 and / or RRO data 325. Therefore, some implementations utilize more servo partitions and consecutive partitioned servos to leave more space for the first servo burst 305 and / or RRO data 325.

[0035] Figure 3C An embodiment of a servo sector 300” is shown, comprising a first servo pulse train 305 arranged sequentially (i.e., one after another) in the longitudinal direction of the track containing the servo sector 300”, followed by a second servo pulse train 320. In this embodiment, the servo sector 300” does not include Gray code, preamble, RRO data, or synchronization markers. In various examples, in the servo wedges of the disk, the control circuitry 22 uses only the second servo pulse train 320 for all write operations, resulting in a longer space in these servo wedges for the first servo pulse train 305. Therefore, in these servo wedges, the read pattern PES determined using the relatively long first servo pulse train 305 is more effective in reducing RRO during read operations, thereby eliminating the need to perform RRO calibration on the read pattern during manufacturing, as well as the need to store the servo sector written to the disk itself or the corresponding RRO data stored in memory, and subsequent operations that read and use such data during servo operations.

[0036] Figure 3D An embodiment of servo sector 300”' is shown, which includes RRO data 325 preceding a first servo pulse train 305, followed by a synchronization marker 315, and then a second servo pulse train 320 in the longitudinal direction of the track containing servo sector 300”'. In this embodiment, servo sector 300”' does not include Gray code or preamble.

[0037] Figure 3E An embodiment of a servo sector 300”” is shown, which includes RRO data 325, a preamble 330, a synchronization marker 315, a Gray code 310, and a second servo burst 320 arranged sequentially (i.e., one after another) in the longitudinal direction of the track containing the servo sector 300””. In this embodiment, for example when the length is insufficient for a set of valid (i.e., sufficiently long) first servo bursts 305, space in the servo sector 300”” prior to the preamble is allocated to write the RRO data 325.

[0038] Figure 4A Exemplary states of a servo gate relative to servo sector 300 according to various aspects of this disclosure are shown. In various embodiments, Figure 2A The servo controller 24 generates a servo timing window that includes a servo gate window, which enables the use of read / write heads passing over the servo sector 300 (e.g., ...). Figure 2AThe servo controller 24 uses a read element in the read head 18A to read servo information in the servo sector 300. In one embodiment, the servo controller 24 demodulates the servo information read using the read element, processes the demodulated servo information to determine the PES, and generates a control signal based on the PES. In one embodiment, the control signal is configured to be applied to the VCM (e.g., VCM). Figure 2A The VCM (Vibration Control Center) is used to control the position of the read / write head, for example, relative to a target position (such as the centerline of the track over which the head is traveling). Figure 4A As shown, arrow "D" indicates the direction of travel of the read / write head over the surface of the disk containing servo sector 300 (i.e., in the longitudinal direction of the track containing servo sector 300), such that the head travels over data sector N-1, then over servo sector 300, and then over data sector N. Figure 4A In the example shown, data sector N follows servo sector 300 and is the data sector associated with servo sector 300.

[0039] In one implementation, when a read operation is performed on a data sector associated with servo sector 300, servo controller 24 opens a servo gate to allow the read element to read the first servo burst 305, Gray code 310, synchronization marker 315, and second servo burst 320 of servo sector 300. However, during a write operation, the servo gate may be opened in a manner that reduces the write gap that would otherwise precede each servo sector. In one example, during a write operation, the servo gate is opened to allow the read element to read the synchronization marker 315 and the second servo burst 320 without reading the first servo burst 305 and Gray code 310. In another example, during a write operation, the servo gate is opened to allow the read element to read some of the Gray code 310 (e.g., the least significant bit of a track ID), the synchronization marker 315, and the second servo burst 320 without reading the first servo burst 305.

[0040] Figure 4B , Figure 4C , Figure 4D and Figure 4E Exemplary states of servo gates relative to servo sectors 300', 300”, 300”' and 300”” are shown respectively according to various aspects of this disclosure. Figure 4B , Figure 4C , Figure 4D and Figure 4E This illustrates how, in the implementation scheme, the servo controller 24 can be configured to behave differently during a read operation compared to during a write operation (e.g., in a similar manner). Figure 4A (in a different way) or in a different way Figure 4AThe various write gate operation modes control the servo gates relative to servo sectors 300', 300", 300"', and 300"". In all configurations, different wedges (such as odd wedges and even wedges) can have different write gate configurations.

[0041] Figure 5A Exemplary specific embodiments of a first servo burst 305 and a second servo burst 320 of a servo sector 300 according to various aspects of this disclosure are shown. In various embodiments, the first servo burst 305 includes a first burst 501 and a second burst 502, and the second servo burst 320 includes a third burst 503 and a fourth burst 504. In embodiments, the first burst 501 and the third burst 503 are of a first burst type, and the second burst 502 and the fourth burst 504 are of a second burst type different from the first burst type. In one example, the first burst 501 and the second burst 502 correspond to a first A burst and a first B burst, respectively, of a first zero-burst servo mode, and the third burst 503 and the fourth burst 504 correspond to a second A burst and a second B burst, respectively, of a second zero-burst servo mode. In this example, the A burst (which may also be referred to as an N burst) has a first mode polarity, and the B burst (which may also be referred to as a Q burst) has a second mode polarity different from the first mode polarity. In various implementations, a first mode polarity and a second mode polarity are selected such that when the first pulse train A and the second pulse train B are read back, their amplitudes have half the track offset relative to the track offset.

[0042] Figure 5B Another exemplary embodiment of a first servo burst 305 and a second servo burst 320 of a servo sector 300 according to various aspects of this disclosure is shown. In various embodiments, the first servo burst 305 includes a first split burst servo mode, and the second servo burst 320 includes a second split burst servo mode. Split burst servo modes are described in U.S. Patent No. 11,830,524 entitled “DATA STORAGE DEVICE WITH SPLIT BURST SERVO PATTERN” and U.S. Patent No. 12,100,431 entitled “DATA STORAGE DEVICE WITH SYMMETRIC SPLIT BURST SERVO PATTERN”, the entire disclosure of which is incorporated herein by reference. In various embodiments, and as Figure 5BAs shown, the first pulse train 501 and the third pulse train 503 (or the second pulse train 502 and the fourth pulse train 504) can be separated into two or more pulse trains (e.g., 501A, 501B, 503A, 503B), and the corresponding PES can be determined using the corresponding separated pulse train servo mode in the manner described in the above patent.

[0043] Figure 5A and 5B It shows in Figure 3A Examples of the first servo pulse train 305 and the second servo pulse train 320 in the background of servo sector 300. However, Figure 5A and Figure 5B The teachings are not limited to servo sector 300, but can be applied to disclosed servo sectors (such as first servo burst 305 and second servo burst 320). Figure 3B Servo sector 300' Figure 3C Servo sector 300” and Figure 3D Use any servo sector (300”') together. Figure 5A and Figure 5B Furthermore, according to various aspects of this disclosure, the servo controller 24 determines the PES of the read / write head using values ​​obtained by reading each of the first servo pulse train 305 and the second servo pulse train 320. In one example, the servo controller 24 uses the first servo pulse train 305 to determine the first PES, uses the second servo pulse train 320 to determine the second PES, and determines the PES of the read / write head based on a function of the first and second PES. For example, the servo controller 24 may also determine the first PES based on values ​​obtained by reading the first pulse train 501 and the second pulse train 502, and determine the second PES based on values ​​obtained by reading the third pulse train 503 and the fourth pulse train 504. In embodiments, the function may be an average value such that the PES of the read / write head is the average of the first and second PES. In one example, the function is a weighted average based on a first number of pulse train cycles associated with reading the first servo pulse train 305 and a second number of pulse train cycles associated with reading the second servo pulse train 320.

[0044] In another example, the servo controller 24 determines the PES of the read / write head by determining a first sum of the values ​​obtained from reading the first pulse train 501 and the third pulse train 503, a second sum of the values ​​obtained from reading the second pulse train 502 and the fourth pulse train 504, and using the first and second sums to determine the PES. In this example, the servo controller 24 can be configured to adjust the values ​​obtained from reading the first pulse train 501 and the third pulse train 503, and the values ​​obtained from reading the second pulse train 502 and the fourth pulse train 504, to a synchronization amplitude before summing the corresponding values.

[0045] In another example, the servo controller 24 determines the PES of the read / write head by performing a first asynchronous PES calculation using a first pulse train 501 and a second pulse train 502, performing a second asynchronous PES calculation using a third pulse train 503 and a fourth pulse train 504, and determining the PES based on the first and second asynchronous PES calculations. In this example, the corresponding asynchronous PES calculation can be performed in the manner described in U.S. Patent No. 12,046,256 entitled “DATA STORAGE DEVICE READ / WRITE CHANNEL WITH DIRECT RADIAL POSITION DEMODULATION IN ASYNCHRONOUS POSITION ERROR SIGNAL DEMODULATION,” the entire disclosure of which is incorporated herein by reference. In this example, the PES can be the average of the first and second asynchronous PES calculations. In some embodiments (such as using…), Figure 3E In those implementations of servo sector 300", synchronous PES calculation is used to determine the PES from the second servo pulse train 320 without the first servo pulse train 305. In implementations that include RRO data 325 (such as...) Figure 3B , Figure 3D and Figure 3E In the RRO data 325, the control signal is determined based on the PES and RRO correction data included in the RRO data 325.

[0046] Figure 6 A flowchart depicts an example method 680 in which a servo controller 24 of a control circuit 22 according to various aspects of the present disclosure may be executed or implemented during operation of a control disk drive 15. In an embodiment, method 680 includes: during a read operation, opening a servo gate in a selected head to read a first servo pulse train, followed by a second servo pulse train, in a servo sector lacking a preamble (682); determining a position error signal of the selected head based on reading the first and second servo pulse trains (684); and using the position error signal to control the position of the selected head (686).

[0047] Figure 7A flowchart depicts an example method 780 in which a servo controller 24 of control circuitry 22 according to various aspects of this disclosure may be executed or implemented during operation of a control disk drive 15. In an embodiment, method 780 includes: during a read operation, opening a servo gate in a selected head to read repeatable yaw (RRO) correction data in a servo sector, followed by a synchronization marker, and then a servo burst (782); generating a control signal for the selected head based on the read RRO correction data and the servo burst (784); and using the control signal to control the position of the selected head (786). Generating the control signal may include: determining the PES using one or more servo burst patterns, and determining the control signal based on the PES and the RRO correction data.

[0048] The flowcharts in the examples above can be implemented using any suitable control circuitry, such as any or any suitable integrated circuit. For example, the control circuitry can be implemented within the read channel integrated circuit, or in a separate component (such as a data storage controller), or some of the operations described above can be performed by the read channel while others can be performed by the data storage controller. In some examples, the read channel and the data storage controller can be implemented as separate integrated circuits, and in some examples, the read channel and the data storage controller can be fabricated as a single integrated circuit or a system-on-a-chip (SoC). In some examples, the control circuitry may include suitable preamplifier circuitry, which is implemented as a separate integrated circuit integrated into the read channel or data storage controller circuitry, or integrated into the SoC.

[0049] In some examples, the control circuitry may include a microprocessor that executes instructions operable to cause the microprocessor to perform one or more aspects of the methods, processes, or techniques shown in the flowchart and described herein with reference to the flowchart. The executable instructions of this disclosure may be stored on any computer-readable medium. In some examples, the executable instructions of this disclosure may be stored on a non-volatile semiconductor memory device, component, or system external to or integrated with the microprocessor in a SoC. In some examples, the executable instructions of this disclosure may be stored on one or more disks and read into volatile semiconductor memory when the disk drive is powered on. In some examples, the control circuitry may include logic circuitry, such as state machine circuitry. In some examples, at least some of the flowchart blocks may be implemented using analog circuitry (e.g., analog comparators, timers, etc.). In some examples, at least some of the flowchart blocks may be implemented using digital circuitry or a combination of analog and digital circuitry.

[0050] In various examples, one or more processing devices may include or constitute the control circuitry as described herein, and / or perform one or more functions of the control circuitry as described herein. In various examples, the control circuitry or other one or more processing devices performing one or more functions of the control circuitry as described herein may be abstracted from physical proximity to the disk and disk surface. In various examples, the control circuitry and / or one or more device drivers thereof, and / or any other type of one or more processing devices performing one or more functions of the control circuitry as described herein, may be part of or near a rack of multiple data storage devices or a single product comprising multiple data storage devices, or may be part of or near one or more physical or virtual servers, or may be part of or near one or more local area networks or storage area networks, or may be part of or near a data center, or may be hosted in one or more cloud services.

[0051] In various examples, a disk drive may include a hard disk drive, an optical disk drive, a hybrid disk drive, or other types of disk drives. Some examples may include electronic devices such as computing devices, data server devices, media content storage devices, or other devices, components, or systems that may include storage media and / or control circuitry as described above.

[0052] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations fall within the scope of this disclosure. In some specific implementations, certain method, event, or process blocks may be omitted. The methods and processes described herein are not limited to any particular order, and the blocks or states associated with them may be executed in other orders. For example, the described tasks or events may be executed in a different order than those specifically disclosed, or multiple tasks or events may be combined in a single block or state. Example tasks or events may be executed serially, in parallel, or in another manner. Tasks or events may be added to or removed from the disclosed examples. The example systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed examples.

[0053] While certain example embodiments are described herein, these embodiments are presented by way of example only and do not limit the scope of the invention disclosed herein. Therefore, nothing in the foregoing description implies that any particular feature, characteristic, step, module, or block is necessary or essential. The novel methods and systems described herein may be embodied in a variety of other forms. Various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit and scope of this disclosure.

[0054] Method 80 and other methods of this disclosure may include additional steps or variations in various other embodiments. Any or all of the methods 80 and other methods of this disclosure may be executed by or embodied in hardware, and / or executed or implemented by a controller, CPU, FPGA, SoC, measurement and control multiprocessor system-on-chip (MPSoC) (which may include both a CPU and an FPGA, and other elements together in an integrated SoC), or other processing or computing device that processes executable instructions to control other associated hardware, devices, systems, or products in implementing, carrying out, or embodying various subjects of the methods. The steps of method 80 and other methods of this disclosure may be performed individually or in combination by one or more processing devices. For example, in some embodiments, one or more processing devices may include a single processing device that performs all the steps of this method. In some embodiments, different corresponding processing devices among one or more processing devices may perform different corresponding steps of this method. For example, in some embodiments, one or more processing devices may include at least a first processing device that performs a first subset of the steps of this method and at least a second processing device that performs a second subset of the steps of this method. In some embodiments, one or more steps of this method may be performed by two or more processing devices among one or more processing devices that operate in combination.

[0055] Therefore, in various basic aspects and in exemplary applications, architectures, techniques, and methods for implementing and embodying the novel advantages of this disclosure, data storage systems, apparatuses, and methods are shown and described herein. Through this disclosure, those skilled in the art will gain a full understanding of the wide range of further applications, architectures, techniques, processes, apparatuses, and systems covered by this disclosure and the claims set forth below, and will be able to put them into practice knowingly.

[0056] As used herein, the expression "at least one of A, B, and C" is intended to mean "A, B, C, or any combination of A, B, and C". The description of the disclosed examples is provided to enable any person skilled in the art to understand how to make or use the subject matter of this disclosure. Various modifications to these embodiments will be apparent to those skilled in the art based on this disclosure, and the general principles defined herein may be applied to other examples without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not limited to the embodiments shown herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

[0057] From the foregoing description, it will be understood that this disclosure and its many incidental advantages are applicable, and that various changes in the form, construction, and arrangement of the components may be made without departing from the disclosed subject matter or without sacrificing all or any of its substantial advantages. The forms described are merely illustrative, and the appended claims cover and include a broad range of embodiments, including a wide range of examples covering any such variations in the form, construction, and arrangement of the components as described herein.

[0058] While this disclosure has been described with reference to various examples, it should be understood that these examples are illustrative and the scope of this disclosure is not limited thereto. All subjects described herein are presented as illustrative, non-limiting examples and not as exclusive specific implementations, whether or not they are explicitly identified as the examples described. Numerous variations, modifications, and additions are possible within the scope of the examples of this disclosure. More generally, examples according to this disclosure have been described in the context of specific implementations. Without departing from the spirit and scope of this disclosure and the appended claims, functions may be separated or combined in blocks in different ways, or described using different terms, in various examples of this disclosure. These and other variations, modifications, additions, and improvements may fall within the scope of this disclosure as defined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: One or more disks, each of the one or more disks including a plurality of servo sectors defining a plurality of data tracks, wherein each of the servo sectors includes a first servo pulse train, followed by a synchronization marker, followed by a second servo pulse train; An actuator mechanism configured to position a selected head of one or more heads adjacent to a corresponding disk surface of a corresponding disk of one or more disks; and One or more processing devices, wherein the one or more processing devices are individually or in combination configured to: During the read operation, the servo gate in the selected head is opened to read the first servo pulse train, the synchronization flag, and the second servo pulse train from one of the servo sectors; and The position error signal of the selected head is determined by reading the first servo pulse train and the second servo pulse train.

2. The data storage device of claim 1, wherein the read operation is configured to read data stored in a data sector immediately following the one servo sector in the servo sector.

3. The data storage device according to claim 1, wherein each servo sector in the servo sector further includes a track ID between the first servo pulse train and the second servo pulse train.

4. The data storage device of claim 1, wherein each servo sector in the servo sector lacks a preamble.

5. The data storage device according to claim 1, wherein each servo sector in the servo sector further includes a preamble located between the first servo pulse train and the second servo pulse train.

6. The data storage device according to claim 1, wherein the position error signal includes the average of a first position error signal determined using the first servo pulse train and a second position error signal determined using the second servo pulse train.

7. The data storage device of claim 6, wherein the average value is a weighted average of a first number of pulse train cycles associated with reading the first servo pulse train and a second number of pulse train cycles associated with reading the second servo pulse train.

8. The data storage device according to claim 1, wherein: The first servo pulse train includes a first pulse train and a second pulse train; The second servo pulse train includes a third pulse train and a fourth pulse train; The first pulse train and the third pulse train are of the first pulse train type; and The second pulse train and the fourth pulse train are of a different type than the first pulse train.

9. The data storage device of claim 8, wherein the position error signal is determined using the sum of values ​​obtained by reading the first pulse train and the third pulse train, and the sum of values ​​obtained by reading the second pulse train and the fourth pulse train.

10. The data storage device of claim 8, wherein determining the position error signal comprises: The first pulse train and the second pulse train are used to perform the calculation of the first asynchronous position error signal; The third pulse train and the fourth pulse train are used to perform the calculation of the second asynchronous position error signal; as well as The position error signal is determined based on the calculation of the first asynchronous position error signal and the calculation of the second asynchronous position error signal.

11. The data storage device of claim 1, wherein each servo sector in the servo sector further includes repeatable yaw (RRO) correction data.

12. The data storage device of claim 11, wherein the synchronization marker is followed by the RRO correction data.

13. The data storage device of claim 1, wherein the one or more processing devices are further configured individually or in combination to use the position error signal to control the position of the selected head.

14. The data storage device according to claim 1, wherein: The first servo pulse train includes a first split pulse train servo mode; and The second servo pulse train includes a second split pulse train servo mode.

15. A method, the method comprising: During the read operation, the servo gate in the selected head is opened to read the first servo pulse train in the servo sector lacking a preamble, followed by the second servo pulse train; The position error signal of the selected magnetic head is determined based on reading the first servo pulse train and the second servo pulse train; and The position error signal is used to control the position of the selected read / write head. The opening of the servo gate, the determination of the position error signal, and the control of the position of the selected magnetic head are performed individually or in combination by one or more processing devices.

16. The method of claim 15, wherein: The first servo pulse train includes a first pulse train and a second pulse train; The second servo pulse train includes a third pulse train and a fourth pulse train; The first pulse train and the third pulse train are of the first pulse train type; and The second pulse train and the fourth pulse train are of a different type than the first pulse train.

17. One or more processing devices, said one or more processing devices comprising: A means for opening the servo gate in a selected head during a read operation to read repeatable yaw (RRO) correction data in a servo sector, followed by a synchronization marker, and then a servo pulse train; A means for generating a control signal for the selected magnetic head based on reading the RRO correction data and the servo pulse train; and A means for using the control signal to control the position of the selected magnetic head.

18. One or more processing devices according to claim 17, wherein: The servo sector includes a first servo pulse train preceding the synchronization marker; The servo pulse train following the synchronization marker includes a second servo pulse train; and The control signal is generated based on reading the RRO correction data, the first servo pulse train, and the second servo pulse train.

19. The processing apparatus of claim 18, further comprising means for determining a position error signal using corresponding values ​​obtained by reading the first servo pulse train and the second servo pulse train.

20. One or more processing devices according to claim 17, wherein the servo sector includes a preamble located between the RRO correction data and the synchronization marker.

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