Low ripple charge pump circuit

Abstract

The invention discloses a low-ripple charge pump circuit, and the circuit comprises a non-overlapping clock circuit which is used for generating a first clock signal and a second clock signal which are not overlapped according to an external clock signal; and the charge pump main body circuit is used for boosting the input voltage according to the first clock signal and the second clock signal to form charge pump output voltage and dynamic substrate bias voltage. According to the OTP memory circuit, the loss of reverse leakage current can be effectively reduced by adopting the non-overlapping clock signals, the reverse leakage current caused by conduction of a path between input and output due to simultaneous conduction of the switching tubes of the charge pump is avoided, and the OTP memory circuit can meet the requirements of high stability and low loss of the OTP memory circuit.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory circuits, and in particular relates to a low-ripple charge pump circuit. Background Technology

[0002] As semiconductor processes advance to more advanced nodes, the operating voltage of integrated circuits continues to decrease. However, modules such as OTP (One-Time Programmable) memory still require relatively high programming voltages to ensure reliable data writing. While traditional charge pump circuits possess boost capabilities, their technical limitations become increasingly apparent in low-voltage environments. These circuits often employ a basic voltage multiplier structure, and their output voltage is easily affected by device parameters and process variations, resulting in low boost efficiency and insufficient output stability. Especially in deep submicron processes, constrained by physical parameters such as device threshold voltage, traditional charge pumps often struggle to generate sufficiently high and stable programming voltages.

[0003] Furthermore, existing charge pump designs typically exhibit significant output voltage ripple, directly impacting the programming accuracy and reliability of OTP memories. During programming, fluctuations in the supply voltage can lead to suboptimal programming states for memory cells, consequently affecting the overall performance consistency of the memory array. Simultaneously, traditional charge pumps have limited output voltage regulation capabilities, making it difficult to flexibly adapt to the specific programming voltage requirements of OTP memories under different process conditions. Therefore, there is an urgent need to develop a novel low-ripple, highly stable charge pump circuit capable of providing a stable and reliable high-voltage output even under extremely low supply voltage conditions, thereby meeting the precise programming requirements of OTP memories at advanced process nodes. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a low ripple charge pump circuit.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A low-ripple charge pump circuit, including A non-overlapping clock circuit is used to generate a non-overlapping first clock signal CLK_1 and a second clock signal CLK_2 based on an external clock signal CLK; and The charge pump main circuit is used to boost the input voltage VIN according to the first clock signal CLK_1 and the second clock signal CLK_2 to form the charge pump output voltage VOUT0 and the dynamic substrate bias voltage VOUT1.

[0006] Furthermore, the non-overlapping clock circuit includes an inverter INV1, a NAND gate NAND1, a NAND gate NAND2, a buffer BUF1, a buffer BUF2, a first phase delay unit, and a second phase delay unit; the first phase delay unit and the second phase delay unit are used to output the input signal after phase delay. The input terminal of the inverter INV1 and the second input terminal of the NAND gate NAND2 are both electrically connected to the input terminal of the non-overlapping clock circuit for receiving the external clock signal CLK; the output terminal of the inverter INV1 and the second input terminal of the NAND gate NAND1 are electrically connected. The first input terminal of the NAND gate NAND1 is electrically connected to the output terminal of the first phase delay unit, and the output terminal of the NAND gate NAND1 is electrically connected to the input terminal of the second phase delay unit and the input terminal of the buffer BUF1, respectively; the output terminal of the buffer BUF1 is electrically connected to the first output terminal of the non-overlapping clock circuit, and is used to output the first clock signal CLK_1. The first input terminal of the NAND gate NAND2 is electrically connected to the output terminal of the second phase delay unit, and the output terminal of the NAND gate NAND2 is electrically connected to the input terminal of the first phase delay unit and the input terminal of the buffer BUF2 respectively; the output terminal of the buffer BUF2 is electrically connected to the second output terminal of the non-overlapping clock circuit, and is used to output the second clock signal CLK_2.

[0007] Furthermore, the first phase delay unit includes inverters INV2, INV3, and INV4, and a NAND gate NAND3; the input terminal of inverter INV2 and the first input terminal of NAND gate NAND3 are electrically connected and serve as the input terminal of the first phase delay unit; the output terminal of inverter INV2 is electrically connected to the input terminal of inverter INV3, and the output terminal of inverter INV2 is electrically connected to the second input terminal of NAND gate NAND3; the output terminal of NAND gate NAND3 is electrically connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 serves as the output terminal of the first phase delay unit.

[0008] Furthermore, the second phase delay unit includes inverters INV5, INV6, and INV7, and a NAND gate NAND4; the input terminal of inverter INV5 and the first input terminal of NAND gate NAND4 are electrically connected and serve as the input terminal of the second phase delay unit; the output terminal of inverter INV5 is electrically connected to the input terminal of inverter INV6, and the output terminal of inverter INV5 is electrically connected to the second input terminal of NAND gate NAND4; the output terminal of NAND gate NAND4 is electrically connected to the input terminal of inverter INV7, and the output terminal of inverter INV7 serves as the output terminal of the second phase delay unit.

[0009] Furthermore, the charge pump main circuit includes An inverting circuit is used to generate corresponding inverted signals based on the first clock signal CLK_1 and the second clock signal CLK_2. The boost control circuit is used to boost the input voltage VIN under the control of the first clock signal CLK_1 and the second clock signal CLK_2 respectively, and then generate the first boost control signal and the second boost control signal. The boost circuit is used to boost the input voltage VIN under the control of the first boost control signal, the second boost control signal, and the inverted signal output by the first control circuit to generate the first boost signal and the second boost signal. An output control circuit is used to generate a first output control signal and a second output control signal based on the inverted signal output by the first control circuit; and The output circuit is used to reduce the ripple of the first boost signal and the second boost signal under the control of the first output control signal and the second output control signal, and then output them as the charge pump output voltage VOUT0 and the dynamic substrate bias voltage VOUT1, respectively.

[0010] Furthermore, the reverse circuit includes inverter INV8, inverter INV9, PMOS transistor MP0, PMOS transistor MP1, NMOS transistor MN4, and NMOS transistor MN5; The input terminal of the inverter INV8 and the gate of the NMOS transistor MN5 are both electrically connected to the first clock input terminal of the charge pump main circuit to receive the first clock signal CLK_1. The output terminal of the inverter INV8 is electrically connected to the gate of the PMOS transistor MP0 and the output control circuit, respectively. The source of the PMOS transistor MP0 is connected to the analog voltage AVDD, and the drain is electrically connected to the drain of the NMOS transistor MN4 and the boost circuit, respectively. The source of the NMOS transistor MN4 is grounded. The input terminal of the inverter INV9 and the gate of the NMOS transistor MN4 are both electrically connected to the second clock input terminal of the charge pump main circuit to receive the second clock signal CLK_2. The output terminal of the inverter INV9 is electrically connected to the gate of the PMOS transistor MP1 and the output control circuit, respectively. The source of the PMOS transistor MP1 is connected to the analog voltage AVDD, and the drain is electrically connected to the drain of the NMOS transistor MN5 and the boost circuit, respectively. The source of the NMOS transistor MN5 is grounded.

[0011] Furthermore, the boost control circuit includes NMOS transistors MN0 and MN1, capacitors C0 and C1; the sources of both NMOS transistors MN0 and MN1 are connected to the input voltage VIN; the gate of NMOS transistor MN0 is electrically connected to the drain of NMOS transistor MN1 and the upper plate of capacitor C1, serving as the first output terminal of the boost control circuit for outputting a first boost control signal; the lower plate of capacitor C1 is electrically connected to the first clock input terminal of the charge pump main circuit for receiving the first clock signal CLK_1; the gate of NMOS transistor MN1 is electrically connected to the drain of NMOS transistor MN0 and the upper plate of capacitor C0, serving as the second output terminal of the boost control circuit for outputting a second boost control signal; the lower plate of capacitor C0 is electrically connected to the second clock input terminal of the charge pump main circuit for receiving the second clock signal CLK_2.

[0012] Furthermore, the boost circuit includes NMOS transistors MN2 and MN3, capacitors C2 and C3; the sources of both NMOS transistors MN2 and MN3 are connected to the input voltage VIN; the gate of NMOS transistor MN3 serves as the first input terminal of the boost circuit for receiving a first boost control signal; the drain of NMOS transistor MN3 is electrically connected to the upper plate of capacitor C3 and serves as the first output terminal of the boost circuit for outputting a first boost signal; the lower plate of capacitor C3 is electrically connected to the inverting circuit; the gate of NMOS transistor MN2 serves as the second input terminal of the boost circuit for receiving a second boost control signal; the drain of NMOS transistor MN2 is electrically connected to the upper plate of capacitor C2 and serves as the second output terminal of the boost circuit for outputting a second boost signal; the lower plate of capacitor C2 is electrically connected to the inverting circuit.

[0013] Furthermore, the output control circuit includes PMOS transistors MP6 and MP7, capacitor C4, and capacitor C5; the sources of PMOS transistors MP6 and MP7 are both connected to the charge pump output voltage VOUT0; the gate of PMOS transistor MP6 is electrically connected to the drain of PMOS transistor MP7 and the upper plate of capacitor C5, respectively, and serves as the first output terminal of the output control circuit for outputting a first output control signal; the lower plate of capacitor C5 is electrically connected to the inverting circuit; the gate of PMOS transistor MP7 is electrically connected to the drain of PMOS transistor MP6 and the upper plate of capacitor C4, respectively, and serves as the second output terminal of the output control circuit for outputting a second output control signal; the lower plate of capacitor C4 is electrically connected to the inverting circuit.

[0014] Furthermore, the output circuit includes PMOS transistors MP2, MP3, MP4, and MP5; the gates of PMOS transistors MP2 and MP3 are both electrically connected to the first output terminal of the output control circuit for receiving a first output control signal; the drains of PMOS transistors MP2 and MP3 are electrically connected and serve as the first input terminal of the output circuit for receiving a first boost signal. The gates of PMOS transistors MP4 and MP5 are both electrically connected to the second output terminal of the output control circuit to receive the second output control signal; the drains of PMOS transistors MP4 and MP5 are electrically connected to serve as the second input terminal of the output circuit to receive the second boost signal. The source of PMOS transistor MP3 and the source of PMOS transistor MP5 are electrically connected to form the first output terminal of the output circuit, which is used to output the charge pump output voltage VOUT0. The substrates of PMOS transistors MP2, MP3, MP4 and MP5 are electrically connected to the source of PMOS transistor MP2 and the source of PMOS transistor MP4, which are used to form the second output terminal of the output circuit, which is used to output the dynamic substrate bias voltage VOUT1.

[0015] In this invention, using a non-overlapping clock signal effectively reduces reverse leakage current loss and avoids the reverse leakage current caused by the simultaneous conduction of the charge pump's switching transistors, which would result in a closed input-output path. The gate control voltages of NMOS transistors MN2 and MN3 are controlled by a signal generated by the cross-coupling of NMOS transistors MN0 and MN1, allowing NMOS transistors MN2 and MN3 to continuously switch between the deep linear region and the cutoff region. When operating in the deep linear region, the on-resistance of the two NMOS transistors is equivalent to a linear resistance, thereby eliminating the influence of the threshold voltage. Furthermore, the two branches supply power to the load capacitor in the first and second half of the cycle, respectively, which reduces the output voltage ripple. In addition, PMOS transistors MP2, MP3, MP4, and MP5 have a dynamic substrate bias structure. Inappropriate substrate potential selection can cause parasitic transistors to conduct and discharge through the substrate, increasing power consumption. This embodiment eliminates the influence of parasitic transistors by ensuring that the substrate voltage always follows the high potential in the circuit. The circuit in this embodiment is suitable for the high stability and low loss requirements of OTP memory circuits, and effectively solves problems such as substrate leakage, high switching loss, and unstable output in charge pumps. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a circuit diagram of an embodiment of the low-ripple charge pump circuit of the present invention.

[0017] Figure 2 This is a waveform diagram of two overlapping clocks in current technology.

[0018] Figure 3 This is a waveform diagram of two non-overlapping clocks in this embodiment.

[0019] Figure 4 The following is a simulation waveform diagram of two non-overlapping clocks in this embodiment.

[0020] Figure 5 This is a waveform comparison diagram of output voltage VOUT0 and output voltage VOUT1.

[0021] Figure 6 This is the ripple diagram of the output voltage VOUT0.

[0022] Figure 7 This is a graph showing the settling time of the output voltage VOUT0.

[0023] The diagrams in the instruction manual are labeled as follows: Non-overlapping clock circuit 100; first phase delay unit 110; second phase delay unit 120; charge pump main circuit 200; inverting circuit 210; boost control circuit 220; boost circuit 230; output control circuit 240; output circuit 250. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] Please see Figure 1 , Figure 1This is a circuit diagram of an embodiment of the low-ripple charge pump circuit for OTP memory according to the present invention. The low-ripple charge pump circuit for OTP memory in this embodiment includes a non-overlapping clock circuit 100 and a charge pump main circuit 200. The non-overlapping clock circuit 100 is used to generate a non-overlapping first clock signal CLK_1 and a second clock signal CLK_2 based on an external clock signal CLK. The charge pump main circuit 200 is used to boost the input voltage VIN based on the first clock signal CLK_1 and the second clock signal CLK_2 to form a charge pump output voltage VOUT0 and a dynamic substrate bias voltage VOUT1.

[0026] The non-overlapping clock circuit 100 may include an inverter INV1, a NAND gate NAND1, a NAND gate NAND2, a buffer BUF1, a buffer BUF2, a first phase delay unit 110, and a second phase delay unit 120. The input terminal of the inverter INV1 and the second input terminal of the NAND gate NAND2 are both electrically connected to the input terminal of the non-overlapping clock circuit 100 for receiving an external clock signal CLK. The output terminal of the inverter INV1 is electrically connected to the second input terminal of the NAND gate NAND1.

[0027] The first input terminal of the NAND gate NAND1 is electrically connected to the output terminal of the first phase delay unit 110, and the output terminal of the NAND gate NAND1 is electrically connected to the input terminal of the second phase delay unit 120 and the input terminal of the buffer BUF1, respectively. The output terminal of the buffer BUF1 is electrically connected to the first output terminal of the non-overlapping clock circuit 100, and is used to output the first clock signal CLK_1 to the charge pump main circuit 200.

[0028] The first input terminal of the NAND gate 2 is electrically connected to the output terminal of the second phase delay unit 120. The output terminal of the NAND gate 2 is electrically connected to the input terminal of the first phase delay unit 110 and the input terminal of the buffer BUF2. The output terminal of the buffer BUF2 is electrically connected to the second output terminal of the non-overlapping clock circuit 100, and is used to output the second clock signal CLK_2 to the charge pump main circuit 200.

[0029] The first phase delay unit 110 and the second phase delay unit 120 are used to output the input signal after phase delay. The first phase delay unit 110 may include inverters INV2, INV3, and INV4, and a NAND gate NAND3. The input terminal of inverter INV2 and the first input terminal of NAND gate NAND3 are electrically connected and then used as the input terminal of the first phase delay unit 110 and the output terminal of NAND gate NAND2. The output terminal of inverter INV2 is electrically connected to the input terminal of inverter INV3, and the output terminal of inverter INV2 is electrically connected to the second input terminal of NAND gate NAND3. The output terminal of NAND gate NAND3 is electrically connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 is used as the output terminal of the first phase delay unit 110 and the first input terminal of NAND gate NAND1. With the above structure, the two input terminals of the NAND gate NAND3 are respectively connected to the input clock signal and the input clock signal after being delayed by two inverters (i.e., inverter INV2 and inverter INV3), thereby realizing the phase delay function.

[0030] The second phase delay unit 120 may include inverters INV5, INV6, and INV7, and a NAND gate NAND4. The input terminal of inverter INV5 and the first input terminal of NAND gate NAND4 are electrically connected, serving as the input terminal of the second phase delay unit 120 and the output terminal of NAND gate NAND1. The output terminal of inverter INV5 is electrically connected to the input terminal of inverter INV6, and the output terminal of inverter INV5 is electrically connected to the second input terminal of NAND gate NAND4. The output terminal of NAND gate NAND4 is electrically connected to the input terminal of inverter INV7, and the output terminal of inverter INV7 serves as the output terminal of the second phase delay unit 120 and the first input terminal of NAND gate NAND2. The principle of the second phase delay unit 120 is the same as that of the first phase delay unit 110.

[0031] The clock signal needs to be processed by the clock control circuit to generate the different duty cycle signals required for the charge pump to operate. Furthermore, the generated clock signals must not overlap. Generating non-overlapping clock signals is crucial as it effectively reduces reverse leakage current loss. The charge pump transfers voltage using MOSFETs, which switch between the linear and cutoff regions. This requires ensuring that the MOSFETs are turned off before being turned on.

[0032] Please see Figure 2In the prior art, the clock output of the clock control circuit overlaps with the clock output. This causes the switch of the charge pump circuit to turn on simultaneously at time T, resulting in a reverse leakage current caused by the connection between the input and output. The reverse leakage current has a significant impact on the power consumption of the circuit. To avoid this problem, a non-overlapping clock needs to be used.

[0033] Please see Figure 3 The two clock outputs from the clock control circuit have a dead time between times T1 and T2. During this dead time, the switching transistors of the charge pump circuit are both off. This prevents the transmission transistors from simultaneously turning on during state switching, thus avoiding reverse leakage current. Please refer to [link / reference]. Figure 4 The non-overlapping clock generation circuit was simulated, and the simulation results show that the non-overlapping clock has a certain dead time, which can meet the requirements of the charge pump circuit and effectively avoid reverse leakage current.

[0034] Please continue reading. Figure 1 The charge pump main circuit 200 includes an inverting circuit 210, a boost control circuit 220, a boost circuit 230, an output control circuit 240, and an output circuit 250. The inverting circuit 210 generates corresponding inverted signals based on a first clock signal CLK_1 and a second clock signal CLK_2. The boost control circuit 220 boosts the input voltage VIN under the control of the first clock signal CLK_1 and the second clock signal CLK_2, respectively, to generate a first boost control signal and a second boost control signal. The boost circuit 230 boosts the input voltage VIN under the control of the first boost control signal, the second boost control signal, and the inverted signal output from the first control circuit, respectively, to generate a first boost signal and a second boost signal. The output control circuit 240 generates a first output control signal and a second output control signal based on the inverted signal output from the first control circuit. The output circuit 250 reduces the ripple of the first and second boost signals under the control of the first and second output control signals, and outputs them as the charge pump output voltage VOUT0 and the dynamic substrate bias voltage VOUT1, respectively.

[0035] The inverting circuit 210 may include inverters INV8 and INV9, PMOS transistors MP0 and MP1, NMOS transistors MN4 and MN5. The input terminal of inverter INV8 and the gate of NMOS transistor MN5 are both electrically connected to the first clock input terminal of the charge pump main circuit 200, for receiving the first clock signal CLK_1 from the non-overlapping clock circuit 100. The output terminal of inverter INV8 is electrically connected to the gate of PMOS transistor MP0 and the output control circuit 240, respectively. The source of PMOS transistor MP0 is connected to the analog voltage AVDD, and its drain is electrically connected to the drain of NMOS transistor MN4 and the boost circuit 230, respectively. The source of NMOS transistor MN4 is grounded.

[0036] The input terminal of the inverter INV9 and the gate of the NMOS transistor MN4 are both electrically connected to the second clock input terminal of the charge pump main circuit 200, for receiving the second clock signal CLK_2 from the non-overlapping clock circuit 100. The output terminal of the inverter INV9 is electrically connected to the gate of the PMOS transistor MP1 and the output control circuit 240, respectively. The source of the PMOS transistor MP1 is connected to the analog voltage AVDD, and the drain is electrically connected to the drain of the NMOS transistor MN5 and the boost circuit 230, respectively. The source of the NMOS transistor MN5 is grounded.

[0037] The boost control circuit 220 may include NMOS transistors MN0 and MN1, capacitor C0, and capacitor C1. NMOS transistors MN0 and MN1 are cross-coupled. Specifically, the sources of both NMOS transistors MN0 and MN1 are connected to the input voltage VIN. The gate of NMOS transistor MN0 is electrically connected to the drain of NMOS transistor MN1 and the upper plate of capacitor C1, serving as the first output terminal of the boost control circuit 220 to output a first boost control signal to the boost circuit 230. The lower plate of capacitor C1 is electrically connected to the first clock input terminal of the charge pump main circuit 200, used to receive the first clock signal CLK_1 from the non-overlapping clock circuit 100.

[0038] The gate of NMOS transistor MN1 is electrically connected to the drain of NMOS transistor MN0 and the upper plate of capacitor C0, respectively, and serves as the second output terminal of boost control circuit 220 to output a second boost control signal to boost circuit 230. The lower plate of capacitor C0 is electrically connected to the second clock input terminal of charge pump main circuit 200, and is used to receive the second clock signal CLK_2 from non-overlapping clock circuit 100.

[0039] The boost circuit 230 may include NMOS transistors MN2 and MN3, capacitors C2 and C3. The sources of both NMOS transistors MN2 and MN3 are connected to the input voltage VIN. The gate of NMOS transistor MN3 serves as the first input terminal of the boost circuit 230 and is electrically connected to the upper plate of capacitor C1 to receive the first boost control signal. The drain of NMOS transistor MN3, after being electrically connected to the upper plate of capacitor C3, serves as the first output terminal of the boost circuit 230 to output the first boost signal to the output circuit 250. The lower plate of capacitor C3 is electrically connected to the drain of NMOS transistor MN1 in the inverting circuit 210.

[0040] The gate of the NMOS transistor MN2 is electrically connected to the upper plate of capacitor C0 as the second input terminal of the boost circuit 230, and is used to receive the second boost control signal. The drain of the NMOS transistor MN2 is electrically connected to the upper plate of capacitor C2, and serves as the second output terminal of the boost circuit 230 to output the second boost signal to the output circuit 250; the lower plate of capacitor C2 is electrically connected to the drain of NMOS transistor MN0 in the inverting circuit 210.

[0041] The output control circuit 240 may include PMOS transistors MP6 and MP7, capacitor C4, and capacitor C5. PMOS transistors MP6 and MP7 are cross-coupled; specifically, the sources of both PMOS transistors MP6 and MP7 are electrically connected to the first output terminal of the output circuit 250 to connect to the charge pump output voltage VOUT0. The gate of PMOS transistor MP6 is electrically connected to the drain of PMOS transistor MP7 and the upper plate of capacitor C5, serving as the first output terminal of the output control circuit 240, used to output a first output control signal to the output circuit 250.

[0042] The lower plate of capacitor C5 is electrically connected to the gate of PMOS transistor MP1 in the inverting circuit 210. The gate of PMOS transistor MP7 is electrically connected to the drain of PMOS transistor MP6 and the upper plate of capacitor C4, serving as the second output terminal of output control circuit 240, used to output a second output control signal to output circuit 250. The lower plate of capacitor C4 is electrically connected to the gate of PMOS transistor MP0 in the inverting circuit 210.

[0043] The output circuit 250 may include PMOS transistors MP2, MP3, MP4, and MP5. The gates of both PMOS transistors MP2 and MP3 are electrically connected to the upper plate of capacitor C5 in the output control circuit 240, thereby connecting them to the first output terminal of the output control circuit 240 to receive the first output control signal. The drains of PMOS transistors MP2 and MP3, after being electrically connected, serve as the first input terminal of the output circuit 250 and are electrically connected to the upper plate of capacitor C3 in the boost circuit 230 to receive the first boost signal.

[0044] The gates of PMOS transistors MP4 and MP5 are both electrically connected to the upper plate of capacitor C4 in the output control circuit 240, thereby connecting them to the second output terminal of the output control circuit 240 for receiving the second output control signal. The drains of PMOS transistors MP4 and MP5, after being electrically connected, serve as the second input terminal of the output circuit 250 and are electrically connected to the upper plate of capacitor C2 in the boost circuit 230 for receiving the second boost signal.

[0045] The sources of PMOS transistors MP3 and MP5 are electrically connected and serve as the first output terminal of output circuit 250, used to output the charge pump output voltage VOUT0. The substrates of PMOS transistors MP2, MP3, MP4, and MP5 are electrically connected to the sources of PMOS transistors MP2 and MP4 and serve as the second output terminal of output circuit 250, used to output the dynamic substrate bias voltage VOUT1.

[0046] The working principle of this embodiment is as follows: Please see Figure 1 When the first clock signal CLK_1 is low, the second clock signal CLK_2 is high (the low level of both clock signals is 0V, and the high level is AVDD). The input voltage VIN charges capacitors C0 and C1 through cross-coupled NMOS transistors MN0 and MN1. Since the charge pump uses capacitors for voltage boosting, the first fundamental property of a capacitor is that the voltage difference across it cannot change abruptly. That is, if the voltage of one plate changes, the voltage of the other plate will also change in the same way to ensure that the voltage difference between the two plates of the capacitor is the same. The second fundamental property of a capacitor is the principle of capacitance sharing. When two capacitors with different initial voltages are connected through a switch, the charge will be redistributed. The final voltage across the capacitor is the weighted average of the voltages of the two capacitors before the switch is closed, with the weight being the capacitance value.

[0047] When the levels of the first clock signal CLK_1 and the second clock signal CLK_2 flip, according to the first fundamental property of capacitors, the upper plates of capacitors C0 and C1 will change by a ΔV following the change of their lower plates. Since the high level of the clock signal is AVDD, ΔV = AVDD. As the clock signals flip, the upper plates of capacitors C0 and C1 will respectively generate a low level of VIN and a high level of VIN+AVDD (i.e., the first boost control signal and the second boost control signal) to control NMOS transistors MN2 and MN3.

[0048] The input signals to the lower plates of capacitors C2 and C3 are the inverted signals of the first clock signal CLK_1 and the second clock signal CLK_2, respectively, after signal processing in the inverting circuit 210. This results in the lower plate of capacitor C2 being at a high level AVDD when the gate signal of NMOS transistor MN2 is low (VIN). NMOS transistors MN2 and MN3 employ dynamic gate bias, making their on-resistance equivalent to a linear resistance when operating in the deep linear region, thus eliminating the influence of the threshold voltage. Furthermore, in the first and second half of the cycle, the two branches supply power to the load capacitors (C2 and C3), respectively, reducing output voltage ripple. The upper plates of capacitors C2 and C3 also generate clock signals (the first boost signal and the second boost signal) with a low level of VIN and a high level of VIN+AVDD, respectively. These boost signals, after passing through the output circuit 250, ultimately generate the charge pump output voltage VOUT0 and the dynamic substrate bias voltage VOUT1.

[0049] In the output circuit 250, PMOS transistors MP3 and MP5 are transmission transistors, while PMOS transistors MP2 and MP4 are auxiliary bias transistors. The substrate bias effect is particularly important for the charge pump. Because the substrate of an NMOS transistor is grounded, as the number of stages in the charge pump circuit increases, the substrate bias effect can cause the threshold voltage to increase to the point where the transmission transistors may not be able to conduct. In this embodiment, PMOS transistors are used instead of NMOS transistors in the output circuit 250 because the deep N-well process of PMOS transistors allows for free selection of their substrate potential. This embodiment also employs a dynamic substrate bias structure. Since the source-drain voltage of a PMOS transistor changes dynamically, fixing the substrate potential at a fixed potential cannot guarantee the complete turn-off of parasitic transistors. Therefore, in this embodiment, two auxiliary transistors (i.e., PMOS transistor MP2 and PMOS transistor MP4) are added. The function of these two auxiliary transistors is to dynamically select the bias of the substrate. It can be seen that whether the voltage of the upper plate of capacitor C2 is higher than that of the upper plate of capacitor C3, or the voltage of the upper plate of capacitor C3 is higher than that of the upper plate of capacitor C2, the two PMOS transistors on the high voltage side are turned on. At this time, the substrates of PMOS transistors MP2, MP3, MP4 and MP5 will be connected to the high voltage side through the conduction of the auxiliary transistors. This ensures that the substrates of the two transmission transistors (i.e., PMOS transistors MP3 and MP5) are always connected to a higher potential, eliminating the influence of parasitic transistors.

[0050] The gate voltages of PMOS transistors MP2, MP3, MP4, and MP5 are provided by the drains of cross-coupled PMOS transistors MP6 and MP7 (i.e., the upper plates of capacitors C4 and C5). The lower plates of capacitors C4 and C5 are input as inverted signals of the first clock signal CLK_1 and the second clock signal CLK_2, processed by inverters INV8 and INV9 in the inverting circuit 210, respectively. This inverted signal ensures that one of the auxiliary bias transistors PMOS transistors MP2 and MP4, and the transmission transistors PMOS transistors MP3 and MP5, is always on, thereby reducing the output voltage ripple.

[0051] For a simulation of the charge pump circuit of this invention, please refer to [link / reference]. Figure 5 The simulation diagram shows the generated charge pump output voltage VOUT0 and dynamic substrate bias voltage VOUT1. With VIN = 1.8V, AVDD = 1.8V, and CLK a 200MHz square wave clock signal with a 50% duty cycle and an amplitude range of 0V to AVDD, it can be seen that the dynamic substrate bias voltage follows the charge pump output voltage very well, eliminating the influence of parasitic transistors.

[0052] Please see Figure 6 The figure shows the ripple of the charge pump output voltage VOUT0. In this embodiment, the ripple after the charge pump voltage is boosted and stabilized is approximately 10mV. Please refer to [link to relevant documentation]. Figure 7 The diagram shows the setup time of the charge pump output VOUT1. In this embodiment, the time required for the charge pump to boost to a stable voltage is approximately 23 ns. It is evident that the optimized charge pump circuit design in this embodiment makes the output voltage VOUT0 more stable, reduces jitter, significantly lowers noise and power consumption, and improves chip efficiency and reliability.

[0053] In this embodiment, using a non-overlapping clock signal can effectively reduce reverse leakage current loss and avoid the simultaneous conduction of the charge pump switching transistors (including NMOS transistors MN2, MN3, MP2, MP3, MP4, and MP5), which would cause reverse leakage current due to the open path between the input and output. The gate control voltages of NMOS transistors MN2 and MN3 are controlled by a signal generated by the cross-coupling of NMOS transistors MN0 and MN1, which allows NMOS transistors MN2 and MN3 to switch continuously between the deep linear region and the cutoff region. When operating in the deep linear region, the on-resistance of NMOS transistors MN2 and MN3 is equivalent to a linear resistance, thereby eliminating the influence of the threshold voltage. Furthermore, the two branches supply power to the load capacitor in the first and second half of the cycle, respectively, which can reduce the output voltage ripple. Furthermore, PMOS transistors MP2, MP3, MP4, and MP5 employ a dynamic substrate bias structure. Inappropriate substrate potential selection can cause parasitic transistors to conduct and discharge through the substrate, increasing power consumption. This embodiment eliminates the influence of parasitic transistors by ensuring the substrate voltage consistently follows the high potential in the circuit. The circuit of this embodiment is suitable for the high stability and low loss requirements of OTP memory circuits, effectively solving problems such as substrate leakage, high switching losses, and unstable output in charge pumps.

[0054] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A low-ripple charge pump circuit, characterized in that: include A non-overlapping clock circuit is used to generate a non-overlapping first clock signal CLK_1 and a second clock signal CLK_2 based on an external clock signal CLK. as well as The charge pump main circuit is used to boost the input voltage VIN according to the first clock signal CLK_1 and the second clock signal CLK_2 to form the charge pump output voltage VOUT0 and the dynamic substrate bias voltage VOUT1.

2. The low-ripple charge pump circuit as described in claim 1, characterized in that: The non-overlapping clock circuit includes an inverter INV1, a NAND gate NAND1, a NAND gate NAND2, a buffer BUF1, a buffer BUF2, a first phase delay unit, and a second phase delay unit; the first phase delay unit and the second phase delay unit are used to delay the phase of the input signal before outputting it. The input terminal of the inverter INV1 and the second input terminal of the NAND gate NAND2 are both electrically connected to the input terminal of the non-overlapping clock circuit for receiving the external clock signal CLK; the output terminal of the inverter INV1 and the second input terminal of the NAND gate NAND1 are electrically connected. The first input terminal of the NAND gate NAND1 is electrically connected to the output terminal of the first phase delay unit, and the output terminal of the NAND gate NAND1 is electrically connected to the input terminal of the second phase delay unit and the input terminal of the buffer BUF1, respectively; the output terminal of the buffer BUF1 is electrically connected to the first output terminal of the non-overlapping clock circuit, and is used to output the first clock signal CLK_1. The first input terminal of the NAND gate NAND2 is electrically connected to the output terminal of the second phase delay unit, and the output terminal of the NAND gate NAND2 is electrically connected to the input terminal of the first phase delay unit and the input terminal of the buffer BUF2 respectively; the output terminal of the buffer BUF2 is electrically connected to the second output terminal of the non-overlapping clock circuit, and is used to output the second clock signal CLK_2.

3. The low-ripple charge pump circuit as described in claim 2, characterized in that: The first phase delay unit includes inverters INV2, INV3, and INV4, and a NAND gate NAND3; the input terminal of inverter INV2 and the first input terminal of NAND gate NAND3 are electrically connected and serve as the input terminal of the first phase delay unit; the output terminal of inverter INV2 is electrically connected to the input terminal of inverter INV3, and the output terminal of inverter INV2 is electrically connected to the second input terminal of NAND gate NAND3; the output terminal of NAND gate NAND3 is electrically connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 serves as the output terminal of the first phase delay unit.

4. The low-ripple charge pump circuit as described in claim 3, characterized in that: The second phase delay unit includes inverters INV5, INV6, and INV7, and a NAND gate NAND4. The input terminal of inverter INV5 and the first input terminal of NAND gate NAND4 are electrically connected and serve as the input terminal of the second phase delay unit. The output terminal of inverter INV5 is electrically connected to the input terminal of inverter INV6, and the output terminal of inverter INV5 is electrically connected to the second input terminal of NAND gate NAND4. The output terminal of NAND gate NAND4 is electrically connected to the input terminal of inverter INV7, and the output terminal of inverter INV7 serves as the output terminal of the second phase delay unit.

5. The low-ripple charge pump circuit as described in any one of claims 1 to 4, characterized in that: The charge pump main circuit includes An inverting circuit is used to generate corresponding inverted signals based on the first clock signal CLK_1 and the second clock signal CLK_2. The boost control circuit is used to boost the input voltage VIN under the control of the first clock signal CLK_1 and the second clock signal CLK_2 respectively, and then generate the first boost control signal and the second boost control signal. The boost circuit is used to boost the input voltage VIN under the control of the first boost control signal, the second boost control signal, and the inverted signal output by the first control circuit to generate the first boost signal and the second boost signal. An output control circuit is used to generate a first output control signal and a second output control signal based on the inverted signal output by the first control circuit. as well as The output circuit is used to reduce the ripple of the first boost signal and the second boost signal under the control of the first output control signal and the second output control signal, and then output them as the charge pump output voltage VOUT0 and the dynamic substrate bias voltage VOUT1, respectively.

6. The low-ripple charge pump circuit as described in claim 5, characterized in that: The reverse circuit includes inverter INV8, inverter INV9, PMOS transistor MP0, PMOS transistor MP1, NMOS transistor MN4, and NMOS transistor MN5; The input terminal of the inverter INV8 and the gate of the NMOS transistor MN5 are both electrically connected to the first clock input terminal of the charge pump main circuit to receive the first clock signal CLK_1. The output terminal of the inverter INV8 is electrically connected to the gate of the PMOS transistor MP0 and the output control circuit, respectively. The source of the PMOS transistor MP0 is connected to the analog voltage AVDD, and the drain is electrically connected to the drain of the NMOS transistor MN4 and the boost circuit, respectively. The source of the NMOS transistor MN4 is grounded. The input terminal of the inverter INV9 and the gate of the NMOS transistor MN4 are both electrically connected to the second clock input terminal of the charge pump main circuit to receive the second clock signal CLK_2. The output terminal of the inverter INV9 is electrically connected to the gate of the PMOS transistor MP1 and the output control circuit, respectively. The source of the PMOS transistor MP1 is connected to the analog voltage AVDD, and the drain is electrically connected to the drain of the NMOS transistor MN5 and the boost circuit, respectively. The source of the NMOS transistor MN5 is grounded.

7. The low-ripple charge pump circuit as described in claim 5, characterized in that: The boost control circuit includes NMOS transistors MN0 and MN1, capacitors C0 and C1. The sources of NMOS transistors MN0 and MN1 are both connected to the input voltage VIN. The gate of NMOS transistor MN0 is electrically connected to the drain of NMOS transistor MN1 and the upper plate of capacitor C1, serving as the first output terminal of the boost control circuit for outputting a first boost control signal. The lower plate of capacitor C1 is electrically connected to the first clock input terminal of the charge pump main circuit for receiving the first clock signal CLK_1. The gate of NMOS transistor MN1 is electrically connected to the drain of NMOS transistor MN0 and the upper plate of capacitor C0, serving as the second output terminal of the boost control circuit for outputting a second boost control signal. The lower plate of capacitor C0 is electrically connected to the second clock input terminal of the charge pump main circuit for receiving the second clock signal CLK_2.

8. The low-ripple charge pump circuit as described in claim 5, characterized in that: The boost circuit includes NMOS transistors MN2 and MN3, capacitors C2 and C3. The sources of both NMOS transistors MN2 and MN3 are connected to the input voltage VIN. The gate of NMOS transistor MN3 serves as the first input terminal of the boost circuit for receiving a first boost control signal. The drain of NMOS transistor MN3 is electrically connected to the upper plate of capacitor C3 and serves as the first output terminal of the boost circuit for outputting a first boost signal. The lower plate of capacitor C3 is electrically connected to an inverting circuit. The gate of NMOS transistor MN2 serves as the second input terminal of the boost circuit for receiving a second boost control signal. The drain of NMOS transistor MN2 is electrically connected to the upper plate of capacitor C2 and serves as the second output terminal of the boost circuit for outputting a second boost signal. The lower plate of capacitor C2 is electrically connected to an inverting circuit.

9. The low-ripple charge pump circuit as described in claim 5, characterized in that: The output control circuit includes PMOS transistors MP6 and MP7, capacitor C4, and capacitor C5. The sources of PMOS transistors MP6 and MP7 are both connected to the charge pump output voltage VOUT0. The gate of PMOS transistor MP6 is electrically connected to the drain of PMOS transistor MP7 and the upper plate of capacitor C5, serving as the first output terminal of the output control circuit for outputting a first output control signal. The lower plate of capacitor C5 is electrically connected to the inverting circuit. The gate of PMOS transistor MP7 is electrically connected to the drain of PMOS transistor MP6 and the upper plate of capacitor C4, serving as the second output terminal of the output control circuit for outputting a second output control signal. The lower plate of capacitor C4 is electrically connected to the inverting circuit.

10. The low-ripple charge pump circuit as described in claim 5, characterized in that: The output circuit includes PMOS transistors MP2, MP3, MP4, and MP5; the gates of PMOS transistors MP2 and MP3 are electrically connected to the first output terminal of the output control circuit for receiving a first output control signal; the drains of PMOS transistors MP2 and MP3 are electrically connected and serve as the first input terminal of the output circuit for receiving a first boost signal. The gates of PMOS transistors MP4 and MP5 are both electrically connected to the second output terminal of the output control circuit to receive the second output control signal; the drains of PMOS transistors MP4 and MP5 are electrically connected to serve as the second input terminal of the output circuit to receive the second boost signal. The source of PMOS transistor MP3 and the source of PMOS transistor MP5 are electrically connected to form the first output terminal of the output circuit, which is used to output the charge pump output voltage VOUT0. The substrates of PMOS transistors MP2, MP3, MP4 and MP5 are electrically connected to the source of PMOS transistor MP2 and the source of PMOS transistor MP4, which are used to form the second output terminal of the output circuit, which is used to output the dynamic substrate bias voltage VOUT1.

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