Piezoresistor packaging structure and packaging method

Abstract

The packaging method comprises the following steps: stacking a bare chip A and a bare chip B in parallel, mounting the bare chip A and the bare chip B on a substrate, packaging the bare chip A and the bare chip B, and grinding the packaging top surface until the surface of the bare chip A is exposed; vertically etching the encapsulating material to form a groove, electroplating a circuit I in the groove, electroplating to extend to the surface of the bare chip A, and continuing to encapsulate the circuit I; the packaging body is overturned up and down to be mounted again, the bare chip B is exposed out of the packaging body in a flush mode, the bare chip B is etched to the bare chip A in a penetrating mode, a conducting hole is formed, a second circuit is electroplated in the conducting hole and extends to the packaging surface, the first circuit is connected with the bare chip B through a third electroplating circuit, and the second circuit and the third circuit are packaged, ground and exposed; and electroplating pins on the exposed circuit II and circuit III, stripping the substrate and cutting into packaging body product units. According to the invention, the technological process is simplified, the packaging space is compressed, the packaging requirement of small-size products is met, a varistor with a larger size can be arranged, and the product performance is further improved.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and particularly relates to a varistor packaging structure and packaging method. Background Technology

[0002] Varistors are core general-purpose devices for overvoltage and surge protection. With their fast response speed, adjustable current carrying capacity, low cost, and flexible size, they are used in almost all scenarios that require overvoltage and surge protection, such as low-voltage microelectronics, consumer electronics, industrial equipment, power grids, new energy, and automotive electronics. Different package types are precisely matched to the voltage, current carrying capacity, and space requirements of different scenarios.

[0003] By packaging varistors in parallel, the total current carrying capacity is increased, and the surge current is evenly distributed to each chip, preventing a single chip from being broken down and burned. The existing parallel packaging structure packages varistors separately and then solders them in parallel to the working area (such as a circuit board), which occupies a large space. The existing process of stacking bare dies and then packaging them is difficult to meet the requirements of small-size packaging, or the performance of products with the same package size is limited. Summary of the Invention

[0004] To address the problems in the prior art, the present invention provides a varistor packaging structure and packaging method.

[0005] To achieve the above objectives, the present invention proposes a varistor packaging method, comprising the following steps: Mounting and encapsulation: Stack bare die A and bare die B in parallel, mount them on the substrate and encapsulate them, and grind the top surface of the encapsulation until the surface of bare die A is exposed; Etching and electroplating: Vertical etching of the encapsulating material forms a groove, and electroplating of line one within the groove extends to the surface of bare die A, continuing to encapsulate line one; Transformer etching: The encapsulation body is flipped up and down and remounted. The bare die B is flush with the encapsulation body and exposed. The bare die B is etched through to the bare die A to form a through hole. Line 2 is electroplated in the through hole and extends to the encapsulation body. Line 1 is connected to the bare die B through electroplated line 3. Line 2 and line 3 are encapsulated and polished to expose them. Electroplated leads: Electroplated leads are applied to exposed lines 2 and 3, the substrate is peeled off and cut into package product units.

[0006] Furthermore, in the mounting and encapsulation step, the copper-clad core of bare die A is stacked in parallel with the copper-clad core of bare die B through thermally and electrically conductive adhesive. After surface etching, it is vertically cut and separated into multiple stacked structures of bare die A and bare die B, and then the stacked structure is mounted on the substrate.

[0007] Furthermore, in the plate etching step, the etched vias avoid the effective area of ​​the bare die B.

[0008] Furthermore, in the board etching step, during the via etching, the exposed copper surface of the die B is etched to form a cross section, severing the electrical connection between line two and the entire exposed copper surface of die B.

[0009] Furthermore, in the board etching step, the second line plated in the through hole leads the bare die A and bare die B in parallel to the pin, and then leads them out of the package body through the pin.

[0010] A varistor packaging structure includes a package body, which encapsulates: Bare dies, bare die A and bare die B are stacked in parallel, one on top of the other; Line 1 is a line that is electrically connected to the bare die A after etching grooves inside the package and electroplating. Line 1 electrically leads the bare die A out of the package. Line 2 is formed by etching through die B to die A to form a via. Line 2 is electroplated in the via and connects die A and die B in parallel to the package body. Line 3 is electrically connected to Line 1, and another electrical connection of the parallel circuit of die A and die B is brought out to the outside of the package.

[0011] Furthermore, the copper-clad core of die A is stacked in parallel with the copper-clad core of die B through thermally and electrically conductive adhesive, and then cut and separated into multiple stacked structures of die A and die B.

[0012] Furthermore, the via is etched to avoid the effective area of ​​die B.

[0013] Furthermore, during the etching of the via, the exposed copper surface of the die B is etched to form a cross section, severing the electrical connection between line two and the entire exposed copper surface of die B.

[0014] Furthermore, pins are electroplated on Line 3 and Line 2, and the pins are electroplated outside the package body, respectively leading the electrical properties of Line 2 and Line 3 out of the package body.

[0015] Beneficial effects of this invention: While simplifying the process and reducing costs, it also compresses the packaging space while encapsulating the same varistor size, thus meeting the packaging requirements of small-size products; and it can maximize the use of packaging space while keeping the same package size, allowing for the placement of larger varistors, thereby further improving product performance. Attached Figure Description

[0016] Figures 1-8 This is a schematic diagram of the mounting and encapsulation steps of a varistor packaging structure and packaging method according to the present invention; Figures 9-12 This is a schematic diagram of the etching and electroplating steps of a varistor packaging structure and packaging method according to the present invention. Figures 13-17 This is a schematic diagram of the board etching step in the packaging structure and packaging method of a varistor according to the present invention; Figures 18-19 This is a schematic diagram of the electroplating pin steps of a varistor packaging structure and packaging method according to the present invention. Figure 20 This is a cross-sectional view of a varistor packaging structure according to the present invention.

[0017] In the diagram: 1. Die A; 2. Die B; 3. Groove; 4. Via; 5. Line 1; 6. Line 2; 7. Line 3; 8. Pin; 9. Package. Detailed Implementation

[0018] The present invention will now be described in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout.

[0019] The directional terms used in this invention, such as up, down, left, right, front, back, inside, outside, front, back, side, etc., are merely for reference to the accompanying drawings. The embodiments and directional terms used in the following description with reference to the accompanying drawings are exemplary and are only used to explain this invention, and should not be construed as limiting this invention. Furthermore, the various specific processes and materials provided in this invention are examples that those skilled in the art will recognize for the application of other processes and / or the use of other materials.

[0020] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an explanation of the varistor packaging structure and packaging method proposed in this invention.

[0021] The encapsulation method specifically includes the following steps: Mounting and encapsulation: Stack bare die A1 and bare die B2 in parallel, mount them on the substrate and encapsulate them, and grind the top surface of the encapsulation until the surface of bare die A1 is exposed; Etching and electroplating: Vertical etching of the encapsulating material forms a groove 3, and electroplating of line 5 is performed in the groove 3. The electroplating extends to the surface of the bare die A1 and continues to encapsulate line 5. Transformer etching: The encapsulation body is flipped up and down and re-attached. The bare die B2 is flush with the encapsulation body and exposed. The bare die B2 is etched through to the bare die A1 to form a through hole 4. The second line 6 is electroplated in the through hole 4 and extends to the encapsulation body. The first line 5 is connected to the bare die B2 through the electroplated third line 7. The second line 6 and the third line 7 are encapsulated and polished to expose them. Electroplated pins 8: Electroplated pins 8 are applied to exposed lines 2 6 and 3 7. The substrate is then peeled off and cut into package 9 product units.

[0022] In the mounting and encapsulation step, firstly, the copper-clad core of die A1 is stacked on top of the copper-clad core of die B2 using thermally and electrically conductive adhesive (such as silver paste). The output terminals of die A1 and die B2 are connected, or the input terminals of die A1 and die B2 are connected, achieving parallel electrical connection between the two dies. Then, the copper-clad surfaces after stacking are etched to form a cutting opening. The stacked core is then vertically cut through the cutting opening, separating it into multiple stacked structures of die A1 and die B2 (e.g., ...). Figures 1-5 (As shown); other methods can also be used to form a two-chip stacked structure, and the present invention does not limit this.

[0023] Another substrate is provided, and a corresponding number of stacked structures are mounted according to the substrate area size. This invention takes mounting two sets of stacked structures as an example (e.g.) Figure 6 As shown), in subsequent processes, the process flow for each stacked structure is the same, ultimately resulting in identical product units. The stacked structures of bare die A1 and bare die B2 are mounted on the corresponding positions of the substrate using chip adhesive (such as die bond adhesive). In this invention, bare die A1 is stacked on bare die B2, meaning that when the stacked structure is mounted on the substrate, the copper-clad side of bare die B2 is mounted on the substrate. Then, the stacked structure is completely encapsulated using encapsulation material through an encapsulation process. This encapsulation is the first encapsulation in the entire method (e.g., Figure 7 (As shown); After the encapsulant has cured, the top surface of the encapsulant is then horizontally ground using a grinding process until the copper-clad surface of the bare die A1 is exposed (as shown). Figure 8 As shown in the figure, the first encapsulation layer is obtained (not shown in the figure).

[0024] In the etching and electroplating step, the encapsulating material is etched at a suitable position on the surface of the exposed copper-clad surface of the encapsulation layer A1. The etching solution vertically etches at the corresponding position of each stacked structure, forming a groove 3 of a certain width. The width of the groove 3 is set in the actual product design stage to match the actual product requirements. This invention does not limit this. The bottom of the groove 3 may be etched to the exposed substrate surface or may not be etched to the exposed substrate surface. This invention also does not limit the etching depth of the groove 3 (e.g., ...). Figure 9 As shown in the figure, the present invention takes the example of not etching to the exposed substrate surface.

[0025] In this invention, the groove 3 is formed by etching. First, a mask is applied to the surface of the encapsulation layer to be etched to expose the position to be etched. Then, anisotropic etching is performed on the position to be etched using a wet etching process to finally form the groove 3. This is a commonly used encapsulation material etching process in the field. Other etching processes, such as dry etching, are also within the scope of protection of this invention.

[0026] Metal is deposited in the etched grooves 3 through an electroplating process. The metal can either completely fill the grooves 3 or be plated on the inner wall of the grooves 3, depending on the width of the grooves 3. For excessively wide grooves 3, complete metal filling increases the electroplating cost. This invention takes metal plating on the inner wall of the grooves 3 as an example (e.g.) Figure 10 As shown), the metal plated on the inner wall of the groove 3 forms a single integral circuit 5. Circuit 5 extends from the plated area in the groove 3 to the surface of the encapsulation layer 1 and is electrically connected to the exposed copper-clad surface of the bare die A1. After the plated area is plated, an encapsulation process is used to further encapsulate the groove 3 using an encapsulation material, completely filling the groove 3 and completely encapsulating circuit 5. After the encapsulation material cures, the top surface of the encapsulation is horizontally mechanically ground until the surface of circuit 5 is exposed. The circuit 5 is then plated thicker using another plated process, forming a single integral circuit 5 (as shown). Figure 11 As shown), re-encapsulate (as shown) Figure 12 As shown in the figure), the encapsulating material cures to become the second encapsulating layer (not shown in the figure). Each encapsulating material is cured into one piece, that is, the first encapsulating layer and the second encapsulating layer are cured into one piece.

[0027] In the transfer etching step, the encapsulation body, consisting of the cured encapsulation layer one and encapsulation layer two, is peeled off from the substrate. The encapsulation body is then flipped over and reattached to the substrate using adhesive. At this point, the copper-clad surface of the bare die B2 is flush with and exposed above the encapsulation layer one (e.g., ...). Figure 13 (As shown).

[0028] Etching is performed perpendicular to the copper-clad surface of die B2, with the etching penetrating die B2 (e.g. Figure 14 As shown in the figure, in this invention, die B2 is a varistor chip with a core of zinc oxide ceramic. Because zinc oxide ceramic is a hard and brittle inorganic sintered body, it is prone to chemical reactions with strong acids and alkalis. Therefore, a process mainly based on wet chemical etching and supplemented by dry plasma etching is required. Furthermore, the etching process must consider the varistor performance, avoiding the effective area of ​​die B2 to prevent damage to the grain boundary phase. During wet etching, a mask that does not react with the etching solution is used to protect the unetched areas; this mask is a commonly used mask in the field. Since die B2 is copper-coated, the copper layer is etched first, followed by the main body of die B2. A two-step compatible etching scheme can be used, where the mainstream acidic etching solution first etches the copper layer, and then the alkaline etching solution is used to continue etching the ceramic. Alternatively, a one-step etching scheme using a dedicated mixed etching solution can be used.

[0029] Through-hole 4 is formed by etching through bare die B2 to bare die A1. When etching through-hole 4, a local area of ​​the exposed copper surface of bare die B2 is also etched to form a cross section, cutting off the electrical connection between the subsequent electroplated line 6 and the exposed copper surface of bare die B2. At the same time, in the etching and electroplating step, taking the example that the groove 3 is not etched to the exposed substrate surface, it is also necessary to etch the end of the groove 3 line 5 to the encapsulation material corresponding to the surface of the encapsulation layer, so that the end of the line 5 is exposed.

[0030] A second line 6 is electroplated inside the via 4. The electroplating of the second line 6 is disposed on the inner wall of the via 4 or completely fills the via 4. Taking the electroplating of the inner wall of the via 4 as an example, the second line 6 is electroplated to extend to the surface of the encapsulation layer and is electrically connected to a portion of the cross-section of the bare die B2. Here, the second line 6 electrically leads out the part of the two bare dies that are stacked in parallel to the outside of the encapsulation. In the mounting and encapsulation step, if the output end of the bare die A1 is connected and stacked with the output end of the bare die B2, then the second line 6 electrically leads out the output end of the parallel circuit of the two bare dies to the outside of the encapsulation. If the input end of the bare die A1 is connected and stacked with the input end of the bare die B2, then the second line 6 electrically leads out the input end of the parallel circuit of the two bare dies to the outside of the encapsulation.

[0031] Through-hole 4 is etched through die B2 to die A1, and line 2 6 is electroplated to bring out the parallel circuit electrical properties. There is no need to horizontally pull this circuit electrical properties to the encapsulation material and then bring it out of the package body 9. This simplifies the process flow, reduces costs, and compresses the package space while encapsulating the same varistor size, thereby meeting the packaging requirements of small-size products. With the same package size, the package space can be utilized to the maximum extent, and larger varistors (such as thickness, diameter / side length) can be laid out, thereby further improving product performance.

[0032] Improving product performance is mainly reflected in: 1. The varistor voltage is the core of the varistor. In this invention, the bare die core is made of zinc oxide. Its grain boundary phase characteristics determine that the thickness of the bare die is strictly linearly positively correlated with the varistor voltage. The varistor voltage meets the standard, the overvoltage protection accuracy is high, and it is compatible with the designed circuit voltage level.

[0033] 2. Furthermore, the current-carrying capacity of a varistor is crucial for surge protection. The effective conductive area / heat dissipation area of ​​the bare die is proportional to the square of the die diameter / side length. Therefore, the diameter / side length directly determines the current-carrying capacity and thermal stability. When the die diameter / side length is matched, the product's current-carrying capacity meets the standards, allowing for rapid current discharge during surges. It also provides fast heat dissipation, prevents localized overheating, and ensures stable product performance.

[0034] The exposed bare die B2 has other copper-plated sections plated with corresponding line 3 7. Line 3 7 extends to the etched exposed end face of line 1 5, achieving electrical connection with line 1 5, and is electrically connected to bare die A1 through line 1 5. Line 3 7 electrically leads one end of the parallel circuit of bare die A1 and bare die B2 out of the encapsulation body. In the mounting and encapsulation step, if the output terminal of bare die A1 is connected to the output terminal of bare die B2, then line 3 7 electrically leads the input terminal of the parallel circuit of the two bare dies out of the encapsulation body; if the input terminal of bare die A1 is connected to the input terminal of bare die B2, then line 3 7 electrically leads the output terminal of the parallel circuit of the two bare dies out of the encapsulation body. The extension plated height of lines 2 6 and lines 3 7 on the surface of the encapsulation layer is consistent, and the surfaces of lines 2 6 and lines 3 7 are horizontal and flat (e.g., Figure 15 (As shown).

[0035] Using encapsulating material, continue encapsulation on top of encapsulation layer one, completely encapsulating line 2 (6) and line 3 (7) (e.g.) Figure 16 As shown), after the encapsulating material has cured, it is horizontally ground on the top surface of the encapsulation by mechanical grinding until the surfaces of line 2 6 and line 3 7 are exposed (as shown). Figure 17 As shown in the figure), encapsulation layer three (not shown in the figure) is formed. Encapsulation layer three and encapsulation layer one are encapsulated and cured into one whole. Encapsulation layer one, encapsulation layer two and encapsulation layer three are cured into a complete encapsulation whole.

[0036] In step 8 of the electroplating process, the exposed portions of line 2 6 and line 3 7 on the encapsulation layer 3 are further covered by the electroplated metal pins 8, which electrically lead out line 2 6 and line 3 7 at their respective positions (e.g., ...). Figure 18 As shown in the diagram, pins 8 lead out the output and input terminals of the two parallel stacked die circuits to the outside of the package. Pins 8 serve as the connection medium between the electrical circuitry in the external working environment of the package and the electrical circuitry of the die circuitry inside the package. The package uses solder paste or other soldering materials to fix pins 8 to the working area, achieving electrical connection. To ensure proper soldering and fixation of the product, the surface of each pin 8 is level and flat after electroplating, and the electroplating height of each pin 8 is the same. Each pin 8 is ultimately exposed to the package material. To protect the pins 8 and prevent corrosion, a protective layer, such as a nickel-gold plating layer or other commonly used materials, needs to be electroplated on the pins 8.

[0037] Finally, the process also includes a product cutting step. Since multiple bare wafers A1 and B2 are stacked on the substrate, and each process step in this invention forms the same structural layout on each stacked structure, the encapsulation assembly encapsulates multiple stacked structures of two bare wafers and their corresponding layouts. The encapsulation assembly is then vertically cut into the encapsulation material in the cutting channel area. The cutting channel is a space reserved in the actual product design stage; the cutting channel area contains no bare wafers or structural layouts, only the encapsulation material. The encapsulation is then separated into multiple product units. In this invention, each product unit contains a stacked structure and its corresponding structural layout; other stacked structures and their corresponding structural layouts are also within the scope of this invention. The encapsulation material of the separated product units forms the package 9 (e.g., ...). Figure 19 (As shown).

[0038] This invention involves etching a through-hole 4 through the bare die B2 to the bare die A1, and electroplating line 2 6 and line 3 7 to lead out the parallel circuit electrical properties. This simplifies the process flow, reduces costs, and compresses the packaging space while encapsulating the same size varistor, thereby meeting the packaging requirements of small-size products. Under the same package size, the packaging space can be utilized to the maximum extent, allowing for the placement of larger varistors, thereby further improving product performance.

[0039] The above-described packaging method can be flexibly adjusted according to actual conditions. This invention is not limited to the above-described process steps, and adjustments to the order of other steps are also within the scope of protection of this invention.

[0040] This invention involves stacking two bare dies, and other similar structures but with different numbers of parallel stacked dies are also within the scope of protection of this invention; at the same time, the bare dies are stacked with thermally conductive but non-conductive adhesive, and then the electrical properties are respectively led out to the outside of the package 9 to form a series structure, which is also within the scope of protection of this invention.

[0041] All encapsulation steps involved in the process of this invention use molding compounds, such as epoxy resin, cyanate ester, and polyimide. These materials are low in cost, have good curing performance, and are commonly used encapsulation methods in the field. Encapsulation technology plays an important role in the semiconductor manufacturing field, mainly in protecting chips, connecting the whole, supporting structures, improving reliability, and promoting technological progress. The encapsulation method in this invention is the commonly used molding injection molding method in the field, but other suitable encapsulation methods are also acceptable.

[0042] In all process steps of this invention involving the grinding of encapsulating material, a three-stage progressive grinding method of coarse grinding, fine grinding, and polishing can be used. First, coarse grinding is performed using low-grit diamond grinding discs or wheels to quickly remove most of the encapsulating material. Then, fine grinding is performed using high-grit diamond abrasive belts or sandpaper to remove scratches from the coarse grinding, gradually grinding down to the surface of the metal structure (such as the copper-clad surface of bare die A1, line 1 5, line 2 6, and line 3 7). Finally, polishing is performed using a polishing cloth. After grinding, the exposed metal structure is free of burrs, the chip is free of microcracks, and the surface is smooth. The degree of grinding can be selected according to the actual requirements of the product, and the above grinding process can be reasonably modified.

[0043] In all process steps of this invention involving electroplating, a photoresist film is first adhered, followed by photolithography techniques such as exposure and development to form an electroplating protection layer on the surface of the area. Areas not requiring electroplating are protected by the photoresist film, exposing the areas to be electroplated. Then, a metal seed layer is formed on the exposed areas to be electroplated using suitable methods such as sputtering or copper deposition. The metal seed layer is made of copper or other metals. The metal seed layer ensures the bonding strength between subsequent metal-to-metal and metal-to-encapsulating materials, while also providing a surface for conductive ion adhesion, ensuring the electroplating effect. The entire electroplating process and the materials used are common knowledge in the field. In the electroplating process of pin 8, line 1 5, line 2 6, and line 3 7 of this invention, the electroplated metal can be copper, and the protective layer can be a nickel-gold layer, but this invention does not limit this.

[0044] Based on the above-mentioned packaging method with exposed pin 8, a varistor packaging structure is obtained (e.g., Figure 20 As shown), this packaging structure can not only be obtained through the packaging methods described above; other packaging methods, processes, and technologies can also yield this packaging structure (such as...). Figure 20 (As shown), it is also within the protection scope of the structure. The packaging structure includes a package body 9, which encapsulates: The bare dies, bare dies A1 and bare dies B2 are stacked in parallel, one on top of the other. The double-sided copper core of bare die A1 is stacked in parallel with the double-sided copper core of bare die B2 through thermally and electrically conductive adhesive. The dies are cut and separated into multiple stacked structures of bare dies A1 and bare dies B2.

[0045] Line 5 is an electroplated circuit that connects to the bare die A1 after the groove 3 is etched inside the package 9. Line 5 electrically leads the bare die A1 out of the package 9.

[0046] Line 2 6 penetrates through the die B2 to the die A1 to form a via 4. During the etching of via 4, the effective area of ​​die B2 is avoided. During the etching of via 4, the exposed copper surface of die B2 is etched to form a cross section, cutting off the electrical connection between line 2 6 and the entire exposed copper surface of die B2. Line 2 6 is electroplated in via 4. Line 2 6 leads the parallel electrical connection between die A1 and die B2 to the outside of package 9.

[0047] Line 3 7 is electrically connected to Line 1 5, and another electrical connection of the parallel circuit of bare die A1 and bare die B2 is brought out to the outside of the package 9. Pins 8 are electroplated on Line 3 7 and Line 2 6, and pins 8 are electroplated on the outside of the package 9, respectively bringing out the electrical connections of Line 2 6 and Line 3 7 to the outside of the package 9.

[0048] This invention involves etching a through-hole 4 through the bare die B2 to the bare die A1, and electroplating line 2 6 and line 3 7 to lead out the parallel circuit electrical properties. This simplifies the process flow, reduces costs, and compresses the packaging space while encapsulating the same size varistor, thereby meeting the packaging requirements of small-size products. Under the same package size, the packaging space can be utilized to the maximum extent, allowing for the placement of larger varistors, thereby further improving product performance.

[0049] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this invention are within the protection scope of this invention.

Claims

1. A method for packaging a varistor, characterized in that, Includes the following steps: Mounting and encapsulation: Stack bare die A and bare die B in parallel, mount them on the substrate and encapsulate them, and grind the top surface of the encapsulation until the surface of bare die A is exposed; Etching and electroplating: Vertical etching of the encapsulating material forms a groove, and electroplating of line one within the groove extends to the surface of bare die A, continuing to encapsulate line one; Transformer etching: The encapsulation body is flipped up and down and remounted. The bare die B is flush with the encapsulation body and exposed. The bare die B is etched through to the bare die A to form a through hole. Line 2 is electroplated in the through hole and extends to the encapsulation body. Line 1 is connected to the bare die B through electroplated line 3. Line 2 and line 3 are encapsulated and polished to expose them. Electroplated leads: Electroplated leads are applied to exposed lines 2 and 3, the substrate is peeled off and cut into package product units.

2. The varistor packaging method according to claim 1, characterized in that, In the mounting and encapsulation step, the copper-clad core of bare die A is stacked in parallel with the copper-clad core of bare die B through thermally and electrically conductive adhesive, and then cut and separated into multiple sets of stacked structures of bare die A and bare die B, and then the stacked structures are mounted on the substrate.

3. The varistor packaging method according to claim 2, characterized in that, In the plate etching step, the etched vias avoid the effective area of ​​the bare die B.

4. The varistor packaging method according to claim 3, characterized in that, In the board etching step, during the via etching, the exposed copper surface of the die B is etched to form a cross section, severing the electrical connection between line 2 and the entire exposed copper surface of die B.

5. The varistor packaging method according to claim 1, characterized in that, In the aforementioned board etching step, the second line plated in the through hole leads the bare die A and bare die B in parallel to the pin, and then leads them out of the package body through the pin.

6. A varistor packaging structure, comprising a package body, characterized in that, The package contains: Bare dies, bare die A and bare die B are stacked in parallel, one on top of the other; Line 1 is a line that is electrically connected to the bare die A after etching grooves inside the package and electroplating. Line 1 electrically leads the bare die A out of the package. Line 2 is formed by etching through die B to die A to form a via. Line 2 is electroplated in the via and connects die A and die B in parallel to the package body. Line 3 is electrically connected to Line 1, and another electrical connection of the parallel circuit of die A and die B is brought out to the outside of the package.

7. The varistor packaging structure according to claim 6, characterized in that, The copper-clad core of die A is stacked in parallel with the copper-clad core of die B through thermally and electrically conductive adhesive, and then cut and separated into multiple stacked structures of die A and die B.

8. The varistor packaging structure according to claim 7, characterized in that, The via is etched away from the effective area of ​​die B.

9. The varistor packaging structure according to claim 8, characterized in that, During the etching of the via, the exposed copper surface of die B is etched to form a cross section, severing the electrical connection between line 2 and the entire exposed copper surface of die B.

10. The varistor packaging structure according to claim 6, characterized in that, The pins of Line 2 and Line 3 are electroplated and set outside the package, respectively, so that the electrical properties of Line 2 and Line 3 are brought out outside the package.

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