A circuit for improving ESD capability of RS485 interface chip
By introducing an ESD event detection circuit into the RS485 interface chip, splitting the NMOS transistor in the power output stage and monitoring the node signal on the sampling resistor, the problem of insufficient ESD protection capability when the bus port outputs a low level is solved, achieving higher ESD tolerance and robustness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HOPE MICROELECTRONICS CO LTD
- Filing Date
- 2026-04-09
- Publication Date
- 2026-06-26
AI Technical Summary
Existing RS485 interface chips have insufficient ESD protection when the bus port outputs a low level, which reduces the chip's robustness and increases the design difficulty.
An ESD event detection circuit is used to split the power output stage NMOS transistor into a main path and a secondary path. ESD events are monitored by detecting the node signal Vs on the sampling resistor. The control signal disconnects the NMOS transistor, so that the bus port enters a high-impedance state, ensuring that the ESD charge is discharged through the ESD protection device.
It significantly improves the ESD tolerance and robustness of the RS485 bus port, overcomes the negative impact of process deviations, voltage and temperature changes on the chip's electrostatic protection performance, and improves mass production consistency.
Smart Images
Figure CN122000849B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, specifically to a circuit for improving the ESD capability of RS485 interface chips. Background Technology
[0002] RS485 interface chips are widely used in automotive electronics, IoT, aerospace and other communication fields, mainly as interfaces for signal acquisition, transmission and remote communication. They need to support hot-swapping and meet high reliability communication requirements. To ensure the chip's operational stability in harsh environments, its electrostatic discharge (ESD) protection requirements are extremely high.
[0003] To systematically evaluate the ESD protection capabilities of electronic systems, the International Electrotechnical Commission (IEC) has established testing standards. Among these, IEC 61000-4-2 contact discharge and air discharge are the two most commonly used methods for ESD testing. For RS485 interface chips, the industry requires that their bus ports have ESD protection capabilities of ±15kV for contact discharge.
[0004] Currently, to achieve such a high level of ESD protection, only the silicon controlled rectifier (SCR) structure with the strongest discharge current capability can be used. Common ESD protection schemes for RS485 interface chips include... Figure 1 As shown.
[0005] The RS485 bus port operates within a voltage range of -7V to +12V. Therefore, the power output stage requires a stacked structure of diodes and MOSFETs, while the ESD protection device uses a bidirectional silicon controlled rectifier (SCR) structure (such as...). Figure 1 (As shown).
[0006] The ESD protection device is connected in parallel with the bus port. Its trigger voltage must be higher than the normal operating voltage of the bus port, but lower than the maximum withstand voltage of the chip's internal output circuit. When the chip is operating normally, the SCR will not trigger and will not affect the bus port. When an ESD event occurs at the bus port, for positive ESD charges, the instantaneous high voltage will cause the reverse-biased junction of NPN2 to undergo avalanche breakdown. The resulting charge carriers flow through the parasitic resistor Rpar2, turning on the parasitic transistor NPN2 and triggering a positive feedback between NPN2 and PNP. The SCR device enters the negative resistance region, forming a low-resistance path that can efficiently discharge ESD charges, thereby protecting the internal circuitry of the chip.
[0007] Circuit analysis revealed that the bus port's ESD protection is weakest when the port output is low. This occurs when the control signals EN=1 and Din=0. Figure 1In this chip, both the diode (Dion) and NMOS are in the ON state, forming a low-impedance discharge path between the bus port and ground. Positive ESD charges will be discharged through this path, potentially causing the SCR (Selective Catalytic Reduction) device to fail to trigger in time or even not trigger at all, thus damaging the internal circuitry of the chip. The trigger voltage of the SCR device is closely related to the device size, PN junction spacing, and doping concentration. However, process variations in these parameters during semiconductor manufacturing can cause changes in the SCR trigger voltage. Furthermore, considering the worst-case scenario for ESD protection, the on-resistance of the diode (Dion) and NMOS will also vary with process variations, power supply voltage, and temperature. These dual factors significantly reduce the chip's robustness.
[0008] Laboratory sampling tests showed that when a batch of RS485 chips were configured with high impedance bus port output, their ESD protection capability reached over ±15kV contact discharge. When another batch was configured with low impedance bus port output, the median ESD protection capability was ±15kV contact discharge, with a maximum of ±20kV, but a minimum of only ±10kV. Since the ESD protection capability of RS485 interface chips is determined by the minimum value under various test conditions, robustness issues can lead to a decrease in the chip's ESD protection parameters. This necessitates the design of higher-requirement ESD protection devices, thereby increasing the chip design complexity and product development cycle. Summary of the Invention
[0009] This invention aims to provide a circuit that improves the ESD capability of RS485 interface chips, ensuring that the ESD protection device SCR can be triggered in a timely manner to protect the internal circuitry of the chip. It can significantly improve the robustness of the chip and enhance its ESD protection parameters.
[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a circuit for improving the ESD capability of an RS485 interface chip, including an RS485 bus port, a power output stage, and an ESD protection device connected in parallel between the RS485 bus port and ground, and also including an ESD event detection circuit.
[0011] The power output stage includes a power diode Diop, a PMOS transistor, a power diode Dion, a first NMOS transistor NM1, and a second NMOS transistor NM2. The first NMOS transistor NM1 serves as the main path of the power output stage, and the second NMOS transistor NM2, connected in series with the sampling resistor Rs, serves as the secondary path of the power output stage and is connected to ground GND. The connection point between the second NMOS transistor NM2 and the sampling resistor Rs is defined as the node signal Vs.
[0012] The input terminal of the ESD event detection circuit is connected to the node signal Vs, and the output terminal is connected to the gate of the first NMOS transistor NM1 and the second NMOS transistor NM2 respectively.
[0013] When an ESD event is detected, the ESD event detection circuit outputs a control signal to disconnect the first NMOS transistor NM1 and the second NMOS transistor NM2, causing the RS485 bus port to enter a high-impedance state, forcing the ESD charge to be discharged through the ESD protection device.
[0014] Preferably, the size ratio of the first NMOS transistor NM1 and the second NMOS transistor NM2 is configured such that the first NMOS transistor NM1 outputs 95% of the current and the second NMOS transistor NM2 outputs 5% of the current.
[0015] Preferably, the ESD event detection circuit includes a first inverter Inv1, an RS latch, a D flip-flop, a second inverter Inv2, a third inverter Inv3, a fourth inverter Inv4, a NAND gate Nand2, a NOR gate Nor, and a delay unit.
[0016] The node signal Vs is connected to the input of the first inverter Inv1, and the output of the first inverter Inv1 is defined as the node signal Vrs1.
[0017] The node signal Vrs1 is connected to the first input terminal of the RS latch and also to the input terminal of the second inverter Inv2;
[0018] The output of the second inverter Inv2 is connected to the clock input Clk of the D flip-flop, and the data input D of the D flip-flop is connected to the power supply voltage VDD.
[0019] The output terminal Q of the D flip-flop is connected to the second input terminal of the RS latch and is defined as the node signal Vrs2.
[0020] The output of the RS latch is connected to the input of the third inverter Inv3, and the output of the third inverter Inv3 is defined as the node signal Vrso.
[0021] The node signal Vrso is connected to the first input terminal of the NAND gate Nand2, the second input terminal of the NAND gate Nand2 is connected to the enable control signal EN, and the output terminal of the NAND gate Nand2 is defined as the node signal Dctl; the node signal Dctl is connected to the first input terminal of the NOR gate Nor, the second input terminal of the NOR gate Nor is connected to the input signal Din, and the output terminal of the NOR gate Nor is defined as the node signal drvn;
[0022] The node signal drvn is connected to the gate of the first NMOS transistor NM1 and the second NMOS transistor NM2.
[0023] Preferably, the node signal Dctl is also connected to the input of the fourth inverter Inv4, the output of the fourth inverter Inv4 is connected to the input of the delay unit, the output of the delay unit is defined as the node signal Drst, and the node signal Drst is connected to the reset input Reset of the D flip-flop;
[0024] The reset input of the D flip-flop is active low.
[0025] Preferably, the resistance of the sampling resistor Rs is 70Ω;
[0026] The logic threshold voltage of the first inverter Inv1 is set to 2.1V, corresponding to a 5V power supply voltage condition.
[0027] The trigger current threshold for ESD events is set to 600mA.
[0028] Preferably, the ESD protection device is a bidirectional silicon controlled rectifier (SCR) structure;
[0029] The trigger voltage of the bidirectional thyristor SCR structure is higher than the normal operating voltage of the RS485 bus port and lower than the maximum withstand voltage of the chip's internal output circuit. Preferably, the delay unit is configured to delay the output signal of the fourth inverter Inv4 by 1µs after detecting an ESD event, and then output it to the node signal Drst to maintain the first NMOS transistor NM1 and the second NMOS transistor NM2 in the off state for 1µs.
[0030] Preferably, in normal operating mode, when the enable control signal EN=1 and the input signal Din=0, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, and the RS485 bus port outputs a low level.
[0031] If the RS485 bus port is experiencing a maximum operating current of 60mA, and the sampling current of the second NMOS transistor NM2 branch is 3mA, the voltage drop across the sampling resistor Rs will be 210mV. This voltage is much lower than the logic flip threshold voltage of the first inverter Inv1, and the node signal Vrs1 output remains at a high level, ensuring that normal operating current will not be falsely triggered as an ESD event.
[0032] Preferably, when an ESD event occurs and the instantaneous current exceeds 600mA, the instantaneous current in the branch of the second NMOS transistor NM2 flows through the sampling resistor Rs, generating a voltage greater than 2.1V on the node signal Vs. This causes the node signal Vrs1 to flip to a low level, which in turn causes the RS latch to flip, resulting in the output node signal Vrso being low, the node signal Dctl being high, and the node signal drvn being low, thereby disconnecting the first NMOS transistor NM1 and the second NMOS transistor NM2. After the second NMOS transistor NM2 is disconnected, the node signal Vs is pulled down to a low level by the resistor Rs. After passing through the first inverter Inv1, the node signal Vrs1 outputs a high level. Due to the delay unit, the node signal Drst will remain high for 1us, therefore the node signal Vrs2 is also high. The input signals of the RS latch are all high, and the output state remains unchanged for 1us, thus maintaining the disconnected state of the first NMOS transistor NM1 and the second NMOS transistor NM2. Preferably, after the ESD event ends and the delay time set by the delay unit has elapsed, the node signal Drst goes low to reset the D flip-flop, causing the node signal Vrs2 to go low, which in turn causes the node signal Vrso to return to a high level and the node signal Dctl to return to a low level. The outputs of the node signals drvn and drvp are then controlled again by the input signal Din, and the RS485 bus port returns to normal operation.
[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0034] This invention introduces an ESD event detection circuit. By splitting the power output stage NMOS transistors (main path NM1 and secondary path NM2) and monitoring the node signal Vs on the sampling resistor Rs, it can quickly output a control signal to forcibly shut down the first NMOS transistor NM1 and the second NMOS transistor NM2 when ESD electrostatic discharge occurs at the bus port. This causes the RS485 bus port to instantly enter a high-impedance state, thereby disconnecting a low-impedance discharge path for ESD positive charge to ground that exists in the prior art. This eliminates the hidden danger of ESD protection devices (SCRs) being difficult to trigger or having delayed triggering, ensuring that all ESD charge is reliably discharged by the SCR. It effectively overcomes the negative impact of process deviations, voltage and temperature changes on the chip's electrostatic protection performance, and significantly improves the ESD tolerance, robustness and mass production consistency of the interface chip's bus port. Attached Figure Description
[0035] Figure 1 This is a circuit diagram of an RS485 bus port in the prior art;
[0036] Figure 2 This is a circuit diagram of the RS485 bus port in this invention;
[0037] Figure 3 This is a circuit diagram of the ESD event detection circuit in this invention. Detailed Implementation
[0038] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.
[0039] like Figures 2-3 As shown, the present invention proposes a circuit to improve the ESD capability of an RS485 interface chip, including an RS485 bus port, a power output stage, and an ESD protection device connected in parallel between the RS485 bus port and ground, and also includes an ESD event detection circuit.
[0040] The power output stage includes a power diode Diop, a PMOS transistor, a power diode Dion, a first NMOS transistor NM1, and a second NMOS transistor NM2. The first NMOS transistor NM1 serves as the main path of the power output stage, and the second NMOS transistor NM2, connected in series with a sampling resistor Rs, serves as a secondary path of the power output stage connected to ground GND. The connection point between the second NMOS transistor NM2 and the sampling resistor Rs is defined as the node signal Vs. The input terminal of the ESD event detection circuit is connected to the node signal Vs, and the output terminal is connected to the gates of the first NMOS transistor NM1 and the second NMOS transistor NM2, respectively.
[0041] When an ESD event is detected, the ESD event detection circuit outputs a control signal to disconnect the first NMOS transistor NM1 and the second NMOS transistor NM2, causing the RS485 bus port to enter a high-impedance state, forcing the ESD charge to be discharged through the ESD protection device.
[0042] In this invention, the NMOS of the power output stage of the RS485 bus port is split into two parts. NMOS NM1 is the main path of the power output stage, outputting 95% of the current. NMOS NM2 and the sampling resistor Rs are connected in series to GND to form the secondary path of the power output stage, outputting 5% of the current.
[0043] Specifically, the ESD event detection circuit includes a first inverter Inv1, an RS latch, a D flip-flop, a second inverter Inv2, a third inverter Inv3, a fourth inverter Inv4, a NAND gate Nand2, a NOR gate Nor, and a delay unit.
[0044] The node signal Vs is connected to the input terminal of the first inverter Inv1, and the output terminal of the first inverter Inv1 is defined as the node signal Vrs1; the node signal Vrs1 is connected to the first input terminal of the RS latch, and also to the input terminal of the second inverter Inv2.
[0045] The output of the second inverter Inv2 is connected to the clock input Clk of the D flip-flop, and the data input D of the D flip-flop is connected to the power supply voltage VDD; the output Q of the D flip-flop is connected to the second input of the RS latch and is defined as the node signal Vrs2.
[0046] The output of the RS latch is connected to the input of the third inverter Inv3, and the output of the third inverter Inv3 is defined as the node signal Vrso. The node signal Vrso is connected to the first input of the NAND gate Nand2, and the second input of the NAND gate Nand2 is connected to the enable control signal EN. The output of the NAND gate Nand2 is defined as the node signal Dctl. The node signal Dctl is connected to the first input of the NOR gate Nor, and the second input of the NOR gate Nor is connected to the input signal Din. The output of the NOR gate Nor is defined as the node signal drvn. The node signal drvn is connected to the gate of the first NMOS transistor NM1 and the second NMOS transistor NM2.
[0047] The node signal Dctl is also connected to the input of the fourth inverter Inv4. The output of the fourth inverter is connected to the input of the delay unit. The output of the delay unit is defined as the node signal Drst. The node signal Drst is connected to the reset input Reset of the D flip-flop. The reset input Reset of the D flip-flop is active low.
[0048] The resistance of the sampling resistor Rs is 70Ω; the logic threshold voltage of the first inverter Inv1 is set to 2.1V, corresponding to a 5V power supply voltage; and the trigger current threshold for the ESD event is set to 600mA.
[0049] The ESD protection device is a bidirectional silicon controlled rectifier (SCR) structure; the trigger voltage of the bidirectional SCR structure is higher than the normal operating voltage of the RS485 bus port and lower than the maximum withstand voltage of the chip's internal output circuit.
[0050] The delay unit is configured to delay the output signal of the fourth inverter Inv4 by 1µs after detecting an ESD event, and then output it to the node signal Drst to maintain the first NMOS transistor NM1 and the second NMOS transistor NM2 in the off state for 1µs.
[0051] In one embodiment, under normal operating mode, when the enable control signal EN=1 and the input signal Din=0, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, and the RS485 bus port outputs a low level.
[0052] If the RS485 bus port is experiencing a maximum operating current of 60mA, and the sampling current of the second NMOS transistor NM2 branch is 3mA, the voltage drop across the sampling resistor Rs will be 210mV. This voltage is much lower than the logic flip threshold voltage of the first inverter Inv1, and the node signal Vrs1 output remains at a high level, ensuring that normal operating current will not be falsely triggered as an ESD event.
[0053] In one embodiment, when an ESD event occurs and the instantaneous current exceeds 600mA, the instantaneous current of the second NMOS transistor NM2 branch flows through the sampling resistor Rs, generating a voltage greater than 2.1V on the node signal Vs. This causes the node signal Vrs1 to flip to a low level, which in turn causes the RS latch to flip, outputting the node signal Vrso to a low level, the node signal Dctl to a high level, and the node signal drvn to a low level, thereby disconnecting the first NMOS transistor NM1 and the second NMOS transistor NM2. After the second NMOS transistor NM2 is disconnected, the node signal Vs is pulled down to a low level by the resistor Rs. After passing through the first inverter Inv1, the node signal Vrs1 outputs a high level. Due to the delay unit, the node signal Drst remains high for 1µs, the node signal Vrs2 is also high, and the input signals of the RS latch are all high. The output state remains unchanged for 1µs, thereby maintaining the disconnected state of the first NMOS transistor NM1 and the second NMOS transistor NM2.
[0054] In one embodiment, after the ESD event ends and the delay time set by the delay unit has elapsed, the node signal Drst goes low to reset the D flip-flop, causing the node signal Vrs2 to go low, which in turn causes the node signal Vrso to return to a high level and the node signal Dctl to return to a low level. The outputs of the node signals drvn and drvp are then controlled again by the input signal Din, and the RS485 bus port returns to normal operation.
[0055] Specifically, the working principle of this invention is as follows:
[0056] The ESD event detection circuit determines whether an ESD event has occurred at the bus port by detecting the current in the NMOS NM2 branch. Under normal operating conditions, the maximum drive current of RS485 is typically 60mA. Considering variations in chip process parameters, power supply voltage, operating temperature, and bus load, and to prevent false triggering during normal operation, a safety margin of 10 is considered, and the trigger current for the ESD event is set to 600mA. The design uses Rs=70Ω, and the size ratio of NMOS NM1 and NM2 is adjusted so that the sampling current of the NM2 branch is 5% of the total bus port current. The logic threshold voltage of the first inverter Inv1 is 2.1V (under a 5V power supply).
[0057] The ESD event detection circuit can only be triggered when an ESD event occurs at the bus port and should not affect the normal operation of the chip. First, let's analyze the situation when no ESD event occurs. When the chip is disabled (EN=0), node signals Dctl=1, drvn=0, drvp=1, and PMOS, NMOS NM1, and NM2 are all off, resulting in a high-impedance state at the bus port. At this time, node signals Vs=0, Vrs1=1, Vrs2=0, and Vrso=1. When the chip is enabled (EN=1), Vrso remains high, node signal Dctl=0, and the outputs of node signals drvn and drvp are controlled by the input signal Din. When Din=1, drvn=0, and drvp=0, the PMOS is on, the NMOS is off, and the bus port output is 1. When Din=0, drvn=1, and drvp=1, the PMOS is off, the NMOS is on, and the bus port output is 0. When the bus output maximum operating current is 60mA, the sampling current of the NM2 branch is approximately 3mA, resulting in a voltage drop of 210mV across the sampling resistor Rs. This voltage is significantly lower than the logic toggle threshold voltage of the first inverter Inv1 (2.1V), providing a substantial safety margin and preventing false triggering. Node signals Vrs1=1, Vrso=1, Dctl=0, and the logic of node signals drvn and drvp is still controlled by the input signal Din.
[0058] With EN=1 and Din=0, the bus port output is low, resulting in the weakest ESD protection. When an ESD event occurs at the bus port, the ESD charge will be discharged to GND through the power diode Dion, the main branch of NMOS NM1, and the secondary branch of NM2. When the instantaneous ESD current exceeds 600mA, an instantaneous current of approximately 30mA will flow through the secondary branch of NM2, generating an instantaneous voltage greater than 2.1V on the node signal Vs. After passing through the first inverter Inv1, the node signal Vrs1=0, causing the RS latch logic to flip, resulting in node signals Vrso=0, Dctl=1, and drvn=0. This disconnects NMOS NM1 and NM2, causing the bus port to enter a high-impedance state where both PMOS and NMOS are off.
[0059] At this moment, the ESD voltage at the bus port will rise sharply. When it exceeds the trigger voltage of the SCR (Silicon Controlled Rectifier), the ESD charge will be discharged to GND through the low-resistance path of the SCR, thus protecting the internal circuitry of the chip. An ESD event is a transient process, typically lasting between tens and hundreds of nanoseconds. Therefore, when an ESD event occurs, the bus port will remain in a high-resistance state for a period of time after the NMOS is disconnected.
[0060] This invention maintains the bus port in a high-impedance state for approximately 1µs by inserting a delay unit before the node signal Drst, ensuring complete ESD charge discharge. Its working principle is as follows:
[0061] When an ESD event is triggered, the detection circuit sets node signals Dctl=1 and drvn=0, disconnects the NMOS, and the bus port is in a high-impedance state. Due to the delay unit, the node signal Drst is delayed by 1µs before going low, meaning the D flip-flop needs a 1µs delay before being reset. Therefore, the second input of the latch, Vrs2, will remain high for 1µs before being reset to low. After NMOS NM2 is disconnected, the node signal Vs is pulled low by resistor Rs, so the first input of the latch, Vrs1, is 1. Both inputs of the latch are 1, and the output state remains unchanged for 1µs. Therefore, the logic state of node signals Vrso=0, Dctl=1, and drvn=0 will be maintained for 1µs, thus disconnecting both NMOS NM1 and NM2, ensuring the bus port is in a high-impedance state for 1µs. Because of the parasitic capacitance between the bus port and ground, the brief 1µs high-impedance state will not change its logic state. After a 1µs delay, node signals Drst=0, Vrs2=0, Vrso=1, and Dctl=0. The outputs of node signals drvn and drvp are controlled by the input signal Din. The bus port returns to its normal operating state.
[0062] In summary, this invention adds an ESD event detection circuit, avoiding the worst operating conditions of the bus port, enabling the SCR protection device to be triggered more stably by ESD events, significantly improving the chip's robustness and enhancing its ESD protection capability.
[0063] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.
Claims
1. A circuit for improving the ESD capability of an RS485 interface chip, comprising an RS485 bus port, a power output stage, and an ESD protection device connected in parallel between the RS485 bus port and ground, characterized in that, It also includes ESD event detection circuitry; The power output stage includes a power diode Diop, a PMOS transistor, a power diode Dion, a first NMOS transistor NM1, and a second NMOS transistor NM2. The first NMOS transistor NM1 serves as the main path of the power output stage, and the second NMOS transistor NM2, connected in series with the sampling resistor Rs, serves as the secondary path of the power output stage and is connected to ground GND. The connection point between the second NMOS transistor NM2 and the sampling resistor Rs is defined as the node signal Vs. In this configuration, the anode of the power diode Diop is connected to the power supply VDD, the cathode is connected to the source of the PMOS transistor, the drain of the PMOS transistor is connected to the anode of the power diode Dion, and the cathode of the power diode Dion is connected to the drain of the first NMOS transistor NM1 and the second NMOS transistor NM2, respectively. The connection point between the drain of the PMOS transistor and the power diode Dion outputs a bus port. The gate of the PMOS transistor is connected to the output of the NAND gate Nand1, the first input of the NAND gate Nand1 is connected to the enable control signal EN, and the second input is connected to the input signal Din. The gate of the first NMOS transistor NM1 is connected to the node signal drvn, and the source is connected to GND. The input terminal of the ESD event detection circuit is connected to the node signal Vs, and the output terminal is connected to the gate of the first NMOS transistor NM1 and the second NMOS transistor NM2 respectively. When an ESD event is detected, the ESD event detection circuit outputs a control signal to disconnect the first NMOS transistor NM1 and the second NMOS transistor NM2, causing the RS485 bus port to enter a high-impedance state, forcing the ESD charge to be discharged through the ESD protection device. The ESD event detection circuit includes a first inverter Inv1, an RS latch, a D flip-flop, a second inverter Inv2, a third inverter Inv3, a fourth inverter Inv4, a NAND gate Nand2, a NOR gate Nor, and a delay unit. The node signal Vs is connected to the input of the first inverter Inv1, and the output of the first inverter Inv1 is defined as the node signal Vrs1. The node signal Vrs1 is connected to the first input terminal of the RS latch and also to the input terminal of the second inverter Inv2; The output of the second inverter Inv2 is connected to the clock input Clk of the D flip-flop, and the data input D of the D flip-flop is connected to the power supply voltage VDD. The output terminal Q of the D flip-flop is connected to the second input terminal of the RS latch and is defined as the node signal Vrs2. The output of the RS latch is connected to the input of the third inverter Inv3, and the output of the third inverter Inv3 is defined as the node signal Vrso. The node signal Vrso is connected to the first input terminal of the NAND gate Nand2, the second input terminal of the NAND gate Nand2 is connected to the enable control signal EN, and the output terminal of the NAND gate Nand2 is defined as the node signal Dctl; the node signal Dctl is connected to the first input terminal of the NOR gate Nor, the second input terminal of the NOR gate Nor is connected to the input signal Din, and the output terminal of the NOR gate Nor is defined as the node signal drvn; The node signal drvn is connected to the gate of the first NMOS transistor NM1 and the second NMOS transistor NM2; The node signal Dctl is also connected to the input of the fourth inverter Inv4. The output of the fourth inverter Inv4 is connected to the input of the delay unit. The output of the delay unit is defined as the node signal Drst. The node signal Drst is connected to the reset input Reset of the D flip-flop. The reset input Reset of the D flip-flop is active low.
2. The circuit for improving the ESD capability of an RS485 interface chip according to claim 1, characterized in that, The size ratio of the first NMOS transistor NM1 and the second NMOS transistor NM2 is configured such that the first NMOS transistor NM1 outputs 95% of the current and the second NMOS transistor NM2 outputs 5% of the current.
3. The circuit for improving the ESD capability of an RS485 interface chip according to claim 1, characterized in that, The resistance of the sampling resistor Rs is 70Ω; The logic threshold voltage of the first inverter Inv1 is set to 2.1V, corresponding to a 5V power supply voltage condition. The trigger current threshold for ESD events is set to 600mA.
4. The circuit for improving the ESD capability of an RS485 interface chip according to claim 1, characterized in that, The ESD protection device is a bidirectional silicon controlled rectifier (SCR) structure. The trigger voltage of the bidirectional thyristor SCR structure is higher than the normal operating voltage of the RS485 bus port, but lower than the maximum withstand voltage of the chip's internal output circuit.
5. The circuit for improving the ESD capability of an RS485 interface chip according to claim 1, characterized in that, The delay unit is configured to delay the output signal of the fourth inverter Inv4 by 1µs after detecting an ESD event, and then output it to the node signal Drst to maintain the first NMOS transistor NM1 and the second NMOS transistor NM2 in the off state for 1µs.
6. The circuit for improving the ESD capability of an RS485 interface chip according to claim 1, characterized in that, In normal operating mode, when the enable control signal EN=1 and the input signal Din=0, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, and the RS485 bus port outputs a low level. If the RS485 bus port is experiencing a maximum operating current of 60mA, and the sampling current of the second NMOS transistor NM2 branch is 3mA, the voltage drop across the sampling resistor Rs will be 210mV. This voltage is much lower than the logic flip threshold voltage of the first inverter Inv1, and the node signal Vrs1 output remains at a high level, ensuring that normal operating current will not be falsely triggered as an ESD event.
7. The circuit for improving the ESD capability of an RS485 interface chip according to claim 1, characterized in that, When an ESD event occurs and the instantaneous current exceeds 600mA, the instantaneous current of the second NMOS transistor NM2 branch flows through the sampling resistor Rs, generating a voltage greater than 2.1V on the node signal Vs. This causes the node signal Vrs1 to flip to a low level, which in turn causes the RS latch to flip, resulting in the output node signal Vrso being low, the node signal Dctl being high, and the node signal drvn being low, thereby disconnecting the first NMOS transistor NM1 and the second NMOS transistor NM2. After the second NMOS transistor NM2 is disconnected, the node signal Vs is pulled down to a low level by the resistor Rs. After passing through the first inverter Inv1, the node signal Vrs1 outputs a high level. Due to the effect of the delay unit, the node signal Drst will remain high for 1us, and the node signal Vrs2 will also be high. The input signals of the RS latch are all high, and the output state remains unchanged for 1us, thereby maintaining the disconnected state of the first NMOS transistor NM1 and the second NMOS transistor NM2.
8. The circuit for improving the ESD capability of an RS485 interface chip according to claim 1, characterized in that, When the ESD event ends and the delay time set by the delay unit has elapsed, the node signal Drst goes low to reset the D flip-flop, causing the node signal Vrs2 to go low, which in turn causes the node signal Vrso to return to high and the node signal Dctl to return to low. The outputs of the node signals drvn and drvp are then controlled again by the input signal Din, and the RS485 bus port returns to normal operation. The node signal drvp is the output of the NAND gate Nand1, used to control the PMOS transistor to turn on or off.