Comparison circuit performing comparator offset calibration and method of operating comparison circuit

Abstract

A comparison circuit performing comparator offset calibration and a method of operating the comparison circuit are provided. The comparison circuit comprises a comparator and a multiplexer. The comparator includes at least one transistor, and generates a first output signal based on a first input signal, a second input signal, and an operation clock signal. The multiplexer outputs a first clock signal as an operation clock signal based on the control signal in a normal mode, and outputs a second clock signal different from the first clock signal as the operation clock signal based on the control signal in an offset calibration mode. In the offset calibration mode, the comparison circuit is configured to perform an offset calibration operation by degenerating at least one transistor based on first and second input signals having the same voltage level and an operation clock signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0157958, filed on November 8, 2024, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to a comparator circuit for performing comparator offset calibration and a method for operating the comparator circuit. Background Technology

[0004] Comparators that generate an output signal indicating the comparison result by comparing input signals can be used in a variety of applications. For example, an analog-to-digital converter (ADC) for converting analog signals to digital signals may include multiple comparators and generate a digital signal by encoding the output signals from the multiple comparators. For example, a switching regulator may include a comparator for comparing a feedback signal with a reference signal.

[0005] The performance and efficiency of an application can depend on the characteristics of the comparator, such as power consumption, operating speed, noise properties, area, and accuracy, and some characteristics of the comparator can be traded off. Therefore, it may be difficult to achieve a comparator that has better characteristics in all aspects. Summary of the Invention

[0006] At least one example embodiment of this disclosure provides a comparator circuit capable of efficiently performing comparator offset calibration.

[0007] At least one example embodiment of this disclosure provides a method for operating a comparison circuit.

[0008] According to an example embodiment, a comparison circuit includes a comparator and a multiplexer. The comparator includes at least one transistor and is configured to generate a first output signal based on a first input signal, a second input signal, and an operating clock signal. The multiplexer is configured to output the first clock signal as an operating clock signal based on a control signal in a normal mode, and to output a second clock signal, different from the first clock signal, as an operating clock signal based on a control signal in an offset calibration mode. In the offset calibration mode, the comparator circuit is configured to perform an offset calibration operation by degrading at least one transistor based on the first and second input signals having the same voltage level and the operating clock signal.

[0009] According to an example embodiment, a method for operating a comparator circuit including at least one transistor includes determining whether the operating mode of the comparator circuit is an offset calibration mode or a normal mode; when the operating mode of the comparator circuit is an offset calibration mode, performing an offset calibration operation by degrading at least one transistor based on a first input signal and a second input signal having the same voltage level and an operating clock signal; and when the operating mode of the comparator circuit is a normal mode, performing a normal operation based on a first input signal and a second input signal having different voltage levels and an operating clock signal.

[0010] According to an example embodiment, a comparison circuit includes a comparator and a multiplexer. The comparator includes at least one transistor and is configured to generate a first output signal based on a first input signal, a second input signal, and an operating clock signal. The multiplexer is configured to output the first clock signal as an operating clock signal based on a control signal in a normal mode, and to output a second clock signal, different from the first clock signal, as an operating clock signal based on a control signal in an offset calibration mode. The comparator includes a first p-channel metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first n-channel metal-oxide-semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The first PMOS transistor and the second PMOS transistor are connected in parallel between a terminal from which a power supply voltage is applied and a terminal from which the first output signal is output. The first PMOS transistor includes a gate terminal connected to the terminal from which the operating clock signal is input. The second PMOS transistor includes a gate terminal connected to the terminal from which the second output signal is output. The third PMOS transistor and the fourth PMOS transistor are connected in parallel between the terminal from which a power supply voltage is applied and the terminal from which the second output signal is output. The third PMOS transistor includes a gate terminal connected to the terminal from which the first output signal is output. The fourth PMOS transistor includes a gate terminal connected to the terminal from which an operating clock signal is input. The first NMOS transistor and the second NMOS transistor are connected in series between the terminal from which the second output signal is output and the first node. The first NMOS transistor includes a gate terminal connected to the terminal from which the first output signal is output. The second NMOS transistor includes a gate terminal connected to the terminal from which the first input signal is input. The third NMOS transistor and the fourth NMOS transistor are connected in series between the terminal from which the first output signal is output and the first node. The third NMOS transistor includes a gate terminal connected to the terminal from which the second output signal is output. The fourth NMOS transistor includes a gate terminal connected to the terminal from which the second input signal is input. The fifth NMOS transistor is connected between the first node and the ground node and includes a gate terminal connected to the terminal from which an operating clock signal is input.

[0011] In the comparison circuit and method of operating the comparison circuit according to the example embodiment, comparator offset calibration can be performed by degrading at least one transistor in the comparator included in the comparison circuit. For example, comparator offset calibration can be performed by degrading a transistor in the comparator without additional circuit configuration. Therefore, comparator offset calibration can be performed efficiently without increasing the load on the circuit. Attached Figure Description

[0012] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 This is a block diagram illustrating a comparison circuit according to an example embodiment.

[0014] Figure 2 This is a block diagram illustrating a comparison circuit according to an example embodiment.

[0015] Figure 3 This illustrates the inclusion of examples according to the embodiment. Figure 1 A circuit diagram of an example comparator in a comparison circuit.

[0016] Figure 4A and Figure 4B It is used to describe according to the example embodiments Figure 3 The circuit diagram for the operation of the comparator.

[0017] Figure 5A It is used to describe according to the example embodiments Figure 3 The timing diagram of the comparator's operation in normal mode.

[0018] Figure 5B It is used to describe according to the example embodiments Figure 4A Timing diagram of the comparator operation in offset calibration mode.

[0019] Figure 5C It is used to describe according to the example embodiments Figure 4B Timing diagram of the comparator operation in offset calibration mode.

[0020] Figure 6 This is a diagram showing the simulation results of the comparison circuit according to an example embodiment.

[0021] Figure 7 This illustrates the inclusion of examples according to the embodiment. Figure 1 A circuit diagram of an example comparator in a comparison circuit.

[0022] Figure 8A and Figure 8B It is used to describe according to the example embodiments Figure 7 The circuit diagram for the operation of the comparator.

[0023] Figure 9 This is a flowchart illustrating a method of operating a comparison circuit according to an example embodiment.

[0024] Figure 10 This is a flowchart illustrating an example of performing normal operation in a method of operating a comparison circuit according to an example embodiment.

[0025] Figure 11 This is a flowchart illustrating an example of performing an offset calibration operation in a method of operating a comparison circuit according to an example embodiment.

[0026] Figure 12 This is a flowchart illustrating a method of operating a comparison circuit according to an example embodiment.

[0027] Figure 13 This is a block diagram illustrating a memory device according to an example embodiment.

[0028] Figure 14 This is a block diagram illustrating an electronic system according to an example embodiment.

[0029] Figure 15 This is a block diagram illustrating an integrated circuit according to an example embodiment. Detailed Implementation

[0030] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, which illustrate embodiments. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0031] Figure 1 This is a block diagram illustrating a comparison circuit according to an example embodiment.

[0032] refer to Figure 1 The comparison circuit 10 includes a comparator 100 and a multiplexer 200.

[0033] Comparator 100 includes at least one transistor and generates a first output signal OS1 based on a first input signal IS1, a second input signal IS2, and an operating clock signal OCK. For example, as referenced... Figure 3 As described above, comparator 100 may include a plurality of p-channel metal-oxide-semiconductor (PMOS) transistors and a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors.

[0034] Comparator 100 can receive a first input signal IS1 and a second input signal IS2, and output a first output signal OS1. The logic level of the first output signal OS1 varies depending on which of the first input signal IS1 and the second input signal IS2 has a higher level.

[0035] For example, when the first input signal IS1 has a higher level than the second input signal IS2, comparator 100 can output a first output signal OS1 with a logic high level. For example, when the second input signal IS2 has a higher level than the first input signal IS1, comparator 100 can output a first output signal OS1 with a logic low level.

[0036] However, the example embodiment is not limited thereto, and when the first input signal IS1 has a level higher than the second input signal IS2, the comparator 100 can output a first output signal OS1 with a logic low level, and when the second input signal IS2 has a level higher than the first input signal IS1, the comparator 100 can output a first output signal OS1 with a logic high level.

[0037] The multiplexer 200 selects one of the first clock signal CK1 and the second clock signal CK2 based on the control signal CTRL, and outputs the selected clock signal as the operation clock signal OCK.

[0038] The comparator circuit 10 according to the example embodiment operates in a normal mode and an offset calibration mode. The normal mode indicates that the comparator circuit 10 operates based on a first clock signal CK1 having a relatively high frequency, and the first output signal OS1 is output based on whichever of the first input signal IS1 and the second input signal IS2 has a higher level. For example, normal operation can be performed in the normal mode. The offset calibration mode indicates that the comparator circuit 10 operates based on a second clock signal CK2 having a relatively low frequency, and the first input signal IS1 and the second input signal IS2, having the same voltage level, are applied to perform an offset calibration operation by degrading at least one transistor.

[0039] For example, the frequency of the first clock signal CK1 can be a high frequency with a unit of gigahertz (GHZ), and the frequency of the second clock signal CK2 can be a low frequency with a unit of kilohertz (KHZ) or megahertz (MHZ).

[0040] For example, an offset calibration operation can be performed in offset calibration mode during the manufacturing process of the comparison circuit 10, and a normal operation can be performed in normal mode after the manufacturing process of the comparison circuit 10. However, the example embodiment is not limited to this, and the offset calibration operation can be performed after the manufacturing process of the comparison circuit 10.

[0041] In normal mode, multiplexer 200 selects the first clock signal CK1 from the first clock signal CK1 and the second clock signal CK2 based on the control signal CTRL, and outputs the first clock signal CK1 as the operation clock signal OCK. For example, when the control signal CTRL has a logic low level, multiplexer 200 can determine that the current operation mode is normal mode and output the first clock signal CK1 as the operation clock signal OCK.

[0042] In offset calibration mode, multiplexer 200 selects the second clock signal CK2 based on the control signal CTRL (first clock signal CK1 and second clock signal CK2) and outputs the second clock signal CK2 as the operation clock signal OCK. For example, multiplexer 200 can determine that the current mode is offset calibration mode when the control signal CTRL has a logic high level and output the second clock signal CK2 as the operation clock signal OCK.

[0043] However, the example embodiment is not limited thereto, and in normal mode, when the control signal CTRL has a logic high level, the multiplexer 200 can output a first clock signal CK1 as an operation clock signal OCK, and in offset calibration mode, when the control signal CTRL has a logic low level, the multiplexer 200 can output a second clock signal CK2 as an operation clock signal OCK.

[0044] Comparators can be used when converting analog signals to digital signals. To operate comparators according to a high-speed clock signal, multiple comparators can be arranged in parallel. However, because the offsets occurring between the comparators are different, the signal margin may be reduced.

[0045] Conventionally, an offset calibration circuit is added to calibrate the offset that occurs between comparators. Adding an offset calibration circuit can increase the circuit's load, which may degrade its characteristics and potentially cause hardware area issues.

[0046] In the comparator circuit 10 according to the example embodiment, comparator offset calibration can be performed by degrading the transistors in comparator 100 without the need for additional offset calibration circuitry. Therefore, comparator offset calibration can be performed efficiently without increasing the circuit load.

[0047] Figure 2 This is a block diagram illustrating a comparison circuit according to an example embodiment.

[0048] refer to Figure 2 ,and Figure 1 Compared to comparator circuit 10, comparator circuit 10a may also include switch 300. For the sake of brevity, the following will omit the references to switch 10. Figure 1The description is repetitive or overlapping.

[0049] In some example embodiments, switch 300 may be connected between the first input signal IS1 and the second input signal IS2. For example, switch 300 may be connected between the input terminal receiving the first input signal IS1 and the input terminal receiving the second input signal IS2.

[0050] In some example embodiments, switch 300 can be open in normal mode and closed in offset calibration mode based on the control signal CTRL. For example, switch 300 can be open when the control signal CTRL is logic high and closed when the control signal CTRL is logic low. However, the example embodiments are not limited to this, and switch 300 can be open when the control signal CTRL is logic low and closed when the control signal CTRL is logic high.

[0051] In some example embodiments, switch 300 may include a transistor having a gate terminal to which a control signal CTRL is applied. For example, switch 300 may be open when the transistor is turned off based on the control signal CTRL, and may be closed when the transistor is turned on based on the control signal CTRL.

[0052] In some example embodiments, when switch 300 is open based on control signal CTRL, the first input signal IS1 and the second input signal IS2 may have different voltage levels. When switch 300 is closed based on control signal CTRL, the first input signal IS1 and the second input signal IS2 may have the same voltage level.

[0053] In some example embodiments, switch 300 and multiplexer 200 can simultaneously receive the control signal CTRL. For example, in normal mode, when the control signal CTRL has a logic high level, switch 300 can be open, allowing the first input signal IS1 and the second input signal IS2 with different voltage levels to be received, and multiplexer 200 can output a first clock signal CK1 as the operation clock signal OCK. For example, in offset calibration mode, when the control signal CTRL has a logic low level, switch 300 can be closed, causing the first input signal IS1 and the second input signal IS2 to have the same voltage level, and multiplexer 200 can output a second clock signal CK2 as the operation clock signal OCK.

[0054] although Figure 2An example is shown where switch 300 is connected between the input terminals of comparator 100, but the example embodiment is not limited thereto. For example, comparator circuit 10a may also include a buffer in front of comparator 100, and switch 300 may be connected between the input terminals of the buffer.

[0055] although Figure 2 The example shows a case where the first input signal IS1 and the second input signal IS2 are controlled by switch 300, but the example embodiment is not limited to this, and the first input signal IS1 and the second input signal IS2 can be controlled by a voltage source without switch 300.

[0056] In the example embodiment, the offset calibration operation can be performed in offset calibration mode during the manufacturing process of the comparison circuit 10a, and normal operation can be performed in normal mode after the manufacturing process of the comparison circuit 10a. However, the example embodiment is not limited to this, and the offset calibration operation can also be performed after the manufacturing process of the comparison circuit 10a.

[0057] Figure 3 This illustrates the inclusion of examples according to the embodiment. Figure 1 A circuit diagram of an example comparator in a comparison circuit.

[0058] refer to Figure 3 The comparator 100a may include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5.

[0059] The first PMOS transistor MP1 may include a source terminal connected to a terminal from which a first power supply voltage VDD1 is applied, a drain terminal connected to a terminal from which a first output signal OS1 is output, and a gate terminal connected to a terminal from which an operating clock signal OCK is input.

[0060] The second PMOS transistor MP2 may include a source terminal connected to a terminal from which a first power supply voltage VDD1 is applied, a drain terminal connected to a terminal from which a first output signal OS1 is output, and a gate terminal connected to a terminal from which a second output signal OS2 is output.

[0061] The third PMOS transistor MP3 may include a source terminal connected to a terminal from which a first power supply voltage VDD1 is applied, a drain terminal connected to a terminal from which a second output signal OS2 is output, and a gate terminal connected to a terminal from which a first output signal OS1 is output.

[0062] The fourth PMOS transistor MP4 may include a source terminal connected to a terminal from which a first power supply voltage VDD1 is applied, a drain terminal connected to a terminal from which a second output signal OS2 is output, and a gate terminal connected to a terminal from which an operating clock signal OCK is input.

[0063] The first PMOS transistor MP1 and the second PMOS transistor MP2 can be connected in parallel between the terminal where the first power supply voltage VDD1 is applied and the terminal from which the first output signal OS1 is output. The third PMOS transistor MP3 and the fourth PMOS transistor MP4 can be connected in parallel between the terminal where the first power supply voltage VDD1 is applied and the terminal from which the second output signal OS2 is output.

[0064] The first NMOS transistor MN1 may include a drain terminal connected to the terminal from which the second output signal OS2 is output, a source terminal connected to the drain terminal of the second NMOS transistor MN2, and a gate terminal connected to the terminal from which the first output signal OS1 is output.

[0065] The second NMOS transistor MN2 may include a drain terminal connected to the source terminal of the first NMOS transistor MN1, a source terminal connected to the first node N1, and a gate terminal connected to the input terminal into which the first input signal IS1 is input.

[0066] The third NMOS transistor MN3 may include a drain terminal connected to the terminal from which the first output signal OS1 is output, a source terminal connected to the drain terminal of the fourth NMOS transistor MN4, and a gate terminal connected to the terminal from which the second output signal OS2 is output.

[0067] The fourth NMOS transistor MN4 may include a drain terminal connected to the source terminal of the third NMOS transistor MN3, a source terminal connected to the first node N1, and a gate terminal connected to the input terminal into which the second input signal IS2 is input.

[0068] The first NMOS transistor MN1 and the second NMOS transistor MN2 can be connected in series between the terminal from which the second output signal OS2 is output and the first node N1. The third NMOS transistor MN3 and the fourth NMOS transistor MN4 can be connected in series between the terminal from which the first output signal OS1 is output and the first node N1.

[0069] The fifth NMOS transistor MN5 may include a drain terminal connected to the first node N1, a source terminal connected to the ground voltage GND, and a gate terminal connected to the terminal to which the operating clock signal OCK is input. In this document, for ease of description, the terms ground voltage GND, ground node GND, and ground GND are used interchangeably.

[0070] Reference Figure 5A An exemplary operation of comparator 100a is described.

[0071] Figure 4A and Figure 4B It is used to describe according to the example embodiments Figure 3 The circuit diagram for the operation of the comparator.

[0072] refer to Figure 4A ,and Figure 3 Compared to comparator 100a, comparator 100b may further include a voltage source providing the offset voltage VOS. For brevity, the following will omit the references to comparator 100a. Figure 3 The description is repetitive or overlapping.

[0073] For example, each of the components included in comparator 100b may have an offset voltage. Considering all the offset voltages of the components, it can be assumed that an offset voltage VOS exists between the input terminal of the first input signal IS1 and the gate terminal of the second NMOS transistor MN2. In this case, even if the first input signal IS1 and the second input signal IS2, which have the same voltage level, are applied, the voltage level at the gate terminal of the second NMOS transistor MN2 may be higher than the voltage level at the gate terminal of the fourth NMOS transistor MN4 due to the offset voltage VOS.

[0074] However, the voltage source is not a component that physically exists in comparator 100b, but can be a component that is conceptually added to describe the offset voltage.

[0075] Reference Figure 5B An example describing the operation of comparator 100b.

[0076] refer to Figure 4B ,and Figure 3 Compared to comparator 100a, comparator 100c may also include an offset voltage VOS'. For brevity, this will be omitted in the following text. Figure 3 and Figure 4A The description is repetitive or overlapping.

[0077] For example, each of the components included in comparator 100c may have an offset voltage. Considering all the offset voltages of the components, it can be assumed that there is an offset voltage VOS' between the input terminal of the second input signal IS2 and the gate terminal of the fourth NMOS transistor MN4. In this case, even if the first input signal IS1 and the second input signal IS2, which have the same voltage level, are applied, the voltage level at the gate terminal of the fourth NMOS transistor MN4 may be higher than the voltage level at the gate terminal of the second NMOS transistor MN2 by the offset voltage VOS'.

[0078] Reference Figure 5C An exemplary operation of comparator 100c is described.

[0079] Figure 5A It is used to describe according to the example embodiments Figure 3 The timing diagram of the comparator's operation in normal mode.

[0080] refer to Figure 3 and Figure 5A The first input signal IS1, the second input signal IS2, the operation clock signal OCK, the first output signal OS1, and the second output signal OS2 are shown at the first time point T1, the second time point T2, the third time point T3, the fourth time point T4, the fifth time point T5, the sixth time point T6, the seventh time point T7, the eighth time point T8, the ninth time point T9, the tenth time point T10, the eleventh time point T11, and the twelfth time point T12.

[0081] For example, at a first time point T1, a first input signal IS1 and a second input signal IS2 with different voltage levels can be provided or received. For example, when the control signal CTRL changes from a logic low level to a logic high level at the first time point T1, the switch (e.g., Figure 2 The switch 300 in the middle can be turned off, and can receive a first input signal IS1 and a second input signal IS2 with different voltage levels.

[0082] For example, from a first time point T1 to a second time point T2, the first input signal IS1 may decrease and the second input signal IS2 may increase. For example, from a second time point T2 to a fifth time point T5, the first input signal IS1 may have a first voltage level, and the second input signal IS2 may have a second voltage level higher than the first voltage level. For example, from a fifth time point T5 to a seventh time point T7, the first input signal IS1 may increase and the second input signal IS2 may decrease. For example, from a seventh time point T7 to a tenth time point T10, the first input signal IS1 may have a second voltage level, and the second input signal IS2 may have a first voltage level. For example, from a tenth time point T10 to a twelfth time point T12, the first input signal IS1 may decrease and the second input signal IS2 may increase.

[0083] For example, the operating clock signal OCK can be logic low until the second time point T2. Alternatively, the operating clock signal OCK can be logic high from the second time point T2 to the third time point T3. Or, the operating clock signal OCK can change to logic low at the third time point T3 and remain logic low from the third time point T3 to the fourth time point T4. Finally, the operating clock signal OCK can change to logic high at the fourth time point T4 and remain logic high from the fourth time point T4 to the fifth time point T5.

[0084] For example, the operating clock signal OCK can change to a logic low level at time point T5 and remain logic low from time point T5 to time point T6. Alternatively, the operating clock signal OCK can change to a logic high level at time point T6 and remain logic high from time point T6 to time point T7. And again, the operating clock signal OCK can change to a logic low level at time point T7 and remain logic low from time point T7 to time point T8.

[0085] For example, the operating clock signal OCK can change to a logic high level at time point T8 and remain logic high from time point T8 to time point T9. Alternatively, the operating clock signal OCK can change to a logic low level at time point T9 and remain logic low from time point T9 to time point T10. Similarly, the operating clock signal OCK can change to a logic high level at time point T10 and remain logic high from time point T10 to time point T11. Finally, the operating clock signal OCK can change to a logic low level at time point T11 and remain logic low from time point T11 to time point T12.

[0086] For example, when the operating clock signal OCK is at a logic low level, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 can be turned on, and the fifth NMOS transistor MN5 can be turned off. Since the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned on, the first output signal OS1 and the second output signal OS2 can be at a logic high level.

[0087] For example, when the operating clock signal OCK changes from logic low to logic high, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 can be turned off, and the fifth NMOS transistor MN5 can be turned on.

[0088] Assuming the voltage level of the second input signal IS2 is higher than the voltage level of the first input signal IS1, the amount of current flowing from the third NMOS transistor MN3 to the fourth NMOS transistor MN4 can be greater than the amount of current flowing from the first NMOS transistor MN1 to the second NMOS transistor MN2. Therefore, the voltage level of the first output signal OS1 can decrease faster than the voltage level of the second output signal OS2. When the first output signal OS1 has a logic low level, since the first output signal OS1 is connected from its output terminal to the gate terminal of the first NMOS transistor MN1 and the gate terminal of the third PMOS transistor MP3, the first NMOS transistor MN1 can be turned off and the third PMOS transistor MP3 can be turned on.

[0089] In this situation, due to the conduction of the third PMOS transistor MP3, the voltage level of the second output signal OS2, which has been slowly decreasing compared to the first output signal OS1, can be increased again.

[0090] Therefore, when the voltage level of the second input signal IS2 is higher than the voltage level of the first input signal IS1, if the operation clock signal OCK changes from logic low to logic high, the first output signal OS1 can change to logic low and the second output signal OS2 can decrease and then increase.

[0091] Assuming the voltage level of the first input signal IS1 is higher than the voltage level of the second input signal IS2, the amount of current flowing from the first NMOS transistor MN1 to the second NMOS transistor MN2 can be greater than the amount of current flowing from the third NMOS transistor MN3 to the fourth NMOS transistor MN4. Therefore, the voltage level of the second output signal OS2 can decrease faster than the voltage level of the first output signal OS1. When the second output signal OS2 has a logic low level, the second output signal OS2 is connected from its output terminal, the gate terminal of the third NMOS transistor MN3, and the gate terminal of the second PMOS transistor MP2, so that the third NMOS transistor MN3 can be turned off and the second PMOS transistor MP2 can be turned on.

[0092] In this situation, due to the conduction of the second PMOS transistor MP2, the voltage level of the first output signal OS1, which has been slowly decreasing compared to the second output signal OS2, can be increased again.

[0093] Therefore, when the voltage level of the first input signal IS1 is higher than the voltage level of the second input signal IS2, if the operation clock signal OCK changes from logic low to logic high, the second output signal OS2 can change to logic low and the first output signal OS1 can decrease and then increase.

[0094] For example, from the first time point T1 to the sixth time point T6, the second input signal IS2 can be greater than the first input signal IS1. In this case, at the second time point T2 and the fourth time point T4 when the operating clock signal OCK changes from logic low to logic high, the first output signal OS1 changes from logic high to logic low, and the second output signal OS2 can decrease and then increase again.

[0095] For example, from the sixth time point T6 to the eleventh time point T11, the first input signal IS1 can be greater than the second input signal IS2. In this case, at the sixth time point T6, the eighth time point T8, and the tenth time point T10, when the operating clock signal OCK changes from logic low to logic high, the second output signal OS2 changes from logic high to logic low, and the first output signal OS1 can decrease and then increase again.

[0096] Figure 5B It is used to describe according to the example embodiments Figure 4A Timing diagram of the comparator operation in offset calibration mode.

[0097] refer to Figure 4A and Figure 5B The first input signal IS1, the second input signal IS2, the operation clock signal OCK, the first output signal OS1, and the second output signal OS2 are shown at the first time point T1', the second time point T2', the third time point T3', the fourth time point T4', the fifth time point T5', the sixth time point T6', the seventh time point T7', the eighth time point T8', the ninth time point T9', the tenth time point T10', the eleventh time point T11', and the twelfth time point T12'.

[0098] For example, at the second time point T2', the first input signal IS1 can increase and the second input signal IS2 can decrease, such that the first input signal IS1 and the second input signal IS2 can have the same voltage level from the third time point T3'. For example, when the control signal CTRL changes from a logic high level to a logic low level at the second time point T2', the switch (e.g., Figure 2 The switch 300 in the middle can be closed.

[0099] For example, the first input signal IS1 and the second input signal IS2 can have different voltage levels up to the third time point T3', and can have the same voltage level from the third time point T3' onwards.

[0100] For example, the operating clock signal OCK can be logic low until the third time point T3'. Alternatively, the operating clock signal OCK can be logic high from the third time point T3' to the fifth time point T5'. Or, the operating clock signal OCK can change to logic low at the fifth time point T5' and remain logic low from the fifth time point T5' to the seventh time point T7'. Or, the operating clock signal OCK can change to logic high at the seventh time point T7' and remain logic high from the seventh time point T7' to the ninth time point T9'. Or, the operating clock signal OCK can change to logic low at the ninth time point T9' and remain logic low from the ninth time point T9' to the eleventh time point T11'. Or, the operating clock signal OCK can change to logic high at the eleventh time point T11' and remain logic high from the eleventh time point T11' to the twelfth time point T12'.

[0101] For example, the operating clock signal OCK in normal mode can be the first clock signal (e.g., Figure 1 CK1 in the offset calibration mode), and the operating clock signal OCK in offset calibration mode can be a second clock signal (e.g., Figure 1 (e.g., CK2 in the first clock signal CK1). For example, the frequency of the first clock signal CK1 can be a high frequency in gigahertz (GHz) units, and the frequency of the second clock signal CK2 can be a low frequency in kilohertz (KHZ) or megahertz (MHZ) units.

[0102] For example, when the operating clock signal OCK is at a logic low level, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 can be turned on, and the fifth NMOS transistor MN5 can be turned off. Since the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned on, the first output signal OS1 and the second output signal OS2 can be at a logic high level.

[0103] For example, when the operating clock signal OCK changes from logic low to logic high, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 can be turned off, and the fifth NMOS transistor MN5 can be turned on.

[0104] In this scenario, because the voltage level at the gate terminal of the second NMOS transistor MN2 is higher than the voltage level at the gate terminal of the fourth NMOS transistor MN4, the offset voltage VOS between the input terminal of the first input signal IS1 and the gate terminal of the second NMOS transistor MN2 allows the amount of current flowing from the first NMOS transistor MN1 to the second NMOS transistor MN2 to be greater than the amount of current flowing from the third NMOS transistor MN3 to the fourth NMOS transistor MN4. Therefore, the voltage level of the second output signal OS2 can decrease faster than the voltage level of the first output signal OS1. When the second output signal OS2 has a logic low level, because the second output signal OS2 is connected from its output terminal to the gate terminal of the third NMOS transistor MN3 and the gate terminal of the second PMOS transistor MP2, the third NMOS transistor MN3 can be turned off and the second PMOS transistor MP2 can be turned on.

[0105] In this situation, because the second PMOS transistor MP2 is turned on, the voltage level of the first output signal OS1, which has been gradually decreasing compared to the second output signal OS2, can be increased again. Since the voltage level of the first output signal OS1 decreases and then increases again, the third PMOS transistor MP3 can remain off.

[0106] For example, when the operating clock signal OCK changes from logic high to logic low, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 can be turned on, and the fifth NMOS transistor MN5 can be turned off. In this case, since the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned on, the first output signal OS1 can have a logic high level, and the second output signal OS2 can change from a logic low level to a logic high level. Therefore, the second PMOS transistor MP2 and the third PMOS transistor MP3 can be turned off.

[0107] For example, at the third time point T3', the seventh time point T7', and the eleventh time point T11' when the operating clock signal OCK changes from logic low to logic high, the first output signal OS1 can decrease and then increase again, and the second output signal OS2 can change from logic high to logic low.

[0108] For example, at the fifth time point T5' and the ninth time point T9' when the operating clock signal OCK changes from logic high to logic low, the first output signal OS1 can have a logic high level, and the second output signal OS2 can change from logic low to logic high level.

[0109] For example, when the voltage level at the gate terminal of the second NMOS transistor MN2 is higher than the voltage level at the gate terminal of the fourth NMOS transistor MN4, in offset calibration mode, the second PMOS transistor MP2 can be repeatedly turned on and off, and the third PMOS transistor MP3 can be turned off. In this case, the threshold voltage level of the second PMOS transistor MP2 can be reduced, and the second PMOS transistor MP2 can have degraded performance outside the reference performance range. For example, because the absolute value of the threshold voltage of the second PMOS transistor MP2 increases, the difference between the gate-source voltage and the threshold voltage of the second PMOS transistor MP2 can be reduced, and the amount of current in the second PMOS transistor MP2 can be reduced.

[0110] For example, when the operating clock signal OCK changes from logic low to logic high, the second output signal OS2 changes from logic high to logic low, and the first output signal OS1 can drop slightly from logic high and then increase again. In this case, if the amount of current in the second PMOS transistor MP2 decreases, the amount of increase in the first output signal OS1 can gradually decrease. Therefore, the difference between the first output signal OS1 and the second output signal OS2 gradually decreases, allowing an offset calibration operation to be performed.

[0111] For example, at the third time point T3', the operating clock signal OCK can change from a logic low level to a logic high level. As described above, the second output signal OS2 has a logic low level, and the first output signal OS1 can decrease and then increase again as the second PMOS transistor MP2 is turned on. For example, as the second PMOS transistor MP2 degrades through repeated on and off cycles, the amount of current in the second PMOS transistor MP2 can decrease. In this case, since the amount of increase in the first output signal OS1 decreases, the difference between the first output signal OS1 and the second output signal OS2 gradually decreases, making it possible to perform an offset calibration operation.

[0112] Figure 5C It is used to describe according to the example embodiments Figure 4B Timing diagram of the comparator operation in offset calibration mode.

[0113] refer to Figure 4B and Figure 5CThe first input signal IS1, the second input signal IS2, the operation clock signal OCK, the first output signal OS1, and the second output signal OS2 are shown at the first time point T1'', the second time point T2'', the third time point T3'', the fourth time point T4'', the fifth time point T5'', the sixth time point T6'', the seventh time point T7'', the eighth time point T8'', the ninth time point T9'', the tenth time point T10'', the eleventh time point T11'', and the twelfth time point T12''.

[0114] For example, at the second time point T2'', the first input signal IS1 can increase and the second input signal IS2 can decrease, such that the first input signal IS1 and the second input signal IS2 can have the same voltage level as at the third time point T3''. For example, when the control signal CTRL changes from a logic high level to a logic low level at the second time point T2'', the switch (e.g., Figure 2 The switch 300 in the middle can be closed.

[0115] For example, the first input signal IS1 and the second input signal IS2 can have different voltage levels up to the third time point T3'', and can have the same voltage level from the third time point T3'' onwards.

[0116] For example, the operating clock signal OCK can be logic low until the third time point T3''. Alternatively, the operating clock signal OCK can be logic high from the third time point T3'' to the fifth time point T5''. Or, the operating clock signal OCK can change to logic low at the fifth time point T5'' and remain logic low from the fifth time point T5'' to the seventh time point T7''. Or, the operating clock signal OCK can change to logic high at the seventh time point T7'' and remain logic high from the seventh time point T7'' to the ninth time point T9''. Or, the operating clock signal OCK can change to logic low at the ninth time point T9'' and remain logic low from the ninth time point T9'' to the eleventh time point T11''. Or, the operating clock signal OCK can change to logic high at the eleventh time point T11'' and remain logic high from the eleventh time point T11'' to the twelfth time point T12''.

[0117] For example, the operating clock signal OCK in normal mode can be the first clock signal (e.g., Figure 1 CK1 in the offset calibration mode), and the operating clock signal OCK in offset calibration mode can be a second clock signal (e.g., Figure 1 (CK2 in the middle).

[0118] For example, when the operating clock signal OCK is at a logic low level, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 can be turned on, and the fifth NMOS transistor MN5 can be turned off. Since the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned on, the first output signal OS1 and the second output signal OS2 can be at a logic high level.

[0119] For example, when the operating clock signal OCK changes from logic low to logic high, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 can be turned off, and the fifth NMOS transistor MN5 can be turned on.

[0120] In this scenario, because the voltage level at the gate terminal of the fourth NMOS transistor MN4 is higher than the voltage level at the gate terminal of the second NMOS transistor MN2, the offset voltage VOS' between the input terminal of the second input signal IS2 and the gate terminal of the fourth NMOS transistor MN4 allows the amount of current flowing from the third NMOS transistor MN3 to the fourth NMOS transistor MN4 to be greater than the amount of current flowing from the first NMOS transistor MN1 to the second NMOS transistor MN2. Therefore, the voltage level of the first output signal OS1 can decrease faster than the voltage level of the second output signal OS2. When the first output signal OS1 has a logic low level, since the first output signal OS1 is connected from its output terminal to the gate terminal of the first NMOS transistor MN1 and the gate terminal of the third PMOS transistor MP3, the first NMOS transistor MN1 can be turned off and the third PMOS transistor MP3 can be turned on.

[0121] In this situation, because the third PMOS transistor MP3 is turned on, the voltage level of the second output signal OS2, which has been gradually decreasing compared to the first output signal OS1, can increase again. Since the voltage level of the second output signal OS2 decreases and then increases again, the second PMOS transistor MP2 can remain off.

[0122] For example, when the operating clock signal OCK changes from logic high to logic low, the first PMOS transistor MP1 and the fourth PMOS transistor MP4 can be turned on, and the fifth NMOS transistor MN5 can be turned off. In this case, since the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are turned on, the second output signal OS2 can have a logic high level, and the first output signal OS1 can change from a logic low level to a logic high level. Therefore, the second PMOS transistor MP2 and the third PMOS transistor MP3 can be turned off.

[0123] For example, at the third time point T3'', the seventh time point T7'', and the eleventh time point T11'' when the operating clock signal OCK changes from logic low to logic high, the second output signal OS2 can decrease and then increase again, and the first output signal OS1 can change from logic high to logic low.

[0124] For example, at the fifth time point T5'' and the ninth time point T9'' when the operating clock signal OCK changes from logic high to logic low, the second output signal OS2 can have a logic high level, and the first output signal OS1 can change from logic low to logic high level.

[0125] For example, when the voltage level at the gate terminal of the fourth NMOS transistor MN4 is higher than the voltage level at the gate terminal of the second NMOS transistor MN2, in offset calibration mode, the third PMOS transistor MP3 can be repeatedly turned on and off, and the second PMOS transistor MP2 can be turned off. In this case, the threshold voltage level of the third PMOS transistor MP3 can be reduced, and the third PMOS transistor MP3 can have degraded performance outside the reference performance range. In other words, because the absolute value of the threshold voltage of the third PMOS transistor MP3 increases, the difference between the gate-source voltage and the threshold voltage of the third PMOS transistor MP3 can be reduced, and the amount of current in the third PMOS transistor MP3 can be reduced.

[0126] For example, when the operating clock signal OCK changes from logic low to logic high, the first output signal OS1 changes from logic high to logic low, and the second output signal OS2 can decrease slightly from logic high and then increase again. In this case, if the amount of current in the second PMOS transistor MP2 decreases, the amount of increase in the second output signal OS2 can gradually decrease. Therefore, the difference between the first output signal OS1 and the second output signal OS2 gradually decreases, making it possible to perform an offset calibration operation.

[0127] For example, at the third time point T3'', the operating clock signal OCK can change from a logic low level to a logic high level. As described above, the first output signal OS1 can have a logic low level, and the second output signal OS2 can decrease as the third PMOS transistor MP3 is turned on and then increase again. For example, as the third PMOS transistor MP3 degrades through repeated on and off cycles, the amount of current in the third PMOS transistor MP3 can decrease. In this case, because the amount of increase in the second output signal OS2 decreases, the difference between the first output signal OS1 and the second output signal OS2 gradually decreases, making it possible to perform an offset calibration operation.

[0128] Figure 6 This is a diagram showing the simulation results of the comparison circuit according to an example embodiment.

[0129] refer to Figure 6 The first input signal IS1, the second input signal IS2, the first output signal OS1-1, the second output signal OS2-1, the first output signal OS1-2, and the second output signal OS2-2 are shown at the first-first time point T1-1 and the first-second time point T1-2.

[0130] The first-first output signal OS1-1 and the second-first output signal OS2-1 correspond to the first output signal and the second output signal, respectively, for which no offset calibration operation is performed. The first-second output signal OS1-2 and the second-second output signal OS2-2 refer to the first output signal and the second output signal after the offset calibration operation is performed by degrading the transistor, according to the example embodiment.

[0131] As a result of the simulation performed by keeping the first input signal IS1 constant and increasing the second input signal IS2, the first-first output signal OS1-1 and the second-first output signal OS2-1 can be inverted at the first-first time point T1-1, and the first-second output signal OS1-2 and the second-second output signal OS2-2 can be inverted at the first-second time point T1-2 after the first-first time point T1-1.

[0132] The offset prior to the offset calibration operation can refer to the first offset DIF1 at the first time point T1-1 where the first output signal OS1-1 and the second output signal OS2-1 are out of phase, and this first offset DIF1 is the difference between the first input signal IS1 and the second input signal IS2. The offset after the offset calibration operation can refer to the second offset DIF2 at the first second time point T1-2 where the first output signal OS1-2 and the second output signal OS2-2 are out of phase, and this second offset DIF2 is the difference between the first input signal IS1 and the second input signal IS2.

[0133] Therefore, the comparator offset can be reduced from the first offset DIF1 to the second offset DIF2 by performing an offset calibration operation.

[0134] Figure 7 This illustrates the inclusion of examples according to the embodiment. Figure 1 A circuit diagram of an example comparator in a comparison circuit.

[0135] refer to Figure 7The comparator 100d may include the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, and the twelfth NMOS transistor MN12.

[0136] The fifth PMOS transistor MP5 may include a source terminal connected to the terminal to which a second power supply voltage VDD2 is applied, a drain terminal connected to the second node N2, and a gate terminal connected to the terminal to which an inverted operating clock signal OCK' is input. In an example embodiment, the second power supply voltage VDD2 may be the same as the first power supply voltage VDD1.

[0137] The sixth PMOS transistor MP6 may include a source terminal connected to the second node N2, a drain terminal connected to the terminal from which the first output signal OS1 is output, and a gate terminal connected to the terminal from which the second output signal OS2 is output.

[0138] The seventh PMOS transistor MP7 may include a source terminal connected to the second node N2, a drain terminal connected to the terminal from which the second output signal OS2 is output, and a gate terminal connected to the terminal from which the first output signal OS1 is output.

[0139] The eighth PMOS transistor MP8 may include a source terminal connected to the terminal to which the second power supply voltage VDD2 is applied, a drain terminal connected to the gate terminal of the eighth NMOS transistor MN8 and the tenth NMOS transistor MN10, and a gate terminal connected to the terminal to which the operating clock signal OCK is input.

[0140] The ninth PMOS transistor MP9 may include a source terminal connected to the terminal to which the second power supply voltage VDD2 is applied, a drain terminal connected to the drain terminal of the ninth NMOS transistor MN9, a gate terminal connected to the gate terminal of the eleventh NMOS transistor MN11, and a gate terminal connected to the terminal to which the operating clock signal OCK is input.

[0141] The sixth NMOS transistor MN6 may include a drain terminal connected to the terminal from which the first output signal OS1 is output, a source terminal connected to the ground voltage GND, and a gate terminal connected to the terminal from which the second output signal OS2 is output.

[0142] The seventh NMOS transistor MN7 may include a drain terminal connected to the terminal from which the second output signal OS2 is output, a source terminal connected to the ground voltage GND, and a gate terminal connected to the terminal from which the first output signal OS1 is output.

[0143] The eighth NMOS transistor MN8 may include a drain terminal connected to the drain terminal of the eighth PMOS transistor MP8 and the gate terminal of the tenth NMOS transistor MN10, a source terminal connected to the third node N3, and a gate terminal connected to the input terminal into which the first input signal IS1 is input.

[0144] The ninth NMOS transistor MN9 may include a drain terminal connected to the drain terminal of the ninth PMOS transistor MP9 and the gate terminal of the eleventh NMOS transistor MN11, a source terminal connected to the third node N3, and a gate terminal connected to the input terminal into which the second input signal IS2 is input.

[0145] The tenth NMOS transistor MN10 may include a drain terminal connected to the terminal from which the first output signal OS1 is output, a source terminal connected to the ground voltage GND, and a gate terminal connected to the drain terminal of the eighth NMOS transistor MN8 and the drain terminal of the eighth PMOS transistor MP8.

[0146] The eleventh NMOS transistor MN11 may include a drain terminal connected to the terminal from which the second output signal OS2 is output, a source terminal connected to the ground voltage GND, and a gate terminal connected to the drain terminal of the ninth NMOS transistor MN9 and the drain terminal of the ninth PMOS transistor MP9.

[0147] The twelfth NMOS transistor MN12 may include a drain terminal connected to the third node N3, a source terminal connected to the ground voltage GND, and a gate terminal connected to the terminal to which the operating clock signal OCK is input.

[0148] For example, the method of operating comparator 100d is similar to operating... Figure 3 The method of comparator 100a, and the timing diagram of control signal CTRL, first input signal IS1, second input signal IS2, operation clock signal OCK, first output signal OS1 and second output signal OS2 can be compared with... Figure 5A The timing diagrams are basically the same. The inverted operating clock signal OCK' can refer to the inverted signal of the operating clock signal OCK.

[0149] Figure 8A and Figure 8B It is used to describe according to the example embodiments Figure 7 The circuit diagram for the operation of the comparator.

[0150] refer to Figure 8A ,and Figure 7 Compared to comparator 100d, comparator 100e may also include a voltage source providing the offset voltage VOS''. For brevity, the following will omit the references to comparator 100d. Figure 7 The description is repetitive or overlapping.

[0151] For example, each of the components included in comparator 100e may have an offset voltage. Considering all the offset voltages of the components, it can be assumed that there is an offset voltage VOS'' between the input terminal of the first input signal IS1 and the gate terminal of the eighth NMOS transistor MN8. In this case, even if the first input signal IS1 and the second input signal IS2, which have the same voltage level, are applied, the voltage level at the gate terminal of the eighth NMOS transistor MN8 may be higher than the voltage level at the gate terminal of the ninth NMOS transistor MN9 by the offset voltage VOS''.

[0152] However, the voltage source is not a component that physically exists in comparator 100e, but can be a component that is conceptually added to describe the offset voltage.

[0153] refer to Figure 8B ,and Figure 7 Compared to comparator 100d, comparator 100f may also include a voltage source providing the offset voltage VOS'''. For brevity, the following will omit the references to comparator 100d. Figure 7 and Figure 8A The description is repetitive or overlapping.

[0154] For example, each of the components included in comparator 100f may have an offset voltage. Considering all the offset voltages of the components, it can be assumed that there is an offset voltage VOS''' between the input terminal of the second input signal IS2 and the gate terminal of the ninth NMOS transistor MN9. In this case, even if the first input signal IS1 and the second input signal IS2, which have the same voltage level, are applied, the voltage level at the gate terminal of the ninth NMOS transistor MN9 may be higher than the voltage level at the gate terminal of the eighth NMOS transistor MN8 by the offset voltage VOS'''.

[0155] For example, operation Figure 8A Comparator 100e and Figure 8B The comparator 100f can be operated in a manner similar to the operation. Figure 4A Comparator 100b and Figure 4B The comparator 100c method. For example, Figure 8A Comparator 100e and Figure 8BThe timing diagrams of the control signal CTRL, first input signal IS1, second input signal IS2, operation clock signal OCK, first output signal OS1, and second output signal OS2 in comparator 100f can be respectively compared with... Figure 5B and Figure 5C The timing diagrams are basically the same.

[0156] For example, in offset calibration mode, if the voltage level at the gate terminal of the eighth NMOS transistor MN8 is higher than the voltage level at the gate terminal of the ninth NMOS transistor MN9, then the sixth PMOS transistor MP6 can be repeatedly turned on and off, and the seventh PMOS transistor MP7 can be turned off. In this case, due to the reduction in threshold voltage, the sixth PMOS transistor MP6 may have degraded performance outside the reference performance range, while the seventh NMOS transistor MP7 may have maintained performance within the reference performance range.

[0157] For example, in offset calibration mode, if the voltage level at the gate terminal of the ninth NMOS transistor MN9 is higher than the voltage level at the gate terminal of the eighth NMOS transistor MN8, then the seventh PMOS transistor MP7 can be repeatedly turned on and off, and the sixth PMOS transistor MP6 can be turned off. In this case, due to the reduction in threshold voltage, the seventh PMOS transistor MP7 may have degraded performance outside the reference performance range, while the sixth NMOS transistor MP6 may have maintained performance within the reference performance range.

[0158] Figure 9 This is a flowchart illustrating a method of operating a comparison circuit according to an example embodiment.

[0159] refer to Figure 9 The method of operation, which includes a comparator circuit with at least one transistor, is performed by a comparator circuit according to an example embodiment (e.g., Figure 1 The comparison circuit 10) is executed.

[0160] like Figure 9 As shown, in a method according to an example embodiment of a comparison circuit including at least one transistor, it is determined whether the operating mode of the comparison circuit is an offset calibration mode or a normal mode (operation S100).

[0161] When the operating mode of the comparator circuit is normal mode (operation S100: no), normal operation is performed based on the operation clock signal and the first and second input signals with different voltage levels (operation S200).

[0162] When the operating mode of the comparator circuit is offset calibration mode (operation S100: yes), the offset calibration operation is performed by degrading at least one transistor based on the operating clock signal and the first and second input signals having the same voltage level (operation S300).

[0163] Figure 10 This is a flowchart illustrating an example of performing normal operation in a method of operating a comparison circuit according to an example embodiment.

[0164] refer to Figure 10 During normal operation (operation S200), a first clock signal is output as the operation clock signal based on the control signal (operation S210).

[0165] Receive a first input signal and a second input signal with different voltage levels (operation S220).

[0166] The first output signal is generated based on the first input signal, the second input signal, and the operation clock signal (operation S230).

[0167] Figure 11 This is a flowchart illustrating an example of performing an offset calibration operation in a method of operating a comparison circuit according to an example embodiment.

[0168] refer to Figure 11 When performing offset calibration operation (operation S300), a second clock signal is output as the operation clock signal based on the control signal (operation S310).

[0169] Receive a first input signal and a second input signal with the same voltage level (operation S320).

[0170] The first output signal is generated based on the first input signal, the second input signal, and the operation clock signal (operation S330).

[0171] Figure 12 This is a flowchart illustrating a method of operating a comparison circuit according to an example embodiment.

[0172] refer to Figure 12 According to the method of operating the comparison circuit in the example embodiment, operations S100, S200, and S300 can be combined with... Figure 9 The operations S100, S200 and S300 are basically the same. Figure 12 Examples of repeatedly performing operations S100, S200, and S300 are shown.

[0173] Figure 13 This is a block diagram illustrating a memory device according to an example embodiment.

[0174] refer to Figure 13The memory device 700 may include control logic circuitry 710, address register 720, memory bank control logic circuitry 730, row address multiplexer 740, refresh counter 745, column address latch 750, row decoder 760, column decoder 770, memory cell array 800, sense amplifier circuitry 785, input / output (I / O) gating circuitry 790, and data I / O buffer 795. For example, the memory device 700 may be one of various volatile memory devices, such as dynamic random access memory (DRAM) devices.

[0175] The memory cell array 800 may include first memory arrays 810 to eighth memory arrays 880 (e.g., first memory arrays 810 to eighth memory arrays 820, 830, 840, 850, 860, 870, and 880). The row decoder 760 may include first memory array row decoders 760a to 760h respectively connected to the first memory arrays 810 to 880. The column decoder 770 may include first memory array column decoders 770a to 770h respectively connected to the first memory arrays 810 to 880. The sense amplifier circuit 785 may include first memory array sense amplifiers 785a to 785h respectively connected to the first memory arrays 810 to 880. Each of the first memory array sense amplifiers 785a to 785h may include components previously described. Figure 1 Comparator circuit 10 or Figure 2 The comparison circuit is the same as that of the comparison circuit 10a. For example, the first memory cell sense amplifier 785a may include a first comparison circuit 787a. The comparison circuit according to the example embodiment can perform an offset calibration operation by degrading the transistors included in the comparison circuit.

[0176] First memory arrays 810 to 880, first memory row decoders 760a to 880h, first memory column decoders 770a to 880h, and first memory sense amplifiers 785a to 885h can form first to eighth memory arrays. Each of the first memory arrays 810 to 880 can include multiple word lines WL, multiple bit lines BL, and multiple memory cells MC located at the intersection of word lines WL and bit lines BL.

[0177] although Figure 13A memory device 700 is shown that includes eight memory banks (and an array of eight memory banks, eight line decoders, etc.), but the memory device 700 may include any number of memory banks; for example, one, two, four, eight, sixteen, or thirty-two memory banks, or any number between one and thirty-two.

[0178] Address register 720 can receive one or more address ADDRs, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from a memory controller located outside the memory device 700. Address register 720 can provide the received bank address BANK_ADDR to the bank control logic circuit 730, the received row address ROW_ADDR to the row address multiplexer 740, and the received column address COL_ADDR to the column address latch 750.

[0179] The memory bank control logic circuit 730 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. It can activate one of the first to eighth memory bank row decoders 760a to 760h corresponding to the memory bank address BANK_ADDR in response to the memory bank control signal, and can also activate one of the first to eighth memory bank column decoders 770a to 770h corresponding to the memory bank address BANK_ADDR in response to the memory bank control signal.

[0180] The row address multiplexer 740 can receive the row address ROW_ADDR from the address register 720 and the refresh row address REF_ADDR from the refresh counter 745. The row address multiplexer 740 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 740 can be applied to the first memory bank row decoders 760a to the eighth memory bank row decoders 760h.

[0181] An active memory bank row decoder among the first to eighth memory bank row decoders 760a and 760h can decode the row address RA output from the row address multiplexer 740 and can activate the word line WL corresponding to the row address RA in the corresponding memory bank array. For example, the active memory bank row decoder can generate a word line drive voltage and can apply the word line drive voltage to the word line WL corresponding to the row address RA.

[0182] Column address latch 750 can receive column address COL_ADDR from address register 720 and can temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode, column address latch 750 can generate a column address COL_ADDR' incremented from the received column address COL_ADDR and provide column address COL_ADDR' to the first memory bank column decoder 770a to the eighth memory bank column decoder 770h. In some example embodiments, column address latch 750 can apply the temporarily stored column address COL_ADDR to the first array decoder 770a to the eighth array decoder 770h.

[0183] An active memory bank column decoder among the first to eighth memory bank column decoders 770a and 770h can decode the column address COL_ADDR output from the column address latch 750 and can control the I / O gate circuit 790 to output data corresponding to the column address COL_ADDR.

[0184] The I / O gate circuit 790 may include a circuit system configured to gate input / output data. The I / O gate circuit 790 may also include a read data latch configured to store data output from the first memory array 810 to the eighth memory array 880, and may also include a write control device for writing data to the first memory array 810 to the eighth memory array 880.

[0185] Data DAT read from one of the first memory arrays 810 to the eighth memory array 880 can be sensed by a sense amplifier connected to the memory array from which the data DAT is to be read, and can be stored in a read data latch. The data DAT stored in the read data latch can be provided to the memory controller via a data I / O buffer 795. Data DAT to be written to one of the memory arrays 810 to the eighth memory array 880 can be provided from the memory controller to an I / O gate circuit 790 via a data I / O buffer 795, and the I / O gate circuit 790 can write the data DAT to a memory array via a write driver.

[0186] Control logic circuitry 710 can control the operation of memory device 700. For example, control logic circuitry 710 can generate control signals for memory device 700 to perform write and / or read operations. Control logic circuitry 710 may include command decoder 711 for decoding commands CMD received from memory controller, and mode register 712 for setting the operating mode of memory device 700. In some example embodiments, the operations described herein as being performed by control logic circuitry 710 may be performed by a processing circuitry system. For example, command decoder 711 can generate control signals corresponding to command CMD by decoding write enable signals, row address strobe signals, column address strobe signals, chip select signals, etc.

[0187] In the example embodiment, the offset calibration operation can be performed during the manufacturing process of the memory device 700, and normal operation can be performed after the manufacturing process of the memory device 700. However, the example embodiment is not limited to this, and the offset calibration operation can also be performed after the manufacturing process of the memory device 700.

[0188] Figure 14 This is a block diagram illustrating an electronic system according to an example embodiment.

[0189] refer to Figure 14 The electronic system 1000 may include a processor 1010, a memory device 1020, a connectivity device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The electronic system 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, and other electronic devices.

[0190] Processor 1010 can control the operation of electronic system 1000. Processor 1010 can execute an operating system and at least one application to provide an internet browser, games, videos, etc. Connection 1030 can communicate with external devices and / or the system. I / O devices 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, touch screen, remote control, etc., and output devices such as a printer, speaker, etc. Power supply 1050 can provide power for the operation of electronic system 1000.

[0191] The memory device 1020 can store data for the operation of the electronic system 1000, and includes data similar to those previously described. Figure 1 Comparator circuit 10 or Figure 2 The comparator circuit 1022 is the same as the comparator circuit 10a. The comparator circuit 1022 can perform an offset calibration operation by degrading the transistors included in the comparator circuit 1022.

[0192] In the example embodiment, the offset calibration operation can be performed during the manufacturing process of the memory device 1020, and normal operation can be performed after the manufacturing process of the memory device 1020. However, the example embodiment is not limited to this, and the offset calibration operation can be performed after the manufacturing process of the memory device 1020.

[0193] Figure 15 This is a block diagram illustrating an integrated circuit according to an example embodiment.

[0194] refer to Figure 15 The integrated circuit 900 includes a power supply device 910 and an internal circuit 920.

[0195] For example, power supply device 910 can generate an output voltage VOUT by performing both three-level operation and two-path operation. Internal circuitry 920 can perform specific (or predetermined) operations based on the output voltage (or supply voltage) VOUT provided from power supply device 910. For example, internal circuitry 920 may include components similar to those previously described. Figure 1 Comparator circuit 10 or Figure 2 The comparator circuit 921 is the same as the comparator circuit 10a. The comparator circuit 921 can perform the offset calibration operation by degrading the transistor.

[0196] In the example embodiment, the offset calibration operation can be performed during the manufacturing process of the internal circuitry 920, and normal operation can be performed after the manufacturing process of the internal circuitry 920. However, the example embodiment is not limited to this, and the offset calibration operation can be performed after the manufacturing process of the internal circuitry 920.

[0197] The example embodiments can be applied to a variety of electronic devices and systems, including storage devices. For example, the example embodiments can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0198] Although the inventive concept has been specifically shown and described with reference to its embodiments, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A comparator circuit, comprising: A comparator includes at least one transistor and is configured to generate a first output signal based on a first input signal, a second input signal, and an operating clock signal; as well as The multiplexer is configured as follows: In normal mode, a first clock signal is output based on the control signal as the operation clock signal, and In offset calibration mode, a second clock signal, different from the first clock signal, is output as the operation clock signal based on the control signal. In the offset calibration mode, the comparison circuit is configured to perform an offset calibration operation by degrading the at least one transistor based on the first input signal and the second input signal having the same voltage level and the operating clock signal.

2. The comparator circuit as described in claim 1, wherein, The comparator includes: A first p-channel metal-oxide-semiconductor PMOS transistor and a second PMOS transistor are connected in parallel between a terminal from which a power supply voltage is applied and a terminal from which the first output signal is output. The first PMOS transistor includes a gate terminal connected to a terminal from which the operating clock signal is input, and the second PMOS transistor includes a gate terminal connected to a terminal from which the second output signal is output. A third PMOS transistor and a fourth PMOS transistor are connected in parallel between the terminal from which the power supply voltage is applied and the terminal from which the second output signal is output. The third PMOS transistor includes a gate terminal connected to the terminal from which the first output signal is output, and the fourth PMOS transistor includes a gate terminal connected to the terminal from which the operating clock signal is input. A first n-channel metal-oxide-semiconductor (NMOS) transistor and a second NMOS transistor are connected in series between a terminal from which the second output signal is output and a first node. The first NMOS transistor includes a gate terminal connected to the terminal from which the first output signal is output, and the second NMOS transistor includes a gate terminal connected to the terminal into which the first input signal is input. A third NMOS transistor and a fourth NMOS transistor are connected in series between the terminal from which the first output signal is output and the first node. The third NMOS transistor includes a gate terminal connected to the terminal from which the second output signal is output, and the fourth NMOS transistor includes a gate terminal connected to the terminal into which the second input signal is input. The fifth NMOS transistor is connected between the first node and the ground node, and includes a gate terminal connected to the terminal into which the operating clock signal is input.

3. The comparator circuit as described in claim 2, wherein, In the normal mode, each gate terminal of the first PMOS transistor, the fourth PMOS transistor, and the fifth NMOS transistor is configured to receive the first clock signal having a first frequency.

4. The comparator circuit as described in claim 3, wherein, In the offset calibration mode, each gate terminal of the first PMOS transistor, the fourth PMOS transistor, and the fifth NMOS transistor is configured to receive a second clock signal having a second frequency lower than the first frequency.

5. The comparator circuit as described in claim 4, wherein, In the offset calibration mode, one of the second PMOS transistor and the third PMOS transistor is configured to repeatedly turn on and off, and the other of the second PMOS transistor and the third PMOS transistor is configured to turn off.

6. The comparator circuit as described in claim 4, wherein, In the offset calibration mode: When the voltage level at the gate terminal of the second NMOS transistor is higher than the voltage level at the gate terminal of the fourth NMOS transistor, the third PMOS transistor is configured to be off, and the second PMOS transistor is configured to repeatedly turn on and off. When the voltage level at the gate terminal of the fourth NMOS transistor is higher than the voltage level at the gate terminal of the second NMOS transistor, the third PMOS transistor is configured to repeatedly turn on and off, and the second PMOS transistor is configured to turn off.

7. The comparator circuit as described in claim 6, wherein, In the offset calibration mode, when the voltage level at the gate terminal of the second NMOS transistor is higher than the voltage level at the gate terminal of the fourth NMOS transistor, the second PMOS transistor is configured to have degraded performance outside the reference performance range, and the third PMOS transistor is configured to have maintained performance within the reference performance range.

8. The comparator circuit as described in claim 7, wherein, In the offset calibration mode, when the voltage level of the gate terminal of the second NMOS transistor is higher than the voltage level of the gate terminal of the fourth NMOS transistor, the threshold voltage level of the second PMOS transistor decreases.

9. The comparator circuit as described in claim 6, wherein, In the offset calibration mode, when the voltage level at the gate terminal of the fourth NMOS transistor is higher than the voltage level at the gate terminal of the second NMOS transistor, the third PMOS transistor is configured to have degraded performance outside the reference performance range, and the second PMOS transistor is configured to have maintained performance within the reference performance range.

10. The comparator circuit as claimed in claim 1, wherein, The comparator includes: The fifth PMOS transistor is connected between the terminal to which the power supply voltage is applied and the second node, and includes a gate terminal connected to the terminal to which an inverted operating clock signal is input, wherein the inverted operating clock signal is the inverse of the operating clock signal. A sixth PMOS transistor and a sixth NMOS transistor are connected in series between the second node and the ground node. The sixth PMOS transistor includes a drain terminal connected to the terminal from which the first output signal is output and a gate terminal connected to the terminal from which the second output signal is output. The sixth NMOS transistor includes a drain terminal connected to the terminal from which the first output signal is output and a gate terminal connected to the terminal from which the second output signal is output. A seventh PMOS transistor and a seventh NMOS transistor are connected in series between the second node and the ground node. The seventh PMOS transistor includes a drain terminal connected to the terminal from which the second output signal is output and a gate terminal connected to the terminal from which the first output signal is output. The seventh NMOS transistor includes a drain terminal connected to the terminal from which the second output signal is output and a gate terminal connected to the terminal from which the first output signal is output. An eighth PMOS transistor and an eighth NMOS transistor are connected in series between the terminal to which the power supply voltage is applied and the third node. The eighth PMOS transistor includes a gate terminal connected to the terminal to which the operating clock signal is input, and the eighth NMOS transistor includes a gate terminal connected to the terminal to which the first input signal is input. A ninth PMOS transistor and a ninth NMOS transistor are connected in series between the terminal to which the power supply voltage is applied and the third node. The ninth PMOS transistor includes a gate terminal connected to the terminal to which the operating clock signal is input, and the ninth NMOS transistor includes a gate terminal connected to the terminal to which the second input signal is input. The tenth NMOS transistor includes a drain terminal connected to the drain terminal of the sixth NMOS transistor and a gate terminal connected to the drain terminal of the eighth PMOS transistor; The eleventh NMOS transistor includes a drain terminal connected to the drain terminal of the seventh NMOS transistor and a gate terminal connected to the drain terminal of the ninth PMOS transistor; and The twelfth NMOS transistor is connected between the third node and the ground node, and includes a gate terminal connected to the terminal into which the operating clock signal is input.

11. The comparator circuit as claimed in claim 10, wherein, In the offset calibration mode, one of the sixth PMOS transistor and the seventh PMOS transistor is configured to repeatedly turn on and off, and the other of the sixth PMOS transistor and the seventh PMOS transistor is configured to turn off.

12. The comparator circuit as claimed in claim 11, wherein, In the offset calibration mode, when the voltage level of the gate terminal of the eighth NMOS transistor is higher than the voltage level of the gate terminal of the ninth NMOS transistor, the threshold voltage level of the sixth PMOS transistor decreases.

13. The comparator circuit as claimed in claim 11, wherein, In the offset calibration mode, when the voltage level at the gate terminal of the ninth NMOS transistor is higher than the voltage level at the gate terminal of the eighth NMOS transistor, the seventh PMOS transistor is configured to have degraded performance outside the reference performance range, and the sixth PMOS transistor is configured to have maintained performance within the reference performance range.

14. The comparator circuit as claimed in claim 10, wherein, In the offset calibration mode: When the voltage level at the gate terminal of the eighth NMOS transistor is higher than the voltage level at the gate terminal of the ninth NMOS transistor, the sixth PMOS transistor is configured to repeatedly turn on and off, and the seventh PMOS transistor is configured to turn off. When the voltage level at the gate terminal of the ninth NMOS transistor is higher than the voltage level at the gate terminal of the eighth NMOS transistor, the sixth PMOS transistor is configured to be turned off, and the seventh PMOS transistor is configured to repeatedly turn on and off.

15. The comparator circuit as claimed in claim 1, wherein, The comparator circuit is configured as follows: During the manufacturing process of the comparator circuit, the offset calibration operation is performed in the offset calibration mode, and After the manufacturing process of the comparator circuit, normal operation is performed in the normal mode.

16. The comparator circuit of claim 1, further comprising: A switch is connected between an input terminal to which the first input signal is input and an input terminal to which the second input signal is input. The switch is configured to open in the normal mode and close in the offset calibration mode based on the control signal.

17. A method of operating a comparator circuit including at least one transistor, the method comprising: Determine whether the operating mode of the comparison circuit is offset calibration mode or normal mode; When the operating mode of the comparison circuit is the offset calibration mode, the offset calibration operation is performed by degrading the at least one transistor based on a first input signal and a second input signal having the same voltage level and an operating clock signal. as well as When the operating mode of the comparator circuit is the normal mode, normal operation is performed based on the first input signal and the second input signal with different voltage levels and the operating clock signal.

18. The method of claim 17, wherein, Performing the normal operation includes: The first clock signal is output based on the control signal as the operation clock signal; Receives a first input signal and a second input signal with different voltage levels; and The first output signal is generated based on the first input signal, the second input signal, and the first clock signal.

19. The method of claim 17, wherein, Performing the offset calibration operation includes: The second clock signal is output based on the control signal as the operation clock signal; Receives a first input signal and a second input signal having the same voltage level; and The first output signal is generated based on the first input signal, the second input signal, and the second clock signal.

20. A comparator circuit, comprising: A comparator includes at least one transistor and is configured to generate a first output signal based on a first input signal, a second input signal, and an operating clock signal; as well as The multiplexer is configured as follows: In normal mode, a first clock signal is output based on the control signal as the operation clock signal; In offset calibration mode, a second clock signal, different from the first clock signal, is output as the operation clock signal based on the control signal. In the offset calibration mode, the first input signal and the second input signal have the same voltage level. The comparator includes: A first p-channel metal-oxide-semiconductor PMOS transistor and a second PMOS transistor are connected in parallel between a terminal from which a power supply voltage is applied and a terminal from which the first output signal is output. The first PMOS transistor includes a gate terminal connected to a terminal from which the operating clock signal is input, and the second PMOS transistor includes a gate terminal connected to a terminal from which the second output signal is output. A third PMOS transistor and a fourth PMOS transistor are connected in parallel between the terminal from which the power supply voltage is applied and the terminal from which the second output signal is output. The third PMOS transistor includes a gate terminal connected to the terminal from which the first output signal is output, and the fourth PMOS transistor includes a gate terminal connected to the terminal from which the operating clock signal is input. A first n-channel metal-oxide-semiconductor (NMOS) transistor and a second NMOS transistor are connected in series between a terminal from which the second output signal is output and a first node. The first NMOS transistor includes a gate terminal connected to the terminal from which the first output signal is output, and the second NMOS transistor includes a gate terminal connected to the terminal into which the first input signal is input. A third NMOS transistor and a fourth NMOS transistor are connected in series between the terminal from which the first output signal is output and the first node. The third NMOS transistor includes a gate terminal connected to the terminal from which the second output signal is output, and the fourth NMOS transistor includes a gate terminal connected to the terminal into which the second input signal is input. A fifth NMOS transistor is connected between the first node and the ground node, and includes a gate terminal connected to the terminal into which the operating clock signal is input. In the offset calibration mode, when the voltage level at the gate terminal of the second NMOS transistor is higher than the voltage level at the gate terminal of the fourth NMOS transistor, the comparator circuit is configured to cause the second PMOS transistor to have a reduced threshold voltage. The comparison circuit is configured as follows: During the manufacturing process of the comparator circuit, an offset calibration operation is performed in the offset calibration mode, and After the manufacturing process of the comparator circuit, normal operation is performed in the normal mode.

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