Method and device for generating jittering frequency clock signal

Abstract

The invention provides a frequency jittering clock signal generation method and device, and relates to the technical field of electronics. The method comprises the following steps: acquiring target jitter frequency parameters including a jitter frequency center frequency, a jitter frequency mode and a jitter frequency width; a modulation signal and a source clock signal are determined according to the target jitter frequency parameter, the amplitude of the modulation signal changes along with time, and the amplitude change range of the modulation signal is configured to enable the first-order sigma-delta modulator to work in an unsaturated linear response area; inputting the modulation signal to a first-order sigma-delta modulator, and under the driving of the source clock signal, performing pulse density modulation on the modulation signal by the first-order sigma-delta modulator and outputting a unit pulse density modulation code stream; and carrying out edge detection on the unit pulse density modulation code stream to generate a jittering frequency clock signal. According to the technical scheme, a complex phase-locked loop circuit is replaced by a scheme which is extremely simple in structure and is completely realized by digital logic, and the problem of balancing the integration level, the cost and the signal purity is synchronously solved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more specifically, to a method and apparatus for generating a frequency-dithered clock signal. Background Technology

[0002] Loads such as motors driven by pulse width modulation (PWM) generate significant electromagnetic interference (EMI) during rapid switching. To suppress EMI, the industry widely employs frequency dithering technology, which involves regularly shifting the frequency of the drive clock signal by small, regular offsets around a set center frequency, thereby spreading the concentrated spectral energy and reducing peak interference.

[0003] Currently, mainstream clock signal generation schemes rely on phase-locked loop (PLL) circuits. This scheme typically uses a phase modulation function to control the PLL, causing its output signal frequency to fluctuate around a set center frequency in accordance with this function. However, using an analog PLL usually requires external passive components such as capacitors, which not only hinders high-level chip integration but also increases system cost and physical area. While using a fully digital PLL avoids external analog components, its circuit structure is inherently more complex, and it is prone to introducing frequency spurious signals and output timing jitter during dynamic frequency switching, thus affecting the quality and stability of the final output clock signal.

[0004] Therefore, existing PLL-based frequency dithering solutions struggle to achieve a good balance in three key dimensions: chip integration, manufacturing cost, and output signal purity. Consequently, finding a simpler, more easily integrated method that can output a stable frequency dithering clock signal to replace the traditional PLL solution has become a pressing technical problem in this field. Summary of the Invention

[0005] The purpose of this application is to provide a method and apparatus for generating a jitter clock signal, which can replace the complex phase-locked loop circuit with a scheme that is extremely simple in structure and completely implemented by digital logic, and simultaneously solve the problem of balancing integration, cost and signal purity.

[0006] This application is implemented as follows: In a first aspect, this application provides a method for generating a jitter clock signal, comprising the following steps: obtaining target jitter parameters, the target jitter parameters including jitter center frequency, jitter mode, and jitter width; determining a modulation signal and a source clock signal based on the target jitter parameters, wherein the amplitude of the modulation signal varies with time, and its amplitude variation range is configured to enable a first-order Sigma-Delta modulator to operate in a non-saturated linear response region; inputting the modulation signal into the first-order Sigma-Delta modulator, and under the drive of the source clock signal, performing pulse density modulation on the modulation signal and outputting a unit pulse density modulated bitstream; performing edge detection on the unit pulse density modulated bitstream to generate a jitter clock signal, wherein the instantaneous frequency of the jitter clock signal varies with the amplitude of the modulation signal.

[0007] Secondly, this application provides a device for generating a jitter clock signal, comprising: a parameter access interface unit configured to: acquire target jitter parameters, the target jitter parameters including a jitter center frequency, a jitter mode, and a jitter width; a modulation signal generator unit configured to: determine a modulation signal based on the target jitter parameters, the amplitude of the modulation signal varying with time, and the amplitude variation range being configured to enable a first-order Sigma-Delta modulator unit to operate in a non-saturated linear response region; a clock source unit configured to: provide a source clock signal based on the target jitter parameters; a first-order Sigma-Delta modulator unit configured to: perform pulse density modulation on the modulation signal under the drive of the source clock signal and output a unit pulse density modulated code stream; and an edge detection unit configured to: perform edge detection on the unit pulse density modulated code stream to generate a jitter clock signal.

[0008] Compared with the prior art, this application has at least the following advantages or beneficial effects: This application proposes a simpler, purely digital method for generating a dithered clock signal by replacing the traditional phase-locked loop circuit with a first-order Sigma-Delta modulator. The method primarily involves converting the target dithering parameters into a dynamically changing modulation signal, then encoding the amplitude information of this modulation signal into pulse density using Sigma-Delta modulation technology, and finally recovering the frequency-controllable dithered clock signal from the pulse sequence.

[0009] Since the entire process eliminates the need for phase-locked loops (PLLs) and their associated analog passive components or complex digital control loops, primarily consisting of digital logic and a first-order Sigma-Delta modulator core, the circuit structure implementing this method is greatly simplified, making it very easy to integrate into modern digital chips and effectively reducing chip area and manufacturing costs. Furthermore, by avoiding the use of PLLs, which are prone to frequency spuriousness and timing jitter during dynamic frequency modulation, and by ensuring conversion accuracy by limiting the modulation signal to the linear region, the final generated jittered clock signal exhibits higher spectral purity and timing stability. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of an embodiment of a method for generating a frequency-dithered clock signal according to this application; Figure 2 This is a spectrum diagram of a 4MHz source square wave clock and the generated jitter clock signal in one embodiment of this application; Figure 3 This is a spectrum diagram of a 1MHz square wave clock signal with a 25% duty cycle and the generated jitter clock signal in one embodiment of this application. Figure 4 This is a graph showing the amplitude-frequency curves of a 1MHz square wave clock signal with a 25% duty cycle and the generated jitter clock signal in one embodiment of this application. Figure 5 This is an amplitude-frequency curve of a 1MHz square wave clock signal with a 25% duty cycle and a generated jitter clock signal, as shown in another embodiment of this application. Figure 6 This is a structural block diagram of an embodiment of a frequency-dithering clock signal generation device according to this application.

[0012] Icons: 101, Parameter access interface unit; 102, Modulation signal generator unit; 103, Clock source unit; 104, First-order Sigma-Delta modulator unit; 105, Edge detection unit. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0014] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0015] In many electronic systems, loads driven by pulse width modulation (PWM), such as motors, generate strong electromagnetic interference (EMI). To suppress this EMI, an effective technique is frequency dithering, which involves regularly shifting the frequency of the driving clock signal by small, regular offsets around a set center frequency, thereby spreading the concentrated spectral energy and reducing peak interference.

[0016] Currently, mainstream clock signal generation schemes rely on phase-locked loop (PLL) circuits. However, in the process of developing this application, the inventors discovered that neither analog nor fully digital PLLs can simultaneously meet the requirements of high integration, low cost, and high output signal quality. Specifically, using an analog PLL requires external passive components, which is detrimental to the requirements of high integration and low cost; while using a fully digital PLL avoids external passive components, its circuit structure is inherently more complex and prone to frequency spurious signals and jitter, thus affecting the quality and stability of the final output clock signal.

[0017] To address the aforementioned contradictions, this application abandons the traditional phase-locked loop (PLL) approach and proposes a novel digital implementation architecture based on a first-order Sigma-Delta modulator. The core idea is as follows: First, obtain specific target dithering parameters according to application requirements; then, based on these target dithering parameters, collaboratively determine a dynamically changing modulation signal and a fixed-frequency source clock signal, where the amplitude of the modulation signal is carefully configured to ensure that the subsequent first-order Sigma-Delta modulator operates in the ideal linear region; next, use the source clock signal to drive the first-order Sigma-Delta modulator to perform pulse density modulation (PDM) on the input modulation signal, converting it into a one-bit PDM bitstream; finally, by performing simple edge detection on this unit PDM bitstream, the required dithering clock signal can be directly generated. In this process, the instantaneous frequency change of the dithering clock signal is entirely determined by the amplitude change of the modulation signal, thus replacing the complex PLL circuit with an extremely simple structure implemented entirely by digital logic, simultaneously solving the balance problem of integration density, cost, and signal purity.

[0018] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0019] Please see Figure 1 The method for generating this jitter clock signal includes the following steps: Step S101: Obtain target dithering parameters, which include dithering center frequency, dithering mode, and dithering width.

[0020] In step S101 above, the specific and complete parameters—namely, the center frequency, dithering mode, and dithering width—can be obtained through preset configuration, interface settings, or reception from the upper-level system. These three parameters collectively define the core spectral characteristics and variation patterns of the final required dithered clock signal. This ensures that customized dithered clock signals can be flexibly generated according to different electromagnetic interference suppression requirements.

[0021] Step S102: Determine the modulation signal and the source clock signal according to the target dithering parameters. The amplitude of the modulation signal changes with time, and its amplitude variation range is configured to make the first-order Sigma-Delta modulator operate in the non-saturated linear response region.

[0022] After obtaining the target dithering parameters in step S101, step S102 utilizes these parameters to complete two tasks: First, it generates (or determines, or selects) a modulation signal whose amplitude varies over time. The waveform (variation pattern) and amplitude range of this modulation signal directly determine how the frequency of the subsequently generated dithering clock signal dithers around the dithering center frequency and the amplitude of the dithering. Specifically, the amplitude range of the modulation signal is actively configured to ensure that it does not cause the subsequent first-order Sigma-Delta modulator to enter the saturation region, but rather operates in its non-saturated linear response region. Second, it generates (or determines, or selects) a source clock signal with a specific frequency. The frequency of this source clock signal is associated with the target dithering parameters (especially the dithering center frequency and dithering mode), and it will serve as the operating clock for the first-order Sigma-Delta modulator in step S103.

[0023] In other words, step S102 above transforms the frequency jitter requirement into a precise design of the waveform and amplitude of the modulation signal, limiting it to the linear response region of the first-order Sigma-Delta modulator. This avoids additional distortion and noise introduced by the modulator's saturation nonlinearity, thus ensuring the accuracy and linearity of frequency modulation.

[0024] For example, in practical applications, the source clock signal can be a square wave pulse signal directly provided by an oscillator circuit, an external crystal oscillator, or a frequency divider.

[0025] Step S103: Input the modulation signal to a first-order Sigma-Delta modulator, and under the drive of the source clock signal, the first-order Sigma-Delta modulator performs pulse density modulation on the modulation signal and outputs a unit pulse density modulated code stream.

[0026] In step S103 above, the first-order Sigma-Delta modulator performs pulse density modulation on the input modulation signal based on the principles of oversampling and noise shaping. Its output is no longer a signal with continuously varying amplitude or frequency, but a high-speed unit pulse density modulated code stream containing only two logic levels: "0" and "1". In this code stream, the average density of "1" levels (i.e., pulse density) is proportional to the instantaneous amplitude of the modulation signal.

[0027] In other words, by utilizing the mature circuit structure of a first-order Sigma-Delta modulator, the amplitude information of a continuously varying modulation signal is encoded into the pulse density of a unit pulse density modulation bitstream in a fully digital manner with high precision. This conversion process does not rely on complex frequency synthesis techniques such as phase-locked loops, simplifying the circuit architecture. Simultaneously, the inherent noise shaping characteristics of Sigma-Delta modulation help push quantization noise to higher frequencies, which is beneficial for improving the signal-to-noise ratio in the low-frequency (i.e., signal bandwidth) range.

[0028] It should be noted that the modulation of the first-order Sigma-Delta modulator in this application is essentially a pulse density modulation. For different inputs, the output will generate different high and low level densities, with the input range being -1 to 1. If the input is 1, the output will be 100% high; if the input is -1, the output will be 100% low; if the input is 0, the output will alternate between 50% high and 50% low; if the input is 0.5, the output will alternate between 75% high and 25% low.

[0029] Step S104: Perform edge detection on the unit pulse density modulated code stream to generate a jitter clock signal, wherein the instantaneous frequency of the jitter clock signal changes with the amplitude of the modulation signal.

[0030] In step S104 above, edge detection is performed on the unit pulse density modulated bitstream output in step S103 (typically detecting rising edges from "0" to "1"). Each time a valid edge is detected, a standard, regular clock pulse is generated. Since the pulse density in the unit pulse density modulated bitstream varies with the amplitude of the modulating signal, the interval between detected edges also varies accordingly. Ultimately, these edges are converted into a series of clock pulses with continuously small periodic (frequency) variations, i.e., a jitter clock signal. The instantaneous frequency of this jitter clock signal strictly follows the instantaneous amplitude variation of the modulating signal.

[0031] In this way, the abstract pulse density information can be restored (converted) into a standard clock signal that can be directly recognized and used in actual circuits (such as microcontrollers and driver chips). The circuit implementation of this S104 step is extremely simple (for example, a D flip-flop can be used to form the corresponding edge detector), and the final output jitter clock signal has clear and clean edges, ensuring its driving capability and timing quality as a clock signal. It can be directly used to drive loads such as pulse width modulation controllers to achieve the purpose of EMI suppression.

[0032] In summary, this application provides a simpler, purely digital dithering clock signal generation scheme by replacing the traditional phase-locked loop circuit with a first-order Sigma-Delta modulator. It primarily involves converting the target dithering parameters into a dynamically changing modulation signal, then encoding the amplitude information of this modulation signal into pulse density using Sigma-Delta modulation technology, and finally recovering the frequency-controllable dithering clock signal from the pulse sequence.

[0033] Specifically, this application first requires obtaining clear target dithering parameters, including the desired dithering center frequency, the desired dithering mode, and the dithering width. These parameters are the basis for all subsequent signal generation and processing. Next, based on these parameters, two key signals are collaboratively determined: one is the source clock signal, which provides the basic working clock for the entire processing flow; the other is the modulation signal, whose amplitude changes as needed over time, and whose range is specifically limited to the linear operating region of a first-order Sigma-Delta modulator to avoid nonlinear distortion. Then, the modulation signal is input into the first-order Sigma-Delta modulator, driven by the source clock signal. This first-order Sigma-Delta modulator performs pulse density modulation on the input modulation signal, outputting a high-speed unit pulse density modulated bitstream, where the density of "1"s is proportional to the instantaneous amplitude of the modulation signal. Finally, by performing simple edge detection (such as detecting rising edges) on this bitstream, the final dithering clock signal is generated. Since the pulse density of the bitstream changes with the amplitude of the modulation signal, the detected edge interval also changes accordingly, thus enabling the instantaneous frequency of the output clock to dynamically jitter precisely following the amplitude of the modulation signal.

[0034] In other words, this application completely eliminates the complex phase-locked loop (PLL) circuits found in traditional solutions, thereby fundamentally solving problems such as low chip integration, high cost, or spurious signals and jitter in the output signal caused by using PLLs. For example, since the entire processing flow can be implemented using standard digital logic units, this solution is very easy to integrate into modern digital chips, while simultaneously generating a stable and controllable jittered clock signal, effectively meeting the application requirements for suppressing electromagnetic interference.

[0035] Based on the aforementioned scheme, in some implementations of this application, the modulation signal is generated by superimposing periodically changing components and randomly changing components; wherein, the periodically changing components have configurable amplitude, period, and offset; and the randomly changing components have configurable distribution range.

[0036] The above implementation decomposes the modulated signal into independently configurable periodically varying components and randomly varying components, and then superimposes them, resulting in a final frequency dithering effect that combines regularity and randomness. Specifically, in this implementation, the modulated signal is composed of two signal components with different sources and characteristics. One component is a periodically varying component, whose waveform exhibits regular, repetitive fluctuations over time. This periodically varying component has three key configurable parameters: the amplitude determines the intensity of its fluctuations, the period determines the speed of its fluctuations, and the offset determines the reference position of the entire waveform on the vertical axis. The other component is a randomly varying component, whose amplitude changes without a fixed period, but fluctuates randomly within a certain range, which is its configurable distribution range. In practical applications, these two components are superimposed to form the final modulated signal input to a first-order Sigma-Delta modulator.

[0037] It should be noted that the combination of periodicity and random perturbation in the above implementation allows the solution to adapt to more complex or demanding application scenarios. This is because the periodic variation component allows for precise control of the main patterns, amplitude, and speed of frequency jitter in the jittered clock signal, thus meeting specific electromagnetic interference suppression spectral requirements. Simultaneously, introducing random variation components effectively disperses discrete spectral spurious signals that may be generated by purely periodic jitter, resulting in a smoother and more continuous spectral energy distribution of the output clock. This further optimizes the overall electromagnetic interference suppression effect and may reduce the risk of interference at specific frequency points.

[0038] Based on the aforementioned scheme, in some implementations of this application, the periodic variation component is a triangular wave signal.

[0039] It's important to note that a triangular wave is a linearly changing periodic signal. Its amplitude rises uniformly to its maximum value over time, then decreases uniformly to its minimum value, repeating this cycle. Because triangular wave signals are easy to generate and precisely control in digital circuits, their amplitude, period, and offset can be easily adjusted, simplifying subsequent circuit design. For example, changing the amplitude of the triangular wave directly and linearly adjusts the width of the jitter, while changing its period adjusts the jitter frequency (i.e., the sweep speed). Furthermore, the jitter clock signal generated by linear sweeping typically has a more uniform and predictable spectral energy distribution, contributing to stable and efficient electromagnetic interference suppression. Compared to other complex waveforms, the triangular wave achieves a good balance between implementation complexity and spectral performance.

[0040] Based on the aforementioned scheme, in some implementations of this application, the amplitude variation range of the modulation signal satisfies the following relationship: amp + bias + σ < 1, where amp is the amplitude of the periodically changing component, bias is the offset of the periodically changing component, σ is the distribution range of the random changing component [-σ, σ], and amp, bias and σ are all numbers greater than zero.

[0041] Understandably, the above implementation ensures reliable and linear operation of the entire scheme by setting an explicit inequality constraint for the parameter configuration of the modulation signal. In other words, by quantizing and limiting the combination of the amplitude and offset of the periodically changing components and the distribution range of the randomly changing components, it can prevent the modulation signal amplitude from exceeding the limit, thus preventing the first-order Sigma-Delta modulator from failing. Specifically, if the jitter center frequency of the jitter clock signal is defined as f, then the jitter range of the jitter clock signal output by the first-order Sigma-Delta modulator is as follows: (1 - (+amp + σ + bias)) × f to (1 - (-amp - σ + bias)) × f.

[0042] In other words, this constraint in the above implementation ensures that the first-order Sigma-Delta modulator always operates within its non-saturated linear response region. It should be noted that if the amplitude of the modulated signal is too large, exceeding the input range of the first-order Sigma-Delta modulator, it will cause its internal integrator to saturate, the quantizer to continuously output limit values, thus losing its ability to track the input signal. The output unit pulse density modulated bitstream will not accurately reflect the changes in the modulated signal, ultimately leading to the failure of the dithering function or severe distortion. By satisfying the above inequality, it can be ensured that even when the peak of the periodically changing component is superimposed with the maximum positive value of the random changing component, the amplitude of the synthesized modulated signal will not overload the first-order Sigma-Delta modulator, thereby maintaining the linearity and fidelity of the entire signal link. This lays a solid foundation for the stable and controllable generation of high-quality dithered clock signals.

[0043] Based on the aforementioned scheme, in some implementations of this application, determining the modulation signal according to the target dithering parameters includes: determining the amplitude of the periodically changing component according to the dithering width; determining the period of the periodically changing component according to the amplitude attenuation requirement of the dithering center frequency; determining the offset of the periodically changing component according to the dithering mode; and determining the distribution range of the random changing component according to the noise optimization requirements.

[0044] Understandably, the above implementation method establishes a clear set of parameter mapping rules to specifically transform the abstract target dithering parameters into executable modulation signal component parameters, thereby achieving precise and convenient engineering control of the dithering effect.

[0045] Specifically, in practical applications, after obtaining the target dithering parameters, it is necessary to determine the detailed composition of the modulation signal. This implementation provides specific decomposition steps: First, the dithering width directly determines the amplitude of the periodic variation component; the larger the dithering width, the larger the required amplitude is usually. Second, the desired amplitude attenuation at the dithering center frequency (an indicator of electromagnetic interference suppression effectiveness) is used to determine the period of the periodic variation component; the size of the period directly affects the energy attenuation depth at the center frequency. Third, the specific function type of the periodic variation classification determines the shape of the spectrum unfolding; for example, using a triangular wave results in a rectangular unfolding, while using a sine wave results in a shape that is high on both sides and low in the middle. The dithering mode (e.g., up-dithering, down-dithering, or bilateral dithering) determines the offset of the periodic variation component; by setting different offsets, the overall frequency dithering range can be shifted. Finally, based on the optimization requirements for the output signal noise level, the distribution range of the random variation component is determined to add an appropriate amount of random perturbation to the regular dithering to optimize the spectrum.

[0046] This mapping rule allows engineers to directly derive and set the internal parameters of the modulation signal based on the desired dithering performance metrics (width, attenuation, mode, noise), avoiding tedious trial and error and complex theoretical calculations.

[0047] Based on the aforementioned scheme, in some implementations of this application, the period of the periodic variation component, the dithering width, and the amplitude attenuation of the dithering center frequency satisfy the following relationship: ;in, This represents the amplitude attenuation at the center frequency of the dithering. For dithering width, The period is the period of the periodically changing component.

[0048] The above implementation provides a quantitative relationship that directly links the core parameters of the periodically changing component to the core indicators of the final dithering effect, facilitating accurate prediction and design of subsequent dithering performance. In other words, by establishing a mathematical relationship between the period of the periodically changing component, the dithering width, and the amplitude attenuation of the dithering center frequency, this implementation provides a direct design criterion for engineering applications. Using this relationship, designers can directly calculate the required period of the periodically changing component based on the required amplitude attenuation of the dithering center frequency and the determined dithering width, or vice versa.

[0049] Based on the aforementioned scheme, in some implementations of this application, the amplitude of the modulation signal is configured to dynamically change within the range of [-1, +1]. The step of determining the modulation signal and the source clock signal according to the target dithering parameters includes: if the dithering mode is a lower dithering mode, then the frequency of the source clock signal is determined to be twice the dithering center frequency, and the offset of the modulation signal is set to 0; if the dithering mode is a double-sided dithering mode, then the frequency of the source clock signal is determined to be four times the dithering center frequency, and the absolute value of the offset of the modulation signal is set to 0.5; if the dithering mode is an upper dithering mode, then the frequency of the source clock signal is determined to be four times the dithering center frequency, and the offset of the modulation signal is set to 0.

[0050] It should be noted that the above implementation provides a standardized and efficient implementation path for the three basic frequency dithering modes by establishing specific configuration rules between the dithering mode, the source clock signal frequency, and the modulation signal offset. In other words, by mapping different target frequency dithering modes to a set of defined combinations of source clock frequency and modulation signal offset parameters, the above implementation simplifies the configuration and ensures the correctness of the dithering effect under different modes. This avoids complex parameter calculations and trial and error, ensuring that accurate and expected frequency dithering clock signals can be generated under different modes, thus improving the ease of use and reliability of the solution.

[0051] Specifically, in this implementation, it is first clarified that the amplitude of the modulation signal varies within the range of [-1, +1] under normalized design. Based on this, specific parameter settings are given for each dithering mode. If the target dithering mode is a down-dithering mode (for example, the dithering range is f-), The frequency range is between f and f, where f is the center frequency of the jitter clock signal. If the frequency jitters only below the center frequency (where the jitter width is specified), then the source clock signal frequency is configured to be twice the jitter center frequency, while the modulation signal offset is set to 0. If the target jitter mode is a dual-sided jitter mode (for example, the jitter range is f-), then... / 2 to f+ If the frequency fluctuates symmetrically around the center frequency (between f and f2), then the frequency of the source clock signal is configured to be four times the center frequency of the frequency fluctuation, and the absolute value of the offset of the modulation signal is set to 0.5. If the target frequency fluctuation mode is an up-frequency fluctuation mode (for example, the frequency fluctuation range is between f and f+), then the frequency of the source clock signal is configured to be four times the center frequency of the frequency fluctuation, and the absolute value of the offset of the modulation signal is set to 0.5. If the frequency jitters only above the center frequency (between / 2), then the frequency of the source clock signal is also four times the jitter center frequency, but the offset of the modulation signal is set to 0.

[0052] Based on the aforementioned scheme, in some implementations of this application, the step of pulse density modulation of the modulation signal by the first-order Sigma-Delta modulator and outputting a unit pulse density modulated code stream includes: calculating the error between the modulation signal and a feedback value, wherein, in the first iteration, the feedback value is an initial value, and in subsequent iterations, the feedback value is a value determined based on the output of the previous iteration; accumulating the error to obtain an accumulated value; quantizing the accumulated value, outputting a first logic level as the current output when the accumulated value is greater than a first threshold, and outputting a second logic level as the current output when the accumulated value is less than a second threshold, and forming the unit pulse density modulated code stream based on the current output; and determining the feedback value for the next iteration based on the current output.

[0053] It is understandable that the above implementation method, by decomposing and explaining the complete iterative process of error calculation, integration, quantization and feedback loop contained in the modulator, enables those skilled in the art to accurately understand how frequency jitter information is encoded into pulse density, and provides clear step-by-step guidance for circuit implementation or digital logic synthesis.

[0054] In practical applications, a first-order Sigma-Delta modulator performs one iteration within each source clock cycle. First, it calculates the difference between the current input modulated signal and a feedback value to obtain the error. In the initial iteration, the feedback value can be a preset initial value; subsequent feedback values ​​are determined by the output of the previous iteration. Then, this error is added to the accumulated historical error to obtain a new accumulated value. Next, this new accumulated value is quantized: if it is greater than a first threshold (e.g., 0), a first logic level representing "positive" (e.g., "1") is output; if it is less than a second threshold (e.g., 0), a second logic level representing "negative" (e.g., "0") is output. This output level constitutes the current bit of the unit pulse density modulated bitstream. Finally, the feedback value for the next iteration is determined based on this current output value, thus forming a closed-loop system.

[0055] Furthermore, the circuit construction of a first-order Sigma-Delta modulator may include the following: a subtractor for calculating the error between the input modulator and the feedback value; an accumulator for accumulating the error output of the subtractor; a 1-bit quantizer for quantizing the result of the accumulator by 1 bit; if the result is greater than 0, the quantizer outputs 1; if the result is less than 0, the quantizer outputs 0; and a 1-bit digital-to-analog converter for processing the quantization result into a +1 / -1 feedback value subtractor.

[0056] Based on the aforementioned scheme, in some implementations of this application, the mathematical expression for the change of the instantaneous frequency of the jitter clock signal with the amplitude of the modulation signal is as follows: ,in, The instantaneous frequency of the jitter clock signal. The frequency of the source clock signal, The normalized instantaneous amplitude of the modulated signal is given by [the normalized value]. .

[0057] Understandably, the above implementation method, by providing a clear mathematical relationship, quantitatively reveals the core principle that the frequency of the dithering clock signal is controlled by the amplitude of the modulation signal, enabling direct calculation from design parameters to output performance. This avoids reliance on experience or simulation, ensuring that the dithering function is implemented on a rigorous mathematical foundation that is calculable and predictable, greatly improving the accuracy and reliability of the design.

[0058] To provide a more intuitive understanding of this application for those skilled in the art, a specific example will be used for illustration. In this example, the desired dithering clock signal has a dithering center frequency of 1MHz, a dithering width of 200kHz, a dithering mode of bilateral dithering, and a required amplitude attenuation of 20dB at the 1MHz center frequency. It should be noted that, for the purpose of demonstrating the technical solution of this application in more detail, the target dithering parameters in this example also include the amplitude attenuation requirement at the center frequency. However, in actual application of the solution of this application, it can be determined whether to set this target as needed. That is, the following example is intended to aid understanding and does not constitute an exhaustive list of all embodiments of this application, nor does it mean that this application must include all the details described below in its specific implementation.

[0059] The method flow in this example is as follows: First, based on the target dithering parameters mentioned above, the modulation signal and the source clock signal are determined. In this example, the frequency of the source clock signal is determined to be 4MHz. After determining the frequency of the source clock signal, the bias of the modulation signal can be further determined to be 0.5 based on the dithering center frequency of the dithering clock signal and the frequency of the source clock signal, according to the scheme configuration rules. Figure 2 As shown ( Figure 2 The 4MHz source square wave clock signal in the example is the 4MHz source clock signal mentioned above, and the generated dithered clock signal is the dithered clock signal generated by the technical solution of this application in the example above. When the input of the first-order Sigma-Delta modulator is fixed at 0.5, its output unit pulse density modulated code stream can obtain a clock signal with a frequency of 1MHz (i.e., a quarter source clock frequency) after edge detection. Figure 3 A comparison was made in the frequency domain of a directly generated 1MHz pulse clock with a 25% duty cycle, and the spectral performance was basically the same. It should be noted that... Figure 3The comparison shows the spectral curves of a 1MHz square wave clock signal with a 25% duty cycle and the dithered clock signal generated by the technical solution of this application in the example above.

[0060] Then, based on a jitter width of 200kHz, the single-sided jitter range can be calculated to be 100kHz. Refer to the instantaneous frequency calculation formula for the jitter clock signal. This allows us to determine the required amplitude change of the modulation signal when the unilateral offset is 0.1, and thus determine the amplitude amp of the periodic component (triangular wave) to be 0.05. Finally, based on the desired 20dB amplitude attenuation requirement, combined with the formula... The period of the periodic component can be calculated as T = 1 / 1000 seconds. Figure 4 The frequency domain response of the final jittered clock signal is shown when the modulation signal is a triangular wave. It can be seen that the center frequency and its harmonics all produce the expected jittering effect. It should be noted that... Figure 4 The 1MHz square wave clock signal with a 25% duty cycle shown is a signal compared with the final generated jitter clock signal. The generated jitter clock signal (modulation signal is only a triangular wave) refers to the final generated jitter clock signal when the modulation signal is a triangular wave.

[0061] Meanwhile, to optimize the noise within the frequency band from 0 to the center frequency of the jittering, the distribution range parameter σ of the random variation component is set to 0.001 (generally taken as 0%-4% of the amp value, 2% here), meaning its actual distribution is [-0.001, 0.001]. The final generated jittering clock signal spectrum effect is as follows: Figure 5 As shown. It should be noted that, Figure 5 The 1MHz 25% duty cycle square wave clock signal shown is a signal compared with the final generated jitter clock signal. The generated jitter clock signal (modulation signal is only a triangular wave) refers to the final generated jitter clock signal when the modulation signal is a triangular wave. The generated jitter clock signal (modulation signal is a triangular wave + random function) refers to the final generated jitter clock signal when the modulation signal is a triangular wave plus a random function superposition.

[0062] Please see Figure 6This application embodiment also provides a jitter clock signal generation device, comprising: a parameter access interface unit 101 configured to: acquire target jitter parameters, the target jitter parameters including jitter center frequency, jitter mode and jitter width; a modulation signal generator unit 102 configured to: determine a modulation signal according to the target jitter parameters, the amplitude of the modulation signal changing with time, and the amplitude change range being configured to make a first-order Sigma-Delta modulator unit 104 operate in a non-saturated linear response region; a clock source unit 103 configured to: provide a source clock signal according to the target jitter parameters; a first-order Sigma-Delta modulator unit 104 configured to: perform pulse density modulation on the modulation signal under the drive of the source clock signal and output a unit pulse density modulation code stream; and an edge detection unit 105 configured to: perform edge detection on the unit pulse density modulation code stream to generate a jitter clock signal.

[0063] For the specific implementation process of the above system, please refer to the method for generating a jitter clock signal provided in the above embodiment, which will not be repeated here.

[0064] Based on the aforementioned scheme, in some implementations of this application, the modulation signal is generated by superimposing periodically changing components and randomly changing components; wherein, the periodically changing components have configurable amplitude, period, and offset; and the randomly changing components have configurable distribution range.

[0065] Based on the aforementioned scheme, in some implementations of this application, the periodic variation component is a triangular wave signal.

[0066] Based on the aforementioned scheme, in some implementations of this application, the amplitude variation range of the modulation signal satisfies the following relationship: amp + bias + σ < 1, where amp is the amplitude of the periodically changing component, bias is the offset of the periodically changing component, σ is the distribution range of the random changing component [-σ, σ], and amp, bias and σ are all numbers greater than zero.

[0067] Based on the aforementioned scheme, in some implementations of this application, determining the modulation signal according to the target dithering parameters includes: determining the amplitude of the periodically changing component according to the dithering width; determining the period of the periodically changing component according to the amplitude attenuation requirement of the dithering center frequency; determining the offset of the periodically changing component according to the dithering mode; and determining the distribution range of the random changing component according to the noise optimization requirements.

[0068] Based on the aforementioned scheme, in some implementations of this application, the period of the periodic variation component, the dithering width, and the amplitude attenuation of the dithering center frequency satisfy the following relationship: ;in, This represents the amplitude attenuation at the center frequency of the dithering. For dithering width, The period is the period of the periodically changing component.

[0069] Based on the aforementioned scheme, in some implementations of this application, the amplitude of the modulation signal is configured to dynamically change within the range of [-1, +1]. Determining the modulation signal according to the target dithering parameters and providing the source clock signal according to the target dithering parameters includes: if the dithering mode is a lower dithering mode, then determining that the frequency of the source clock signal is twice the dithering center frequency, and setting the offset of the modulation signal to 0; if the dithering mode is a double-sided dithering mode, then determining that the frequency of the source clock signal is four times the dithering center frequency, and setting the absolute value of the offset of the modulation signal to 0.5; if the dithering mode is an upper dithering mode, then determining that the frequency of the source clock signal is four times the dithering center frequency, and setting the offset of the modulation signal to 0.

[0070] Based on the aforementioned scheme, in some implementations of this application, the first-order Sigma-Delta modulator unit 104 is further configured to: calculate the error between the modulated signal and a feedback value, wherein, in the first iteration, the feedback value is an initial value, and in subsequent iterations, the feedback value is a value determined based on the output of the previous iteration; accumulate the error to obtain an accumulated value; quantize the accumulated value, output a first logic level as the current output when the accumulated value is greater than a first threshold, output a second logic level as the current output when the accumulated value is less than a second threshold, and form the unit pulse density modulated code stream based on the current output; and determine the feedback value for the next iteration based on the current output.

[0071] Based on the aforementioned scheme, in some implementations of this application, the mathematical expression for the change of the instantaneous frequency of the jitter clock signal with the amplitude of the modulation signal is as follows: ,in, The instantaneous frequency of the jitter clock signal. The frequency of the source clock signal, The normalized instantaneous amplitude of the modulated signal is given by [the normalized value]. .

[0072] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for generating a frequency-dithered clock signal, characterized in that, Includes the following steps: Obtain target dithering parameters, which include dithering center frequency, dithering mode, and dithering width; Based on the target dithering parameters, the modulation signal and the source clock signal are determined. The amplitude of the modulation signal varies with time, and its amplitude variation range is configured to make the first-order Sigma-Delta modulator operate in the non-saturated linear response region. The modulation signal is input to a first-order Sigma-Delta modulator, and driven by the source clock signal, the first-order Sigma-Delta modulator performs pulse density modulation on the modulation signal and outputs a unit pulse density modulated code stream. Edge detection is performed on the unit pulse density modulated bitstream to generate a jitter clock signal, the instantaneous frequency of which varies with the amplitude of the modulation signal.

2. The method according to claim 1, characterized in that, The modulated signal is generated by superimposing periodically changing components and randomly changing components; wherein the periodically changing components have configurable amplitude, period, and offset; and the randomly changing components have configurable distribution range.

3. The method according to claim 2, characterized in that, The periodic variation component is a triangular wave signal.

4. The method according to claim 2, characterized in that, The amplitude variation range of the modulation signal satisfies the following relationship: amp + bias + σ < 1, where amp is the amplitude of the periodic variation component, bias is the offset of the periodic variation component, σ is the distribution range of the random variation component [-σ, σ], and amp, bias and σ are all numbers greater than zero.

5. The method according to claim 2, characterized in that, Determining the modulation signal based on the target dithering parameters includes: The amplitude of the periodic variation component is determined based on the dithering width. The period of the periodic variation component is determined based on the amplitude attenuation requirement of the center frequency of the dithering. Based on the dithering pattern, determine the offset of the periodic variation component; Based on the noise optimization requirements, the distribution range of the random variation component is determined.

6. The method according to claim 5, characterized in that, The period of the periodic variation component, the dithering width, and the amplitude attenuation of the dithering center frequency satisfy the following relationship: ;in, This represents the amplitude attenuation at the center frequency of the dithering. For dithering width, The period is the period of the periodically changing component.

7. The method according to claim 1, characterized in that, The amplitude of the modulation signal is configured to dynamically change within the interval [-1, +1]. The step of determining the modulation signal and the source clock signal based on the target dithering parameters includes: If the frequency dithering mode is the lower frequency dithering mode, then the frequency of the source clock signal is determined to be twice the frequency dithering center frequency, and the offset of the modulation signal is set to 0. If the frequency dithering mode is a bilateral frequency dithering mode, then the frequency of the source clock signal is determined to be four times the frequency dithering center frequency, and the absolute value of the offset of the modulation signal is set to 0.

5. If the frequency dithering mode is the upper frequency dithering mode, then the frequency of the source clock signal is determined to be four times the center frequency of the frequency dithering, and the offset of the modulation signal is set to 0.

8. The method according to claim 1, characterized in that, The step of performing pulse density modulation on the modulated signal by the first-order Sigma-Delta modulator and outputting a unit pulse density modulated code stream includes: Calculate the error between the modulated signal and a feedback value, wherein, in the first iteration, the feedback value is an initial value, and in subsequent iterations, the feedback value is a value determined based on the output of the previous iteration; The errors are accumulated to obtain the accumulated value; The accumulated value is quantized, and when the accumulated value is greater than a first threshold, a first logic level is output as the current output; when the accumulated value is less than a second threshold, a second logic level is output as the current output, and the unit pulse density modulated code stream is formed based on the current output. The feedback value for the next iteration is determined based on the current output.

9. The method according to claim 1, characterized in that, The mathematical expression for how the instantaneous frequency of the jitter clock signal changes with the amplitude of the modulation signal is: ,in, The instantaneous frequency of the jitter clock signal. The frequency of the source clock signal. The normalized instantaneous amplitude of the modulated signal is given by [the normalized value]. .

10. A device for generating a frequency-dithered clock signal, characterized in that, include: The parameter access interface unit is configured to: acquire target dithering parameters, the target dithering parameters including dithering center frequency, dithering mode and dithering width; The modulation signal generator unit is configured to: determine a modulation signal based on the target dithering parameters, wherein the amplitude of the modulation signal varies with time, and the amplitude variation range is configured to enable the first-order Sigma-Delta modulator unit to operate in a non-saturated linear response region. The clock source unit is configured to provide a source clock signal according to the target jitter parameters; A first-order Sigma-Delta modulator unit is configured to perform pulse density modulation on the modulation signal under the drive of the source clock signal and output a unit pulse density modulated code stream; An edge detection unit is configured to perform edge detection on the unit pulse density modulated bitstream to generate a jitter clock signal.

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