Time-to-digital converter based on split capacitor and low-jitter digital phase-locked loop

Abstract

The invention discloses a time-to-digital converter based on a split capacitor and a low-jitter digital phase-locked loop. The time-to-digital converter comprises a capacitor array, a time-to-voltage conversion circuit, a charging and discharging power supply and a control signal generation circuit, the control signal generation circuit receives a reference clock and a frequency division clock thereof, and generates a charging control signal and a discharging control signal. The charging and discharging power supply charges and discharges the capacitor array according to the signals, so that residual voltage is formed. The time voltage conversion circuit is electrically connected with the capacitor array, receives the residual voltage and performs multiple quantization operations on the residual voltage. And in each quantization operation, a corresponding residual voltage value is obtained by switching the reference voltage connection state of the capacitor array, a multi-bit digital code word corresponding to the residual voltage is finally obtained, and a conversion completion mark signal is generated and fed back to the control signal generation circuit, so that the noise of the final digital code word is reduced through multiple quantization processes.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop technology, specifically to a time-to-digital converter based on split capacitors and a low-jitter digital phase-locked loop. Background Technology

[0002] Modern wireless communication systems require high-order modulation schemes to achieve high data rates, which places extremely high demands on the phase noise of phase-locked loops (PLLs). Digital PLLs not only exhibit superior robustness under variations in process technology, voltage, and temperature, but also offer higher reconfigurability, smaller chip area, and seamless integration with digital signal processing modules. However, the in-band phase noise of digital PLLs is severely limited by the quantization error of the time-to-digital converter, resulting in higher integral jitter than analog PLLs. Narrowing the performance gap between analog and digital PLLs is a highly promising endeavor, especially as integrated circuit technology advances, continuously improving digital circuit performance while significantly reducing power consumption.

[0003] In recent years, achieving fine time resolution has become a research hotspot in the field of time-to-digital converters (TDCs). Flash-based TDCs are relatively simple to design, but their performance is limited by the inherent delay resolution of the inverters. While vernier-based TDCs can effectively overcome the single-gate delay limitation, the mismatch between delay lines still hinders their practical application. Time-domain noise-shaping TDCs, such as gated ring oscillators and noise-shaping Bang-Bang phase detectors, have the potential to improve TDC resolution. However, the inherent 1-bit quantization characteristic of Bang-Bang phase detectors limits in-band noise performance. Furthermore, increasing the order of time-domain noise shaping faces significant challenges.

[0004] Voltage domain quantization offers an attractive alternative to traditional time-domain (TDC). However, existing voltage domain quantization methods require high resolution, high power consumption, and stringent capacitor matching accuracy. Furthermore, with the introduction of voltage domain quantization, the noise introduced by the time-to-digital converter becomes the primary source of in-band noise, leading to significant noise and unnecessary power consumption. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention discloses a time-to-digital converter based on a split capacitor and a low-jitter digital phase-locked loop, used to reduce noise during the time difference conversion process.

[0006] To achieve the above objectives, the present invention discloses a time-to-digital converter based on split capacitors, comprising a capacitor array, a control signal generation circuit, a time-to-digital conversion circuit, and a charging / discharging power supply; wherein, the output terminal of the capacitor array is electrically connected to the input terminal of the time-to-digital conversion circuit; the control terminal of the capacitor array is signal-connected to the output terminal of the time-to-voltage conversion circuit; and the output terminal of the charging / discharging power supply is electrically connected to the input terminal of the capacitor array. The control signal generation circuit is signal-connected to the time-to-digital converter circuit and is used to receive the conversion completion flag signal fed back by the time-to-digital converter circuit, so as to receive the reference clock signal and the frequency-divided clock signal corresponding to the reference clock signal according to the conversion completion flag signal. The control signal generation circuit generates a charging control signal based on the reference clock signal and a discharging control signal based on the frequency-divided clock signal. The charging and discharging power supply is connected to the control signal generation circuit to charge the capacitor array according to the charging control signal and discharge the capacitor array according to the discharging control signal, so that the capacitor array forms a residual voltage. The input terminal of the time-to-voltage conversion circuit is electrically connected to the output terminal of the capacitor array, and is used to receive the residual voltage and perform multiple quantization operations on the residual voltage to obtain the digital codeword corresponding to each quantization operation, thereby obtaining the multi-bit digital codeword corresponding to the residual voltage and generating the conversion completion flag signal; wherein, the quantization operation includes the time-to-voltage conversion circuit switching the reference voltage connection state of the capacitor array according to the residual voltage to obtain the residual voltage corresponding to each reference voltage connection state.

[0007] This invention discloses a time-to-digital converter based on split capacitors, which achieves accurate conversion of time difference to voltage through a split capacitor structure, reducing quantization errors and power consumption. Specifically, the capacitor array provides the basis for split capacitors, allowing independent control of the charging and discharging processes and reducing capacitor matching requirements. The control signal generation circuit receives a reference clock and a frequency-divided clock based on the conversion completion flag signal to ensure timing synchronization and avoid error accumulation. It then generates a charging control signal corresponding to the reference time signal based on the reference clock and a discharging control signal corresponding to the feedback time signal based on the frequency-divided clock, thus accurately capturing the time difference. The charging and discharging power supply operates the capacitor array according to the charging and discharging control signals respectively, forming a residual voltage representing the time difference information. After receiving the residual voltage, the time-to-voltage conversion circuit dynamically switches the reference voltage connection state through multiple quantization operations, obtaining the residual voltage values ​​under different states, generating a multi-bit digital codeword and a conversion completion flag signal, improving resolution and reducing noise introduction.

[0008] As a preferred example, the capacitor array includes a plurality of mirror-symmetrical charging capacitors and a plurality of discharging capacitors; wherein each of the charging capacitors is connected in series with a charging switch; and each of the discharging capacitors is connected in series with a discharging switch. The lower electrode of the charging capacitor is electrically connected to the fixed terminal of the charging switch; the lower electrode of the discharging capacitor is electrically connected to the fixed terminal of the discharging switch. The first terminal of the charging switch is electrically connected to the positive reference voltage terminal; the second terminal of the charging switch is electrically connected to the negative reference voltage terminal; the third terminal of the charging switch is electrically connected to the output terminal of the charging power supply in the charging and discharging power supply, and is used to receive the charging current of the charging power supply; the first terminal of the discharging switch is electrically connected to the positive reference voltage terminal; the second terminal of the discharging switch is electrically connected to the negative reference voltage terminal; the third terminal of the discharging switch is electrically connected to the output terminal of the discharging power supply in the charging and discharging power supply, and is used to receive the discharging current of the discharging power supply. The control terminal of the third end of the charging switch is connected to the control signal generating circuit for receiving the charging control signal and transmitting the charging current to the charging capacitor according to the charging control signal to charge the charging capacitor. The control terminal of the third end of the discharge switch is connected to the control signal generating circuit for receiving the discharge control signal and transmitting the discharge current to the discharge capacitor according to the discharge control signal to charge the discharge capacitor. The upper plates of each of the charging capacitors are electrically connected to each other to form a charging sensing node; the upper plates of each of the discharging capacitors are electrically connected to each other to form a discharging sensing node; the charging sensing node and the discharging sensing node are respectively electrically connected to the input terminal of the time-to-digital conversion circuit. The charging sensing node acquires the energy of the multiple charging capacitors to form a charging voltage; the discharging sensing node acquires the energy of the multiple discharging capacitors to form a discharging voltage. The charging sensing node and the discharging sensing node serve as the output terminals of the capacitor array to form a residual voltage based on the charging voltage and the discharging voltage, and then transmit the residual voltage to the time-to-digital conversion circuit.

[0009] The above solution solves the noise and power consumption problems caused by capacitor mismatch through mirror symmetry design and independent switching control mechanism, thereby improving the accuracy of residual voltage.

[0010] As a preferred example, the time-to-digital conversion circuit includes a residual integrator; wherein the residual integrator includes a switched capacitor integrator circuit, a floating inverter amplifier, and an output sampling circuit. The input terminal of the switched capacitor integrator circuit is electrically connected to the output terminal of the capacitor array, used to receive the residual voltage, integrate the residual voltage, and output an integrated voltage. The switched capacitor integrator circuit includes a first switch, a second switch, a first capacitor, and a second capacitor. The positive terminal of the first switch is electrically connected to the charging sensing node; the positive terminal of the second switch is electrically connected to the discharging sensing node; the control terminals of the first and second switches are used to receive an integration control clock signal; the positive terminal of the first capacitor and the negative input terminal of the floating inverter amplifier are respectively electrically connected to the negative terminal of the first switch; the positive terminal of the second capacitor and the positive input terminal of the floating inverter amplifier are respectively electrically connected to the negative terminal of the second switch; when the integration control clock signal is high, the first and second switches are turned on, and the residual voltage is sampled to the input terminal of the floating inverter amplifier through the first and second capacitors. The input terminal of the floating inverter amplifier is electrically connected to the output terminal of the switched capacitor integrator circuit, and is used to receive the integrated voltage and amplify the integrated voltage to output a common-mode voltage. The output sampling circuit is used to sample the integrated voltage to the input terminal of the comparator; wherein, the output sampling circuit includes a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, and a fourth capacitor; wherein, the control terminals of the third switch and the fourth switch are used to receive the NOT signal of the integration control clock; the negative terminals of the third switch and the fourth switch are electrically connected to the common-mode level; the control terminals of the fifth switch and the sixth switch are used to receive the integration control clock; the positive terminal of the fifth switch is electrically connected to the negative terminal of the third capacitor; the positive terminal of the sixth switch is electrically connected to the negative terminal of the fourth capacitor; the negative terminals of the fifth switch and the sixth switch are respectively electrically connected to the common-mode level; Specifically, when the integral control clock is low, the third and fourth switches are turned on, the output of the floating inverter amplifier is connected to the common-mode voltage, the fifth and sixth switches are turned off, and the output sampling circuit is in a reset state; when the integral control clock is high, the third and fourth switches are turned off, and the fifth and sixth switches are turned on; the third and fourth capacitors sample the common-mode voltage output by the floating inverter amplifier. The negative terminal of the first capacitor, the positive terminal of the third capacitor, and the positive terminal of the third switch are respectively connected to the positive output terminal of the floating inverter amplifier; the negative terminal of the second capacitor, the positive terminal of the fourth capacitor, and the positive terminal of the fourth switch are respectively electrically connected to the negative output terminal of the floating inverter amplifier. The floating inverter amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a seventh switch, an eighth switch, and a fifth capacitor; wherein: the positive terminal of the seventh switch is electrically connected to the positive terminal of the fifth capacitor; the negative terminal of the seventh switch is electrically connected to the positive node of the floating power supply; the control terminal of the seventh switch is used to receive the non-signal of the integration control clock; the positive terminal of the eighth switch is electrically connected to the negative terminal of the fifth capacitor; the negative terminal of the eighth switch is electrically connected to the negative node of the floating power supply; the control terminal of the eighth switch is used to receive the non-signal of the integration control clock. Specifically, when the integral control clock is low, the seventh and eighth switches are turned on, and the floating inverter amplifier is in a reset state; when the integral control clock is high, the seventh and eighth switches are turned off, and the two ends of the fifth capacitor are respectively connected to the negative node and the positive node of the floating power supply to provide floating power to the floating inverter amplifier. The gates of the first transistor and the seventh transistor are electrically connected to the positive input terminal of the floating inverter amplifier; the gates of the second transistor and the eighth transistor are electrically connected to the negative input terminal of the floating inverter amplifier; the gates of the third transistor and the fourth transistor are electrically connected to the positive node of the floating power supply; the gates of the fifth transistor and the sixth transistor are electrically connected to the negative node of the floating power supply; the source of the first transistor is electrically connected to the negative node of the floating power supply; the drain of the first transistor is electrically connected to the source of the third transistor; the source of the second transistor is electrically connected to the negative node of the floating power supply; the drain of the second transistor is electrically connected to the source of the fourth transistor; the source of the seventh transistor is electrically connected to the positive node of the floating power supply; the drain of the seventh transistor is electrically connected to the source of the fifth transistor; the source of the eighth transistor is connected to the positive node of the floating power supply; and the drain of the eighth transistor is electrically connected to the source of the sixth transistor. The drains of the sixth transistor and the fourth transistor are electrically connected to the positive output terminal of the floating inverter amplifier, respectively; the drains of the third transistor and the fifth transistor are electrically connected to the negative output terminal of the floating inverter amplifier, respectively. The gates of the third transistor and the fourth transistor are electrically connected to the positive node of the floating power supply; the gates of the fifth transistor and the sixth transistor are electrically connected to the negative node of the floating power supply; the sources of the seventh transistor and the eighth transistor are electrically connected to the positive node of the floating power supply; and the sources of the first transistor and the second transistor are electrically connected to the negative node of the floating power supply.

[0011] The above solution effectively solves the problems of noise interference and insufficient accuracy in the integration process through the specific structural design of the residual integrator. The residual integrator includes a switched capacitor integrator circuit, a floating inverter amplifier, and an output sampling circuit, which work together to improve quantization accuracy.

[0012] As a preferred example, the time-to-digital conversion circuit includes a dual-input comparator; wherein, the dual-input comparator is used to obtain the common-mode voltage and the residual voltage output by the capacitor array, so as to obtain a binary comparison result between the common-mode voltage and the residual voltage; The dual-input comparator includes a first input transistor, a second input transistor, a third input transistor, a fourth input transistor, a fifth input transistor, a sixth input transistor, a seventh input transistor, an eighth input transistor, a ninth input transistor, a tenth input transistor, an eleventh input transistor, a twelfth input transistor, a thirteenth input transistor, a first output buffer, and a second output buffer. In this configuration, the source of the first input transistor is grounded; the sources of the second, third, fourth, and fifth input transistors are electrically connected to the drain of the first input transistor; the gates of the second and fifth input transistors are electrically connected to form the first differential input pair of the dual-input comparator; the gates of the third and fourth input transistors are electrically connected to form the second differential input pair of the dual-input comparator; the drains of the third, eighth, and sixth input transistors are electrically connected to the drain of the second input transistor; the drains of the fifth, thirteenth, and seventh input transistors are electrically connected to the source of the second input transistor. The drain of the fourth input transistor is not electrically connected; the drain of the ninth input transistor, the drain of the tenth input transistor, the gate of the seventh input transistor, the gate of the eleventh input transistor, and the input terminal of the first output buffer are respectively electrically connected to the drain of the sixth input transistor; the drain of the eleventh input transistor, the drain of the twelfth input transistor, the gate of the sixth input transistor, the gate of the tenth input transistor, and the input terminal of the second output buffer are respectively electrically connected to the drain of the seventh input transistor; the source of the eighth input transistor, the source of the ninth input transistor, the source of the tenth input transistor, the source of the eleventh input transistor, the source of the twelfth input transistor, and the source of the thirteenth input transistor are respectively electrically connected to the power supply voltage; The output terminals of the first and second output buffers constitute the differential output terminals of the dual-input comparator, which are used to output the binary comparison result.

[0013] The above scheme solves the accuracy and noise problems in the comparison process by designing a dual-input comparator. The comparator adopts a differential input structure and multi-stage transistor connection to ensure efficient comparison of common-mode voltage and residual voltage, thereby generating accurate binary comparison results.

[0014] As a preferred example, the time-to-digital conversion circuit further includes a successive approximation logic circuit; The input terminal of the successive approximation logic circuit is electrically connected to the differential output terminal of the dual-input comparator to receive the binary comparison result; the output terminal of the successive approximation logic circuit is connected to the control terminal signal of the capacitor array to switch the switching connection state of the capacitor array according to the binary comparison result. The successive approximation logic circuit includes a first AND gate, a first NOR gate, a first inverter, a first XOR gate, a delay circuit, multiple latches, and multiple flip-flops. The data input terminal of each latch and the input terminal of the first AND gate are electrically connected to the differential output terminal, respectively. The clock terminal of each latch is electrically connected to the output terminal of the first AND gate to receive the valid signal output by the first AND gate; The enable terminals of multiple latches are connected in series; the output terminal of each latch is connected to the control terminal signal of the charging switch or the discharging switch to switch the connection state of the charging switch or the discharging switch. The input terminal of the delay circuit, the first input terminal of the first XOR gate, and the output terminal of the last latch among the plurality of latches are electrically connected; The output of the delay circuit is electrically connected to the second input of the first XOR gate, and is used to output a conversion completion flag signal; the output of the first XOR gate outputs an integrator to control the clock. The output terminal of the latch is electrically connected to the data input terminal of the flip-flop; the clock terminal of each flip-flop is electrically connected to the output terminal of the last latch; the output terminals of multiple flip-flops are used to output the multi-bit digital codeword corresponding to the residual voltage.

[0015] In the above scheme, the successive approximation logic circuit efficiently processes binary comparison results through the collaborative design of logic components to control switch switching and generate digital codewords, thereby solving the problems of delay and noise.

[0016] As a preferred example, the latch includes a first latch transistor, a second latch transistor, a third latch transistor, a fourth latch transistor, a fifth latch transistor, a sixth latch transistor, a seventh latch transistor, an eighth latch transistor, a ninth latch transistor, a tenth latch transistor, an eleventh latch transistor, a twelfth latch transistor, and a thirteenth latch transistor. The source of the first latching transistor and the source of the fourth latching transistor are electrically connected to the power supply voltage; the gate of the first latching transistor is electrically connected to the gate of the fourth latching transistor. The gates of the fourth latch transistor, the sixth latch transistor, the seventh latch transistor, and the drain of the second latch transistor are electrically connected to the drain of the first latch transistor, respectively. The source of the second latch transistor is connected to the drain of the third latch transistor; the gate of the second latch transistor receives the latch clock. The source of the third latch transistor is grounded; the gate of the third latch transistor receives the latch enable signal; the drain of the fourth latch transistor is electrically connected to the source of the fifth latch transistor; the drain of the fifth latch transistor is electrically connected to the drain of the sixth latch transistor and serves as the latch output terminal; the gate of the fifth latch transistor receives the latch clock; the source of the sixth latch transistor is grounded. The source of the seventh latch transistor is connected to the power supply voltage; the sources of the eighth latch transistor and the ninth latch transistor are electrically connected to the drain of the seventh latch transistor, respectively. The gate of the eighth latch transistor serves as the first data input terminal of the latch; the gate of the ninth latch transistor serves as the second data input terminal of the latch; the source of the tenth latch transistor and the source of the eleventh latch transistor are electrically connected to the gate of the eighth latch transistor, respectively; the source of the tenth latch transistor and the source of the eleventh latch transistor are electrically connected to the gate of the ninth latch transistor, respectively. The gates of the tenth latch transistor and the eleventh latch transistor are respectively connected to the output terminal of the latch; the drain of the tenth latch transistor serves as the first output terminal of the latch; and the drain of the eleventh latch transistor serves as the second output terminal of the latch. The source of the twelfth latch transistor and the source of the thirteenth latch transistor are grounded; the gate of the twelfth latch transistor and the gate of the thirteenth latch transistor are respectively connected to the output terminal of the latch; the drain of the twelfth latch transistor is electrically connected to the first output terminal; and the drain of the thirteenth latch transistor is electrically connected to the second output terminal.

[0017] The above solution addresses issues such as signal delay, increased power consumption, and unstable output by optimizing the transistor structure of the latch, thereby improving the accuracy and efficiency of time-to-digital conversion.

[0018] As a preferred example, the control signal generation circuit includes a logic control circuit and a plurality of switch control circuits; wherein, each of the charging capacitor switch arrays corresponds to one switch control circuit; and each of the discharging capacitor switch arrays corresponds to one switch control circuit. The logic control circuit includes a first edge-triggered flip-flop, a second edge-triggered flip-flop, a third edge-triggered flip-flop, and an AND gate. The data terminal of the first edge-triggered flip-flop is connected to a high level. The clock terminal of the first edge-triggered flip-flop is connected to the time-to-voltage conversion circuit and is used to receive a conversion completion flag signal sent by the time-to-voltage conversion circuit. The reset terminal of the first edge-triggered flip-flop is connected to the output terminal of the AND gate. The output terminal of the first edge-triggered flip-flop is used to output a sampling control signal based on the conversion completion flag signal. The data terminal of the second edge-triggered flip-flop is connected to a high level. The clock terminal of the second edge-triggered flip-flop is used to receive a reference clock signal. The reset terminal of the second edge-triggered flip-flop is connected to the output terminal of the AND gate. The output terminal of the second edge-triggered flip-flop is used to output a charging control signal based on the reference clock signal. The data terminal of the third edge-triggered flip-flop is connected to a high level. The clock terminal of the third edge-triggered flip-flop is used to receive a frequency-divided clock signal. The reset terminal of the third edge-triggered flip-flop is connected to the output terminal of the AND gate. The output terminal of the third edge-triggered flip-flop is used to output a discharging control signal based on the frequency-divided clock signal. The first input terminal of the AND gate is electrically connected to the output terminal of the second edge-triggered flip-flop to receive the charging control signal; the second input terminal of the AND gate is electrically connected to the output terminal of the third edge-triggered flip-flop to receive the discharging control signal. The switch control circuit includes a first NOR gate, a second NOR gate, and a third NOR gate. The output of the first edge-triggered trigger and the output of the successive approximation circuit are respectively connected to the input of the first NOR gate, so that the first NOR gate receives the sampling control signal and the control signal output by the successive approximation circuit. The output of the first NOR gate and the output of the AND gate are respectively connected to the input of the second NOR gate, so that the second NOR gate receives the charging control signal or the discharging control signal. The output of the second NOR gate is connected to the control terminal of the charging switch or the discharging switch for control. One end of the charging switch or the discharging switch is electrically connected to the positive reference voltage terminal; the output terminal of the first edge-triggered trigger, the output terminal of the AND gate, and the control signal output by the successive approximation circuit are respectively connected to the input terminal signal of the third NOR gate, so that the third NOR gate receives the charging control signal, the discharging control signal, or the control signal output by the successive approximation circuit; the output terminal of the third NOR gate is connected to the control terminal signal of the charging switch or the discharging switch, and is used to control one end of the charging switch or the discharging switch to switch the connection state with the negative reference voltage terminal or the positive reference voltage terminal.

[0019] The above solution solves the problems of inaccurate timing and switching noise by optimizing the design of the control signal generation circuit, ensuring stable and reliable charging and discharging operation of the capacitor array.

[0020] On the other hand, the present invention discloses a low-jitter digital phase-locked loop, including a digital filter, a digitally controlled oscillator, a frequency divider, and a time-to-digital converter based on a split capacitor as described in the foregoing scheme; wherein, the input terminal of the time-to-digital converter is signal-connected to the output terminal of the frequency divider; The input terminal of the time-to-digital converter receives a reference clock signal and a divided clock signal output by the frequency divider, and is used to obtain the residual voltage corresponding to the reference clock signal and the divided clock signal, and the multi-bit digital codeword corresponding to the residual voltage. The input terminal of the digital filter is connected to the output terminal of the time-to-digital converter, and is used to receive the multi-digit codeword and generate the frequency control word corresponding to the multi-digit codeword. The control terminal of the numerically controlled oscillator is connected to the output terminal of the digital filter, and is used to receive the frequency control word and output the frequency multiplication signal corresponding to the reference clock signal according to the frequency control word. The input terminal of the frequency divider is connected to the output terminal of the numerically controlled oscillator, and is used to receive the frequency multiplier signal and divide the frequency multiplier signal to output a frequency-divided clock signal to the time-to-digital converter.

[0021] This invention discloses a low-jitter digital phase-locked loop (PLL) that reduces in-band phase noise and integral jitter by integrating a time-to-digital converter (TD-RC) based on split capacitors. This TD-RC can measure the time difference between a reference clock and a divided clock with high precision. Specifically, the input of the TD-RC is connected to the output of the divider, allowing the TD-RC to directly receive the divided clock signal output by the divider. The TD-RC obtains the corresponding residual voltage and multi-bit digital codewords based on the received reference clock signal and divided clock signal. This step utilizes a split capacitor structure to convert the time difference into a voltage domain and perform multi-bit quantization, reducing the quantization error of traditional TD-RCs and thus improving resolution. The input of a digital filter is connected to the output of the TD-RC, receiving the multi-bit digital codewords and generating a frequency based on these codewords. The control word and digital filter process the quantized signal to smooth noise and generate a stable control signal. The control terminal of the numerically controlled oscillator (CNC) is connected to the output of the digital filter, receives the frequency control word, and outputs a frequency multiplier signal corresponding to the reference clock signal based on the frequency control word. The CNC oscillator adjusts the output frequency through the control word to achieve precise generation of the frequency multiplier signal. The input of the frequency divider is connected to the output of the CNC oscillator, receives the frequency multiplier signal, and divides the frequency multiplier signal to output a divided clock signal to the time-to-digital converter (TD-SCDMA). This forms a closed-loop feedback mechanism to ensure stable operation and low jitter performance of the phase-locked loop (PLL). The entire scheme effectively reduces noise problems caused by quantization errors of the time-to-digital converter through closed-loop control and high-precision time measurement based on split capacitors.

[0022] As a preferred example, the numerically controlled oscillator includes a digital shaping and modulation circuit, a resistive digital-to-analog converter circuit, an analog filter circuit, and an inductor-capacitor voltage-controlled oscillator circuit. The input terminal of the digital shaping and modulation circuit is electrically connected to the output terminal of the digital filter, and is used to receive the frequency control word, perform noise shaping and modulation on the frequency control word, and output a one-bit wide digital code stream. The input terminal of the resistive digital-to-analog converter circuit is electrically connected to the output terminal of the digital shaping and modulation circuit, and is used to convert the one-bit wide digital code stream into an analog voltage signal. The input terminal of the analog filter circuit is electrically connected to the output terminal of the resistive digital-to-analog converter circuit, and is used to filter out high-frequency quantization noise in the analog voltage signal to obtain a filtered analog voltage signal. The voltage control terminal of the inductor-capacitor voltage-controlled oscillator circuit is electrically connected to the output terminal of the analog filter circuit, and is used to generate a frequency multiplier signal with a target frequency based on the filtered analog control voltage.

[0023] The above solution solves the phase-locked loop jitter problem caused by high-frequency quantization noise in the prior art by optimizing the circuit structure of the numerically controlled oscillator.

[0024] As a preferred example, the numerically controlled oscillator includes a digital-to-analog converter, a first oscillation capacitor, a second oscillation capacitor, an oscillation resistor, an adjustable resistor, a first oscillation transistor, a second oscillation transistor, a third oscillation transistor, a fourth oscillation transistor, an inductor, a first varactor transistor, and a second varactor transistor; wherein, the positive terminal of the first oscillation capacitor and the positive terminal of the oscillation resistor are electrically connected to the output terminal of the digital-to-analog converter; the negative terminal of the first oscillation capacitor is grounded; the negative terminal of the second oscillation capacitor is grounded; the positive terminals of the second oscillation capacitor, the first varactor transistor, and the second varactor transistor are electrically connected to the negative terminal of the oscillation resistor; the source terminals of the first oscillation transistor and the second oscillation transistor are electrically connected to the positive terminal of the adjustable resistor. The gate of the second oscillating transistor, the gate of the fourth oscillating transistor, the drain of the third oscillating transistor, the positive terminal of the inductor, the positive terminal of the capacitor array, and the negative terminal of the first varactor transistor are respectively electrically connected to the drain of the first oscillating transistor. The gate of the first oscillating transistor, the gate of the third oscillating transistor, the drain of the fourth oscillating transistor, the negative terminal of the inductor, the negative terminal of the capacitor array, and the negative terminal of the second varactor transistor are respectively electrically connected to the negative terminal of the second oscillating transistor. The source of the third oscillating transistor and the source of the fourth oscillating transistor are respectively connected to the power supply voltage.

[0025] The above solution addresses noise and power consumption issues by optimizing the specific circuit structure of the numerically controlled oscillator, thereby improving the low-jitter performance of the phase-locked loop. Attached Figure Description

[0026] Figure 1 A schematic diagram of a time-to-digital converter based on a split capacitor is provided in an embodiment of the present invention; Figure 2 A schematic diagram of a time-to-digital converter based on a capacitor array is provided in an embodiment of the present invention; Figure 3 A schematic diagram illustrating the workflow of a time-to-digital converter provided in an embodiment of the present invention; Figure 4 is a timing diagram of a time-to-digital converter provided in an embodiment of the present invention; wherein, Figure 4(a) is a timing diagram of a phase-locked loop when locked in an embodiment of the present invention; and Figure 4(b) is a timing diagram of a phase-locked loop when unlocked in an embodiment of the present invention. Figure 5 is a schematic diagram of a residual integrator provided in an embodiment of the present invention; wherein, Figure 5(a) is a schematic diagram of a switched capacitor provided in an embodiment of the present invention; and Figure 5(b) is a schematic diagram of a switched capacitor provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the circuit structure of a dual-input comparator provided in an embodiment of the present invention; Figure 7 A schematic diagram of the circuit structure of a successive approximation logic circuit provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the circuit structure of a latch provided in an embodiment of the present invention; Figure 9 A schematic diagram of the circuit structure of a control signal generation circuit provided in an embodiment of the present invention; Figure 10 A schematic diagram of a low-jitter digital phase-locked loop provided in an embodiment of the present invention; Figure 11 A schematic diagram of the circuit structure of a digital filter provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the circuit structure of a numerically controlled oscillator provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Please refer to Figure 1 To address the issue of mutual constraints between current noise and linear range in traditional time-to-voltage converters, thereby reducing the noise introduced by the time-to-voltage converter, this embodiment discloses a time-to-digital converter based on split capacitors, including a capacitor array 101, a control signal generation circuit 102, a time-to-digital conversion circuit 103, and a charging / discharging power supply 104; wherein, the output terminal of the capacitor array 101 is electrically connected to the input terminal of the time-to-digital conversion circuit 103; the control terminal of the capacitor array 101 is signal-connected to the output terminal of the time-to-voltage conversion circuit 103; and the output terminal of the charging / discharging power supply 104 is electrically connected to the input terminal of the capacitor array 101.

[0029] The control signal generation circuit 102 is connected to the time-to-digital converter circuit 103 and is used to receive the conversion completion flag signal fed back by the time-to-digital converter circuit 103, so as to receive the reference clock signal and the frequency division clock signal corresponding to the reference clock signal according to the conversion completion flag signal.

[0030] The control signal generation circuit 102 generates a charging control signal based on the reference clock signal and a discharging control signal based on the frequency division clock signal.

[0031] The charging and discharging power supply 104 is connected to the control signal generation circuit 102 to charge the capacitor array 101 according to the charging control signal and discharge the capacitor array 101 according to the discharging control signal, so that the capacitor array 101 forms a residual voltage.

[0032] The input terminal of the time-voltage conversion circuit 103 is electrically connected to the output terminal of the capacitor array, and is used to receive the residual voltage and perform multiple quantization operations on the residual voltage to obtain the digital codeword corresponding to each quantization operation, thereby obtaining the multi-bit digital codeword corresponding to the residual voltage and generating the conversion completion flag signal; wherein, the quantization operation includes the time-voltage conversion circuit 103 switching the reference voltage connection state of the capacitor array 101 according to the residual voltage to obtain the residual voltage corresponding to each reference voltage connection state.

[0033] In this first embodiment, the capacitor array 101 includes a plurality of mirror-symmetrical charging capacitors and a plurality of discharging capacitors; wherein each charging capacitor is connected in series with a charging switch; each discharging capacitor is connected in series with a discharging switch; wherein the lower plate of the charging capacitor is electrically connected to the fixed terminal of the charging switch; the lower plate of the discharging capacitor is electrically connected to the fixed terminal of the discharging switch; the first terminal of the charging switch is electrically connected to the positive reference voltage terminal; the second terminal of the charging switch is electrically connected to the negative reference voltage terminal; the third terminal of the charging switch is electrically connected to the output terminal of the charging power supply in the charging and discharging power supply 104, for receiving the charging current of the charging power supply; the first terminal of the discharging switch is electrically connected to the positive reference voltage terminal; the second terminal of the discharging switch is electrically connected to the negative reference voltage terminal; the third terminal of the discharging switch is electrically connected to the output terminal of the discharging power supply in the charging and discharging power supply 104, for receiving the discharging current of the discharging power supply; the control terminal of the third terminal of the charging switch is signal-connected to the control signal generation circuit 102, for receiving the charging control signal. The charging current is delivered to the charging capacitor according to the charging control signal to charge the charging capacitor; the control terminal of the third terminal of the discharge switch is connected to the control signal generation circuit 102 to receive the discharge control signal and deliver the discharge current to the discharge capacitor according to the discharge control signal to charge the discharge capacitor; the upper plates of each charging capacitor are electrically connected to each other to form a charging sensing node; the upper plates of each discharge capacitor are electrically connected to each other to form a discharge sensing node; the charging sensing node and the discharge sensing node are respectively electrically connected to the input terminal of the time-to-digital converter circuit 103; the charging sensing node acquires the energy of multiple charging capacitors to form a charging voltage; the discharge sensing node acquires the energy of multiple discharge capacitors to form a discharge voltage; the charging sensing node and the discharge sensing node serve as the output terminals of the capacitor array 101 to form a residual voltage according to the charging voltage and the discharge voltage, and deliver the residual voltage to the time-to-digital converter circuit 103.

[0034] In this embodiment, refer to Figure 2 As shown in the capacitor array, the array is divided into mirror-symmetric charging capacitors and discharging capacitors; wherein, the charging capacitors are connected in parallel from the highest to the lowest bit, including 64C, 32C, 16C, 8C, 4C, 2C, C, C; where C is the unit capacitance. From Figure 2 It is known that the lower plate of each capacitor is connected to the fixed terminal of a three-terminal switch for three-way selection; the other three terminals of the switch are respectively connected to the positive reference voltage VREFP, the negative reference voltage VREFN, and the charging current source ITVCP.

[0035] from Figure 2 It is understood that, in order to measure the voltage difference formed by the charging capacitor and the discharging capacitor being charged at different times, a sampling switch can be additionally set in the capacitor array; wherein, the upper plate of all capacitors is connected to the input terminal of the time-voltage conversion circuit and the sampling switch; wherein, the other end of the sampling switch is connected to the common-mode level VCM; the sampling switch is controlled by the sampling clock CLKS; the control terminal of each of the switches is electrically connected to the output terminal of the time-voltage conversion circuit to control the conduction state of each terminal of the switch, that is, to switch the connection state of the switch.

[0036] Specifically, refer to Figure 3 As can be seen from the workflow of the time-to-digital converter shown in Figure 4 and the timing diagram of the time-to-digital converter shown in Figure 4(a), the timing diagram includes the timing when the phase-locked loop is locked, as shown in Figure 4(b), and the timing when the phase-locked loop is unlocked. Taking the highest-order capacitor as an example, CP1 and CP0 respectively correspond to... Figure 2 The discharge capacitor 64C and the charging capacitor 64C are respectively; CN1 and CN0 correspond to Figure 2 The discharge capacitor 64C and the charging capacitor 64C are shown in Figure 4. During the reset phase, the upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of capacitors CP1 and CN1 are connected to VREFP, and the lower plates of capacitors CP0 and CN0 are connected to VREFN. When the rising edge of either the reference clock signal or the corresponding frequency-divided clock signal arrives, the time-to-digital converter begins digitizing the time difference. Specifically, when the phase-locked loop (PLL) containing the time-to-digital converter is locked, the rising edges of the reference clock signal REF and the reference clock signal DIV arrive simultaneously. At this time, capacitors CP1 and CN1 discharge through a constant current source, while capacitors CP0 and CN0 charge through a constant current source, and the charge on the positive and negative capacitor array remains unchanged. However, when the PLL is not locked, assuming the rising edge of DIV arrives first and the rising edge of REF arrives later, CP1 discharges through a constant current source and CN0 charges through a constant current source during this time difference, resulting in a decrease in the charge on the positive capacitor and an increase in the charge on the negative capacitor. The change in charge is proportional to the time difference. When the rising edges of REF and DIV arrive, the sampling clock signal CLKS, which controls the sampling switch to turn on, the charging control signal UP, which controls the charging power supply to charge, and the discharging control signal DN, which controls the discharging power supply to charge, are reset to low level. At this time, the sampling switch is closed, and the charging and discharging ends. At this time, the lower plates of capacitors CP1 and CN1 are connected to VREFN, while the lower plates of capacitors CP0 and CN0 are connected to VREFP. The time difference between the rising edges of REF and DIV is converted into a differential analog voltage and stored in the capacitor array.

[0037] In this first embodiment, the time-to-digital converter 102 includes a residual integrator; wherein the residual integrator includes a switched-capacitor integrator circuit, a floating inverter amplifier, and an output sampling circuit; wherein the input terminal of the switched-capacitor integrator circuit is electrically connected to the output terminal of the capacitor array 101, for receiving the residual voltage, performing charge integration on the residual voltage, and outputting an integrated voltage; wherein the switched-capacitor integrator circuit includes a first switch, a second switch, a first capacitor, and a second capacitor; the positive terminal of the first switch is electrically connected to the charging sensing node; the positive terminal of the second switch is electrically connected to the discharging sensing node; the control terminals of the first switch and the second switch are used to receive integration control... A clock signal is generated; the positive terminal of the first capacitor and the negative input terminal of the floating inverter amplifier are electrically connected to the negative terminal of the first switch, respectively; the positive terminal of the second capacitor and the positive input terminal of the floating inverter amplifier are electrically connected to the negative terminal of the second switch, respectively; when the integration control clock signal is high, the first switch and the second switch are turned on, and the residual voltage is sampled to the input terminal of the floating inverter amplifier through the first capacitor and the second capacitor; the input terminal of the floating inverter amplifier is electrically connected to the output terminal of the switched capacitor integration circuit, for receiving the integrated voltage and amplifying the integrated voltage to output a common-mode voltage; the output sampling circuit is used to sample the integrated voltage to a comparison circuit. The input terminal of the device; wherein, the output sampling circuit includes a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, and a fourth capacitor; wherein, the control terminals of the third switch and the fourth switch are used to receive the non-signal of the integration control clock; the negative terminals of the third switch and the fourth switch are electrically connected to the common-mode level; the control terminals of the fifth switch and the sixth switch are used to receive the integration control clock; the positive terminal of the fifth switch is electrically connected to the negative terminal of the third capacitor; the positive terminal of the sixth switch is electrically connected to the negative terminal of the fourth capacitor; the negative terminals of the fifth switch and the sixth switch are respectively electrically connected to the common-mode level; wherein, when the integration control clock is low, the... When the third and fourth switches are turned on, the output terminal of the floating inverter amplifier is connected to the common-mode level, the fifth and sixth switches are turned off, and the output sampling circuit is in a reset state; when the integration control clock is high, the third and fourth switches are turned off, and the fifth and sixth switches are turned on; the third and fourth capacitors sample the common-mode voltage output by the floating inverter amplifier; wherein, the negative terminal of the first capacitor, the positive terminal of the third capacitor, and the positive terminal of the third switch are respectively connected to the positive output terminal of the floating inverter amplifier; the negative terminal of the second capacitor, the positive terminal of the fourth capacitor, and the positive terminal of the fourth switch are respectively electrically connected to the negative output terminal of the floating inverter amplifier;The floating inverter amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a seventh switch, an eighth switch, and a fifth capacitor; wherein: the positive terminal of the seventh switch is electrically connected to the positive terminal of the fifth capacitor; the negative terminal of the seventh switch is electrically connected to the positive node of the floating power supply; the control terminal of the seventh switch is used to receive the non-signal of the integration control clock; the positive terminal of the eighth switch is electrically connected to the negative terminal of the fifth capacitor; the negative terminal of the eighth switch is electrically connected to the negative node of the floating power supply; the control terminal of the eighth switch is used to receive the non-signal of the integration control clock; wherein, when the integration control clock is low, the seventh and eighth switches are turned on, and the floating inverter amplifier is in a reset state; when the integration control clock is high, the seventh and eighth switches are turned off, and the two ends of the fifth capacitor are respectively connected to the negative and positive nodes of the floating power supply to provide floating power to the floating inverter amplifier; the gates of the first transistor and the seventh transistor are electrically connected to the positive input terminal of the floating inverter amplifier; the fifth transistor... The gates of the second transistor and the eighth transistor are electrically connected to the negative input terminal of the floating inverter amplifier; the gates of the third transistor and the fourth transistor are electrically connected to the positive node of the floating power supply; the gates of the fifth transistor and the sixth transistor are electrically connected to the negative node of the floating power supply; the source of the first transistor is electrically connected to the negative node of the floating power supply; the drain of the first transistor is electrically connected to the source of the third transistor; the source of the second transistor is electrically connected to the negative node of the floating power supply; the drain of the second transistor is electrically connected to the source of the fourth transistor; the source of the seventh transistor is electrically connected to the positive node of the floating power supply; the drain of the seventh transistor is electrically connected to the source of the fifth transistor; the source of the eighth transistor is connected to the positive node of the floating power supply; the drain of the eighth transistor is electrically connected to the source of the sixth transistor; the drains of the sixth transistor and the fourth transistor are electrically connected to the positive output terminal of the floating inverter amplifier; the drains of the third transistor and the fifth transistor are electrically connected to the negative output terminal of the floating inverter amplifier. The gates of the third transistor and the fourth transistor are electrically connected to the positive node of the floating power supply; the gates of the fifth transistor and the sixth transistor are electrically connected to the negative node of the floating power supply; the sources of the seventh transistor and the eighth transistor are electrically connected to the positive node of the floating power supply; and the sources of the first transistor and the second transistor are electrically connected to the negative node of the floating power supply.

[0038] In this embodiment, refer to Figure 2As shown in the schematic diagram of the capacitor array, after acquiring the residual voltage that characterizes the time difference between the reference clock signal and the frequency-divided clock signal, the capacitor array 101 needs to integrate the residual voltage to eliminate noise in the voltage. Specifically, referring to the residual integrator shown in Figures 5(a) and 5(b), the residual integrator is composed of a floating inverter amplifier (FIA) and switched capacitors; specifically, CDAC+ and CDAC- are the positive and negative ports of the capacitor array 101, respectively connected to the positive terminals of the first switch and the second switch; the control terminals of the first and second switches are connected to the integrator clock (INT); the negative terminal of the first switch is connected to the positive terminal of capacitor C1 and the negative input terminal of the FIA; the negative terminal of the second switch is connected to the positive terminal of capacitor C2 and the positive input terminal of the FIA; the positive output terminal of the FIA ​​is connected to the negative terminal of capacitor C1, the positive terminal of capacitor C3, and the third switch. Positive terminal; the negative output terminal of FIA is connected to the negative terminal of C2, the positive terminal of C4, and the positive terminal of the fourth switch; the control terminals of the third and fourth switches are connected to the NOT signal of INT; the negative terminals of the third, fourth, fifth, and sixth switches are connected to the common-mode level VCM; the control terminals of the fifth and sixth switches are connected to INT; COMP2+ and COMP2- are the second positive and negative input ports of the comparator, COMP2+ is connected to the negative terminal of C3 and the positive terminal of the fifth switch; COMP2- is connected to the negative terminal of C4 and the positive terminal of the sixth switch; INT is the control clock of the integrator.

[0039] The circuit structure of the FIA ​​(Floating Inverter Amplifier) ​​is shown in Figure 5(b), including transistors M1-M8 and switched capacitors. The positive terminal of the seventh switch is connected to the positive terminal of capacitor Cs, the negative terminal is connected to power supply VDD and VP, and the control terminal is connected to the NOT signal of INT. The positive terminal of the eighth switch is connected to the negative terminal of capacitor Cs, the negative terminal is connected to ground VSS and VN, and the control terminal is connected to the NOT signal of INT. The gate terminals of transistors M1 and M7 are connected to the positive input terminal VIN+ of the FIA. The gate terminals of transistors M2 and M8 are connected to the negative input terminal VIN- of the FIA. The gate terminals of transistors M3 and M4 are connected to VP. The gate terminals of transistors M5 and M6 are connected to VN. The source terminal of transistor M1 is connected to VN, and the drain terminal is connected to the source terminal of transistor M3. The source of transistor M2 is connected to VN, and its drain is connected to the source of transistor M4; the source of transistor M7 is connected to VP, and its drain is connected to the source of transistor M5; the source of transistor M8 is connected to VP, and its drain is connected to the source of transistor M6; the positive output terminal VOUT+ of the FIA ​​is connected to the drains of transistors M6 and M4; the negative output terminal VOUT- of the FIA ​​is connected to the drains of transistors M3 and M5. After the capacitor array successively approximates the input voltage, a residual voltage still exists between the positive and negative plates. This voltage is integrated by the residual integrator and input to the additional input terminal of the comparator. In the next analog-to-digital conversion, it is first summed with the voltage on the capacitor array and then compared to achieve first-order noise shaping, pushing low-frequency quantization noise and comparator noise to higher frequencies. The dynamic FIA features high energy efficiency and stable common-mode output. By adopting a self-biased cascode structure, this amplifier can achieve a DC gain of over 40 dB, resulting in a high quality factor for the integrator. When INT is low, capacitor Cs is connected to VDD and VSS, and VOUT+ and VOUT- are connected to the common-mode voltage VCM. The integrator is in a reset state. When the rising edge of INT arrives, Cs is connected to VP and VN to provide power to the FIA. According to the law of conservation of charge, the amount of charge injected into VOUT+ is equal to the amount of charge flowing out of VOUT-. Therefore, the voltage increase of VOUT+ is equal to the voltage decrease of VOUT-. The common-mode output of the FIA ​​remains unchanged, which is the common-mode stabilization mechanism of the FIA.

[0040] In this embodiment, the time-to-digital converter 103 includes a dual-input comparator. The dual-input comparator is used to acquire the common-mode voltage and the residual voltage output by the capacitor array to obtain a binary comparison result between the common-mode voltage and the residual voltage. The dual-input comparator includes a first input transistor, a second input transistor, a third input transistor, a fourth input transistor, a fifth input transistor, a sixth input transistor, a seventh input transistor, an eighth input transistor, a ninth input transistor, a tenth input transistor, an eleventh input transistor, a twelfth input transistor, a thirteenth input transistor, a first output buffer, and a second output buffer. The source of the first input transistor is grounded. The sources of the second, third, fourth, and fifth input transistors are electrically connected to the drain of the first input transistor. The gates of the second and fifth input transistors are electrically connected to form a first differential input pair of the dual-input comparator. The gates of the third and fourth input transistors are electrically connected to form a second differential input pair of the dual-input comparator. The drains of the third input transistor, the eighth input transistor, and the source of the sixth input transistor are electrically connected to the drain of the second input transistor; the drains of the fifth input transistor, the thirteenth input transistor, and the source of the seventh input transistor are electrically connected to the drain of the fourth input transistor; the drains of the ninth input transistor, the tenth input transistor, the gate of the seventh input transistor, the gate of the eleventh input transistor, and the input terminal of the first output buffer are electrically connected to the drain of the sixth input transistor; the drains of the eleventh input transistor, the twelfth input transistor, the gate of the sixth input transistor, the gate of the tenth input transistor, and the input terminal of the second output buffer are electrically connected to the drain of the seventh input transistor; the sources of the eighth input transistor, the ninth input transistor, the tenth input transistor, the eleventh input transistor, the twelfth input transistor, and the thirteenth input transistor are electrically connected to the power supply voltage; the output terminals of the first and second output buffers constitute the differential output terminals of the dual-input comparator, used to output the binary comparison result.

[0041] In this embodiment, refer to Figure 6The circuit diagram of the dual-input comparator shown indicates that the comparator includes 13 transistors (M1-M13) and two output buffers. The source terminal of M1 is grounded, its drain terminal is connected to the source terminals of M2, M3, M4, and M5, and its gate terminal is connected to CLKC. The positive and negative terminals COMP1+ and COMP1- of the first input port are connected to the gate terminals of transistors M2 and M5, respectively. The positive and negative terminals COMP2+ and COMP2- of the second input port are connected to the gate terminals of transistors M3 and M4, respectively. The drain terminal of M2 is connected to the drain terminals of M3 and M8 and the source terminal of M6. The drain terminal of M4 is connected to the source terminal of M5 and... The drain of M13 is connected to the source of M7; the drain of M6 is connected to the drains of M9 and M10, the gates of M7 and M11, and the input of the first buffer; the drain of M7 is connected to the drains of M11 and M12, the gates of M6 and M10, and the input of the second buffer; the comparator's clock CLKS is connected to the gates of M1, M8, M9, M12, and M13; the outputs of the two buffers are connected to the positive and negative outputs of the comparator, COMP_OUT+ and COMP_OUT-; the sources of M8, M9, M10, M11, M12, and M13 are connected to the power supply. When CLKC is low, the comparator is in the reset phase. The positive and negative outputs are reset to high by M12 and M9, respectively. When the rising edge of CLKC arrives, transistor M1 turns on, discharging nodes P and N through transistors M2, M3, M4, and M5. The different input voltages of the positive and negative terminals cause nodes P and N to discharge at different rates, resulting in a voltage difference between nodes P and N. This voltage difference is amplified by two inverters connected end-to-end through positive feedback to generate a high-level signal and a low-level signal. One of COMP_OUT+ and COMP_OUT- is reduced to low, while the other remains high to obtain the comparison result.

[0042] In this embodiment, the time-to-digital converter 103 further includes a successive approximation logic circuit; wherein, the input terminal of the successive approximation logic circuit is electrically connected to the differential output terminal of the dual-input comparator, for receiving the binary comparison result; the output terminal of the successive approximation logic circuit is connected to the control terminal signal of the capacitor array, for switching the switching connection state of the capacitor array according to the binary comparison result; wherein, the successive approximation logic circuit includes a first AND gate, a first NOR gate, a first inverter, a first XOR gate, a delay circuit, multiple latches, and multiple flip-flops; wherein, the data input terminal of each latch and the input terminal of the first AND gate are respectively electrically connected to the differential output terminal; the clock terminal of each latch is respectively electrically connected to the output terminal of the first AND gate to receive the binary comparison result. The first AND gate outputs a valid signal; the enable terminals of the plurality of latches are connected in series; the output terminal of each latch is connected to the control terminal signal of the charging switch or the discharging switch to switch the connection state of the charging switch or the discharging switch; the input terminal of the delay circuit, the first input terminal of the first XOR gate, and the output terminal of the last latch among the plurality of latches are electrically connected; the output terminal of the delay circuit is electrically connected to the second input terminal of the first XOR gate to output a conversion completion flag signal; the output terminal of the first XOR gate outputs an integrator control clock; the output terminal of the latch is electrically connected to the data input terminal of the flip-flop; the clock terminal of each flip-flop is electrically connected to the output terminal of the last latch; the output terminals of the plurality of flip-flops are used to output a multi-bit digital codeword corresponding to the residual voltage.

[0043] The latch includes a first latch transistor, a second latch transistor, a third latch transistor, a fourth latch transistor, a fifth latch transistor, a sixth latch transistor, a seventh latch transistor, an eighth latch transistor, a ninth latch transistor, a tenth latch transistor, an eleventh latch transistor, a twelfth latch transistor, and a thirteenth latch transistor. The sources of the first and fourth latch transistors are electrically connected to a power supply voltage. The gate of the first latch transistor is electrically connected to the gate of the fourth latch transistor. The gates of the fourth, sixth, and seventh latch transistors, and the drain of the second latch transistor are electrically connected to the drain of the first latch transistor. The source of the second latch transistor is connected to the drain of the third latch transistor. The gate of the second latch transistor receives the latch clock. The source of the third latch transistor is grounded. The third latch transistor... The gate of the transistor receives the latch enable signal; the drain of the fourth latch transistor is electrically connected to the source of the fifth latch transistor; the drain of the fifth latch transistor is electrically connected to the drain of the sixth latch transistor and serves as the latch output terminal; the gate of the fifth latch transistor receives the latch clock; the source of the sixth latch transistor is grounded; the source of the seventh latch transistor is connected to the power supply voltage; the sources of the eighth and ninth latch transistors are electrically connected to the drain of the seventh latch transistor, respectively; the gate of the eighth latch transistor serves as the first data input terminal of the latch; the gate of the ninth latch transistor serves as the second data input terminal of the latch; the sources of the tenth and eleventh latch transistors are electrically connected to the gate of the eighth latch transistor, respectively; the sources of the tenth and eleventh latch transistors are electrically connected to the gate of the ninth latch transistor, respectively. The gates of the tenth latch transistor and the eleventh latch transistor are respectively connected to the output terminal of the latch; the drain of the tenth latch transistor serves as the first output terminal of the latch; and the drain of the eleventh latch transistor serves as the second output terminal of the latch. The source of the twelfth latch transistor and the source of the thirteenth latch transistor are grounded; the gate of the twelfth latch transistor and the gate of the thirteenth latch transistor are respectively connected to the output terminal of the latch; the drain of the twelfth latch transistor is electrically connected to the first output terminal; and the drain of the thirteenth latch transistor is electrically connected to the second output terminal.

[0044] In this embodiment, refer to Figure 7 As shown in the successive approximation logic circuit, the successive approximation logic circuit includes multiple latches L6-L0, multiple flip-flops, inverters, AND gates, NOR gates, XOR gates, and delay units. Among them, as... Figure 6The positive and negative outputs COMP_OUT+ and COMP_OUT- of the comparator are connected to the DP and DN inputs of the seven latches, respectively, and also to the input of the AND gate. The output of the AND gate is connected to the comparison completion flag signal Valid. The Valid signal is connected to the CLK clock input of the seven latches and the input of the inverter. The output of the inverter, along with the sampling clocks CLKS and Q0, is connected to the input of the NOR gate. The output of the NOR gate is connected to the asynchronous comparator clock CLKC. The D and Q inputs of the seven latches are connected end-to-end. The D terminal of L6 is connected to CLKS (not connected), the Q terminal of L0 is connected to the delay unit and the XOR gate input, the output of the delay unit is connected to the conversion completion flag signal DONE and the XOR gate input, the XOR gate output is connected to the integrator clock INT, the outputs P<6:0> and Q<6:0> of the 7 latches are connected to the switched capacitor array to control the selection of the switch, and P<6:0> is connected to the D terminal of the 7 flip-flops, the flip-flop clock CLK is connected to Q0, and the Q output of the 7 flip-flops is connected to the TDC digital output D<6:0>.

[0045] During sampling, CLKS is high, and the seven latches are reset sequentially. After sampling, CLKS goes low, and latch L6 is activated. When the falling edge of the Valid signal arrives, it indicates that the comparison is complete, and latch L6 is triggered. Its Q output goes high, latching the current comparison results COMP_OUT+ and COMP_OUT- to P6 and N6, simultaneously activating the next latch L5. P6 and N6 control the most significant bit of the switched capacitor array to complete the switching, the comparator clock is reset to low, and COMP_OUT+ and COMP_OUT- are reset to high. The aild signal is reset to a high level, generating the next comparator clock for the next comparison. When the last latch L0 completes its latching operation, the successive approximation conversion stage ends, Q0 jumps to a high level, and the flip-flop outputs the 7-bit comparison result in parallel to D<6:0>. At the same time, an integrator clock INT is generated, and the ADC enters the residual processing stage. The residual integrator starts working and performs integration on the residual. After the delay of the delay unit, INT is reset to a low level, the residual integration ends, and the DONE signal rises to a high level, marking the end of one quantization cycle of the ADC.

[0046] The circuit structure and timing diagram of the latch are as follows: Figure 8As shown, the latch includes 13 transistors, M1-M13. The latch clock CLK is connected to the gates of M2 and M5; the latch inputs DP and DN are connected to the gates of M8 and M9 respectively; the latch input D is connected to the gates of M1 and M3; the latch output Q is connected to the drains of M5 and M6 and the gates of M10 and M11; the latch output P is connected to the drains of M11 and M13; the latch output N is connected to the drains of M10 and M12; the latch power supply VDD is connected to the sources of M1, M4, and M7; the latch ground VSS is connected to the sources of M3, M6, M12, and M13; the drain of M1 is connected to the gates of M4, M6, and M7, and the drain of M2. QN node; the source of M2 is connected to the drain of M3; the drain of M4 is connected to the source of M5; the drain of M7 is connected to the sources of M8 and M9; the drain of M8 is connected to the source of M10; the drain of M9 is connected to the source of M11; during sampling, CLKS is high, that is, the D terminal is low, at this time M1 is turned on, M3 is turned off, the QN node is charged to high level, M6, M12 and M13 are turned on, M4 and M7 are turned off, and nodes Q, P and N are discharged to low level. It can be found that when the D terminal input is low, the Q terminal output is also low. Therefore, by connecting these latches in series, it is only necessary to input a low level at the D terminal of latch L6 to achieve the sequential reset of all latches. When the input at terminal D is high, M3 is turned on, M1 is turned off, and the comparator starts working. At this time, both COMP_OUT+ and COMP_OUT- are high, the Valid signal is high, M2 is turned on, M5 is turned off, QN is discharged to low, M4 and M7 are turned on, M6, M12 and M13 are turned off, Q terminal floats and remains low, M10 and M11 are turned on, M8 and M9 are turned off, P and N terminals float and remain low. After the comparison is completed, COMP_OUT+ or COMP_OUT- jumps to low. Considering the case where COMP_OUT- is low, M9 is turned on, node P is charged to high. Subsequently, the falling edge of the Valid signal arrives, M5 is turned on to charge node Q to high, M10 and M11 are turned off, and nodes P and N float and latch the comparison result.

[0047] In this embodiment, the control signal generation circuit 102 includes a logic control circuit and multiple switch control circuits; wherein, each charging capacitor switch array corresponds to one switch control circuit; each discharging capacitor switch array corresponds to one switch control circuit; the logic control circuit includes a first edge-triggered flip-flop, a second edge-triggered flip-flop, a third edge-triggered flip-flop, and an AND gate; the data terminal of the first edge-triggered flip-flop is connected to a high level; the clock terminal of the first edge-triggered flip-flop is connected to the time-voltage conversion circuit signal, and is used to receive the conversion completion flag signal sent by the time-voltage conversion circuit; the reset terminal of the first edge-triggered flip-flop is connected to the output terminal of the AND gate; the output terminal of the first edge-triggered flip-flop... The third edge-triggered flip-flop is used to output a sampling control signal based on the conversion completion flag signal; the data terminal of the second edge-triggered flip-flop is connected to a high level; the clock terminal of the second edge-triggered flip-flop is used to receive a reference clock signal; the reset terminal of the second edge-triggered flip-flop is connected to the output terminal of the AND gate; the output terminal of the second edge-triggered flip-flop is used to output the charging control signal based on the reference clock signal; the data terminal of the third edge-triggered flip-flop is connected to a high level; the clock terminal of the third edge-triggered flip-flop is used to receive the frequency-divided clock signal; the reset terminal of the third edge-triggered flip-flop is connected to the output terminal of the AND gate; the output terminal of the third edge-triggered flip-flop is used to output the discharging control signal based on the frequency-divided clock signal; the first input terminal of the AND gate is connected to the second edge-triggered flip-flop. The output of the edge-triggered flip-flop is electrically connected to receive the charging control signal; the second input of the AND gate is electrically connected to the output of the third edge-triggered flip-flop to receive the discharging control signal; the switch control circuit includes a first NOR gate, a second NOR gate, and a third NOR gate; the output of the first edge-triggered flip-flop and the output of the successive approximation circuit are respectively connected to the input of the first NOR gate, so that the first NOR gate receives the sampling control signal and the control signal output by the successive approximation circuit; the output of the first NOR gate and the output of the AND gate are respectively connected to the input of the second NOR gate, so that the second NOR gate receives the charging control signal or the discharging control signal; the third edge-triggered flip-flop is electrically connected to the output of the third edge-triggered flip-flop to receive the charging control signal or the discharging control signal; the second edge-triggered flip-flop is electrically connected to the output of the third edge-triggered flip-flop to receive ... second edge-triggered flip-flop is electrically connected to the output of the third edge-triggered flip-flop to receive the charging control signal or the discharging control signal; the second edge-triggered flip-flop is electrically The output of the NOR gate is connected to the control signal of the charging switch or the discharging switch, and is used to control one end of the charging switch or the discharging switch to be electrically connected to the positive reference voltage terminal; the output of the first edge-triggered trigger, the output of the AND gate, and the control signal output by the successive approximation circuit are respectively connected to the input signal of the third NOR gate, so that the third NOR gate receives the charging control signal, the discharging control signal, or the control signal output by the successive approximation circuit; the output of the third NOR gate is connected to the control signal of the charging switch or the discharging switch, and is used to control one end of the charging switch or the discharging switch to switch the connection state with the negative reference voltage terminal or the positive reference voltage terminal.

[0048] In this embodiment, the control circuit of the switched capacitor array is as follows: Figure 9 As shown, the circuit includes three D flip-flops, an AND gate, a selection switch, a charging / discharging current source, a NOR gate combinational logic, and a capacitor. The D terminal of the first D flip-flop is connected to a high level, the clock terminal is connected to DONE, the reset terminal is connected to the output of the AND gate, and the Q terminal is connected to CLKS. The D terminal of the second D flip-flop is connected to a high level, the clock terminal is connected to REF, the reset terminal is connected to the output of the AND gate, and the Q terminal is connected to UP. The D terminal of the third D flip-flop is connected to a high level, the clock terminal is connected to DIV, the reset terminal is connected to the output of the AND gate, and the Q terminal is connected to DN. The input terminals of the AND gate are connected to UP and DN, and the output is connected to the reset terminal of the D flip-flops. The positive terminal of the first current source is connected to the positive terminal of the first switch, and the negative terminal is grounded. The negative terminal of the first switch is connected to the lower plate of capacitor CP1, and the control terminal is connected to DN. The input terminals of the first NOR gate are connected to CLKS and Ni, and the output terminal is connected to DN and then to the second NOR gate. The inputs of the second NOR gate are connected to the control terminal of the second switch. The positive terminal of the second switch is connected to VREFP, and the negative terminal is connected to the lower stage board of CP1. The inputs of the third NOR gate are connected to CLKS, Ni, and DN, and the output is connected to the control terminal of the third switch. The positive terminal of the third switch is connected to VREFN, and the negative terminal is connected to the lower stage board of CP1. The positive terminal of the second current source is connected to the positive terminal of the fourth switch, and the negative terminal is grounded. The negative terminal of the fourth switch is connected to the lower stage board of capacitor CPN1, and the control terminal is connected to UP. The inputs of the fourth NOR gate are connected to CLKS and Pi, and the output and UP are connected to the inputs of the fifth NOR gate. The output of the fifth NOR gate is connected to the control terminal of the fifth switch, and the positive terminal of the fifth switch is connected to VREFP. The negative terminal of the FP gate is connected to the CN1 sub-board; the input of the sixth NOR gate is connected to CLKS, Pi, and UP, and the output is connected to the control terminal of the sixth switch. The positive terminal of the sixth switch is connected to VREFN, and the negative terminal is connected to the CN1 sub-board; the negative terminal of the third current source is connected to the positive terminal of the seventh switch, and the negative terminal is connected to the power supply. The negative terminal of the seventh switch is connected to the capacitor CP0 sub-board, and the control terminal is connected to UP; the input of the seventh NOR gate is connected to CLKS, Pi, and UP, and the output is connected to the control terminal of the eighth switch. The positive terminal of the eighth switch is connected to VREFP, and the negative terminal is connected to the CP0 sub-board; the input of the eighth NOR gate is connected to CLKS and Pi, and the output and UP are connected to the input of the ninth NOR gate. The output of the ninth NOR gate is connected to the... The control terminal of switch 9 is connected to VREFN, and the negative terminal is connected to the lower stage board of CP0. The negative terminal of the fourth current source is connected to the positive terminal of switch 10, and the negative terminal is connected to the power supply. The negative terminal of switch 10 is connected to the lower stage board of capacitor CN0, and the control terminal is connected to DN. The input terminal of the tenth NOR gate is connected to CLKS, Ni, and DN, and the output terminal is connected to the control terminal of switch 11. The positive terminal of switch 11 is connected to VREFP, and the negative terminal is connected to the lower stage board of CN0. The input terminal of switch 11 is connected to CLKS and Ni, and the output terminal and DN are connected to the input terminal of switch 12. The output terminal of switch 12 is connected to the control terminal of switch 12. The positive terminal of switch 12 is connected to VREFN, and the negative terminal is connected to the lower stage board of CN0. Three D flip-flops and an AND gate are used to generate the charging signal UP, the discharging signal DN, and the sampling clock CLKS. The D terminal of the D flip-flops is connected to a high level, and the clock port is connected to the reference clock REF, the frequency divider output DIV, and the conversion end flag signal DONE, respectively. UP and DN control the selection switch of the charging and discharging current source. At the same time, after passing through an AND gate, they are connected to the reset terminal of the three D flip-flops. The switch for selecting the positive and negative reference voltages VREFP and VREFN is controlled by NOR gate combinational logic. The input signals of the NOR gate include UP, DN, CLKS, Pi, and Ni (i is an integer between 0 and 6, corresponding to the comparison results from low to high bits, respectively). The DONE, Pi, and Ni signals are generated by successive approximation logic circuits. When the rising edge of the DIV signal arrives, DN is set to high level, and the current source begins to discharge capacitor CP1 and charge CN0. When the rising edge of REF also arrives, the AND gate outputs high level, resetting UP, DN, and CLKS to low level. CP1 and CN1 are connected to VREFN, and CP0 and CN0 are connected to VREFP. The time difference between DIV and REF is the charging and discharging time of CP1 and CN0. The difference in charge between the positive and negative capacitors of the capacitor array is positively correlated with the time difference, and the voltage difference between CDAC+ and CDAC- is positively correlated with the time difference, thus realizing a linear conversion from time to voltage.

[0049] In this embodiment, refer to Figures 2 to 9In any one of the time-to-digital converters, the integrator output is connected to the second input of the comparator, and the integrator is controlled by the integrator clock INT; the comparator output is connected to the successive approximation logic circuit, which controls the selection of the switches in the switched capacitor array and outputs a 7-bit digital codeword D<6:0> and a conversion completion flag signal DONE; wherein, after sampling, the asynchronous successive approximation logic circuit will sequentially generate 7 comparator clocks CLKC, 1 integrator clock INT, and 1 conversion completion flag signal DONE. The capacitor array employs a VCM-based switching scheme to achieve successive approximation conversion. If the voltage on the positive capacitor is greater than the voltage on the negative capacitor, the comparator output Comp is 1. The successive approximation logic controls the lower plate of CP0 to switch from VREFP to VREFN, decreasing the voltage on the positive capacitor, and the lower plate of CN1 to switch from VREFN to VREFP, increasing the voltage on the negative capacitor. The opposite occurs when Comp is 0. After the switching of the highest-order switching capacitor is completed, the comparison of the second-highest-order switching capacitor is performed, followed by the switching of the second-highest-order switching capacitor, and so on, until seven comparisons are completed. The comparison result is output through the D<6:0> output port of the successive approximation logic circuit. As mentioned above, when the phase-locked loop is locked, the switch that selects the charging and discharging current source will only be turned on within the dead time. The current noise will only integrate within the dead time, which is only related to the delay of the logic gate and is approximately 60ps. Overall, the structure proposed in this patent breaks the trade-off between noise and linear range in traditional TVCs. Without sacrificing linear range, the integration time of current noise is significantly reduced, thereby reducing the noise introduced by TVC.

[0050] In this embodiment one implementation, refer to Figures 1 to 9 In addition to any of the time-to-digital converters based on split capacitors described in any one of the embodiments, this embodiment also provides a... Figure 10 The low-jitter digital phase-locked loop shown mainly includes a digital filter 801, a digitally controlled oscillator 802, and a frequency divider 803. Figures 1 to 9 The time-to-digital converter 804 as described in any one of the claims; wherein the input terminal of the time-to-digital converter 804 is signal-connected to the output terminal of the frequency divider 803.

[0051] The input terminal of the time-to-digital converter 804 receives a reference clock signal and a frequency-divided clock signal output by the frequency divider, and is used to obtain the residual voltage corresponding to the reference clock signal and the frequency-divided clock signal, as well as the multi-bit digital codeword corresponding to the residual voltage.

[0052] The input terminal of the digital filter 801 is connected to the output terminal of the time-to-digital converter 804, and is used to receive the multi-digit codeword and generate the frequency control word corresponding to the multi-digit codeword.

[0053] The control terminal of the numerically controlled oscillator 802 is connected to the output terminal of the digital filter 801, and is used to receive the frequency control word and output the frequency multiplication signal corresponding to the reference clock signal according to the frequency control word.

[0054] The input terminal of the frequency divider 803 is connected to the output terminal of the numerically controlled oscillator 802, and is used to receive the frequency multiplication signal and divide the frequency multiplication signal to output a frequency-divided clock signal to the time-to-digital converter 804.

[0055] In this embodiment, the reference clock signal is connected to the positive input terminal of the time-to-digital converter (TD-SCDMA); the frequency divider output signal DIV is connected to the negative input terminal of the TD-SCDMA; the output of the TD-SCDMA is connected to the input terminal of the digital filter; the output of the digital filter is connected to the input terminal of the numerically controlled oscillator (CNC). The CNC oscillator output OUT is connected to the input terminal of the frequency divider. The time-to-digital converter converts the time difference between the rising edges of the reference clock signal REF and the frequency divider output signal DIV into a digital codeword. This digital codeword is filtered by a digital filter to adjust the oscillation frequency of the CNC oscillator. The oscillation signal is divided by the frequency divider to obtain the DIV signal. After the system stabilizes, the rising edges of REF and DIV are aligned. The output frequency of the CNC oscillator is N times that of the reference clock signal, realizing the functions of frequency multiplication and phase locking, where N is the division ratio of the frequency divider.

[0056] In this embodiment one implementation, refer to Figure 11 As shown in the diagram, the digital filter is clocked by a reference clock (REF) and achieves loop stabilization through proportional and integral control. An Infinite Impulse Response (IIR) low-pass filter attenuates the high-frequency quantization noise generated by the NS SAR ADC, limiting its impact on the output phase noise. This type of filter is chosen because of its inherent stability. The preceding NS SAR ADC outputs a 7-bit digital codeword, which is fed into the digital filter. After subtracting the digital code corresponding to the common-mode voltage, the codeword passes through a first-order IIR low-pass filter and a proportional-integral (PI) controller, finally outputting a 16-bit digital codeword to the subsequent stage. In the digital-to-analog converter, coefficient a is set to 256, which is used to left-shift the 7-bit input codeword to the second-highest bit (the highest bit is the sign bit) to improve calculation accuracy. Coefficient b is set to 0.7, which determines the cutoff frequency of the filter. If the cutoff frequency is too low, the system will be unstable. If the cutoff frequency is too high, the high-frequency quantization noise of the noise-integrated SAR ADC will not be sufficiently attenuated. Coefficient c is set to 40, and the loop bandwidth is 1MHz.

[0057] In this first embodiment, the numerically controlled oscillator 802 includes a digital shaping and modulation circuit, a resistive digital-to-analog converter circuit, an analog filter circuit, and an inductor-capacitor voltage-controlled oscillator circuit. The input terminal of the digital shaping and modulation circuit is electrically connected to the output terminal of the digital filter, and is used to receive the frequency control word, perform noise shaping and modulation on the frequency control word, and output a one-bit wide digital code stream. The input terminal of the resistive digital-to-analog converter circuit is electrically connected to the output terminal of the digital shaping and modulation circuit, and is used to convert the one-bit wide digital code stream into an analog voltage signal. The input terminal of the analog filter circuit is electrically connected to the output terminal of the resistive digital-to-analog converter circuit, and is used to filter out high-frequency quantization noise in the analog voltage signal to obtain a filtered analog voltage signal. The voltage control terminal of the inductor-capacitor voltage-controlled oscillator circuit is electrically connected to the output terminal of the analog filter circuit, and is used to generate a frequency multiplier signal with a target frequency based on the filtered analog control voltage. Specifically, the numerically controlled oscillator includes a digital-to-analog converter, a first oscillation capacitor, a second oscillation capacitor, an oscillation resistor, an adjustable resistor, a first oscillation transistor, a second oscillation transistor, a third oscillation transistor, a fourth oscillation transistor, an inductor, a first varactor transistor, and a second varactor transistor; wherein, the positive terminal of the first oscillation capacitor and the positive terminal of the oscillation resistor are electrically connected to the output terminal of the digital-to-analog converter; the negative terminal of the first oscillation capacitor is grounded; the negative terminal of the second oscillation capacitor is grounded; the positive terminal of the second oscillation capacitor, the positive terminal of the first varactor transistor, and the positive terminal of the second varactor transistor are electrically connected to the negative terminal of the oscillation resistor; the source of the first oscillation transistor and the second varactor transistor ... source of the first oscillation transistor and the second varactor transistor are electrically connected to the output terminal of the digital-to-analog converter; the source of the first oscillation transistor and the second varactor transistor are electrically connected to the output terminal of the digital-to-analog converter; the source of the first oscillation transistor and the second varactor transistor are electrically connected to the output terminal of the digital-to-analog converter; the source of the first oscillation transistor and the second varactor transistor are electrically connected to the output terminal of the digital-to-analog converter; the source of the first oscil The source of the oscillating transistor is electrically connected to the positive terminal of the adjustable resistor; the gate of the second oscillating transistor, the gate of the fourth oscillating transistor, the drain of the third oscillating transistor, the positive terminal of the inductor, the positive terminal of the capacitor array, and the negative terminal of the first varactor transistor are electrically connected to the drain of the first oscillating transistor; the gate of the first oscillating transistor, the gate of the third oscillating transistor, the drain of the fourth oscillating transistor, the negative terminal of the inductor, the negative terminal of the capacitor array, and the negative terminal of the second varactor transistor are electrically connected to the negative terminal of the second oscillating transistor; the source of the third oscillating transistor and the source of the fourth oscillating transistor are connected to the power supply voltage.

[0058] In this embodiment, refer to Figure 12The schematic diagram of the numerically controlled oscillator (VCO) shows that it employs an architecture combining a digital-to-analog converter (DAC) and an analog voltage-controlled oscillator (VCO). This approach simplifies the VCO design by eliminating the need for an ultra-high-precision capacitor array. The digital loop filter outputs a 16-bit signal to a first-order digital Δ-Σ modulator, which then drives a 7-bit R-2R architecture DAC. The shaped high-frequency quantization noise is attenuated by a second-order RC filter, thereby improving the DAC's effective resolution. The first-stage resistor of the second-order RC filter is the equivalent output resistance of the R-2R DAC. The core advantage of the R-2R DAC architecture is that its output resistance remains constant regardless of changes in the DAC input codeword. The design of the VCO determines the phase noise performance outside the PLL loop bandwidth. To achieve lower integral jitter, an inductor-capacitor resonant oscillator is used instead of a ring oscillator. Using complementary cross-coupled transistors provides twice the negative resistance, thus improving energy efficiency. The center frequency of the voltage-controlled oscillator is 5.8 GHz. Oscillation signals at this frequency are commonly used in 5G wireless communication systems. The coarse and fine tuning of the voltage-controlled oscillator frequency are achieved through a switched capacitor array and a varactor transistor, respectively. The frequency tuning coefficient KVCO of the varactor transistor is 100 MHz / V, the output swing of the DAC is 600 mV, and the frequency fine tuning range is 60 MHz. This is used to combat frequency shifts caused by temperature and power supply voltage fluctuations. The 5-bit switched capacitor array is used to combat frequency shifts caused by process technology. The tuning accuracy is 50 MHz / bit, which is slightly higher than the frequency tuning range of the varactor transistor to ensure the continuity of the frequency tuning curve.

[0059] Specifically, the DAC output is connected to the positive terminals of C1 and R1; the negative terminals of C1 and C2 are grounded; the negative terminal of R1 is connected to the positive terminal of C2 and the positive terminal of the varactor transistor; the positive terminal of the adjustable resistor R2 is connected to the source terminals of M1 and M2, and the negative terminal is grounded; the drain terminal of M1 is connected to the gate terminals of M2 and M4, the drain terminal of M3, the positive terminal of inductor L1, the positive terminal of the switched capacitor array, and the negative terminal of the first varactor transistor; the drain terminal of M2 is connected to the gate terminals of M1 and M3, the drain terminal of M4, the negative terminal of inductor L1, the negative terminal of the switched capacitor array, and the negative terminal of the second varactor transistor; the source terminals of M3 and M4 are connected to the power supply.

[0060] This embodiment provides a time-to-digital converter and a low-jitter digital phase-locked loop based on split capacitors. The split capacitor structure achieves accurate conversion of time difference to voltage, reducing quantization errors and power consumption. Specifically, the capacitor array provides the foundation for split capacitors, allowing independent control of the charging and discharging processes and reducing capacitor matching requirements. The control signal generation circuit receives a reference clock and a frequency-divided clock based on the conversion completion flag signal, ensuring timing synchronization to avoid error accumulation. It then generates a charging control signal corresponding to the reference time signal based on the reference clock and a discharging control signal corresponding to the feedback time signal based on the frequency-divided clock, thus accurately capturing the time difference. The charging and discharging power supply operates the capacitor array according to the charging and discharging control signals respectively, forming a residual voltage representing the time difference information. After receiving the residual voltage, the time-to-voltage conversion circuit dynamically switches the reference voltage connection state through multiple quantization operations, obtaining the residual voltage values ​​under different states, generating a multi-bit digital codeword and a conversion completion flag signal, improving resolution and reducing noise introduction.

[0061] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A time-to-digital converter based on a split capacitor, characterized in that, It includes a capacitor array, a control signal generation circuit, a time-to-digital conversion circuit, and a charging / discharging power supply; wherein, the output terminal of the capacitor array is electrically connected to the input terminal of the time-to-digital conversion circuit; the control terminal of the capacitor array is signal-connected to the output terminal of the time-to-voltage conversion circuit; and the output terminal of the charging / discharging power supply is electrically connected to the input terminal of the capacitor array. The control signal generation circuit is signal-connected to the time-to-digital converter circuit and is used to receive the conversion completion flag signal fed back by the time-to-digital converter circuit, so as to receive the reference clock signal and the frequency-divided clock signal corresponding to the reference clock signal according to the conversion completion flag signal. The control signal generation circuit generates a charging control signal based on the reference clock signal and a discharging control signal based on the frequency-divided clock signal. The charging and discharging power supply is connected to the control signal generation circuit to charge the capacitor array according to the charging control signal and discharge the capacitor array according to the discharging control signal, so that the capacitor array forms a residual voltage. The input terminal of the time-to-voltage conversion circuit is electrically connected to the output terminal of the capacitor array, and is used to receive the residual voltage and perform multiple quantization operations on the residual voltage to obtain the digital codeword corresponding to each quantization operation, thereby obtaining the multi-bit digital codeword corresponding to the residual voltage and generating the conversion completion flag signal; wherein, the quantization operation includes the time-to-voltage conversion circuit switching the reference voltage connection state of the capacitor array according to the residual voltage to obtain the residual voltage corresponding to each reference voltage connection state.

2. A time-to-digital converter based on a split capacitor according to claim 1, characterized in that, The capacitor array includes multiple charging capacitors and multiple discharging capacitors that are mirror-symmetrical; wherein each charging capacitor is connected in series with a charging switch; and each discharging capacitor is connected in series with a discharging switch. The lower electrode of the charging capacitor is electrically connected to the fixed terminal of the charging switch; the lower electrode of the discharging capacitor is electrically connected to the fixed terminal of the discharging switch. The first terminal of the charging switch is electrically connected to the positive reference voltage terminal; the second terminal of the charging switch is electrically connected to the negative reference voltage terminal; the third terminal of the charging switch is electrically connected to the output terminal of the charging power supply in the charging and discharging power supply, and is used to receive the charging current of the charging power supply; the first terminal of the discharging switch is electrically connected to the positive reference voltage terminal; the second terminal of the discharging switch is electrically connected to the negative reference voltage terminal; the third terminal of the discharging switch is electrically connected to the output terminal of the discharging power supply in the charging and discharging power supply, and is used to receive the discharging current of the discharging power supply. The control terminal of the third end of the charging switch is connected to the control signal generating circuit for receiving the charging control signal and transmitting the charging current to the charging capacitor according to the charging control signal to charge the charging capacitor. The control terminal of the third end of the discharge switch is connected to the control signal generating circuit for receiving the discharge control signal and transmitting the discharge current to the discharge capacitor according to the discharge control signal to charge the discharge capacitor. The upper plates of each of the charging capacitors are electrically connected to each other to form a charging sensing node; the upper plates of each of the discharging capacitors are electrically connected to each other to form a discharging sensing node; the charging sensing node and the discharging sensing node are respectively electrically connected to the input terminal of the time-to-digital conversion circuit. The charging sensing node acquires the energy of the multiple charging capacitors to form a charging voltage; the discharging sensing node acquires the energy of the multiple discharging capacitors to form a discharging voltage. The charging sensing node and the discharging sensing node serve as the output terminals of the capacitor array to form a residual voltage based on the charging voltage and the discharging voltage, and then transmit the residual voltage to the time-to-digital conversion circuit.

3. A time-to-digital converter based on a split capacitor according to claim 2, characterized in that, The time-to-digital conversion circuit includes a residual integrator; wherein the residual integrator includes a switched capacitor integrator circuit, a floating inverter amplifier, and an output sampling circuit. The input terminal of the switched capacitor integrator circuit is electrically connected to the output terminal of the capacitor array, used to receive the residual voltage, integrate the residual voltage, and output an integrated voltage. The switched capacitor integrator circuit includes a first switch, a second switch, a first capacitor, and a second capacitor. The positive terminal of the first switch is electrically connected to the charging sensing node; the positive terminal of the second switch is electrically connected to the discharging sensing node; the control terminals of the first and second switches are used to receive an integration control clock signal; the positive terminal of the first capacitor and the negative input terminal of the floating inverter amplifier are respectively electrically connected to the negative terminal of the first switch; the positive terminal of the second capacitor and the positive input terminal of the floating inverter amplifier are respectively electrically connected to the negative terminal of the second switch; when the integration control clock signal is high, the first and second switches are turned on, and the residual voltage is sampled to the input terminal of the floating inverter amplifier through the first and second capacitors. The input terminal of the floating inverter amplifier is electrically connected to the output terminal of the switched capacitor integrator circuit, and is used to receive the integrated voltage and amplify the integrated voltage to output a common-mode voltage. The output sampling circuit is used to sample the integrated voltage to the input terminal of the comparator; wherein, the output sampling circuit includes a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, and a fourth capacitor; wherein, the control terminals of the third switch and the fourth switch are used to receive the NOT signal of the integration control clock; the negative terminals of the third switch and the fourth switch are electrically connected to the common-mode level; the control terminals of the fifth switch and the sixth switch are used to receive the integration control clock; the positive terminal of the fifth switch is electrically connected to the negative terminal of the third capacitor; the positive terminal of the sixth switch is electrically connected to the negative terminal of the fourth capacitor; the negative terminals of the fifth switch and the sixth switch are respectively electrically connected to the common-mode level; Specifically, when the integral control clock is low, the third and fourth switches are turned on, the output of the floating inverter amplifier is connected to the common-mode voltage, the fifth and sixth switches are turned off, and the output sampling circuit is in a reset state; when the integral control clock is high, the third and fourth switches are turned off, and the fifth and sixth switches are turned on; the third and fourth capacitors sample the common-mode voltage output by the floating inverter amplifier. The negative terminal of the first capacitor, the positive terminal of the third capacitor, and the positive terminal of the third switch are respectively connected to the positive output terminal of the floating inverter amplifier; the negative terminal of the second capacitor, the positive terminal of the fourth capacitor, and the positive terminal of the fourth switch are respectively electrically connected to the negative output terminal of the floating inverter amplifier. The floating inverter amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a seventh switch, an eighth switch, and a fifth capacitor; wherein: the positive terminal of the seventh switch is electrically connected to the positive terminal of the fifth capacitor; the negative terminal of the seventh switch is electrically connected to the positive node of the floating power supply; the control terminal of the seventh switch is used to receive the non-signal of the integration control clock; the positive terminal of the eighth switch is electrically connected to the negative terminal of the fifth capacitor; the negative terminal of the eighth switch is electrically connected to the negative node of the floating power supply; the control terminal of the eighth switch is used to receive the non-signal of the integration control clock. Specifically, when the integral control clock is low, the seventh and eighth switches are turned on, and the floating inverter amplifier is in a reset state; when the integral control clock is high, the seventh and eighth switches are turned off, and the two ends of the fifth capacitor are respectively connected to the negative node and the positive node of the floating power supply to provide floating power to the floating inverter amplifier. The gates of the first transistor and the seventh transistor are electrically connected to the positive input terminal of the floating inverter amplifier; the gates of the second transistor and the eighth transistor are electrically connected to the negative input terminal of the floating inverter amplifier; the gates of the third transistor and the fourth transistor are electrically connected to the positive node of the floating power supply; the gates of the fifth transistor and the sixth transistor are electrically connected to the negative node of the floating power supply; the source of the first transistor is electrically connected to the negative node of the floating power supply; the drain of the first transistor is electrically connected to the source of the third transistor; the source of the second transistor is electrically connected to the negative node of the floating power supply; the drain of the second transistor is electrically connected to the source of the fourth transistor; the source of the seventh transistor is electrically connected to the positive node of the floating power supply; the drain of the seventh transistor is electrically connected to the source of the fifth transistor; the source of the eighth transistor is connected to the positive node of the floating power supply; and the drain of the eighth transistor is electrically connected to the source of the sixth transistor. The drains of the sixth transistor and the fourth transistor are electrically connected to the positive output terminal of the floating inverter amplifier, respectively; the drains of the third transistor and the fifth transistor are electrically connected to the negative output terminal of the floating inverter amplifier, respectively. The gates of the third transistor and the fourth transistor are electrically connected to the positive node of the floating power supply; the gates of the fifth transistor and the sixth transistor are electrically connected to the negative node of the floating power supply; the sources of the seventh transistor and the eighth transistor are electrically connected to the positive node of the floating power supply; and the sources of the first transistor and the second transistor are electrically connected to the negative node of the floating power supply.

4. A time-to-digital converter based on a split capacitor according to claim 3, characterized in that, The time-to-digital converter circuit includes a dual-input comparator; wherein the dual-input comparator is used to obtain the common-mode voltage and the residual voltage output by the capacitor array, so as to obtain the binary comparison result of the common-mode voltage and the residual voltage; The dual-input comparator includes a first input transistor, a second input transistor, a third input transistor, a fourth input transistor, a fifth input transistor, a sixth input transistor, a seventh input transistor, an eighth input transistor, a ninth input transistor, a tenth input transistor, an eleventh input transistor, a twelfth input transistor, a thirteenth input transistor, a first output buffer, and a second output buffer. In this configuration, the source of the first input transistor is grounded; the sources of the second, third, fourth, and fifth input transistors are electrically connected to the drain of the first input transistor; the gates of the second and fifth input transistors are electrically connected to form the first differential input pair of the dual-input comparator; the gates of the third and fourth input transistors are electrically connected to form the second differential input pair of the dual-input comparator; the drains of the third, eighth, and sixth input transistors are electrically connected to the drain of the second input transistor; the drains of the fifth, thirteenth, and seventh input transistors are electrically connected to the source of the second input transistor. The drain of the fourth input transistor is not electrically connected; the drain of the ninth input transistor, the drain of the tenth input transistor, the gate of the seventh input transistor, the gate of the eleventh input transistor, and the input terminal of the first output buffer are respectively electrically connected to the drain of the sixth input transistor; the drain of the eleventh input transistor, the drain of the twelfth input transistor, the gate of the sixth input transistor, the gate of the tenth input transistor, and the input terminal of the second output buffer are respectively electrically connected to the drain of the seventh input transistor; the source of the eighth input transistor, the source of the ninth input transistor, the source of the tenth input transistor, the source of the eleventh input transistor, the source of the twelfth input transistor, and the source of the thirteenth input transistor are respectively electrically connected to the power supply voltage; The output terminals of the first and second output buffers constitute the differential output terminals of the dual-input comparator, which are used to output the binary comparison result.

5. A time-to-digital converter based on a split capacitor according to claim 4, characterized in that, The time-to-digital conversion circuit also includes a successive approximation logic circuit. The input terminal of the successive approximation logic circuit is electrically connected to the differential output terminal of the dual-input comparator to receive the binary comparison result; the output terminal of the successive approximation logic circuit is connected to the control terminal signal of the capacitor array to switch the switching connection state of the capacitor array according to the binary comparison result. The successive approximation logic circuit includes a first AND gate, a first NOR gate, a first inverter, a first XOR gate, a delay circuit, multiple latches, and multiple flip-flops. The data input terminal of each latch and the input terminal of the first AND gate are electrically connected to the differential output terminal, respectively. The clock terminal of each latch is electrically connected to the output terminal of the first AND gate to receive the valid signal output by the first AND gate; The enable terminals of multiple latches are connected in series; the output terminal of each latch is connected to the control terminal signal of the charging switch or the discharging switch to switch the connection state of the charging switch or the discharging switch. The input terminal of the delay circuit, the first input terminal of the first XOR gate, and the output terminal of the last latch among the plurality of latches are electrically connected; The output of the delay circuit is electrically connected to the second input of the first XOR gate, and is used to output a conversion completion flag signal; the output of the first XOR gate outputs an integrator to control the clock. The output terminal of the latch is electrically connected to the data input terminal of the flip-flop; the clock terminal of each flip-flop is electrically connected to the output terminal of the last latch; the output terminals of multiple flip-flops are used to output the multi-bit digital codeword corresponding to the residual voltage.

6. A time-to-digital converter based on a split capacitor according to claim 5, characterized in that, The latch includes a first latch transistor, a second latch transistor, a third latch transistor, a fourth latch transistor, a fifth latch transistor, a sixth latch transistor, a seventh latch transistor, an eighth latch transistor, a ninth latch transistor, a tenth latch transistor, an eleventh latch transistor, a twelfth latch transistor, and a thirteenth latch transistor. The source of the first latching transistor and the source of the fourth latching transistor are electrically connected to the power supply voltage; the gate of the first latching transistor is electrically connected to the gate of the fourth latching transistor. The gates of the fourth latch transistor, the sixth latch transistor, the seventh latch transistor, and the drain of the second latch transistor are electrically connected to the drain of the first latch transistor, respectively. The source of the second latch transistor is connected to the drain of the third latch transistor; the gate of the second latch transistor receives the latch clock. The source of the third latch transistor is grounded; the gate of the third latch transistor receives the latch enable signal; the drain of the fourth latch transistor is electrically connected to the source of the fifth latch transistor; the drain of the fifth latch transistor is electrically connected to the drain of the sixth latch transistor and serves as the latch output terminal; the gate of the fifth latch transistor receives the latch clock; the source of the sixth latch transistor is grounded. The source of the seventh latch transistor is connected to the power supply voltage; the sources of the eighth latch transistor and the ninth latch transistor are electrically connected to the drain of the seventh latch transistor, respectively. The gate of the eighth latch transistor serves as the first data input terminal of the latch; the gate of the ninth latch transistor serves as the second data input terminal of the latch; the source of the tenth latch transistor and the source of the eleventh latch transistor are electrically connected to the gate of the eighth latch transistor, respectively; the source of the tenth latch transistor and the source of the eleventh latch transistor are electrically connected to the gate of the ninth latch transistor, respectively. The gates of the tenth latch transistor and the eleventh latch transistor are respectively connected to the output terminal of the latch; the drain of the tenth latch transistor serves as the first output terminal of the latch; and the drain of the eleventh latch transistor serves as the second output terminal of the latch. The source of the twelfth latch transistor and the source of the thirteenth latch transistor are grounded; the gate of the twelfth latch transistor and the gate of the thirteenth latch transistor are respectively connected to the output terminal of the latch; the drain of the twelfth latch transistor is electrically connected to the first output terminal; and the drain of the thirteenth latch transistor is electrically connected to the second output terminal.

7. A time-to-digital converter based on a split capacitor according to any one of claims 2-6, characterized in that, The control signal generation circuit includes a logic control circuit and multiple switch control circuits; wherein, each of the charging capacitor switch arrays corresponds to one switch control circuit; and each of the discharging capacitor switch arrays corresponds to one switch control circuit. The logic control circuit includes a first edge-triggered flip-flop, a second edge-triggered flip-flop, a third edge-triggered flip-flop, and an AND gate. The data terminal of the first edge-triggered flip-flop is connected to a high level. The clock terminal of the first edge-triggered flip-flop is connected to the time-to-voltage conversion circuit and is used to receive a conversion completion flag signal sent by the time-to-voltage conversion circuit. The reset terminal of the first edge-triggered flip-flop is connected to the output terminal of the AND gate. The output terminal of the first edge-triggered flip-flop is used to output a sampling control signal based on the conversion completion flag signal. The data terminal of the second edge-triggered flip-flop is connected to a high level. The clock terminal of the second edge-triggered flip-flop is used to receive a reference clock signal. The reset terminal of the second edge-triggered flip-flop is connected to the output terminal of the AND gate. The output terminal of the second edge-triggered flip-flop is used to output a charging control signal based on the reference clock signal. The data terminal of the third edge-triggered flip-flop is connected to a high level. The clock terminal of the third edge-triggered flip-flop is used to receive a frequency-divided clock signal. The reset terminal of the third edge-triggered flip-flop is connected to the output terminal of the AND gate. The output terminal of the third edge-triggered flip-flop is used to output a discharging control signal based on the frequency-divided clock signal. The first input terminal of the AND gate is electrically connected to the output terminal of the second edge-triggered flip-flop to receive the charging control signal; the second input terminal of the AND gate is electrically connected to the output terminal of the third edge-triggered flip-flop to receive the discharging control signal. The switch control circuit includes a first NOR gate, a second NOR gate, and a third NOR gate. The output of the first edge-triggered trigger and the output of the successive approximation circuit are respectively connected to the input of the first NOR gate, so that the first NOR gate receives the sampling control signal and the control signal output by the successive approximation circuit. The output of the first NOR gate and the output of the AND gate are respectively connected to the input of the second NOR gate, so that the second NOR gate receives the charging control signal or the discharging control signal. The output of the second NOR gate is connected to the control terminal of the charging switch or the discharging switch for control. One end of the charging switch or the discharging switch is electrically connected to the positive reference voltage terminal; the output terminal of the first edge-triggered trigger, the output terminal of the AND gate, and the control signal output by the successive approximation circuit are respectively connected to the input terminal signal of the third NOR gate, so that the third NOR gate receives the charging control signal, the discharging control signal, or the control signal output by the successive approximation circuit; the output terminal of the third NOR gate is connected to the control terminal signal of the charging switch or the discharging switch, and is used to control one end of the charging switch or the discharging switch to switch the connection state with the negative reference voltage terminal or the positive reference voltage terminal.

8. A low-jitter digital phase-locked loop, characterized in that, The system includes a digital filter, a numerically controlled oscillator, and a frequency divider, as well as a time-to-digital converter based on a split capacitor as described in any one of claims 1-7; wherein the input terminal of the time-to-digital converter is signal-connected to the output terminal of the frequency divider; The input terminal of the time-to-digital converter receives a reference clock signal and a divided clock signal output by the frequency divider, and is used to obtain the residual voltage corresponding to the reference clock signal and the divided clock signal, and the multi-bit digital codeword corresponding to the residual voltage. The input terminal of the digital filter is connected to the output terminal of the time-to-digital converter, and is used to receive the multi-digit codeword and generate the frequency control word corresponding to the multi-digit codeword. The control terminal of the numerically controlled oscillator is connected to the output terminal of the digital filter, and is used to receive the frequency control word and output the frequency multiplication signal corresponding to the reference clock signal according to the frequency control word. The input terminal of the frequency divider is connected to the output terminal of the numerically controlled oscillator, and is used to receive the frequency multiplier signal and divide the frequency multiplier signal to output a frequency-divided clock signal to the time-to-digital converter.

9. A low-jitter digital phase-locked loop according to claim 8, characterized in that, The numerically controlled oscillator includes a digital shaping and modulation circuit, a resistive digital-to-analog converter circuit, an analog filter circuit, and an inductor-capacitor voltage-controlled oscillator circuit. The input terminal of the digital shaping and modulation circuit is electrically connected to the output terminal of the digital filter, and is used to receive the frequency control word, perform noise shaping and modulation on the frequency control word, and output a one-bit wide digital code stream. The input terminal of the resistive digital-to-analog converter circuit is electrically connected to the output terminal of the digital shaping and modulation circuit, and is used to convert the one-bit wide digital code stream into an analog voltage signal. The input terminal of the analog filter circuit is electrically connected to the output terminal of the resistive digital-to-analog converter circuit, and is used to filter out high-frequency quantization noise in the analog voltage signal to obtain a filtered analog voltage signal. The voltage control terminal of the inductor-capacitor voltage-controlled oscillator circuit is electrically connected to the output terminal of the analog filter circuit, and is used to generate a frequency multiplier signal with a target frequency based on the filtered analog control voltage.

10. A low-jitter digital phase-locked loop according to claim 9, characterized in that, The numerically controlled oscillator includes a digital-to-analog converter, a first oscillation capacitor, a second oscillation capacitor, an oscillation resistor, an adjustable resistor, a first oscillation transistor, a second oscillation transistor, a third oscillation transistor, a fourth oscillation transistor, an inductor, a first varactor transistor, and a second varactor transistor. The positive terminals of the first oscillation capacitor and the oscillation resistor are electrically connected to the output terminal of the digital-to-analog converter. The negative terminal of the first oscillation capacitor is grounded. The negative terminal of the second oscillation capacitor is grounded. The positive terminals of the second oscillation capacitor, the first varactor transistor, and the second varactor transistor are electrically connected to the negative terminal of the oscillation resistor. The sources of the first and second oscillation transistors are electrically connected to the positive terminal of the adjustable resistor. The gate of the second oscillating transistor, the gate of the fourth oscillating transistor, the drain of the third oscillating transistor, the positive terminal of the inductor, the positive terminal of the capacitor array, and the negative terminal of the first varactor transistor are respectively electrically connected to the drain of the first oscillating transistor. The gate of the first oscillating transistor, the gate of the third oscillating transistor, the drain of the fourth oscillating transistor, the negative terminal of the inductor, the negative terminal of the capacitor array, and the negative terminal of the second varactor transistor are respectively electrically connected to the negative terminal of the second oscillating transistor. The source of the third oscillating transistor and the source of the fourth oscillating transistor are respectively connected to the power supply voltage.

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