High-precision low-delay analog-to-digital converter based on proportional floating inverting amplifier

Abstract

The invention discloses a high-precision and low-delay analog-to-digital converter based on a proportional floating inverting amplifier, which solves the problems that in the prior art, the circuit power consumption overhead is relatively high, and linear scaling of power consumption along with sampling frequency is difficult to realize, and realizes that event driving can be supported and the power consumption is low. Comprising a first summator used for calculating a difference value between an input signal and an output signal of a feedback DAC module; the cascaded first-stage integrator, the cascaded second-stage integrator and the cascaded third-stage integrator are used for respectively carrying out integration processing on the difference signal and the upper-stage output signal subjected to gain coefficient scaling so as to realize noise shaping; the summing circuit is used for summing the input signal scaled by the feed-forward coefficient and the output signal of the three-stage integrator; the single-bit quantizer module quantizes the summation result to generate a digital code stream; the feedback DAC converts the digital code stream into an analog feedback signal; and the cascaded integrator comb filter filters the digital code stream and then outputs a Nyquist rate digital signal.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuits, and more particularly to a high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier. Background Technology

[0002] With the development of digital signal processing technology, the computational precision of digital systems has met complex processing requirements. However, physical signals in nature mainly exist in analog form. Analog-to-digital converters (ADCs), acting as a bridge between the analog information domain and the digital signal domain, function to convert continuous analog signals into discrete digital signals. Among various ADC architectures, the Sigma-Delta ADC, through oversampling and noise shaping techniques, can effectively reduce quantization noise within the signal bandwidth, thereby achieving high resolution. Based on these characteristics, the Sigma-Delta ADC is widely used in medical electronic devices, Internet of Things (IoT) terminals, and high-precision sensor interface circuits.

[0003] However, for applications with extremely limited energy consumption, such as the Internet of Things (IoT) and smart wearable devices, the design of Sigma-Delta analog-to-digital converters (ADCs) is facing unprecedented challenges. To meet the long battery life requirements of portable devices, ADCs must achieve high resolution within a power budget of microwatts or even nanowatts. Traditional discrete-time Sigma-Delta ADCs typically rely on operational transconductance amplifiers (OTAs), which require continuous static bias current to maintain gain and bandwidth. This results in high circuit power consumption and makes it difficult to achieve linear scaling of power consumption with sampling frequency, severely limiting the improvement of energy efficiency. Summary of the Invention

[0004] This invention provides a high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier, which solves the problems of high circuit power consumption and difficulty in achieving linear scaling of power consumption with sampling frequency in the prior art, and achieves event-driven operation with low power consumption.

[0005] This invention provides a high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier, comprising: The first adder 107 is used to receive the input signal V. IN (z) and the first feedback signal, and according to the input signal V IN (z) and the first feedback signal are used to calculate the first difference signal; wherein, the first feedback signal is the output signal of the feedback DAC module 106; the input signal V IN (z) includes: positive phase input signal V IP and inverted input signal V IN ; The first-stage integrator 101 is used to integrate the first difference signal to obtain the first-stage output signal. The second-stage integrator 102 is used to integrate the first-stage output signal after it has been scaled by the first-stage interstage gain coefficient to obtain the second-stage output signal. The third-stage integrator 103 is used to integrate the second-stage output signal after it has been scaled by the inter-stage gain coefficient to obtain the third-stage output signal. A summing circuit is used to scale the input signal V by the input feedforward coefficients. IN (z) and sum the first-stage output signal, the second-stage output signal and the third-stage output signal scaled by different feedforward coefficients respectively to obtain the summation result; Single-bit quantizer module 105 is used to quantize the summation result to generate a digital code stream; Feedback DAC module 106 is used to convert the digital code stream into an analog signal and provide it to the first adder 107 as the first feedback signal; A cascaded integrator comb filter 108 is used to filter the digital code stream and output a Nyquist rate digital signal.

[0006] One or more technical solutions provided in this invention have at least the following technical effects or advantages: This invention improves system linearity by constructing a closed-loop feedback structure using a first adder and significantly enhances common-mode noise suppression by utilizing a fully differential signal processing mechanism. The first-stage integrator performs first-order noise shaping on the difference between the input and feedback signals, pushing quantization noise into the high-frequency region and laying the foundation for subsequent higher-order shaping. The second-stage integrator further enhances the noise shaping effect through second-stage integration, optimizes the signal transfer function, reduces in-band quantization noise power, and optimizes system stability by combining inter-stage gain coefficients. The third-stage integrator performs third-order noise shaping, significantly improving the signal-to-noise ratio within the signal band. Simultaneously, through reasonable gain coefficient settings, it balances system stability and dynamic range, effectively suppressing nonlinear distortion. The summing circuit uses a feedforward architecture to directly weight and sum the integrator output and input signal, avoiding the delay accumulation caused by the main signal path passing through all integrators, and significantly reducing the overall system latency. Furthermore, the zero-point position of the signal transfer function was optimized to improve transient response. The single-bit quantizer module utilizes the inherent linearity of the single-bit quantizer module to completely avoid the complex linearization techniques such as dynamic element matching required in multi-bit ADCs, simplifying system design. At the same time, its one-bit output directly drives the feedback DAC, simplifying the feedback loop structure. The feedback DAC module forms a closed-loop negative feedback system to ensure system stability and confine the quantization error to the feedback loop for shaping. The single-bit DAC only requires two precise reference voltages, avoiding the matching error of multi-level DACs and improving the linearity of the feedback signal. The cascaded integrator-comb filter efficiently filters out quantization noise shaped to the high-frequency region through cascaded integration and comb filtering operations, and performs downsampling to finally output a high signal-to-noise ratio Nyquist rate digital signal, completing the conversion from oversampled high-speed bitstream to high-precision low-frequency output. Attached Figure Description

[0007] Figure 1 A schematic diagram of a high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the feedback DAC module provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a cascaded integrator comb filter structure provided in an embodiment of the present invention; Figure 4 The structural schematic diagram and timing diagram of the proportional floating inverting amplifier provided in the embodiments of the present invention; Figure 5 This is a driving energy storage sub-circuit diagram provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a dual-level shift module provided in an embodiment of the present invention. Detailed Implementation

[0008] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0009] The present invention provides a high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier, comprising: a first adder 107, a first-stage integrator 101, a second-stage integrator 102, a third-stage integrator 103, a summing circuit, a single-bit quantizer module 105, a feedback DAC module 106, and a cascaded integrator-comb filter 108.

[0010] The first adder 107 is used to receive the input signal V. IN (z) and the first feedback signal, and according to the input signal V IN (z) and the first feedback signal are used to calculate the first difference signal; wherein, the first feedback signal is the output signal of the feedback DAC module 106; the input signal V IN (z) includes: positive phase input signal V IP and inverted input signal V IN The first-stage integrator 101 integrates the first difference signal to obtain the first-stage output signal. The second-stage integrator 102 integrates the first-stage output signal scaled by the inter-stage gain coefficient to obtain the second-stage output signal. The third-stage integrator 103 integrates the second-stage output signal scaled by the inter-stage gain coefficient to obtain the third-stage output signal. A summing circuit is used to scale the input signal V by the input feedforward coefficient. IN (z) and the first-stage output signal, the second-stage output signal, and the third-stage output signal scaled by different feedforward coefficients are summed to obtain the summation result. A single-bit quantizer module 105 is used to quantize the summation result to generate a digital code stream; a feedback DAC module 106 is used to convert the digital code stream into an analog signal, which is provided as the first feedback signal to the first adder 107. A cascaded integrator-comb filter 108 is used to filter the digital code stream and output a Nyquist rate digital signal.

[0011] Here, the first-stage integrator 101, the second-stage integrator 102, and the third-stage integrator 103 each include: a dual-level shift module and a proportional floating inverting amplifier 104; the dual-level shift module is used to perform level shifting processing on the output signal of the proportional floating inverting amplifier 104 through multi-sub-phase timing control; the proportional floating inverting amplifier 104 is used as the core operation unit of the integrator, providing signal amplification function through an energy storage capacitor power supply mechanism.

[0012] Specifically, the dual-level shift module includes: a first shift circuit for the positive output terminal and a second shift circuit for the negative output terminal; The first shift circuit includes: a first switch S1 and a first shift capacitor C. CLS1 Second shift capacitor C CLS2 The first switch is connected to the first terminal of the first switch S1, which is connected to the non-inverting output terminal V of the proportional floating inverting amplifier 104. OP The second terminal of the first switch S1 is connected to the first shift capacitor C. CLS1 The upper plate and the second shift capacitor C CLS2 The upper plates are all connected; the first shift capacitor C CLS1 The lower plate is connected to the second terminal of the third switch S3 and the second terminal of the second switch S2; the first terminal of the third switch S3 is connected to the non-inverting output terminal V of the proportional floating inverting amplifier 104. OP Connection; the first terminal of the second switch S2 and the first terminal of the fourth switch S4 are both connected to the common-mode reference voltage V. CM Connection; the second terminal of the fourth switch S4 is connected to the second shift capacitor C. CLS2 The lower stage board and the second terminal of the fifth switch S5 are both connected; the first terminal of the fifth switch S5 is connected to the positive output terminal of the first stage integrator 101.

[0013] Here, the proportional floating inverting amplifier 104 in the first-stage integrator 101 includes: a driver-stage floating inverting amplifier and a load-stage floating inverting amplifier; The driver-stage floating inverting amplifier is used to convert the first difference signal into a first current signal; the load-stage floating inverting amplifier is used to provide an impedance load for the driver-stage floating inverting amplifier and to set the voltage gain of the proportional floating inverting amplifier 104 by the transistor size ratio between the driver-stage floating inverting amplifier and the load-stage floating inverting amplifier, so as to obtain the first stage output signal.

[0014] For details, see as follows Figure 4 A driver-stage floating inverting amplifier, comprising: a first PMOS transistor M P1 The first NMOS transistor M N1 The second PMOS transistor M P2 The second NMOS transistor M N2 and drive energy storage sub-circuit; here, the first PMOS transistor MP1 and the first NMOS transistor M N1 The first inverter is formed by the first PMOS transistor MP2 and the second NMOS transistor MN2.

[0015] First PMOS transistor MP1 The gate of the first NMOS transistor M N1 The gate and the positive input signal V IP Connection; First PMOS transistor M P1 The source of the second PMOS transistor M P2 The sources of all transistors are connected to the first power supply point of the driving energy storage sub-circuit; the first PMOS transistor M P1 The drain of the first NMOS transistor M N1 The third PMOS transistor M in the drain-load stage floating inverting amplifier P3 The third PMOS transistor M in the gate, load stage floating inverting amplifier P3 The third NMOS transistor M in the drain-load stage floating inverting amplifier N3 The drain and the third NMOS transistor M in the load stage floating inverting amplifier N3 The gates of all are connected to the inverting output terminal V. ON The first NMOS transistor M N1 The source of the second NMOS transistor M N2 The source of the second PMOS transistor is connected to the second power supply node of the driving energy storage sub-circuit; P2 Gate of the second NMOS transistor M N2 The gate and inverted input signal V IN Connection; Second PMOS transistor M P2 The drain of the second NMOS transistor M N2 The fourth PMOS transistor M in the drain-load stage floating inverting amplifier P4 The fourth PMOS transistor M in the gate-load stage floating inverting amplifier P4 The fourth NMOS transistor M in the drain-load stage floating inverting amplifier N4 The gate and the fourth NMOS transistor M in the load stage floating inverting amplifier N4 The drains of all terminals are connected to the non-inverting output terminal V. OP .

[0016] See Figure 4 and Figure 5 The driving energy storage sub-circuit includes: three parallel driving energy storage units; each driving energy storage unit includes: a first energy storage capacitor C. R1 Switches S6, S7, S8, and S9; and the first energy storage capacitor C. R1 The upper plate is connected to the first terminal of the sixth switch S6 and the first terminal of the seventh switch S7; the first energy storage capacitor C R1The lower electrode plate is connected to the first terminal of the ninth switch S9 and the first terminal of the eighth switch S8; the second terminal of the sixth switch S6 is connected to the power supply voltage VDD; the second terminal of the seventh switch S7 is connected to the first power supply point; the second terminal of the ninth switch S9 is grounded; and the second terminal of the eighth switch S8 is connected to the second power supply node.

[0017] Specifically, the load-stage floating inverting amplifier includes: a third PMOS transistor M P3 The third NMOS transistor M N3 The fourth PMOS transistor M P4 The fourth NMOS transistor M N4 and load energy storage sub-circuit; here, the third PMOS transistor M P3 and the third NMOS transistor M N3 Forming the third inverter, the fourth PMOS transistor M P4 and the fourth NMOS transistor M N4 Form the fourth inverter; The third PMOS transistor M P3 The gate of the first PMOS transistor M of the driver stage floating inverting amplifier P1 The drain, driver stage, floating inverting amplifier's first NMOS transistor M N1 The drain of the third PMOS transistor M P3 The drain of the third NMOS transistor M N3 The drain and the third NMOS transistor M N3 The gate is connected to the inverting output terminal V. ON The third PMOS transistor M P3 The source of the fourth PMOS transistor M P4 The source of the transistor is connected to the third power supply node of the load energy storage sub-circuit; the third NMOS transistor M N3 The source of the fourth NMOS transistor M N4 The source of the transistor is connected to the fourth power supply node of the load energy storage sub-circuit; the third NMOS transistor M N3 The gate of the third PMOS transistor M P3 Gate connection; fourth PMOS transistor M P4 The drain of the fourth PMOS transistor M P4 The gate of the fourth NMOS transistor M N4 The drain and the fourth NMOS transistor M N4 The second PMOS transistor M of the gate, driver stage floating inverting amplifier P2 The drain and driver stage of the floating inverting amplifier's second NMOS transistor M N2 The drain is connected to the non-inverting output terminal V. OP .

[0018] The load energy storage sub-circuit includes: three load energy storage units connected in parallel; each load energy storage unit includes: a fourth energy storage capacitor C. R4 18th switch S 18 Nineteenth switch S 19 20th switch S 20 Twentieth switch S 21 Fourth energy storage capacitor C R4 The upper electrode plate and the eighteenth switch S 18 The first terminal and the nineteenth switch S 19 The first terminal is connected; the fourth energy storage capacitor C R4 The lower electrode plate and the twentieth switch S 20 The first terminal and the twentieth switch S 21 The first end is connected; the eighteenth switch S 18 The second terminal is connected to the power supply voltage VDD; the nineteenth switch S 19 The second terminal is connected to the third power supply point; the twentieth switch S 21 The second terminal is grounded; the twentieth switch S 20 The second end is connected to the fourth power supply node.

[0019] Specifically, the feedback DAC module 106 includes: a digital selection circuit 1061 and a switch gating circuit 1062; The input terminal of the digital selection circuit 1061 is connected to the output terminal of the single-bit quantizer module 105, and is used to generate a switch control signal according to the digital code stream; the control terminal of the switch gating circuit 1062 is connected to the output terminal of the digital selection circuit 1061, and the output terminal of the switch gating circuit 1062 is connected to the input terminal of the first adder 107, and is used to select the reference voltage according to the switch control signal to generate a first feedback signal.

[0020] Specifically, the feedback DAC module 106 includes: a digital selection circuit 1061 and a switch gating circuit 1062; The input terminal of the digital selection circuit 1061 is connected to the output terminal of the single-bit quantizer module 105, and is used to generate a switch control signal according to the digital code stream; the control terminal of the switch gating circuit 1062 is connected to the output terminal of the digital selection circuit 1061, and the output terminal of the switch gating circuit 1062 is connected to the input terminal of the first adder 107, and is used to select the reference voltage according to the switch control signal to generate a first feedback signal.

[0021] Specifically, the cascaded integrator-comb filter 108 includes: a multi-stage cascaded integrator-comb filter; The input of the multi-stage cascaded integrator-comb filter is connected to the output of the single-bit quantizer module 105; the output of the multi-stage cascaded integrator-comb filter outputs a Nyquist rate digital signal.

[0022] For example, see Figure 1 , Figure 1 This invention provides a system architecture and signal flow diagram for a high-precision, low-delay analog-to-digital converter (ADC) based on a proportional floating inverting amplifier. The ADC employs a third-order CIFF (Cascade of Integrators Feed-Forward) topology, including an input terminal V... IN (z) First adder 107, first-stage integrator 101, second-stage integrator 102, third-stage integrator 103, single-bit quantizer module 105, feedback DAC (Digital to The Analog Converter module 106, the cascaded integrator comb filter 108, and the proportional floating inverting amplifier 104, which serves as the core of the integrator.

[0023] like Figure 1 As shown, the input signal V IN (z) After being scaled by the scaling factor c1, the signal is transmitted to the first adder 107. The first adder 107 is used to calculate the first difference between the input signal and the feedback signal from the feedback DAC module 106, scaled by the feedback factor b1. The output of the first adder 107 is connected to the input of the first-stage integrator 101, and is used to integrate the difference between the input signal obtained by the first adder 107 and the first difference from the feedback DAC module 106 to obtain the output signal of the first-stage integrator 101, i.e., the first-stage output signal. The Z-domain transfer functions of the first-stage integrator 101, the second-stage integrator 102, and the third-stage integrator 103 are all... , which represents the discrete-time integration operation based on the delay unit.

[0024] In this embodiment, the input signal V IN (z) After being scaled by the feedforward coefficient c1, it is subtracted from the feedback signal from the feedback DAC module 106 after being scaled by coefficient b1 by the first adder 107. In this embodiment, both coefficients c1 and b1 are 0.4. The result of this subtraction is input to the first-stage integrator 101 for integration to obtain the first-stage output signal Y1(z). Under the coefficient matching condition, the first-stage output signal is expressed as: ; in, The constant coefficients, To quantify the noise, the first-stage output signal does not include the input signal V. IN (z) component.

[0025] The second-stage integrator 102 is connected to the first-stage integrator 101 and is used to integrate the first-stage output signal to obtain the second-stage output signal. The transfer function of the second-stage output signal in the Z-domain is: H(z) = z - ¹ / (1-z - ¹). The first-stage output signal Y1(z) is first scaled by the second-stage inter-gain c2 (0.4 times in this embodiment) before being input to the second-stage integrator 102. The Z-domain transfer function of the second-stage output signal obtained from the second-stage integrator 102 is: ,in, The coefficients are constants, and this signal also does not contain the input signal V. IN (z) component.

[0026] The third-stage integrator 103 is connected to the second-stage integrator 102, and its Z-domain transfer function is also: H(z) = z - ¹ / (1-z - ¹). The second-stage output signal Y2(z) is first scaled by a third-stage inter-gain c3 (0.2x in this embodiment) before being input to the third-stage integrator 103. The resulting Z-domain transfer function of the third-stage output signal is: ,in, The coefficients are constants, and this signal does not contain the input signal V. IN (z) component.

[0027] This invention introduces a signal feedforward path, ensuring that the output signals Y1(z), Y2(z), and Y3(z) of the first-stage integrator 101, the second-stage integrator 102, and the third-stage integrator 103 do not contain the input signal V. IN The signal processing mechanism effectively isolates the inherent nonlinearity of the circuit from the input signal at the physical level, preventing nonlinear sources from affecting the input signal.

[0028] In the topology of this invention, the input signal V IN (z) is directly connected to the second adder before the quantizer via the feedforward coefficient a1. Simultaneously, the output signals of the first, second, and third stage integrators are weighted by coefficients a2, a3, and a4 (a1=1, a2=2, a3=1.8, a4=1.4), respectively. The summed signals from all paths are then fed into the single-bit quantizer module 105 for quantization, yielding the digital code stream D(z).

[0029] like Figure 1 As shown, the feedback DAC module 106 is connected between the output of the single-bit quantizer module 105 and the input of the first-stage integrator 101. It is used to convert the quantized single-bit digital signal into an analog feedback signal, completing the closed-loop feedback. Please refer to... Figure 2The feedback DAC module 106 in this embodiment mainly includes a digital selection circuit 1061 and a switch gating circuit 1062.

[0030] The input of the digital selection circuit 1061 is connected to the output of the single-bit quantizer module 105. Since this embodiment uses single-bit quantization, the digital code stream output by the single-bit quantizer module 105 contains only two logic states, such as logic "1" and logic "0". The digital selection circuit 1061 performs logical processing on the received single-bit digital code stream, generates complementary switch control signals, and transmits the control signals to the switch gating circuit 1062.

[0031] The switch selection circuit 1062 is connected to the input terminals of the digital selection circuit 1061 and the first adder 107. The switch selection circuit 1062 responds to a control signal, switching between preset reference voltages, and sends this as a feedback signal to the input terminal of the first adder 107 along with the input signal V. IN (z) Perform the difference operation to complete the negative feedback operation in the Sigma-Delta analog-to-digital converter loop.

[0032] In this embodiment, the cascaded integrator comb filter 108 is used to digitally filter the quantized digital signal D(z) to obtain the Nyquist rate digital signal D. OUT (z). For details, please see [link / reference]. Figure 3 , Figure 3 This is a schematic diagram of a cascaded integrator comb filter structure provided in an embodiment of the present invention, which consists of several adders, several delay modules and downsampling modules.

[0033] For a cascaded integrator comb filter 108, generally an L+1 stage filter is needed to digitally filter the digital bitstream of the L-stage modulator.

[0034] In this embodiment, L=3, therefore a 4-stage cascaded integrator-comb filter can be used to output essentially the same spectral result. Finally, the digital code stream D(z) of the modulator is digitally filtered to achieve downsampling and obtain the Nyquist rate digital signal D. OUT (z).

[0035] For performance requirements such as low power consumption, high energy efficiency, and scalable power bandwidth, Figure 1 As shown, in this embodiment, the first-stage integrator 101, the second-stage integrator 102, and the third-stage integrator 103 all use a proportional floating inverting amplifier 104 with dual-level shift as the core operation unit of the integrator.

[0036] Specifically, please see Figure 4 and Figure 6 , Figure 4This is a detailed circuit structure diagram and timing diagram of a proportional floating inverting amplifier provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of a dual-level shift module provided in an embodiment of the present invention. The proportional floating inverting amplifier 104 itself consists of a driver-stage floating inverting amplifier and a load-stage floating inverting amplifier. The key to the load-stage floating inverting amplifier is that the transistors are connected in diode form. Due to the introduction of the dual-level shift module, six energy storage capacitors and several switches are required to power the amplifier. The entire amplifier forms a fully differential structure, including the non-inverting input terminal V. IP Inverting input terminal V IN Negative output terminal V ON and the positive output terminal V OP .

[0037] In this embodiment, the driver stage transistor M P1 M N1 M P2 M N2 With load stage transistor M P3， M N3 M P4 M N4 The aspect ratio is set to m:1, and the size of the drive stage energy storage capacitor and the load stage energy storage capacitor are both set to m:1.

[0038] The ratio of transistor size between the driver stage and the load stage, along with the ratio of energy storage capacitor size between the driver stage and the load stage, work together to achieve an amplifier gain of m times.

[0039] For details, please see Figure 4 When φ1 is high, the proportional floating inverting amplifier 104 is in the pre-charge and reset phases; when φ1 is low, the proportional floating inverting amplifier 104 enters the amplification phase. To achieve the dual-level shift function, the amplification phase is further divided into three non-overlapping sub-phases, namely the first sub-phase φ1. 2-1 Second sub-phase φ 2-2 and the third sub-phase φ 2-3 .

[0040] For details, please see Figure 4 and Figure 5 Taking the first energy storage capacitor C1 and the fourth energy storage capacitor C4 as examples, each energy storage capacitor is connected to four switches for reset and amplification operations. When the φ1 clock goes high, the switches controlled by the φ1 clock are connected to the power supply VDD and the ground GND respectively. At this time, the circuit is in the reset state, and the first energy storage capacitor C... R1 and the fourth energy storage capacitor C R4 It is charged to the power supply voltage. When φ 2-1 The clock rises to a high level, CR1 and C R4 The driver-stage and load-stage floating inverting amplifiers are powered separately, achieving an m-fold amplification. To implement the dual-level shift function, four energy storage capacitors are still required, along with matching switches and timing control, each powered by φ... 2-2 clock and φ 2-3 Clock control powers both the driver-stage and load-stage floating inverting amplifiers. When φ 2-2 The clock rises to a high level, C R2 and C R5 Power supplies are provided to the driver-stage floating inverting amplifier and the load-stage floating inverting amplifier, respectively; when φ 2-3 The clock rises to a high level, C R3 and C R6 They supply power to the driver-stage floating inverting amplifier and the load-stage floating inverting amplifier, respectively. And φ 2-2 and φ 2-3 The operating state of the controlled circuit needs to be analyzed in conjunction with the dual-level shift module.

[0041] In this embodiment, a dual-level shift module is used to improve amplifier gain. Please refer to [link / reference]. Figure 6 , Figure 6 This is a schematic diagram of a dual-level shift module provided in an embodiment of the present invention. The dual-level shift module itself is composed of a switched capacitor circuit. This module is connected to the output terminal of a proportional floating inverting amplifier and is used to perform time-domain level shifting processing on the amplifier's output signal to improve the output swing and open-loop gain. Specifically, the dual-level shift module includes a first shift capacitor C. CLS1 Second shift capacitor C CLS2 And five control switches, namely switch S1, switch S2, switch S3, switch S4, and switch S5. It should be noted that, although... Figure 6 It is shown in single-ended form, but in the fully differential architecture of this embodiment, the non-inverting output V OP and negative output terminal V ON Each is connected to a set of identical dual-level shift modules.

[0042] like Figure 4 As shown, the specific timing logic is as follows: After the falling edge of φ1 arrives, the first sub-phase φ 2-1 The signal transitions to a high level. During this period, the first switch S1 and the second switch S2 in the dual-level shift module are closed. The dual-level shift module performs coarse setting along with the output of the proportional floating inverting amplifier, storing the preliminary amplification result in the first shift capacitor C. CLS1 Up. Then, φ 2-1 The transition to low level, the second sub-phase φ2-2 The signal transitions to a high level. During this period, the third switch S3 and the fourth switch S4 close, performing the first level shifting operation, and the second shift capacitor C... CLS2 The electrical signal is stored in it. Finally, φ 2-2 The transition to low level, third sub-phase φ 2-3 It then jumps to a high level. During this period, the fifth switch S5 closes, performing a second level shift operation, combined with the shift capacitor C. CLS2 The electrical signal is finely settling to obtain the output signal V after two shifts. OUTN / P When φ 2-3 After completion, φ1 jumps high again, entering the next reset cycle. Through the above strict timing control, this invention efficiently completes the entire process of coarse setup, fine setup, and level shifting within a single amplification cycle.

[0043] It should be noted that the proportional floating inverting amplifier proposed in this embodiment uses capacitor power supply, thereby simultaneously achieving high energy efficiency and scalable power consumption and bandwidth. A precise m-fold proportional gain is achieved based on the ratio of the amplifier transistor geometry and the capacitor size. The specific principle is explained as follows: This embodiment utilizes an energy storage capacitor to power the amplifier. Under this architecture, the amplifier's power consumption mainly depends on the energy required for the energy storage capacitor to charge to the power supply voltage in the reset phase (φ1 phase). Since this charging and discharging frequency is directly determined by the signal bandwidth, the power consumption of this proportional floating inverting amplifier can scale linearly with changes in the signal bandwidth, achieving scalable power consumption and bandwidth characteristics with on-demand power supply.

[0044] The circuit provided by this invention follows the principle of charge conservation. During the amplification phase, the energy storage capacitor discharges as a temporary power source, and the current flowing out of the upper plate is the same as the current flowing into the lower plate. With charge transfer, negative charge accumulates on the upper plate of the energy storage capacitor, causing its potential to decrease, while negative charge is released from the lower plate, causing its potential to increase. This dynamic drift of the node potential compresses the overdrive voltage of the transistor. Specifically, as the amplification process continues, the transistor's operating state dynamically changes: it gradually slides from the initial strong inversion region to the weak inversion region, until the circuit automatically shuts off prematurely due to insufficient supply potential difference ("self-quenching mechanism"). Ultimately, the current I flowing through the loop... AMP The efficiency approaches zero. This self-quenching mechanism avoids the problem of traditional amplifiers consuming quiescent current after stabilization, thus significantly improving energy efficiency. Furthermore, this structure reuses the currents of the NMOS and PMOS transistors, making the amplifier's equivalent transconductance G... m ≈2G mp =2G mnThis provides twice the transconductance efficiency under the same current budget. Therefore, the circuit has high energy efficiency.

[0045] This embodiment utilizes the matching ratio between device size and capacitor value to precisely set the closed-loop gain. Specifically, the size ratio of the driver-stage transistor to the load-stage transistor is set to m:1, and the size ratio between the driver-stage and load-stage energy storage capacitors is also set to m:1. The load stage consists of diode-connected transistors with an equivalent impedance of 1 / G. m At this time, G m The load stage transconductance is given by the analogy to ... m Therefore, its gain expression can be expressed as: .

[0046] Therefore, this gain value depends only on the geometric scaling factor m of the design. Since the relative proportions of devices in integrated circuit manufacturing processes are highly accurate, this gain characteristic exhibits good robustness to changes in process angle, power supply voltage, and temperature, i.e., PVT variations.

[0047] It is important to explain how this dual-level shift module works in conjunction with a proportional floating inverting amplifier to achieve high gain. While the proportional floating inverting amplifier boasts high efficiency and an m-fold proportional gain, its open-loop DC gain is limited by transistor size. This embodiment introduces a dual-level shift module, utilizing level-shifting technology to decompose the amplification process without adding additional active components or static power consumption. At φ 2-1 and φ 2-2 In this stage, the first shift capacitor C is used. CLS1 The finite gain error of the amplifier is sampled and shifted; at φ 2-3 In this stage, previously stored information is used to assist in establishing the output. This mechanism effectively improves the open-loop gain of the proportional floating inverting amplifier, enabling it to achieve output accuracy closer to the ideal value, thereby significantly reducing the linearity error of the integrator while maintaining low power consumption characteristics.

[0048] In summary, the high-precision, low-delay analog-to-digital converter (ADC) based on a proportional floating inverting amplifier proposed in this embodiment effectively improves the system's linearity by adopting a cascaded integrator feedforward (CIFF) architecture and introducing an input signal feedforward path. In terms of circuit implementation, the integrator, as the core operational unit, employs a proportional floating inverting amplifier with dual-level shifting. This amplifier utilizes capacitor power supply and achieves extremely high energy efficiency through a self-quenching mechanism and current multiplexing technology, establishing a dynamic characteristic where power consumption scales linearly with signal bandwidth. Simultaneously, by precisely setting the ratio (m:1) of the driver stage and load stage transistors and energy storage capacitors, a proportional gain with high robustness to process, voltage, and temperature variations is achieved. Furthermore, the system introduces a dual-level shift module controlled by multi-phase timing, using level shifting technology to decompose the amplification process in the time domain, significantly improving the amplifier's equivalent open-loop gain without adding additional active components or static power consumption. The above technical solution endows the system with full dynamic operation characteristics, and achieves a unity of high energy efficiency, low latency, low distortion and high precision, which fully meets the application requirements of modern low power consumption and high performance sensor interface circuits.

[0049] The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0050] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier, characterized in that, include: The first adder (107) is used to receive the input signal V. IN (z) and the first feedback signal, and according to the input signal V IN (z) and the first feedback signal are used to calculate the first difference signal; wherein, the first feedback signal is the output signal of the feedback DAC module (106); the input signal V IN (z) includes: positive phase input signal V IP and inverted input signal V IN ; The first-stage integrator (101) is used to integrate the first difference signal to obtain the first-stage output signal; The second-stage integrator (102) is used to integrate the first-stage output signal after it has been scaled by the first-stage interstage gain coefficient to obtain the second-stage output signal. The third-stage integrator (103) is used to integrate the second-stage output signal after it has been scaled by the interstage gain coefficient to obtain the third-stage output signal. A summing circuit is used to scale the input signal V by the input feedforward coefficients. IN (z) and sum the first-stage output signal, the second-stage output signal and the third-stage output signal scaled by different feedforward coefficients respectively to obtain the summation result; A single-bit quantizer module (105) is used to quantize the summation result to generate a digital code stream; Feedback DAC module (106) is used to convert the digital code stream into an analog signal and provide it to the first adder (107) as the first feedback signal; A cascaded integrator comb filter (108) is used to filter the digital code stream and output a Nyquist rate digital signal.

2. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 1, characterized in that, The first-stage integrator (101), the second-stage integrator (102), and the third-stage integrator (103) each include: a dual-level shift module and a proportional floating inverting amplifier (104); The dual-level shift module is used to perform level shifting processing on the output signal of the proportional floating inverting amplifier (104) through multi-sub-phase timing control; The proportional floating inverting amplifier (104) is used as the core operation unit of the integrator and provides signal amplification function through the energy storage capacitor power supply mechanism.

3. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 2, characterized in that, The dual-level shift module includes: a first shift circuit for the positive output terminal and a second shift circuit for the negative output terminal; The first shift circuit includes: a first switch S1 and a first shift capacitor C. CLS1 Second shift capacitor C CLS2 The second switch S2, the third switch S3, the fourth switch S4, and the fifth switch S5; The first terminal of the first switch S1 is connected to the non-inverting output terminal V of the proportional floating inverting amplifier (104). OP The second terminal of the first switch S1 is connected to the first shift capacitor C. CLS1 The upper plate and the second shift capacitor C CLS2 The upper plates are all connected; The first shift capacitor C CLS1 The lower electrode plate is connected to the second terminal of the third switch S3 and the second terminal of the second switch S2. The first terminal of the third switch S3 is connected to the non-inverting output terminal V of the proportional floating inverting amplifier (104). OP connect; The first terminal of the second switch S2 and the first terminal of the fourth switch S4 are both connected to the common-mode reference voltage V. CM connect; The second terminal of the fourth switch S4 is connected to the second shift capacitor C CLS2 The lower-level board and the second terminal of the fifth switch S5 are both connected; The first terminal of the fifth switch S5 is connected to the positive output terminal of the first-stage integrator (101).

4. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 2, characterized in that, The proportional floating inverting amplifier (104) in the first-stage integrator (101) includes: a driver-stage floating inverting amplifier and a load-stage floating inverting amplifier; The driver-stage floating inverting amplifier is used to convert the first difference signal into a first current signal; The load-stage floating inverting amplifier is used to provide an impedance load to the driver-stage floating inverting amplifier for the first current signal, and to set the voltage gain of the proportional floating inverting amplifier (104) by the transistor size ratio between the driver-stage floating inverting amplifier and the load-stage floating inverting amplifier, so as to obtain the first stage output signal.

5. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 4, characterized in that, The driver-stage floating inverting amplifier includes: a first PMOS transistor M P1 The first NMOS transistor M N1 The second PMOS transistor M P2 The second NMOS transistor M N2 and drive energy storage sub-circuit; The first PMOS transistor M P1 The gate of the first NMOS transistor M N1 The gate and the positive input signal V IP Connection; the first PMOS transistor M P1 The source of the second PMOS transistor M P2 The sources of all are connected to the first power supply point of the driving energy storage sub-circuit; the first PMOS transistor M P1 The drain of the first NMOS transistor M N1 The drain of the third PMOS transistor M in the load stage floating inverting amplifier P3 The gate of the third PMOS transistor M in the load stage floating inverting amplifier P3 The drain of the third NMOS transistor M in the load stage floating inverting amplifier N3 The drain of the third NMOS transistor M in the load stage floating inverting amplifier N3 The gates of all are connected to the inverting output terminal V. ON ; The first NMOS transistor M N1 The source of the second NMOS transistor M N2 The source is connected to the second power supply node of the drive energy storage sub-circuit; The second PMOS transistor M P2 The gate of the second NMOS transistor M N2 The gate and inverted input signal V IN Connection; the second PMOS transistor M P2 The drain of the second NMOS transistor M N2 The drain of the fourth PMOS transistor M in the load stage floating inverting amplifier P4 The gate of the fourth PMOS transistor M in the load stage floating inverting amplifier P4 The drain of the fourth NMOS transistor M in the load stage floating inverting amplifier N4 The gate of the fourth NMOS transistor M in the load stage floating inverting amplifier N4 The drains of all terminals are connected to the non-inverting output terminal V. OP .

6. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 5, characterized in that, The driving energy storage sub-circuit includes: three driving energy storage units connected in parallel; each driving energy storage unit includes: a first energy storage capacitor C. R1 Switches S6, S7, S8, and S9; The first energy storage capacitor C R1 The upper plate is connected to both the first terminal of the sixth switch S6 and the first terminal of the seventh switch S7; the first energy storage capacitor C R1 The lower electrode plate is connected to the first end of the ninth switch S9 and the first end of the eighth switch S8; The second terminal of the sixth switch S6 is connected to the power supply voltage VDD; The second end of the seventh switch S7 is connected to the first power supply point; The second terminal of the ninth switch S9 is grounded; The second end of the eighth switch S8 is connected to the second power supply node.

7. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 4, characterized in that, The load-stage floating inverting amplifier includes: a third PMOS transistor M P3 The third NMOS transistor M N3 The fourth PMOS transistor M P4 The fourth NMOS transistor M N4 and load energy storage sub-circuit; The third PMOS transistor M P3 The gate of the first PMOS transistor M of the driver stage floating inverting amplifier P1 The drain of the first NMOS transistor M of the driver stage floating inverting amplifier N1 The drain of the third PMOS transistor M P3 The drain of the third NMOS transistor M N3 The drain of the third NMOS transistor M N3 The gate is connected to the inverting output terminal V. ON The third PMOS transistor M P3 The source of the fourth PMOS transistor M P4 The source is connected to the third power supply node of the load energy storage sub-circuit; The third NMOS transistor M N3 The source of the fourth NMOS transistor M N4 The source of the third NMOS transistor is connected to the fourth power supply node of the load energy storage sub-circuit; N3 The gate of the third PMOS transistor M P3 Gate connection; The fourth PMOS transistor M P4 The drain of the fourth PMOS transistor M P4 The gate of the fourth NMOS transistor M N4 The drain of the fourth NMOS transistor M N4 The gate of the second PMOS transistor M of the driver stage floating inverting amplifier P2 The drain of the second NMOS transistor M of the driver stage floating inverting amplifier N2 The drain is connected to the non-inverting output terminal V. OP .

8. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 7, characterized in that, The load energy storage sub-circuit includes: three load energy storage units connected in parallel; each load energy storage unit includes: a fourth energy storage capacitor C. R4 18th switch S 18 Nineteenth switch S 19 20th switch S 20 Twentieth switch S 21 ; The fourth energy storage capacitor C R4 The upper electrode plate and the eighteenth switch S 18 The first end and the nineteenth switch S 19 The first end of each capacitor is connected; the fourth energy storage capacitor C R4 The lower electrode plate and the twentieth switch S 20 The first end and the twentieth switch S 21 The first end of each is connected; The eighteenth switch S 18 The second terminal is connected to the power supply voltage VDD; The nineteenth switch S 19 The second end is connected to the third power supply point; The twentieth switch S 21 The second terminal is grounded; The twentieth switch S 20 The second end is connected to the fourth power supply node; Fourth energy storage capacitor C R4 Fifth energy storage capacitor C R5 The sixth energy storage capacitor C R6 13th switch S 13 Fourteenth switch S 14 Fifteenth switch S 15 Sixteenth switch S 16 Seventeenth switch S 17 18th switch S 18 Nineteenth switch S 19 Twentieth switch S 20 .

9. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 1, characterized in that, The feedback DAC module (106) includes: a digital selection circuit (1061) and a switch gating circuit (1062); The input terminal of the digital selection circuit (1061) is connected to the output terminal of the single-bit quantizer module (105) and is used to generate a switch control signal according to the digital code stream; The control terminal of the switch selection circuit (1062) is connected to the output terminal of the digital selection circuit (1061), and the output terminal of the switch selection circuit (1062) is connected to the input terminal of the first adder (107), which is used to select the reference voltage according to the switch control signal and generate the first feedback signal.

10. The high-precision, low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 1, characterized in that, The cascaded integrator comb filter (108) includes: a multi-stage cascaded integrator comb filter; The input of the multi-stage cascaded integrator comb filter is connected to the output of the single-bit quantizer module (105); The Nyquist rate digital signal is output from the output terminal of the multi-stage cascaded integrator comb filter.

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