Transistor device with selective thick gate dielectric and method

Abstract

The invention relates to a transistor device with selective thick gate dielectric and a method. Apparatuses and methods including transistors, semiconductor devices, and systems are disclosed. Example semiconductor devices and methods include gate dielectrics having different thicknesses in transistor devices. Apparatuses and methods are disclosed that use dopants to alter growth of a gate dielectric at a desired location within a semiconductor device.

Description

Technical Field

[0001] This application relates to semiconductor devices and methods of forming the same, and more specifically, to transistor devices having selective thick gate dielectrics. Background Technology

[0002] Memory devices are semiconductor circuits that provide electronic storage for data to a host system (such as a computer or other electronic device). Memory devices can be volatile or non-volatile. Volatile memory requires power to maintain data and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain stored data when not powered and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory (e.g., phase-change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM)).

[0003] A host system typically includes a host processor, a first amount of main memory (e.g., typically volatile memory, such as DRAM) to support the host processor, and one or more storage systems (e.g., typically non-volatile memory, such as flash memory) that provide additional storage to hold data, in addition to or independently of the main memory.

[0004] For example, a solid-state drive (SSD) storage system may include a memory controller and one or more memory devices, comprising several dies or logic units (LUNs). In a particular instance, each die may contain several memory arrays and peripheral circuitry, such as die logic or die processors. The memory controller may include interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) via a communication interface (e.g., a bidirectional parallel or serial communication interface).

[0005] This description generally relates to the structure and fabrication of transistors in complementary metal-oxide-semiconductor (CMOS) devices. Summary of the Invention

[0006] One aspect of this application relates to a semiconductor memory device comprising: a transmission line having a width and a thickness between a top surface and a bottom surface; a body region extending through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source / drain region and a second source / drain region separated by a channel region; and a gate dielectric surrounding the body region and laterally separating the body region from the transmission line, wherein the thickness of the gate dielectric varies, with a thicker region adjacent to the top surface and the bottom surface.

[0007] Another aspect of this application relates to a semiconductor memory device comprising: a transmission line having a width and a thickness between a top surface and a bottom surface; a body region extending through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source / drain region and a second source / drain region separated by a channel region; a gate oxide surrounding the body region and laterally separating the body region from the transmission line, wherein the thickness of the gate oxide varies, with a thicker region adjacent to the top surface and the bottom surface; and an oxide promoting dopant within the gate oxide.

[0008] Another aspect of this application relates to a method of forming a semiconductor device, comprising: forming a transistor body region on a semiconductor substrate; forming a transmission line around the transistor body region; promoting doping with a dopant using a dielectric in a region adjacent to an opposite end of the transistor body region, wherein the concentration of the dopant is higher adjacent to the opposite end than in the middle of the transistor body region; forming a gate dielectric surrounding the transistor body region, wherein: a central portion of the gate dielectric includes a first thickness; and an end portion of the gate dielectric includes a second thickness greater than the first thickness. Attached Figure Description

[0009] In diagrams that are not necessarily drawn to scale, the same numbering can describe similar components in different views. The same numbering with different letter suffixes can represent different examples of similar components. The diagrams generally illustrate the various embodiments discussed in this document by way of example rather than limitation.

[0010] Figure 1 This describes a memory device according to some example embodiments.

[0011] Figure 2A A top view illustrating a portion of a memory device according to some example embodiments.

[0012] Figure 2B The description is based on some example embodiments from Figure 2A An isometric view of a portion of the image.

[0013] Figure 3 This illustrates a cross-sectional view of a portion of a memory device according to some example embodiments.

[0014] Figure 4A Another cross-sectional view illustrating a portion of a memory device according to some example embodiments.

[0015] Figure 4B Another cross-sectional view illustrating a portion of a memory device according to some example embodiments.

[0016] Figure 5 This illustrates a plot of gate dielectric thickness versus dopant dosage based on some example embodiments.

[0017] Figure 6 This describes the instance method flowchart based on other example embodiments.

[0018] Figure 7 This section illustrates an example block diagram of an information processing system based on some exemplary embodiments. Detailed Implementation

[0019] The following description and figures fully illustrate specific embodiments to enable those skilled in the art to practice the embodiments. Other embodiments may incorporate structural variations, logical variations, electrical variations, process variations, and other variations. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The embodiments set forth in the claims cover all available equivalents of those claims.

[0020] Figure 1 A block diagram illustrating a device in the form of a memory device 100 according to an embodiment of the present invention is shown. The memory device 100 may include transistors having gate oxide configurations of varying thicknesses, as described in more detail below. The memory device 100 may include a memory array 102 having memory cells 103 arranged in rows and columns together with lines (e.g., access lines) 104 and lines (e.g., data lines) 105. The memory device 100 may access the memory cells 103 using the lines 104 and exchange information with the memory cells 103 using the lines 105.

[0021] Memory cell 103 and other circuits 114, 116, etc., may include transistors and utilize the methods described in more detail in Figures 2 to 7. In one example, memory array 102 includes a NAND memory array, and peripheral circuitry (e.g., circuits 114, 116, 108, 109, etc.) may include transistors described in more detail in Figures 2 to 7. One example of peripheral circuitry utilizing the described transistors includes a string driver circuit, but the invention is not limited thereto.

[0022] Row access circuitry 108 and column access circuitry 109 can access memory cell 103 in response to address register 112 based on row and column address signals on lines 110, 111, or both. Data input / output circuitry 114 can be configured to exchange information between memory cell 103 and line 110. Lines 110 and 111 may include nodes within memory device 100 or pins (or solder balls) on a package in which memory device 100 may reside.

[0023] Control circuit 116 can control the operation of memory device 100 based on signals present on lines 110 and 111. External devices (e.g., processors or memory controllers) can send different commands (e.g., read, write, or erase commands) to memory device 100 using different combinations of signals on lines 110, 111, or both.

[0024] The memory device 100 can perform memory operations on the memory cells 103 in response to commands, such as performing a read operation to read information from the memory cells 103 or performing a write operation (e.g., programming) to store information in the memory cells 103. The memory device 100 can also perform an erase operation to clear information from some or all of the memory cells 103.

[0025] The memory device 100 may receive a supply voltage, including a supply voltage Vcc and a supply voltage Vss. The supply voltage Vss may operate at a ground potential (e.g., having a value of approximately 0 volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source, such as a battery or an AC-DC converter circuit system.

[0026] Each of the memory cells 103 can be programmed to store information representing the value of a portion of a bit, the value of a single bit, or the value of multiple bits (e.g., two, three, four, or another number of bits). For example, each of the memory cells 103 can be programmed to store information representing the binary value "0" or "1" of a single bit. A single bit per cell is sometimes referred to as a single-level cell. In another instance, each of the memory cells 103 can be programmed to store information representing the value of multiple bits (e.g., one of the four possible values ​​"00", "01", "10", "11" for two bits, one of the eight possible values ​​"000", "001", "010", "011", "100", "101", "110", and "111" for three bits, or one of another number of other values ​​for multiple bits). Cells capable of storing multiple bits are sometimes referred to as multi-level cells (or multi-state cells).

[0027] Memory device 100 may include a non-volatile memory device, and memory cell 103 may include a non-volatile memory cell, such that memory cell 103 can retain information stored thereon when power (e.g., Vcc, Vss, or both) is disconnected from memory device 100. For example, memory device 100 may be a flash memory device, such as a NAND flash or NOR flash memory device, or another type of memory device, such as a variable resistance memory device (e.g., a phase-change or resistive RAM device).

[0028] The memory device 100 may include a memory device in which memory cells 103 may be physically located in multiple layers on the same device, such that some of the memory cells 103 may be stacked on top of some other memory cells 103 in multiple layers above a substrate (e.g., a semiconductor substrate) of the memory device 100.

[0029] Those skilled in the art will recognize that the memory device 100 may include other elements, some of which are... Figure 1 Examples of embodiments described herein are not shown in order not to obscure them.

[0030] Figure 2A and 2B A memory device 200 is shown according to a selected example. In the shown example, the memory device 200 includes one or more 4F... 2 Memory cell 211.4F 2 This refers to a memory cell whose available area on each side is 2F (e.g., each side of a square represents memory cell 211). The cell area is 2F x 2F, which equals 4F. 2 The term "F" refers to the minimum lithographic feature size and is determined by the wavelength of the beam used to form a given feature. In one example, memory cell 211 includes a thin-film transistor. A plurality of transmission lines 202 and a plurality of data lines 204 are shown. A body region 210 is contained between the plurality of transmission lines 202 and the plurality of data lines 204. In one example, the plurality of transmission lines 202 include word lines. In one example, the plurality of data lines 204 include bit lines.

[0031] The body region 210 is shown extending through the thickness 201 of the transmission line 202 within the width 203 of the transmission line 202. A channel region 216 and a gate dielectric 230 surrounding the body region 210 and laterally separating it from the transmission line 202 are shown. A first source / drain region 212 and a second source / drain region 214 are shown, with the channel region 216 positioned between the source / drain regions 212 and 214. In one example, the source / drain regions 212 and 214 are N-type doped, and the channel region is P-type doped. In another example, the source / drain regions 212 and 214 are P-type doped, and the channel region is N-type doped. A capacitor 220 is shown at the top of the body region. In one example, the capacitor 220 includes a storage capacitor for storing memory data.

[0032] In example Figure 2A and 2B In this configuration, technical challenges may arise, such as a degradation in electrical performance at the top or bottom of transmission line 202 near the corner of the main body region 210. Figure 3 This demonstrates examples of configurations for solving this problem and others.

[0033] Figure 3 Showing from Figure 2A and 2B A cross-sectional view of portion 300 of the memory device 200. A segment of the body region 210 and transmission line 202 is shown. The gate dielectric 230, which laterally separates the body region 210 and the transmission line 202, is shown. A first source / drain region 212 and a second source / drain region 214 are shown, wherein a channel region 216 is coupled between the first source / drain region 212 and the second source / drain region 214. Data lines 204 and capacitors 220 are shown in electrical schematic format.

[0034] exist Figure 3 In this example, the first source / drain region 212 and the second source / drain region 214 are at least partially located within the thickness of the transmission line 202. In other words, the first source / drain region 212 penetrates the bottom edge of the transmission line 202 to a distance of 213. Similarly, the second source / drain region 214 penetrates the top edge of the transmission line 202 to a distance of 215.

[0035] In the illustrated example, transmission line 202 serves as a word line, and the applied charge serves as a gate that selectively activates channel region 216 and provides transistor functionality. As mentioned above, at corner 237, it is necessary to prevent electrical performance degradation. Examples of conditions that cause electrical performance degradation include gate-induced drain leakage.

[0036] In one example, the oxide 230 on the source / drain overlap regions 212, 214 is responsible for increasing the gate electric field in the source / drain overlap regions 212, 214. In one example where the transmission line 202 (gate) is off (Vg <= 0) and the source / drain regions 212, 214 are under a higher potential (Vdd) bias condition, a large amount of gate-induced drain leakage (GIDL) is generated. For an n-type thin-film transistor (TFT), electrons generated by the GIDL process sweep into the source / drain regions 212, 214, while holes move in the channel region 216 (body) of the TFT (the charge carriers are reversed in a p-type TFT).

[0037] In this example, because this device has no host contacts (channel region 216 is electrically floating), these holes accumulate in channel region 216, thereby reducing the TFT threshold voltage and increasing leakage from the cell to the bit line, or vice versa. This phenomenon is called the floating host effect (FBE). The result is cell charge loss and a shortened refresh time (degraded DRAM performance).

[0038] To address this issue, the thickness of the gate dielectric 230 varies, with a thicker region adjacent to the top and bottom surfaces of the transmission line 202. For example... Figure 3 As shown, the gate dielectric 230 includes a first thicker region 232 adjacent to the bottom surface of the transmission line 202 and a second thicker region 234 adjacent to the top surface of the transmission line 202.

[0039] The thicker regions 232 and 234 provide increased protection for the memory device 200 by reducing degraded electrical performance at the corner 237. Concurrently, a thinner intermediate region 236, adjacent to the channel region 216, provides improved transistor switching characteristics across all regions of the gate dielectric 230 compared to the thicker gate dielectric 230.

[0040] Compared to the intermediate region 236, the formation of the thicker regions 232 and 234 is achieved using dopants that promote the growth of the gate dielectric. In one example, the gate dielectric 230 comprises a gate oxide. In another example, the gate dielectric 230 comprises silicon oxide. In yet another example, the gate dielectric comprises other oxides, such as transition metal oxides. Examples include tantalum oxide, hafnium oxide, lanthanum oxide, etc.

[0041] In one example, the dopant promoting gate dielectric growth includes fluorine. In one example, the dopant promoting gate dielectric growth includes argon. In one example, the dopant promoting gate dielectric growth includes deuterium. In one example, multiple dopants are used to promote gate dielectric growth. In one example, a dopant is included that hinders the growth of the gate dielectric in regions where a thinner gate dielectric is desired, rather than a dopant that promotes gate dielectric growth. This produces a similar effect to gate dielectrics of varying thicknesses.

[0042] Several methods for incorporating dopants are feasible, each with its own advantages. In one example, the dopant promoting gate dielectric growth is implanted into the substrate material via ion implantation. In another example, the substrate material is formed with dopants incorporated into a bulk substrate material. In yet another example, the dopant promoting gate dielectric growth is chemically or physically deposited onto a carrier material on the surface of the substrate material, and then annealed or otherwise driven onto the substrate material surface for oxidation. An example of a carrier material comprises polycrystalline silicon.

[0043] Figure 4A An example is shown of a gate dielectric 430 contained in a memory device 400, formed by oxidation within an opening in a via 420 or a substrate material (e.g., a word line 410 described in the above example). Figure 4A In this example, the word line 410 is formed in multiple layers. The first layer 412 contains dopants that promote gate dielectric growth. The second layer 414 contains less or no dopants that promote gate dielectric growth, and the third layer 416 again contains dopants that promote gate dielectric growth. In one example, the second layer 414 does not contain dopants that promote gate dielectric growth, but the invention is not limited thereto. The different concentrations of dopants that promote gate dielectric growth are all the dopants required to form the described gate dielectric thickness variations.

[0044] exist Figure 4A In the process, after oxidation within the aperture 420, the first portion 432 of the grown oxide is thicker than the second portion 434 of the grown oxide. Similarly, the third portion 436 of the grown oxide is thicker than the second portion 434 of the grown oxide. As described, the thickness difference between portions 432, 434, and 436 is attributed to the different dopant concentrations in the oxidized layers 412, 414, and 416.

[0045] After the gate dielectric 430 is grown, a detectable amount of dopant will be present in or adjacent to portions of the gate dielectric 430. For example, in 4A, if fluorine is used as a dopant to promote oxide growth, then the thicker top and bottom first portions 432 and third portions 436 will contain a detectable amount of fluorine.

[0046] In such Figure 4A Following the growth of the gate dielectric 430 shown, further processing is performed to form a host region within the via 420, similar to host region 210 described above. The formed host region will include the source / drain region and channel region described herein.

[0047] Figure 4B Another example of the formation method and the resulting structure is shown. The body region 450 is shown. The bottom portion 452 and the top portion 456 are doped by a suitable method (e.g., ion implantation) or by diffusion of dopant from a sacrificial material that is subsequently removed. One example of the sacrificial material comprises doped polysilicon. In one example, the bottom portion 452 and the top portion 456 of the body region comprise source / drain regions, while the middle portion 454 comprises a channel. The middle portion 454 is doped with less or no dopant to promote oxide growth.

[0048] Next, a gate dielectric 460 is grown on the body region 450. Due to the different dopant concentrations in the body region, the gate dielectric 460 is grown thicker in the first portion 462 and the third portion 466 than in the middle second portion 464. Figure 4B After the growth of the gate dielectric 460 shown in the figure, further processing is performed to form word lines around the body region 450, similar to word lines 202 described above.

[0049] Figure 5 A graph shows the non-limiting choice of possible dopants and the change in oxide thickness in response to larger dopant implantation doses and implantation energies. Argon and fluorine are shown in the graph. As can be seen, larger doses of fluorine result in greater oxide growth thickness.

[0050] Figure 6 A flowchart illustrating an example manufacturing method is provided. In operation 602, a transistor body region is formed on a semiconductor substrate. In operation 604, a transmission line is formed around the transistor body region. In operation 606, a dielectric-promoting dopant is introduced into a region adjacent to the opposite end of the transistor body region. The dopant concentration is higher near the opposite end compared to the center of the transistor body region. In operation 608, a gate dielectric is formed surrounding the transistor body region. The central portion of the gate dielectric has a first thickness, and the ends of the gate dielectric have a second thickness greater than the first thickness.

[0051] Figure 7The description may include a block diagram of an example machine (e.g., a host system) 700 having one or more transistors, memory devices, and / or memory systems with gate dielectrics as described above. As discussed above, machine 700 may benefit from enhanced memory performance through the use of one or more of the described transistor structures and / or memory systems, thereby promoting performance improvements in machine 700 (because for many such machines or systems, efficient read and write operations to memory can promote performance improvements in the processor or other components in that machine, as further described below).

[0052] In alternative embodiments, machine 700 may operate as a standalone device or be connected (e.g., networked) to other machines. In a networked deployment, machine 700 may operate as a server machine or a client machine, or both, in a server-client network environment. In an example, machine 700 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 700 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, IoT device, automotive system, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by said machine. Furthermore, while only a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any or more of the methods discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations).

[0053] As described herein, an instance may comprise, or be operable through, logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a set of circuits) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system can be flexible over time and with the variability of the underlying hardware. A circuit system contains members that can perform specific tasks individually or in combination during operation. In an instance, the hardware of a circuit system may be designed immutably to perform a specific operation (e.g., hardwiring). In an instance, the hardware of a circuit system may contain variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) and computer-readable media that are physically modified (e.g., immutable particle magnetism, electrically movable placement, etc.) to encode the specific operation. When connecting physical components, the underlying electrical properties of the hardware composition (e.g.,) change from an insulator to a conductor or vice versa. Instructions enable participating hardware (e.g., execution units or loading mechanisms) to form portions of the circuit system, presented as hardware, via variable connections to perform specific tasks during operation. Therefore, when the device is operating, it can be communicatively coupled to other components of the circuit system via computer-readable media. In an example, any of the physical components can be used in more than one member of more than one circuit system. For instance, in operation, an execution unit may be used at one point in time in a first circuit of a first circuit system and reused at different times by a second circuit of the first circuit system or by a third circuit of the second circuit system.

[0054] Machine (e.g., computer system, host system, etc.) 700 may include processing device 702 (e.g., hardware processor, central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 704 (e.g., read-only memory (ROM), dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 706 (e.g., static random access memory (SRAM), etc.), and storage system 718, some or all of which may communicate with each other via a communication interface (e.g., bus) 730. In one example, main memory 704 includes one or more memory devices as described in the examples above.

[0055] Processing device 702 may represent one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or several processors implementing combinations of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 702 may be configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0056] The storage system 718 may include a machine-readable storage medium (also referred to as a computer-readable medium) on which one or more sets of instructions 726 or software embodying any or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially in main memory 704 or processing device 702 during execution by computer system 700, which also constitute machine-readable storage media.

[0057] The term "machine-readable storage medium" should be understood as any medium that contains a single or multiple media storing one or more sets of instructions, or any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methods disclosed herein. The term "machine-readable storage medium" should be understood accordingly to include (but is not limited to) solid-state memory, optical media, and magnetic media. In examples, massed machine-readable media includes machine-readable media having a plurality of particles with invariant (e.g., rest) mass. Therefore, massed machine-readable media is not a transient propagation signal. Specific examples of massed machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0058] Machine 700 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, and UI navigation device may be a touchscreen display. The machine may also include a signal generating device (e.g., a speaker) or one or more sensors (e.g., a Global Positioning System (GPS) sensor, a compass, an accelerometer, or one or more other sensors). Machine 700 may include an output controller, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0059] Instructions 726 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage system 718 and are accessible by main memory 704 for use by processing device 702. Main memory 704 (e.g., DRAM) is typically fast but volatile and is therefore a different type of storage than storage system 718 (e.g., SSD), which is suitable for long-term storage (including under “off” conditions). Instructions 726 or data used by user or machine 700 are typically loaded into main memory 704 for use by processing device 702. When main memory 704 is full, virtual space from storage system 718 can be allocated to supplement main memory 704; however, because storage system 718 devices are typically slower than main memory 704, and write speeds are typically at least twice as slow as read speeds, using virtual memory can significantly degrade the user experience (compared to main memory 704, e.g., DRAM) due to storage system latency. Furthermore, using storage system 718 for virtual memory may significantly shorten the usable lifespan of storage system 718.

[0060] Instruction 726 can further transmit or receive data via network 720 using a transmission medium through network interface device 708 that utilizes any of several transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), simple old-fashioned telephone (POTS) networks, and wireless data networks (e.g., the IEEE 802.15 series of standards known as Wi-Fi). ® ), IEEE 802.16 series standards (known as WiMax) ®(e.g., IEEE 802.15.4 series standards, peer-to-peer (P2P) networks, etc.). In an example, network interface device 708 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to network 720. In an example, network interface device 708 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or transmitting instructions executed by machine 700, and containing digital or analog communication signals or other intangible media that facilitate communication of this software.

[0061] The detailed description above includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Furthermore, the inventors contemplate examples (or examples) of any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0062] All publications, patents, and patent files referenced in this document are incorporated herein by full citation, as if individually incorporated by reference. In the event of any inconsistency between the usage in this document and the documents incorporated by reference, the usage in the incorporated reference shall be considered supplementary to the usage in this document; in the case of irreconcilable inconsistencies, the usage in this document shall prevail.

[0063] In this document, the term "a / an," as is common in patent documents, is used to include one or more, independent of any other examples or usages of "at least one" or "one or more." In this document, the term "or" is used to mean non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "comprising" and "in which" are used as their common English equivalents to the corresponding terms "including" and "wherein." Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after the term in the claims is still considered to fall within the scope of the claims. Additionally, in the appended claims, the terms "first," "second," and "third," etc., are used merely as designations and are not intended to impose numerical requirements on their objects.

[0064] In various instances, the components, controllers, processors, units, engines, or tables described herein may include, in particular, physical circuitry systems or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as (but not limited to) a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuitry (including processor groups or multi-core devices).

[0065] The term “horizontal” as used in this document is defined as a plane parallel to a conventional plane or surface of the substrate (e.g., a plane lying beneath a wafer or die), regardless of the actual orientation of the substrate at any point in time. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions (e.g., “on,” “above,” and “below”) are defined relative to a conventional plane or surface on top of or over an exposed surface of the substrate, regardless of the orientation of the substrate; while “on” is intended to indicate direct contact between one structure and another structure located “above” it (unless explicitly indicated otherwise); the terms “above” and “below” are intended to identify the relative placement of structures (or layers, features, etc.) that explicitly include (but are not limited to) direct contact between the identified structures, unless explicitly identified as such. Similarly, the terms “above” and “below” are not limited to horizontal orientation, because if a structure is the outermost part of the construction under discussion at a certain point in time, then the structure may be “above” the reference structure, even if the structure extends vertically relative to the reference structure rather than in a horizontal orientation.

[0066] The term "wafer" is generally used herein to refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit manufacturing. The term "substrate" is used to refer to a wafer or other structures that support or connect to other components, such as a memory die or a portion thereof. Therefore, the term "substrate" includes, for example, circuitry or "PC" boards, interposers, and other organic or inorganic support structures (which in some cases may also contain active or passive components). Therefore, the following detailed description should not be considered limiting, and the scope of the various embodiments is defined only by the full scope of the appended claims and their equivalents.

[0067] It should be understood that when an element is referred to as "on another element," "connected to another element," or "coupled to another element," it may be directly on, directly connected to, or directly coupled to the other element, or there may be an intermediary element present. In contrast, when an element is referred to as "directly on another element," "directly connected to another element," or "directly coupled to another element," there is no intermediary element or layer. Unless otherwise indicated, if two elements are shown in the diagram as being connected by a line, then the two elements may be coupled or directly coupled.

[0068] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure electronic devices to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. This code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media (e.g., during execution or at other times). Examples of such tangible computer-readable media may include (but are not limited to): hard disks, removable disks, removable optical disks (e.g., optical discs and digital video disks), magnetic tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0069] To better illustrate the methods and apparatus disclosed herein, a non-limiting list of embodiments is provided:

[0070] Example 1. A semiconductor memory device comprising: a transmission line having a width and a thickness between a top surface and a bottom surface; a body region extending through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source / drain region and a second source / drain region separated by a channel region; and a gate dielectric surrounding the body region and laterally separating the body region from the transmission line, wherein the thickness of the gate dielectric varies, with a thicker region adjacent to the top surface and the bottom surface.

[0071] Example 2. The semiconductor memory device according to Example 1, wherein the first source / drain region and the second source / drain region are N-type doped, and the channel region is P-type doped.

[0072] Example 3. The semiconductor memory device according to Example 1, wherein the first source / drain region and the second source / drain region are P-type doped, and the channel region is N-type doped.

[0073] Example 4. The semiconductor memory device according to Example 1, wherein the gate dielectric comprises an oxide material.

[0074] Example 5. A semiconductor memory device according to Example 1, wherein the memory cell of the semiconductor memory device comprises 4F 2 Shape factor memory unit.

[0075] Example 6. The semiconductor memory device according to Example 1, further comprising a storage capacitor coupled to the second source / drain region.

[0076] Example 7. The semiconductor memory device according to Example 1, wherein the first source / drain region and the second source / drain region are at least partially located within the thickness of the transmission line.

[0077] Example 8. A semiconductor memory device according to Example 1, wherein the transmission line includes a word line.

[0078] Example 9. A semiconductor memory device comprising: a transmission line having a width and a thickness between a top surface and a bottom surface; a body region extending through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source / drain region and a second source / drain region separated by a channel region; a gate oxide surrounding the body region and laterally separating the body region from the transmission line, wherein the thickness of the gate oxide varies, with a thicker region adjacent to the top surface and the bottom surface; and an oxide promoting dopant within the gate oxide.

[0079] Example 10. The semiconductor memory device according to Example 9, wherein the oxide promoting dopant comprises fluorine.

[0080] Example 11. The semiconductor memory device according to Example 9, wherein the oxide promoting dopant comprises argon.

[0081] Example 12. The semiconductor memory device according to Example 9, wherein the oxide promoting dopant comprises deuterium.

[0082] Example 13. The semiconductor memory device according to Example 9, wherein the gate oxide comprises silicon oxide.

[0083] Example 14. The semiconductor memory device according to Example 9, wherein the gate oxide comprises a transition metal oxide.

[0084] Example 15. A method of forming a semiconductor device, comprising: forming a transistor body region on a semiconductor substrate; forming a transmission line around the transistor body region; promoting doping with a dielectric dopant in a region adjacent to an opposite end of the transistor body region, wherein the concentration of the dopant adjacent to the opposite end is higher than that in the middle of the transistor body region; forming a gate dielectric surrounding the transistor body region, wherein: a central portion of the gate dielectric includes a first thickness; and an end portion of the gate dielectric includes a second thickness greater than the first thickness.

[0085] Example 16. The method according to Example 15, wherein doping with a dielectric-promoting dopant is performed on ion implantation comprising the dielectric-promoting dopant.

[0086] Example 17. The method according to Example 15, wherein doping with a dielectric-promoted dopant comprises depositing a doped material.

[0087] Example 18. The method according to Example 15, wherein forming the transmission line includes forming a transmission line comprising polysilicon.

[0088] Example 19. The method according to Example 18, wherein forming the transmission line includes forming a plurality of layers, wherein the top transmission line layer and the bottom transmission line layer are doped.

[0089] Example 20. The method according to Example 19, wherein the transmission line is formed before the transistor body region, and wherein the gate dielectric is formed by oxidation within an opening in the transmission line and then the opening is filled with the transistor body region.

[0090] Example 21. The method according to Example 15, wherein the transistor body region is formed before the transmission line, and wherein forming the gate dielectric includes oxidizing the transistor body region before forming the transmission line around the gate dielectric.

[0091] The foregoing description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the foregoing description. An abstract is provided to conform to 37 CFR §1.72(b) to allow the reader to quickly determine the nature of the technical disclosure. The abstract is provided so that it is not intended to interpret or limit the scope or meaning of the claims. Moreover, in the above detailed description, various features may be grouped together to simplify this disclosure. This should not be interpreted as an intention that unclaimed features are essential to any claim. Rather, the subject matter of the invention may lie in fewer than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is itself an individual embodiment, and such embodiments are contemplated to be combined or arranged in various ways. The scope of the invention should be determined with reference to the appended claims together with the full scope of the equivalents granted to such claims.

Claims

1. A semiconductor memory device, comprising: A transmission line having width and thickness between its top and bottom surfaces; A body region extending through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source / drain region and a second source / drain region separated by a channel region; and A gate dielectric that surrounds the body region and laterally separates the body region from the transmission line, wherein the thickness of the gate dielectric varies, with a thicker region adjacent to the top surface and the bottom surface.

2. The semiconductor memory device of claim 1, wherein the first source / drain region and the second source / drain region are N-type doped, and the channel region is P-type doped.

3. The semiconductor memory device of claim 1, wherein the first source / drain region and the second source / drain region are P-type doped, and the channel region is N-type doped.

4. The semiconductor memory device of claim 1, wherein the gate dielectric comprises an oxide material.

5. The semiconductor memory device of claim 1, wherein the memory cell of the semiconductor memory device comprises 4F 2 Shape factor memory unit.

6. The semiconductor memory device of claim 1, further comprising a storage capacitor coupled to the second source / drain region.

7. The semiconductor memory device of claim 1, wherein the first source / drain region and the second source / drain region are at least partially located within the thickness of the transmission line.

8. The semiconductor memory device of claim 1, wherein the transmission line comprises a word line.

9. A semiconductor memory device, comprising: A transmission line having width and thickness between its top and bottom surfaces; A body region that extends through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source / drain region and a second source / drain region separated by a channel region; A gate oxide surrounding the body region and laterally separating the body region from the transmission line, wherein the thickness of the gate oxide varies, with a thicker region adjacent to the top surface and the bottom surface; and An oxide-promoting dopant is present within the gate oxide.

10. The semiconductor memory device of claim 9, wherein the oxide promoting dopant comprises fluorine.

11. The semiconductor memory device of claim 9, wherein the oxide promoting dopant comprises argon.

12. The semiconductor memory device of claim 9, wherein the oxide promoting dopant comprises deuterium.

13. The semiconductor memory device of claim 9, wherein the gate oxide comprises silicon oxide.

14. The semiconductor memory device of claim 9, wherein the gate oxide comprises a transition metal oxide.

15. A method of forming a semiconductor device, comprising: The transistor body region is formed on a semiconductor substrate; A transmission line is formed around the transistor body region; In a region adjacent to the opposite end of the transistor body region, a dielectric is used to promote doping with a dopant, wherein the concentration of the dopant is higher near the opposite end compared to the middle of the transistor body region; A gate dielectric is formed surrounding the transistor body region, wherein: The central portion of the gate dielectric includes a first thickness; and The end of the gate dielectric includes a second thickness greater than the first thickness.

16. The method of claim 15, wherein doping with a dielectric-promoting dopant is performed on ion implantation comprising the dielectric-promoting dopant.

17. The method of claim 15, wherein doping with a dielectric-promoted dopant comprises depositing a doped material.

18. The method of claim 15, wherein forming the transmission line comprises forming a transmission line comprising polysilicon.

19. The method of claim 18, wherein forming the transmission line comprises forming a plurality of layers, wherein the top transmission line layer and the bottom transmission line layer are doped.

20. The method of claim 19, wherein the transmission line is formed prior to the transistor body region, and wherein forming the gate dielectric includes oxidizing within an opening in the transmission line and then filling the opening with the transistor body region.

21. The method of claim 15, wherein the transistor body region is formed before the transmission line, and wherein forming the gate dielectric includes oxidizing the transistor body region before forming the transmission line around the gate dielectric.

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