image sensor

Abstract

An image sensor can include a semiconductor substrate of a first conductivity type; an isolation structure in the semiconductor substrate to define a plurality of pixel regions; a shallow trench isolation pattern in the semiconductor substrate to define an active portion in each of the plurality of pixel regions; a transfer gate electrode in each of the plurality of pixel regions between a photoelectric conversion region and a floating diffusion region; and a plurality of pixel transistors in the plurality of pixel regions, respectively. Each of the plurality of pixel transistors can include a pixel gate electrode on the active portion and a plurality of source / drain regions in the active portion at two sides of the pixel gate electrode. The transfer gate electrode on the plurality of pixel regions and the pixel gate electrodes of the plurality of pixel transistors can include dopants of the first conductivity type. The plurality of source / drain regions can include dopants of a second conductivity type.

Description

[0001] This U.S. non-provisional patent application claims priority to Korean Patent Application No. 10-2025-0004210, filed on January 10, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to image sensors, and more particularly, to image sensors having improved electrical and optical properties. Background Technology

[0003] An image sensor is a device that converts light signals into electrical signals. With the development of the computer and communications industries, the demand for high-performance image sensors is likely to increase in various applications such as digital cameras, camcorders, personal communication systems, game consoles, security cameras, micro-cameras for medical applications, and / or robots.

[0004] Image sensors are generally classified into charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. CMOS image sensors can operate in a simplified manner, and because the signal processing circuitry of a CMOS image sensor can be integrated on a single chip, the size of the product can be reduced. Furthermore, because CMOS image sensors can operate with relatively low power consumption, they are more easily applied to electronic devices with limited battery capacity. In addition, because CMOS image sensors can be manufactured using existing CMOS manufacturing technologies, their manufacturing costs can be reduced. Moreover, the use of CMOS image sensors is rapidly increasing due to the improvement in resolution. Summary of the Invention

[0005] Embodiments of the inventive concept provide an image sensor with improved electrical and optical properties.

[0006] According to embodiments of the inventive concept, an image sensor may include: a semiconductor substrate of a first conductivity type; an isolation structure defining a plurality of pixel regions in the semiconductor substrate; a shallow trench isolation pattern defining an active portion in each of the plurality of pixel regions; a transfer gate electrode between a photoelectric conversion region and a floating diffusion region in each of the plurality of pixel regions; and a plurality of pixel transistors, respectively, in the plurality of pixel regions. Each of the plurality of pixel transistors may include: a pixel gate electrode on the active portion, and a plurality of source / drain regions on both sides of the pixel gate electrode in the active portion. The transfer gate electrode in each of the plurality of pixel regions may be provided as a transfer gate electrode on the plurality of pixel regions. The pixel gate electrode in each of the plurality of pixel transistors may be provided as a pixel gate electrode of the plurality of pixel transistors. The transfer gate electrode on the plurality of pixel regions and the pixel gate electrode of the plurality of pixel transistors may include a dopant of a first conductivity type. The plurality of source / drain regions may include a dopant of a second conductivity type.

[0007] According to embodiments of the inventive concept, an image sensor may include: a semiconductor substrate of a first conductivity type; an isolation structure defining a plurality of pixel regions in the semiconductor substrate; a shallow trench isolation pattern defining an active portion in each of the plurality of pixel regions to provide an active portion in each of the plurality of pixel regions; a photoelectric conversion region comprising a dopant of a second conductivity type in each of the plurality of pixel regions and in the semiconductor substrate; a floating diffusion region spaced apart from the photoelectric conversion region in each of the plurality of pixel regions and in the semiconductor substrate; a transfer gate electrode between the photoelectric conversion region and the floating diffusion region in each of the plurality of pixel regions; a source follower gate electrode on a first active portion, the first active portion being one of the active portions in the plurality of pixel regions; a first fin active pattern between the first active portion and the source follower gate electrode; and a plurality of first source / drain regions on either side of the source follower gate electrode in the first active portion. The transfer gate electrode and the source follower gate electrode may comprise a dopant of the first conductivity type.

[0008] According to embodiments of the inventive concept, an image sensor may include: a semiconductor substrate of a first conductivity type, an isolation structure in the semiconductor substrate, a plurality of transport gate electrodes, a shallow trench isolation pattern, a plurality of pixel transistors, a plurality of color filters, a grid, and a plurality of microlenses on the plurality of color filters. A first surface of the semiconductor substrate may be opposite to a second surface of the semiconductor substrate. The isolation structure may define a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region in the semiconductor substrate. Each of the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region may include: a first photoelectric conversion region, a second photoelectric conversion region, a third photoelectric conversion region, and a fourth photoelectric conversion region, and a first floating diffusion region, a second floating diffusion region, a third floating diffusion region, and a fourth floating diffusion region, respectively, and spaced apart from the first photoelectric conversion region, the second photoelectric conversion region, the third photoelectric conversion region, and the fourth photoelectric conversion region in the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region. Each of the plurality of transport gate electrodes may have a bottom surface at a height between the first surface and the second surface of the semiconductor substrate. The plurality of transmission gate electrodes may include: a first transmission gate electrode between a first photoelectric conversion region and a first floating diffusion region; a second transmission gate electrode between a second photoelectric conversion region and a second floating diffusion region; a third transmission gate electrode between a third photoelectric conversion region and a third floating diffusion region; and a fourth transmission gate electrode between a fourth photoelectric conversion region and a fourth floating diffusion region. A shallow trench isolation pattern may be adjacent to a first surface of the semiconductor substrate. The shallow trench isolation pattern may define an active portion in each of the first pixel region, second pixel region, third pixel region, and fourth pixel region to provide an active portion in each of the first pixel region, second pixel region, third pixel region, and fourth pixel region, respectively. The plurality of pixel transistors may be on the active portions in the first pixel region, second pixel region, third pixel region, and fourth pixel region, respectively. The plurality of color filters may be on a second surface of the semiconductor substrate, and the plurality of color filters may correspond to the first pixel region, second pixel region, third pixel region, and fourth pixel region, respectively. A grid may be between the plurality of color filters, and the grid may be stacked with an isolation structure. Each of the plurality of pixel transistors may include a finned active pattern, a pixel gate electrode intersecting the finned active pattern, and source / drain regions located on both sides of the pixel gate electrode within an active portion. In each of the plurality of pixel transistors, the finned active pattern may protrude from an active portion in each of the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region. The pixel gate electrode in each of the plurality of pixel transistors may serve as the pixel gate electrode of the plurality of pixel transistors. The pixel gate electrode, the first transport gate electrode, the second transport gate electrode, the third transport gate electrode, and the fourth transport gate electrode of the plurality of pixel transistors may include dopants of a first conductivity type.The source / drain regions of the plurality of pixel transistors may include dopants of a second conductivity type. Attached Figure Description

[0009] Figure 1A This is a circuit diagram illustrating a unit pixel of a pixel array according to an embodiment of the inventive concept.

[0010] Figure 1B This is a circuit diagram illustrating a unit pixel of a pixel array according to an embodiment of the inventive concept.

[0011] Figure 2 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept.

[0012] Figure 3A It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 2 A sectional view taken by lines A-A' and D-D'.

[0013] Figure 3B It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 2 A sectional view taken by lines B-B' and E-E'.

[0014] Figure 3C It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 2 A sectional view taken by line C-C'.

[0015] Figure 4 and Figure 5 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 2 A sectional view taken from lines A-A', B-B', and C-C'.

[0016] Figure 6 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept.

[0017] Figure 7 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 6 A sectional view taken from lines A-A', B-B', and C-C'.

[0018] Figure 8 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept.

[0019] Figure 9 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 8 A sectional view taken from lines A-A', B-B', and C-C'.

[0020] Figure 10 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept.

[0021] Figure 11 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 10 A sectional view taken from lines A-A', B-B', and C-C'.

[0022] Figure 12 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept.

[0023] Figure 13 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 12 A sectional view taken from lines A-A', B-B', and C-C'.

[0024] Figure 14 and Figure 15 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept.

[0025] Figure 16 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 14 and Figure 15 The sectional view taken by line F-F'.

[0026] Figure 17 This is a plan view illustrating an image sensor according to an embodiment of the inventive concept.

[0027] Figure 18 This is a schematic plan view of an image sensor according to an embodiment of the inventive concept.

[0028] Figure 19 and Figure 20 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 18 A sectional view taken by line I-I'. Detailed Implementation

[0029] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are illustrated.

[0030] When a phrase such as “at least one of…” follows an element in a column, it modifies the entire column, not a single element within the column. For example, “at least one of A, B, and C” and similar language (e.g., “at least one selected from a group consisting of A, B, and C” and “at least one of A, B, or C”) can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C (e.g., ABC, AB, BC, and AC).

[0031] When the terms “about” or “basic” are used in conjunction with numerical values ​​in this specification, it is intended that the associated numerical values ​​include manufacturing or operational tolerances (e.g., ±10%) centered on the stated numerical value. Furthermore, when the terms “approximately” and “basic” are used in conjunction with geometry, it is intended that precision of the geometry is not required, but the range of the shape is within the disclosed range. Moreover, regardless of whether numerical values ​​or shapes are modified to “about” or “basic,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) centered on the stated numerical value or shape. When a range is specified, the range includes all values ​​within that range (e.g., increments of 0.1%).

[0032] Although the term "equal to" is used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is said to be "equal to" another element, it should be understood that the element or value may be "equal to" the other element within a range of expected manufacturing or operational tolerances (e.g., ±10%).

[0033] The concept of "substantially identical" components can indicate that components can be completely identical, and can also indicate that components can be determined to be identical taking into account errors or deviations that occur during the process.

[0034] Figure 1A This is a circuit diagram illustrating a unit pixel of a pixel array according to an embodiment of the inventive concept. Figure 1B This is a circuit diagram illustrating a unit pixel of a pixel array according to an embodiment of the inventive concept.

[0035] Reference Figure 1A and Figure 1B An image sensor may include multiple unit pixels arranged in two dimensions, and each unit pixel PX may be configured to convert an optical signal into an electrical signal.

[0036] A unit pixel PX may include photoelectric conversion circuit 1 and pixel circuit 2.

[0037] The photoelectric conversion circuit 1 may include multiple photoelectric conversion groups 1a, 1b, 1c, and 1d. The photoelectric conversion circuit 1 may include at least four, eight, or sixteen photoelectric conversion groups 1a, 1b, 1c, and 1d. Each of the photoelectric conversion groups 1a, 1b, 1c, and 1d may include at least two photoelectric conversion devices (e.g., photodiodes), multiple transmission transistors, and a floating diffusion region. Each of the photoelectric conversion groups 1a, 1b, 1c, and 1d may include four, eight, or sixteen photoelectric conversion devices.

[0038] In one embodiment, the photoelectric conversion circuit 1 may include a first photoelectric conversion group 1a, a second photoelectric conversion group 1b, a third photoelectric conversion group 1c, and a fourth photoelectric conversion group 1d.

[0039] The first photoelectric conversion group 1a may include a first photodiode PD1, a second photodiode PD2, a first transfer transistor TX1, and a second transfer transistor TX2. The first transfer transistor TX1 and the second transfer transistor TX2 may be configured to transfer the charge accumulated in the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 to the floating diffusion region FD.

[0040] The second photoelectric conversion group 1b may include a third photodiode PD3, a fourth photodiode PD4, a third transfer transistor TX3, and a fourth transfer transistor TX4. The third transfer transistor TX3 and the fourth transfer transistor TX4 may be configured to transfer the charge accumulated in the third photoelectric conversion device PD3 and the fourth photoelectric conversion device PD4 to the floating diffusion region FD. The third photoelectric conversion group 1c may include a fifth photodiode PD5, a sixth photodiode PD6, a fifth transfer transistor TX5, and a sixth transfer transistor TX6. The fifth transfer transistor TX5 and the sixth transfer transistor TX6 may be configured to transfer the charge accumulated in the fifth photoelectric conversion device PD5 and the sixth photoelectric conversion device PD6 to the floating diffusion region FD. The fourth photoelectric conversion group 1d may include a seventh photodiode PD7, an eighth photodiode PD8, a seventh transfer transistor TX7, and an eighth transfer transistor TX8. The seventh transfer transistor TX7 and the eighth transfer transistor TX8 may be configured to transfer the charge accumulated in the seventh photoelectric conversion device PD7 and the eighth photoelectric conversion device PD8 to the floating diffusion region FD.

[0041] The first to fourth photoelectric conversion groups 1a, 1b, 1c and 1d can be connected together to the floating diffusion region FD. That is, the first transmission transistor TX1 to the eighth transmission transistor TX8 can be connected together to the floating diffusion region FD.

[0042] Each of the first to fourth photoelectric conversion groups 1a, 1b, 1c and 1d is shown to include two photodiodes, but the inventive concept is not limited to this example. For example, each photoelectric conversion group may include four or eight photodiodes.

[0043] The transfer gate electrodes TG1 to TG8 of the first transfer transistor TX1 to the eighth transfer transistor TX8 can be controlled by the first charge transfer signal to the eighth charge transfer signal. In this specification, the transfer gate electrode of each transfer transistor may have a dual vertical gate structure. A dual vertical gate structure can refer to a structure that provides two vertical transfer gates for a photodiode. The same transfer control signal can be applied to both vertical transfer gates in the dual vertical gate structure.

[0044] The floating diffusion region FD can be configured to accumulate and store charge generated in at least one of the first photodiodes PD1 to the eighth photodiodes PD8 and transferred from at least one of the first photodiodes PD1 to the eighth photodiodes PD8. The source follower transistor SF can be controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

[0045] like Figure 1A As shown, pixel circuit 2 may include a reset transistor RX, a source follower transistor SF, a select transistor SX, and a dual-conversion gain transistor DCX. Optionally, as... Figure 1B As shown, pixel circuit 2 may include a reset transistor RX, a source follower transistor SF, and a select transistor SX.

[0046] In one embodiment, the number of pixel transistors in pixel circuit 2 is not limited to this, and the number of pixel transistors in each unit pixel PX can vary.

[0047] In detail, the reset transistor RX can periodically reset the charge accumulated in the charge detection node or the floating diffusion region FD according to the reset signal applied to the reset gate electrode RG. The reset transistor RX can be arranged in the floating diffusion region FD and (e.g., for supplying the power supply voltage V) PIX Between the pixel power supplies.

[0048] If the reset transistor RX and the dual-conversion gain transistor DCX are turned on, the power supply voltage V PIX It can be transferred to the floating diffusion region FD. Therefore, the charge accumulated in the floating diffusion region FD can be discharged to reset the floating diffusion region FD.

[0049] A dual-conversion-gain transistor (DCX) can be arranged between and connected to the floating diffusion region (FD) and the reset transistor (RX). The DCX can be configured to change the capacitance of the charge detection node or the floating diffusion region (FD) in response to a dual-conversion-gain control signal applied to the dual-conversion gate (DCG), thereby adjusting the conversion gain in a unit pixel (PX).

[0050] Specifically, during image capture, low-intensity light and high-intensity light can be incident on the pixel array, and here, the dual-conversion-gain transistor DCX can be turned on in high-intensity mode and turned off in low-intensity mode. By using the dual-conversion-gain transistor DCX, the difference in conversion gain between the high-intensity mode and the low-intensity mode can be achieved.

[0051] If the dual conversion gain transistor DCX is turned on, the capacitance of the floating diffusion region FD can be increased, thereby reducing the conversion gain. Conversely, if the dual conversion gain transistor DCX is turned off, the capacitance of the floating diffusion region FD can be decreased, thereby increasing the conversion gain.

[0052] In one embodiment, two or more dual conversion gain transistors (DCX) may be arranged between the reset transistor RX and the floating diffusion region FD and connected to the reset transistor RX and the floating diffusion region FD, and the conversion gain in a unit pixel PX may vary depending on the number of dual conversion gain transistors (DCX).

[0053] The source follower transistor SF can be a source follower buffer amplifier that generates a source-drain current proportional to the charge in the floating diffusion region FD, with the charge in the floating diffusion region FD input to the gate electrode of the source follower transistor SF. The source follower transistor SF can amplify changes in the potential of the floating diffusion region FD, and the amplified signal can be output to the output line Vout via the selection transistor SX.

[0054] The select transistor SX can be used to select each row of a unit pixel PX for a read operation. If the select transistor SX is turned on by a select signal applied to the select gate electrode SG, an electrical signal can be output from the source terminal of the source follower transistor SF to the output line Vout.

[0055] Figure 2 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept. Figure 3A It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 2 A sectional view taken by lines A-A' and D-D'. Figure 3B It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 2 A sectional view taken by lines B-B' and E-E'. Figure 3C It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 2 A sectional view taken by line C-C'.

[0056] Reference Figure 2 , Figure 3A , Figure 3B and Figure 3C An image sensor according to an embodiment of the inventive concept may include a photoelectric conversion circuit layer 10, a pixel circuit layer 20, and a light-transparent layer 30.

[0057] When viewed in a vertical cross-section, the photoelectric conversion circuit layer 10 may be disposed between the pixel circuit layer 20 and the light-transparent layer 30. The photoelectric conversion circuit layer 10 may include a semiconductor substrate 100, an isolation structure PIS, a shallow trench isolation pattern STI, photoelectric conversion regions 110a and 110b, transfer gate electrodes TG1 and TG2, and floating diffusion regions FD1 and FD2.

[0058] Pixel circuit layer 20 may include pixel circuitry (e.g., MOS transistors) electrically connected to the floating diffusion regions FD1 and FD2. That is, pixel circuit layer 20 may include previously referenced... Figure 1A and Figure 1B The described transistors include a reset transistor RX, a select transistor SX, a dual-conversion gain transistor DCX, and a source follower transistor SF, and may include transistors connected to... Figure 1A and Figure 1B The interconnects of pixel circuit 2.

[0059] The light-transparent layer 30 can be configured to focus and filter light incident from the outside and provide the light to the photoelectric conversion circuit layer 10. The light-transparent layer 30 may include a planarization insulating layer 310, a grid 320, a color filter (C / F) 330, and a microlens 340.

[0060] Specifically, the semiconductor substrate 100 may have a first surface or top surface 100a and a second surface or bottom surface 100b opposite to each other. The semiconductor substrate 100 may be a substrate comprising a bulk silicon substrate and epitaxial layers, the bulk silicon substrate and epitaxial layers being sequentially stacked and having a first conductivity type (e.g., p-type), and if the bulk silicon substrate is removed during the image sensor manufacturing process, the semiconductor substrate 100 may consist only of p-type epitaxial layers. In one embodiment, the semiconductor substrate 100 may be a bulk semiconductor substrate comprising wells of a first conductivity type.

[0061] The semiconductor substrate 100 may include a plurality of pixel regions PR1, PR2, PR3, and PR4 defined by an isolation structure PIS. The pixel regions PR1, PR2, PR3, and PR4 may be arranged in a first direction D1 and a second direction D2 that are not parallel to each other, or in a matrix shape. The pixel regions may include a first pixel region PR1, a second pixel region PR2, a third pixel region PR3, and a fourth pixel region PR4, wherein the first pixel region PR1 and the second pixel region PR2 are adjacent to each other in the first direction D1, and the first pixel region PR1 and the third pixel region PR3 are adjacent to each other in the second direction D2. The second pixel region PR2 and the fourth pixel region PR4 may be adjacent to each other in the second direction D2, and the second pixel region PR2 and the third pixel region PR3 may be arranged in a diagonal direction oblique to the first direction D1 and the second direction D2. Here, the first direction D1 and the second direction D2 may be parallel to the first surface 100a of the semiconductor substrate 100 and may not be parallel to each other. The third direction D3 may be perpendicular to the first surface 100a of the semiconductor substrate 100.

[0062] When viewed in a planar view, each of the first pixel regions PR1 to the fourth pixel region PR4 can be surrounded by an isolation structure PIS. Each of the first pixel regions PR1 to the fourth pixel region PR4 can be defined by a pair of first portions Pa extending in a first direction D1 and a pair of second portions Pb extending in a second direction D2 of the isolation structure PIS. In each of the first pixel regions PR1 to the fourth pixel region PR4, the isolation structure PIS may include a pair of third portions Pc. The third portions Pc may extend from the first portions Pa in the second direction D2, or may extend from the second portions Pb in the first direction D1, and may be spaced apart from each other.

[0063] The isolation structure PIS may be configured to penetrate the semiconductor substrate 100 vertically. Specifically, the isolation structure PIS may have a length in a direction perpendicular to the top surface of the semiconductor substrate 100 (e.g., a third direction D3), and the length of the isolation structure PIS may be substantially equal to the vertical thickness of the semiconductor substrate 100. In one embodiment, the isolation structure PIS may extend vertically from a first surface 100a of the semiconductor substrate 100 to a second surface 100b, and may contact the second surface 100b of the semiconductor substrate 100.

[0064] The isolation structure PIS may include a substrate insulating pattern 111, a gap-filling pattern 113, and a cap insulating pattern 115. The gap-filling pattern 113 may be configured to vertically penetrate a portion of the semiconductor substrate 100, and the substrate insulating pattern 111 may be disposed between the gap-filling pattern 113 and the semiconductor substrate 100. The cap insulating pattern 115 may be disposed on the gap-filling pattern 113. The substrate insulating pattern 111 and the cap insulating pattern 115 may be formed of at least one of silicon oxide, silicon oxynitride, and silicon nitride, or may include at least one of silicon oxide, silicon oxynitride, and silicon nitride. The gap-filling pattern 113 may be formed of undoped polysilicon or doped polysilicon, or may include undoped polysilicon or doped polysilicon. The gap-filling pattern 113 may include air gaps or voids. The cap insulating pattern 115 of the isolation structure PIS may include the same insulating material as the shallow trench isolation pattern STI, and in this case, there may be no observable interface between the cap insulating pattern 115 and the shallow trench isolation pattern STI.

[0065] In one embodiment, in each of the first pixel regions PR1 to the fourth pixel regions PR4, a first photoelectric conversion region 110a and a second photoelectric conversion region 110b may be disposed in the semiconductor substrate 100. In the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, light incident from the outside can be converted into electrical signals.

[0066] The first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be impurity regions doped with a dopant having a second conductivity type (e.g., n-type) different from the first conductivity type of the semiconductor substrate 100. The semiconductor substrate 100 of the first conductivity type and the first photoelectric conversion region 110a and the second photoelectric conversion region 110b can constitute a pair of photodiodes. That is, the semiconductor substrate 100 of the first conductivity type and the first photoelectric conversion region 110a or the second photoelectric conversion region 110b can form a junction that serves as a photodiode. When light is incident on the first photoelectric conversion region 110a and the second photoelectric conversion region 110b constituting the photodiode, photocharge can be generated and accumulated proportionally to the intensity of the incident light.

[0067] In each of the first pixel regions PR1 to the fourth pixel regions PR4, a phase difference may exist between the electrical signals output from the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, respectively. The image sensor may be configured to measure the distance to a target object based on the phase difference between the electrical signals output from the paired photoelectric conversion regions (e.g., the first photoelectric conversion region 110a and the second photoelectric conversion region 110b), to check the degree to which the target object is in focus or out of focus, and to automatically correct the focus of the image sensor based on the results of the check.

[0068] Each of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may have a first width in the first direction D1 and a first length in the second direction D2 that is greater than the first width. In one embodiment, the first length may be approximately twice the first width.

[0069] The first photoelectric conversion region 110a and the second photoelectric conversion region 110b are spaced apart from each other in the first direction D1, and the third part Pc of the isolation structure PIS is placed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The third part Pc of the isolation structure PIS can physically reflect the incident light at the edge portion of each of the first pixel region PR1 to the fourth pixel region PR4, and in this case, the crosstalk problem between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be reduced.

[0070] In each of the first pixel regions PR1 to the fourth pixel regions PR4, the shallow trench isolation pattern STI may be configured to be adjacent to the first surface 100a of the semiconductor substrate 100. The bottom surface of the shallow trench isolation pattern STI may be perpendicularly spaced from the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0071] Shallow trench isolation patterns (STIs) can be formed in trenches created by recessing the first surface 100a of a semiconductor substrate 100. The shallow trench isolation patterns (STIs) can be formed of an insulating material or may include an insulating material.

[0072] Reference Figure 3A , Figure 3B and Figure 3C Shallow trench isolation pattern (STI) may include an insulating liner formed to conformally cover the surface of the trench and an insulating gap filler formed to fill the trench covered by the insulating liner. The insulating gap filler may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0073] In one embodiment, the shallow trench isolation pattern (STI) may be configured to define a first active portion ACT1 and a second active portion ACT2 in each of the first pixel regions PR1 to PR4. The first active portion ACT1 and the second active portion ACT2 may be portions of the semiconductor substrate 100. When viewed in a plan view, the first active portion ACT1 and the second active portion ACT2 may be superimposed on each of the first photoelectric conversion region 100a and the second photoelectric conversion region 110b. That is, two first active portions ACT1 and two second active portions ACT2 may be disposed in each of the pixel regions PR1 to PR4, but the inventive concept is not limited to this example.

[0074] The first active portion ACT1 and the second active portion ACT2 can be spaced apart from each other in the second direction D2 by a shallow trench isolation pattern STI, and can have different sizes and shapes. The first active portion ACT1 can be T-shaped, but the inventive concept is not limited to this example; for example, the first active portion ACT1 can be quadrilateral or polygonal. The second active portion ACT2 can have a major axis in the second direction D2 and a minor axis in the first direction D1. When measured in the second direction D2, each of the second active portions ACT2 can have a second length smaller than the first length of the first photoelectric conversion region 110a or the second photoelectric conversion region 110b.

[0075] The first active portion ACT1 and the second active portion ACT2 in the third pixel region PR3 and the fourth pixel region PR4 can be set in a mirror symmetrical manner with respect to the first active portion ACT1 and the second active portion ACT2 in the first pixel region PR1 and the second pixel region PR2.

[0076] The first transmission gate electrode TG1 and the second transmission gate electrode TG2 may be disposed on each of the first pixel regions PR1 to the fourth pixel regions PR4. In some embodiments, the first transmission gate electrode TG1 may be disposed between the first photoelectric conversion region 110a and the first floating diffusion region FD1, and the second transmission gate electrode TG2 may be disposed between the second photoelectric conversion region 110b and the second floating diffusion region FD2.

[0077] The first transmission gate electrode TG1 may be disposed on the first active portion ACT1 and may be stacked with the first photoelectric conversion region 110a. The second transmission gate electrode TG2 may be disposed on the first active portion ACT1 and may be stacked with the second photoelectric conversion region 110b.

[0078] Each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may include a portion disposed in a trench formed by recessing the first surface 100a of the semiconductor substrate 100. In one embodiment, each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may include a first portion P1 disposed on the first surface 100a of the semiconductor substrate 100 and a second portion P2 extending vertically from the first portion P1 into the semiconductor substrate 100. Each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may have a first bottom surface BS1 disposed at a height lower than the height of the first surface 100a of the semiconductor substrate 100.

[0079] In one embodiment, each of the first transmission gate electrode TG1 and the second transmission gate electrode TG2 may have a dual-gate electrode structure, in which a pair of first vertical gates GE1 and second vertical gates GE2 are disposed on each of the first active portion ACT1. In one embodiment, the shape and position of the first transmission gate electrode TG1 and the second transmission gate electrode TG2 may be varied. In each of the first transmission gate electrode TG1 and the second transmission gate electrode TG2, the pair of first vertical gates GE1 and the second vertical gates GE2 may be electrically connected to each other via metal wire 223.

[0080] In one embodiment, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be formed of a conductive layer comprising a dopant of the same conductivity type as that of the semiconductor substrate 100. As an example, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be formed of polysilicon doped with a first conductivity type (e.g., p-type), or may comprise polysilicon doped with a first conductivity type (e.g., p-type).

[0081] A gate insulating layer of uniform thickness may be disposed between the first transmission gate electrode TG1 and the second transmission gate electrode TG2 and the semiconductor substrate 100. An insulating spacer SP may be disposed on the opposite side surfaces of the first transmission gate electrode TG1 and the second transmission gate electrode TG2.

[0082] In each of the first pixel regions PR1 to the fourth pixel regions PR4, a first floating diffusion region FD1 may be disposed in the first active portion ACT1 between the first transmission gate electrodes TG1. A second floating diffusion region FD2 may be disposed in the first active portion ACT1 between the second transmission gate electrodes TG2.

[0083] The first floating diffusion region FD1 and the second floating diffusion region FD2 can be formed by a doping process in which a dopant of a second conductivity type different from that of the semiconductor substrate 100 is implanted into the semiconductor substrate 100. For example, the first floating diffusion region FD1 and the second floating diffusion region FD2 can be n-type doped regions.

[0084] The first floating diffusion region FD1 and the second floating diffusion region FD2 in the first pixel region PR1 to the fourth pixel region PR4 can be electrically connected to each other via contact plug 221 and metal wire 223. The first floating diffusion region FD1 and the second floating diffusion region FD2 in the first pixel region PR1 to the fourth pixel region PR4 can be electrically connected to and jointly connected to a reference. Figure 1A and Figure 1B The pixel transistors described are SF, DCX, RX, and SX.

[0085] In each of the first pixel regions PR1 to the fourth pixel regions PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be respectively disposed on the second active portion ACT2. In each of the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, the first pixel gate electrode PG1 may be stacked with the first photoelectric conversion region 110a, and the second pixel gate electrode PG2 may be stacked with the second photoelectric conversion region 110b.

[0086] In each of the first pixel regions PR1 to the fourth pixel regions PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 can constitute a reference. Figure 1A and Figure 1B One of the pixel transistors described (e.g., reset transistor RX, source follower transistor SF, dual conversion gain transistor DCX, and select transistor SX).

[0087] The first pixel gate electrode PG1 on the first pixel region PR1 can be set as a reference. Figure 1A and Figure 1B The selection gate electrode of the selection transistor SX is described, and the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG) on the third pixel region PR3 can be set as a reference. Figure 1A and Figure 1B The source follower gate electrode of the described source follower transistor SF. The first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG) on the third pixel region PR3 can be electrically connected to each other via metal line 223.

[0088] The first pixel gate electrode PG1 on the fourth pixel region PR4 can be set as a reference. Figure 1A and Figure 1B The dual-conversion-gain transistor DCX is described as having a dual-conversion-gain gate electrode. The second pixel gate electrode PG2 on the fourth pixel region PR4 can be set as a reference. Figure 1A and Figure 1B The reset gate electrode of the reset transistor RX is described. Optionally, both the first pixel gate electrode PG1 and the second pixel gate electrode PG2 on the fourth pixel region PR4 can be set as the reset gate electrodes of the reset transistor RX.

[0089] Additionally, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 on the second pixel region PR2 can be used as one of the pixel transistors constituting a unit pixel, and can be configured as a dummy gate. In one embodiment, the functions of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 on the first pixel region PR1 to the fourth pixel region PR4 can be changed differently.

[0090] In the first pixel regions PR1 to the fourth pixel regions PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be formed of a conductive layer containing dopants of the same conductivity type as the semiconductor substrate 100. The first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be formed of polysilicon doped with a first conductivity type (e.g., p-type) or may include polysilicon doped with a first conductivity type (e.g., p-type).

[0091] Because the first pixel gate electrode PG1 and the second pixel gate electrode PG2 contain dopants of the first conductivity type, the threshold voltages of the pixel transistors SF, RX, DCX, and SX can be increased. Therefore, the linearity of the output characteristics of the source follower transistor SF can be improved under low-light conditions, and the leakage current characteristics of the source follower transistor SF can also be improved.

[0092] An insulating spacer SP may be disposed on the opposite side surface of the first pixel gate electrode PG1 and the second pixel gate electrode PG2. The insulating spacer SP may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), and silicon carbonitride (SiCON), or may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), and silicon carbonitride (SiCON).

[0093] The first source / drain region SD1 may be disposed on one side of each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 in the second active portion ACT2, and the second source / drain region SD2 may be disposed on the opposite side of each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 (for example, on the other side opposite to said one side in the second direction D2).

[0094] The first source / drain region SD1 and the second source / drain region SD2 can be formed by a doping process in which a dopant of a second conductivity type different from that of the semiconductor substrate 100 is implanted into the semiconductor substrate 100. Each of the first source / drain region SD1 and the second source / drain region SD2 can be, for example, an n-type doped region.

[0095] In one embodiment, constitute Figure 1A and Figure 1B At least one of the pixel transistors SF, DCX, RX, and SX of a unit pixel PX may be included in a fin-shaped active pattern FP between the first pixel gate electrode PG1 and the second pixel gate electrode PG2 and the second active portion ACT2.

[0096] In the third pixel region PR3 Figure 1A and Figure 1BThe source follower transistor SF can be disposed on the second active portion ACT2, and the fin-shaped active pattern FP can protrude vertically from each of the second active portions ACT2. The fin-shaped active pattern FP can be part of the semiconductor substrate 100, and can be formed by patterning a part of the semiconductor substrate 100.

[0097] Specifically, the top surface of the fin-shaped active pattern FP may be disposed at substantially the same height as the first surface 100a of the semiconductor substrate 100. The fin-shaped active pattern FP may be disposed between the first source / drain region SD1 and the second source / drain region SD2. The fin-shaped active pattern FP may have a strip shape extending in the second direction D2.

[0098] Each of the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG) on the third pixel region PR3 can be configured to surround the top surface and the opposite side surface of each of the fin active patterns FP. Gate insulating layers can be disposed between the first pixel gate electrode PG1 and the second pixel gate electrode PG2 and the fin active patterns FP, respectively.

[0099] In the third pixel region PR3, since the fin-shaped active pattern FP is disposed on the second active portion ACT2, the effective channel width of the pixel transistor (e.g., a source follower transistor) in the first direction D1 and the effective channel length of the pixel transistor in the second direction D2 can be ensured. Therefore, even when the area of ​​each pixel region PR is reduced, the electrical characteristics of the pixel transistor can be improved or optimized.

[0100] In one embodiment, the finned active pattern FP may include a channel region CH doped with a dopant of a second conductivity type. The channel region CH may be located between a first source / drain region SD1 and a second source / drain region SD2. The concentration of the dopant of the second conductivity type in the channel region CH may be lower than the concentration of the dopant of the second conductivity type in the first source / drain region SD1 and the second source / drain region SD2. Simultaneously, the channel region CH of the finned active pattern FP may be undoped, and the channel region of the pixel transistor in the third pixel region PR3 may have a first conductivity type.

[0101] Since the channel region CH, the first source / drain region SD1, and the second source / drain region SD2 have the same conductivity type, the pixel transistor composed of the first pixel gate electrode PG1, the second pixel gate electrode PG2, and the fin active pattern FP can form a junctionless transistor. Therefore, junction leakage current can be limited and / or prevented from occurring between the channel region CH and the first source / drain region SD1 and the second source / drain region SD2.

[0102] Between the fin-shaped active patterns FP, each of the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG) on the third pixel region PR3 may have a second bottom surface BS2 disposed at a height lower than the height of the first surface 100a of the semiconductor substrate 100. Furthermore, the second bottom surface BS2 of the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG) may be disposed at a height higher than the height of the first bottom surface BS1 of the first transfer gate electrode TG1 and the second transfer gate electrode TG2. That is, each of the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG) on the third pixel region PR3 may have a second bottom surface BS2 disposed at a height between the first surface 100a and the first bottom surface BS1 of the semiconductor substrate 100. Moreover, when measured from the first surface 100a of the semiconductor substrate 100, the vertical length d1 of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be greater than the vertical length d2 of the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG).

[0103] In one embodiment, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 disposed on the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, but not on the third pixel region PR3, may have a bottom surface parallel to the first surface 100a of the semiconductor substrate 100. That is, the pixel transistor disposed in the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4 may be a planar MOS transistor.

[0104] The first pixel gate electrode PG1 and the second pixel gate electrode PG2 on the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4 may be disposed on a channel region CH containing a dopant of a second conductivity type. Optionally, the pixel transistors on the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4 may be disposed on a semiconductor substrate 100 of a first conductivity type. Each of the pixel transistors on the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4 may include a channel region of a first conductivity type.

[0105] Furthermore, in each of the first pixel regions PR1 to the fourth pixel regions PR4, a ground impurity region GR may be disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The ground impurity region GR may be disposed between the third portion Pc of the isolation structure PIS. The ground impurity region GR may be formed by doping with a dopant of the same conductivity type as the semiconductor substrate 100 (e.g., the first conductivity type).

[0106] An interlayer insulating layer 210 may be stacked on a first surface 100a of a semiconductor substrate 100, and the interlayer insulating layer 210 may be configured to cover pixel transistors RX, SF, DCX, and SX constituting a readout circuit, as well as a first transfer gate electrode TG1 and a second transfer gate electrode TG2. The interlayer insulating layer 210 may be formed of at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride, or may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0107] Interconnection structures connected to the readout circuit may be disposed in the interlayer insulating layer 210. The interconnection structures may include contact plugs 221 and metal wires 223 connecting the contact plugs 221 to each other.

[0108] Reference Figure 3A , Figure 3B and Figure 3C The light-transparent layer 30 can be disposed on the second surface 100b of the semiconductor substrate 100.

[0109] The planarization insulating layer 310 may cover the second surface 100b of the semiconductor substrate 100. The planarization insulating layer 310 may be formed of a transparent insulating material and may include multiple layers. The planarization insulating layer 310 may be formed of an insulating material with a different refractive index than the semiconductor substrate 100. The planarization insulating layer 310 may include at least one of a metal oxide and / or silicon oxide.

[0110] A grid 320 may be disposed on the planarized insulating layer 310. When viewed in a plan view, similar to the isolation structure PIS, the grid 320 may have a grid shape. When viewed in a plan view, the grid 320 may be superimposed on the isolation structure PIS. That is, the grid 320 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2 to intersect the first portion. The width of the grid 320 may be substantially equal to or less than the minimum width of the isolation structure PIS.

[0111] The grid 320 may include conductive patterns and / or low-refractive-index patterns. The conductive patterns may be formed of or may include at least one of metallic materials (e.g., titanium, tantalum, and tungsten). The low-refractive-index patterns may be formed of or may include materials with a lower refractive index than the conductive patterns. The low-refractive-index patterns may be formed of organic materials and may have a refractive index of about 1.1 to 1.3. For example, the grid 320 may be a polymer layer comprising silica nanoparticles.

[0112] Color filters 330 may be configured to correspond to each of pixel regions PR1 to PR4. Color filters 330 may fill the space defined by grid 320. Depending on the unit pixel, color filters 330 may include a red, green, or blue color filter, or a magenta, cyan, or yellow color filter. As another example, some of the color filters 330 may include a white color filter or an infrared light filter.

[0113] Microlenses 340 may be disposed on color filters 330. Microlenses 340 may have a convex shape and a specific radius of curvature. Microlenses 340 may be formed of or may comprise light-transparent resin. Microlenses 340 may be disposed on color filters 330 to correspond to pixel regions PR respectively. In one embodiment, at least one of microlenses 340 may be disposed jointly on at least two pixel regions PR.

[0114] Figure 4 and Figure 5 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 2 The sectional views are taken along lines A-A', B-B', and C-C'. For a concise description, refer to... Figure 2 , Figure 3A , Figure 3B and Figure 3C The same elements in the image sensor described may be identified by the same reference numerals without repeating their overlapping descriptions.

[0115] Reference Figure 4 Unlike the previous embodiments, the first bottom surface BS1 of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 can be arranged at substantially the same height as the second bottom surface BS2 of the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG), and the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG) are disposed in the third pixel region PR3. In other words, the first bottom surface BS1 and the second bottom surface BS2 can be arranged at a height that is spaced apart from the first surface 100a of the semiconductor substrate 100. That is, when measured from the first surface 100a of the semiconductor substrate 100, the vertical length d1 of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 can be substantially the same as the vertical length d2 of the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG).

[0116] The first transfer gate electrode TG1 and the second transfer gate electrode TG2, as well as the first pixel gate electrode PG1 and the second pixel gate electrode PG2, on the first pixel region PR1 to the fourth pixel region PR4 can be formed simultaneously, and can be formed of the same conductive material or may include the same conductive material. In one embodiment, the first transfer gate electrode TG1 and the second transfer gate electrode TG2, as well as the first pixel gate electrode PG1 and the second pixel gate electrode PG2 on the first pixel region PR1 to the fourth pixel region PR4, can be formed of polysilicon doped with a first conductivity type (e.g., p-type) or may include polysilicon doped with a first conductivity type (e.g., p-type).

[0117] Furthermore, a channel region CH doped with a second conductivity type (e.g., n-type) can be disposed on the first pixel region PR1 to the fourth pixel region PR4 below the first pixel gate electrode PG1 and the second pixel gate electrode PG2.

[0118] Reference Figure 5 The pixel transistor on the third pixel region PR3 may include a first pixel gate electrode PG1 and a second pixel gate electrode PG2 disposed on a channel region CH doped with a dopant of a second conductivity type (e.g., n-type).

[0119] Planar pixel transistors can be disposed in a first pixel region PR1, a second pixel region PR2, and a fourth pixel region PR4, and a semiconductor substrate 100 of a first conductivity type can be used as the channel region of the pixel transistors in the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, respectively. In the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 can have a bottom surface parallel to the first surface 100a of the semiconductor substrate 100.

[0120] Figure 6 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept. Figure 7 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 6 The sectional views are taken along lines A-A', B-B', and C-C'. For a concise description, refer to... Figure 2 , Figure 3A , Figure 3B and Figure 3C The same elements in the image sensor described may be identified by the same reference numerals without repeating their overlapping descriptions.

[0121] Reference Figure 6 and Figure 7All pixel transistors in the first pixel region PR1 to the fourth pixel region PR4 can be fin-type MOS transistors.

[0122] In each of the first pixel region PR1 to the fourth pixel region PR4, the fin-shaped active pattern FP can be disposed between the second active portion ACT2 and the first pixel gate electrode PG1 and the second pixel gate electrode PG2.

[0123] Each of the fin-shaped active patterns FP can protrude vertically from the second active portion ACT2. Each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 can have a bottom surface disposed between the fin-shaped active patterns FP at a height lower than the height of the first surface 100a of the semiconductor substrate 100.

[0124] In at least one of the first pixel regions PR1 to the fourth pixel regions PR4, the fin active pattern FP may be doped with a dopant of a second conductivity type. In one embodiment, the fin active pattern FP may be doped with a dopant of a second conductivity type in all of the first pixel regions PR1 to the fourth pixel regions PR4. In another embodiment, the fin active pattern FP in the third pixel region PR3 may be doped with a dopant of a second conductivity type, and the fin active patterns FP in the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4 may not be doped with a dopant of a second conductivity type. That is, the pixel transistor on the third pixel region PR3 may include a channel region of a second conductivity type, and each of the pixel transistors on the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4 may include a channel region of a first conductivity type.

[0125] In another embodiment, the fin active pattern FP in the third pixel region PR3 may not be doped with a dopant of the second conductivity type, while the fin active patterns FP in the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4 may be doped with a dopant of the second conductivity type. That is, the pixel transistor on the third pixel region PR3 may include a channel region of the first conductivity type, and each of the pixel transistors on the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4 may include a channel region of the second conductivity type.

[0126] Figure 8 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept. Figure 9 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 8 The sectional views are taken along lines A-A', B-B', and C-C'. For a concise description, refer to... Figure 6 and Figure 7The same elements in the image sensor described may be identified by the same reference numerals without repeating their overlapping descriptions.

[0127] Reference Figure 8 and Figure 9 All pixel transistors in the first pixel region PR1 to the fourth pixel region PR4 can be fin-type MOS transistors, and the widths of the fin active patterns FP1 and FP2 can vary depending on the pixel transistors set in the first pixel region PR1 to the fourth pixel region PR4.

[0128] In the third pixel region PR3, a first fin-shaped active pattern FP1 may be disposed between the second active portion ACT2 and the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG). In the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, a second fin-shaped active pattern FP2 may be disposed between the second active portion ACT2 and the first pixel gate electrode PG1 and the second pixel gate electrode PG2. In the third pixel region PR3, each of the first pixel gate electrode PG1 (SFG) and the second pixel gate electrode PG2 (SFG) may be configured to intersect with the first fin-shaped active pattern FP1. In each of the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be configured to intersect with the second fin-shaped active pattern FP2. In one embodiment, when measured in the first direction D1, the width of each of the first fin-shaped active patterns FP1 may be smaller than the width of each of the second fin-shaped active patterns FP2.

[0129] Figure 10 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept. Figure 11 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 10 A sectional view taken from lines A-A', B-B', and C-C'.

[0130] Reference Figure 10 and Figure 11 As described above, in each of the first pixel regions PR1 to the fourth pixel regions PR4, the first transmission gate electrode TG1 and the second transmission gate electrode TG2 may be disposed on the first active portion ACT1, and each of the first transmission gate electrode TG1 and the second transmission gate electrode TG2 may include a single vertical portion extending into the semiconductor substrate 100.

[0131] In each of the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be respectively disposed on the second active portion ACT2. In the third pixel region PR3, a pixel gate electrode PG (SFG) may be disposed on the second active portion ACT2 and may be configured to intersect with the fin-shaped active pattern FP.

[0132] In the third pixel region PR3, the pixel gate electrode PG (SFG) may be longer than the first pixel gate electrode PG1 and the second pixel gate electrode PG2 in the first direction D1. That is, the pixel gate electrode PG (SFG) may be partially superimposed with the first photoelectric conversion region 110a and the second photoelectric conversion region 110b in the third pixel region PR3.

[0133] In the third pixel region PR3, the fin-shaped active pattern FP can be disposed between the pixel gate electrode PG (SFG) and the second active portion ACT2. In the fourth pixel region PR4, the fin-shaped active pattern FP can be disposed between the first pixel gate electrode PG1 and the second pixel gate electrode PG2 and the second active portion ACT2.

[0134] The fin-shaped active pattern FP in the third pixel region PR3 may be doped with a dopant of the second conductivity type, while the fin-shaped active pattern FP in the fourth pixel region PR4 may not be doped with a dopant of the second conductivity type.

[0135] Optionally, the channel regions of the pixel transistors on the first pixel region PR1 to the fourth pixel region PR4 may not be doped with dopants of the second conductivity type. That is, each pixel transistor on the first pixel region PR1 to the fourth pixel region PR4 may include a channel region of the first conductivity type.

[0136] Figure 12 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept. Figure 13 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 12 A sectional view taken from lines A-A', B-B', and C-C'.

[0137] Reference Figure 12 and Figure 13 All pixel transistors on the first pixel region PR1 to the fourth pixel region PR4 can be planar MOS transistors, and the first pixel gate electrode PG1 and the second pixel gate electrode PG2 of the pixel transistors can be polysilicon containing dopants of a first conductivity type. Therefore, the threshold voltage of the pixel transistors on the first pixel region PR1 to the fourth pixel region PR4 can be increased.

[0138] Additionally, the channel region CH between the first source / drain region SD1 and the second source / drain region SD2 may include a dopant of a second conductivity type. The threshold voltage of each pixel transistor can be adjusted according to the concentration of the dopant of the second conductivity type present in the channel region CH.

[0139] Figure 14 and Figure 15 This is a plan view illustrating a unit pixel of an image sensor according to an embodiment of the inventive concept. Figure 16 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 14 and Figure 15 A cross-sectional view taken along line F-F'. For the sake of brevity, the same elements in the image sensor according to the foregoing embodiments may be identified by the same reference numerals without repeating their overlapping descriptions.

[0140] Reference Figure 14 and Figure 16 The image sensor may include multiple pixel groups (GPXs). Each pixel group (GPX) may include at least four, eight, nine, or sixteen pixel regions PR1 to PR4. Within each pixel group (GPX), pixel regions PR1 to PR4 may be arranged in a matrix shape along a first direction D1 and a second direction D2 that are not parallel to each other. In one embodiment, the first pixel regions PR1 to the fourth pixel regions PR4 may constitute a single pixel group (GPX). In one embodiment, each pixel group (GPX) is shown as including four pixel regions, but the inventive concept is not limited to this example.

[0141] The first photoelectric conversion region 110a to the fourth photoelectric conversion region 110d can be respectively located in the first pixel region PR1 to the fourth pixel region PR4. The first photoelectric conversion region 110a to the fourth photoelectric conversion region 110d can be impurity regions doped with dopants of a second conductivity type.

[0142] The first active portion ACT1 and the second active portion ACT2 can be provided in each of the first pixel regions PR1 to the fourth pixel regions PR4 by shallow trench isolation patterns STI provided in the first surface 100a of the semiconductor substrate 100. The first active portion ACT1 and the second active portion ACT2 can be defined by the shallow trench isolation pattern STI adjacent to the first surface 100a of the semiconductor substrate 100.

[0143] The first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4 may be respectively disposed in the first pixel region PR1 to the fourth pixel region PR4. As described above, each of the first to fourth transfer gate electrodes TG1 to TG4 may have a dual vertical gate structure including two vertical portions extending into the semiconductor substrate 100. As described above, in the first to fourth pixel regions PR1 to PR4, the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4 may be formed of polysilicon doped with a first conductivity type or may include polysilicon doped with a first conductivity type.

[0144] The first floating diffusion region FD1 to the fourth floating diffusion region FD4 can be respectively disposed in the portion of the first active part ACT1 located near the first transmission gate electrode TG1 to the fourth transmission gate electrode TG4. The first floating diffusion region FD1 to the fourth floating diffusion region FD4 can be disposed adjacent to each other and can be disposed in the center of each pixel group GPX.

[0145] In each of the first pixel regions PR1 to the fourth pixel regions PR4, a pixel transistor may be disposed on the second active portion ACT2. The first pixel gate electrodes to the fourth pixel gate electrodes PG1, PG2, PG3, and PG4 may be disposed on the second active portion ACT2 in each of the first pixel regions PR1 to the fourth pixel regions PR4. As described above, the first pixel gate electrodes PG1 to the fourth pixel gate electrodes PG4 may be formed of polysilicon doped with a first conductivity type, or may comprise polysilicon doped with a first conductivity type.

[0146] At least one of the pixel transistors on the first pixel region PR1 to the fourth pixel region PR4 can be a fin transistor. That is, the fin active pattern FP can be disposed between the second active portion ACT2 and the first pixel gate electrode PG1 to the fourth pixel gate electrode PG4. As described above, in one embodiment, some of the pixel transistors on the first pixel region PR1 to the fourth pixel region PR4 can be planar transistors.

[0147] In one embodiment, the pixel transistor may include a channel region between the source and drain regions, and the channel region may contain a dopant of a second conductivity type.

[0148] Reference Figure 15 A common active part ACT can be set on the first pixel region PR1 to the fourth pixel region PR4, and a second active part ACT2 can be set in each of the pixel regions PR1 to PR4.

[0149] In the first pixel region PR1 to the fourth pixel region PR4, the first transmission gate electrode to the fourth transmission gate electrode can be respectively disposed on the common active part ACT.

[0150] In each pixel group GPX, a common floating diffusion region CFD can be disposed in a common active region ACT. In one embodiment, the common floating diffusion region CFD can be disposed together in at least four pixel regions PR1 to PR4. The first portions Pa of the isolation structure PIS can be spaced apart from each other in the first direction D1, and the common floating diffusion region CFD is placed between the first portions Pa of the isolation structure PIS. The second portions Pb can be spaced apart from each other in the second direction D2, and the common floating diffusion region CFD is placed between the second portions Pb. The common floating diffusion region CFD can be disposed in the portion of the semiconductor substrate 100 adjacent to the first transmission gate electrodes TG1 to the fourth transmission gate electrodes TG4.

[0151] The first pixel gate electrode to the fourth pixel gate electrode PG1, PG2, PG3, and PG4 can be respectively disposed on the second active portion ACT2 in the first pixel region PR1 to the fourth pixel region PR4. As described above, in the first pixel region PR1 to the fourth pixel region PR4, the first transfer gate electrode TG1 to the fourth transfer gate electrode TG4 and the first pixel gate electrode PG1 to the fourth pixel gate electrode PG4 can be formed of polysilicon doped with a first conductivity type, or may include polysilicon doped with a first conductivity type.

[0152] Figure 17 This is a plan view illustrating an image sensor according to an embodiment of the inventive concept.

[0153] Reference Figure 17The image sensor may include a first pixel group to a third pixel group GPX1, GPX2, and GPX3 arranged two-dimensionally in a first direction D1 and a second direction D2. In odd-numbered rows, the first pixel group GPX1 and the second pixel group GPX2 may be arranged alternately and repeatedly. In even-numbered rows, the second pixel group GPX2 and the third pixel group GPX3 may be arranged alternately and repeatedly. Each of the first pixel group to the third pixel group GPX1, GPX2, and GPX3 may include a pixel region PR arranged in a 2×2 shape. An isolation structure PIS may be configured to separate the first pixel group to the third pixel group GPX1, GPX2, and GPX3 from each other. When viewed in a planar view, the isolation structure PIS may be inserted into each of the pixel groups GPX1, GPX2, and GPX3 to separate the pixel regions PR from each other. However, the isolation structure PIS may be configured to cut each of the pixel groups GPX1, GPX2, and GPX3 at the center of the pixel groups GPX1, GPX2, and GPX3, and the pixel regions PR in a single pixel group may be connected to each other. The first pixel group GPX1 may be covered by a first color filter CF1. The second pixel group GPX2 may be covered by a second color filter CF2. The third pixel group GPX3 may be covered by a third color filter CF3. The first color filter CF1 may have one of red, green, and blue. The second color filter CF2 may have another of red, green, and blue. The third color filter CF3 may have the remaining one of red, green, and blue. Microlenses ML may be disposed on the first to third color filters CF1, CF2, and CF3. Microlenses ML may be disposed corresponding to and superimposed on pixel regions PR respectively. That is, microlenses ML may be disposed on pixels PX respectively. Microlenses ML arranged in a 2×2 shape may be disposed on each of the pixel groups GPX1, GPX2, and GPX3. The aforementioned arrangement of microlenses ML can enhance the light collection efficiency in each of the pixel regions PR, thereby achieving a clear image.

[0154] Figure 18 This is a schematic plan view of an image sensor according to an embodiment of the inventive concept. Figure 19 and Figure 20 It is used to illustrate the image sensor along an embodiment according to the inventive concept. Figure 18 A sectional view taken by line I-I'.

[0155] Reference Figure 18 and Figure 19 The image sensor may include a sensor chip C1 and a logic chip C2. The sensor chip C1 may include a pixel array region R1 and a pad region R2, and the pixel array region R1 may include a transfer gate electrode TG.

[0156] The pixel array region R1 may include a plurality of unit pixels PX arranged in two dimensions in two different directions (e.g., in a first direction D1 and a second direction D2). Each of the unit pixels PX may include a photoelectric conversion device and a readout device. An electrical signal generated by incident light may be output from each of the unit pixels PX in the pixel array region R1.

[0157] The pixel array region R1 may include a light-receiving region AR and a light-blocking region OB. When viewed in a planar view, the light-blocking region OB may be configured to surround the light-receiving region AR. For example, when viewed in a planar view, the light-blocking region OB may be configured to surround the light-receiving region AR in four different directions (e.g., up, down, left, and right). In one embodiment, a reference pixel to which light is not incident may be provided in the light-blocking region OB, and in this case, the magnitude of the electrical signal sensed from the unit pixel PX can be calculated by comparing the amount of charge obtained by sensing the unit pixel PX in the light-receiving region AR with the amount of reference charge generated in the reference pixel.

[0158] Multiple conductive pads CP for inputting or outputting control signals and photoelectric signals can be disposed in pad region R2. When viewed in a planar view, pad region R2 can be configured to surround pixel array region R1, and in this case, the image sensor can be easily connected to an external device. The conductive pads CP can be used to output electrical signals generated in a unit pixel PX to an external device or to input electrical signals from an external device.

[0159] In the light-receiving region AR, the sensor chip C1 may have the same technical features as the image sensor described above. As described above, the sensor chip C1 may include a photoelectric conversion circuit layer 10 disposed vertically between the pixel circuit layer 20 and the light-transparent layer 30. As described above, the photoelectric conversion circuit layer 10 of the sensor chip C1 may include a semiconductor substrate 100, an isolation structure PIS defining the pixel region, and a photoelectric conversion region 110 disposed in the pixel region. The isolation structure PIS may have substantially the same structure in both the light-receiving region AR and the light-blocking region OB. The isolation structure PIS may be disposed in the semiconductor substrate 100 in the light-blocking region OB. The gap-filling pattern 113 of the isolation structure PIS may be electrically connected to the back-side contact plug PLG in the light-blocking region OB. The gap-filling pattern 113 may be subjected to a specific bias through the back-side contact plug PLG. The back-side contact plug PLG may have a width larger than the width of the isolation structure PIS. The back-side contact plug PLG may be formed of at least one of a metallic material and / or a metal nitride material, or may include at least one of a metallic material and / or a metal nitride material. For example, the back-side contact plug PLG may be formed of titanium and / or titanium nitride, or may include titanium and / or titanium nitride.

[0160] The contact pattern CT can be embedded in a contact hole having a back-side contact plug PLG. The contact pattern CT and the back-side contact plug PLG may be made of different materials. For example, the contact pattern CT may be formed of aluminum (Al) or may include aluminum (Al).

[0161] The contact pattern CT and the back contact plug PLG are electrically connected to the gap-filling pattern 113 of the isolation structure PIS. A positive bias voltage can be applied to the gap-filling pattern 113 of the isolation structure PIS through the contact pattern CT, and the positive bias voltage can be transmitted from the light-blocking region OB to the light-receiving region AR. In this case, the dark current generated at the interface between the isolation structure PIS and the semiconductor substrate 100 can be reduced.

[0162] In the light-blocking region OB, the light-transparent layer 30 may include a light-blocking pattern OBP, a filter layer 335, and an organic layer 345. In one embodiment, the isolation structure PIS may extend continuously from the light-receiving region AR to the light-blocking region OB.

[0163] In the light-blocking region OB, a light-blocking pattern OBP may be disposed on the top surface of the planarized insulating layer 310. The light-blocking pattern OBP may be formed of the same material as the conductive pattern of the grid 320 in the light-receiving region AR, or may include the same material as the conductive pattern of the grid 320 in the light-receiving region AR. That is, the light-blocking pattern OBP may include metal patterns and metal oxide patterns. The light-blocking pattern OBP may be formed of, for example, at least one of titanium nitride and titanium oxynitride, or may include, for example, at least one of titanium nitride and titanium oxynitride. The light-blocking pattern OBP may not extend into the light-receiving region AR.

[0164] A light-blocking pattern (OBP) can limit and / or prevent light from incident on the photoelectric conversion region 110 disposed in the light-blocking region OB. The photoelectric conversion region 110 in the reference pixel region of the light-blocking region OB can be configured to output a noise signal instead of a photoelectric signal. The noise signal can be generated by electrons generated via heat or dark current.

[0165] The filter layer 335 may cover the light-blocking pattern OBP in the light-blocking region OB. The filter layer 335 may be configured to block light with a wavelength different from that of the color filter 330. For example, the filter layer 335 may be configured to block infrared light. The filter layer 335 may include a blue color filter, but the inventive concept is not limited to this example.

[0166] The organic layer 345 and the passivation layer can be disposed on the filter layer 335 in the light-blocking region OB and the pad region R2. The organic layer 345 can be made of the same material as the microlens 340.

[0167] In the light-blocking region OB, a first penetrating conductive pattern 511 may be configured to penetrate the semiconductor substrate 100 and electrically connect the metal lines of the pixel circuit layer 20 to the interconnect structure 1111 of the logic chip C2. The first penetrating conductive pattern 511 may have a first bottom surface and a second bottom surface located at different heights. A first gap-filling pattern 521 may be disposed within the first penetrating conductive pattern 511. The first gap-filling pattern 521 may be formed of or may include a low-refractive-index material, and may exhibit insulating properties.

[0168] In pad region R2, a conductive pad CP may be disposed on the second surface 100b of the semiconductor substrate 100. The conductive pad CP may be embedded in a portion of the semiconductor substrate 100 located near the second surface 100b. In one embodiment, the conductive pad CP may be disposed in a pad trench formed in the second surface 100b of the semiconductor substrate 100 and located in the pad region R2. The conductive pad CP may be formed of at least one of metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, and alloys thereof), or may include at least one of metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, and alloys thereof). In the image sensor mounting process, bonding wires may be bonded to the conductive pad CP. The conductive pad CP may be electrically connected to an external device via bonding wires.

[0169] In pad region R2, a second penetrating conductive pattern 520 may be configured to penetrate the semiconductor substrate 100 and be electrically connected to the interconnect structure 1111 of the logic chip C2. The second penetrating conductive pattern 520 may extend to a region on the second surface 100b of the semiconductor substrate 100 and be electrically connected to the conductive pad CP. A portion of the second penetrating conductive pattern 520 may cover the bottom and side surfaces of the conductive pad CP. A second gap-filling pattern 510 may be disposed within the second penetrating conductive pattern 520. The second gap-filling pattern 510 may comprise a low-refractive-index material and may have insulating properties. In pad region R2, an isolation structure PIS may be disposed around the second penetrating conductive pattern 520.

[0170] The logic chip C2 may include a logic semiconductor substrate 1000, a logic circuit TR, an interconnect structure 1111 connected to the logic circuit TR, and an interlayer insulating layer 1100. The uppermost layer of the interlayer insulating layer 1100 may be bonded to the pixel circuit layer 20 of the sensor chip C1. The logic chip C2 may be electrically connected to the sensor chip C1 through a first through-conductive pattern 511 and a second through-conductive pattern 520.

[0171] In one embodiment, sensor chip C1 and logic chip C2 are shown to be electrically connected to each other via a first through conductive pattern 511 and a second through conductive pattern 520, but the inventive concept is not limited to this example.

[0172] exist Figure 20In this embodiment, the first and second penetrating conductive patterns can be omitted, and since the bonding pads disposed in the uppermost metal layers of the sensor chip C1 and the logic chip C2 are directly bonded to each other, the sensor chip C1 and the logic chip C2 can be electrically connected to each other.

[0173] In the sensor chip C1, the gap-filling pattern 113 of the isolation structure PIS extending from the light-receiving region AR to the light-blocking region OB can be connected to the back-side contact plug PLG in the light-blocking region OB.

[0174] Furthermore, the sensor chip C1 may include a first bonding pad BP1 disposed in the uppermost metal layer of the pixel circuit layer 20, and the logic chip C2 may include a second bonding pad BP2 disposed in the uppermost metal layer of the logic chip C2. The first bonding pad BP1 and the second bonding pad BP2 may be formed of at least one of, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN), or may include at least one of, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0175] The first bonding pad BP1 of sensor chip C1 and the second bonding pad BP2 of logic chip C2 can be electrically and directly connected to each other using a hybrid bonding method. Here, a hybrid bonding method can refer to a method of bonding two materials of the same kind at the interface between them (e.g., through a fusion process). For example, if the first bonding pad BP1 and the second bonding pad BP2 are formed of copper (Cu), they can be physically and electrically connected to each other using a Cu-Cu bonding method. Additionally, the insulating layers of sensor chip C1 and logic chip C2 can be bonded to each other using a dielectric-dielectric bonding method.

[0176] According to embodiments of the inventive concept, since the pixel gate electrode of the pixel transistor constituting a unit pixel contains a dopant of a first conductivity type, the threshold voltage of the pixel transistor can be increased. Even with miniaturization of the unit pixel, the threshold voltage of the pixel transistor can still be ensured. Furthermore, the linearity of the output characteristics of the source follower transistor can be improved under low-light conditions. Additionally, the leakage current characteristics of the source follower transistor can be improved.

[0177] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: Semiconductor substrate of the first conductivity type; An isolation structure, in a semiconductor substrate, defines multiple pixel regions; Shallow trench isolation pattern, in a semiconductor substrate, the shallow trench isolation pattern defines an active portion in each of the plurality of pixel regions; A transfer gate electrode, in each of the plurality of pixel regions, is located between the photoelectric conversion region and the floating diffusion region; as well as Multiple pixel transistors, respectively, in the multiple pixel regions, Each of the plurality of pixel transistors includes: Pixel gate electrode, on the active part, and Multiple source / drain regions are located in the active portion on both sides of the pixel gate electrode. Wherein, the transfer gate electrodes on the plurality of pixel regions and the pixel gate electrodes of the plurality of pixel transistors include dopants of a first conductivity type, and The plurality of source / drain regions include dopants of a second conductivity type.

2. The image sensor according to claim 1, wherein, At least one of the plurality of pixel transistors includes a channel region between the plurality of source / drain regions, and The channel region includes dopants of the second conductivity type.

3. The image sensor according to claim 1, wherein, The first pixel transistor of the plurality of pixel transistors also includes a fin-shaped active pattern between the active portion and the pixel gate electrode.

4. The image sensor according to claim 3, wherein, The fin-shaped active pattern includes a dopant of a first conductivity type or a dopant of a second conductivity type.

5. The image sensor according to claim 3, wherein, The top surface of the fin-shaped active pattern is coplanar with the first surface of the semiconductor substrate.

6. The image sensor according to claim 3, wherein, The vertical portion of the transfer gate electrode penetrates a portion of the semiconductor substrate. The vertical portion of the transfer gate electrode has a first bottom surface, which is located at a height lower than the height of the first surface of the semiconductor substrate. The pixel gate electrode of the first pixel transistor has a second bottom surface, and the second bottom surface is located at a height between the first surface and the first bottom surface of the semiconductor substrate.

7. The image sensor according to claim 1, wherein, The first pixel transistor and the second pixel transistor are among the plurality of pixel transistors, and the first pixel transistor further includes a fin-shaped active pattern between the active portion and the pixel gate electrode. The pixel gate electrode of the first pixel transistor intersects with the fin-shaped active pattern, and The bottom surface of the pixel gate electrode of the second pixel transistor is parallel to the first surface of the semiconductor substrate.

8. The image sensor according to claim 1, wherein, The vertical portion of the transfer gate electrode penetrates a portion of the semiconductor substrate vertically.

9. The image sensor according to claim 8, wherein, The vertical portion of the transfer gate electrode has a first bottom surface, which is located at a height lower than the height of the first surface of the semiconductor substrate. The pixel gate electrode has a second bottom surface, and the second bottom surface is located at a height between the first surface and the first bottom surface of the semiconductor substrate.

10. The image sensor according to claim 1, wherein, The transfer gate electrode includes a first vertical gate and a second vertical gate, and The first vertical gate and the second vertical gate extend into the semiconductor substrate.

11. The image sensor according to claim 1, wherein, In each of the plurality of pixel regions, the photoelectric conversion region includes a first photoelectric conversion region and a second photoelectric conversion region. In each of the plurality of pixel regions, the floating diffusion region includes a first floating diffusion region and a second floating diffusion region, and In each of the plurality of pixel regions, the transmission gate electrode includes a first transmission gate electrode between a first photoelectric conversion region and a first floating diffusion region, and a second transmission gate electrode between a second photoelectric conversion region and a second floating diffusion region.

12. The image sensor according to claim 11, wherein, The pixel gate electrodes of the plurality of pixel transistors include a first pixel gate electrode and a second pixel gate electrode that are respectively superimposed on the first photoelectric conversion region and the second photoelectric conversion region.

13. An image sensor, comprising: Semiconductor substrate of the first conductivity type; An isolation structure, in a semiconductor substrate, defines multiple pixel regions; Shallow trench isolation pattern, in a semiconductor substrate, the shallow trench isolation pattern defines an active portion in each of the plurality of pixel regions to provide an active portion in the plurality of pixel regions respectively; The photoelectric conversion region, in each of the plurality of pixel regions and in the semiconductor substrate, includes a dopant of a second conductivity type; A floating diffusion region, in each of the plurality of pixel regions and in the semiconductor substrate, is spaced apart from the photoelectric conversion region; A transfer gate electrode, in each of the plurality of pixel regions, is located between the photoelectric conversion region and the floating diffusion region; The source follower gate electrode is on the first active portion, which is one of the active portions in the plurality of pixel regions; A first fin-shaped active pattern is located between the first active portion and the gate electrode of the source follower; and Multiple first source / drain regions are located in the first active portion on both sides of the gate electrode of the source follower. The transport gate electrode and the source follower gate electrode include dopants of the first conductivity type.

14. The image sensor according to claim 13, wherein, The plurality of first source / drain regions include dopants of a second conductivity type.

15. The image sensor according to claim 13, wherein, The bottom surface of the transfer gate electrode and the bottom surface of the source follower gate electrode are at a height lower than the height of the first surface of the semiconductor substrate.

16. The image sensor according to claim 13, wherein, The first fin-shaped active pattern includes a first channel region between the plurality of first source / drain regions, and The first channel region includes dopants of the second conductivity type.

17. The image sensor of claim 13, further comprising: A pixel gate electrode is located on the second active portion among the active portions in the plurality of pixel regions. as well as Multiple second source / drain regions are located in the second active portion on both sides of the pixel gate electrode. The pixel gate electrode includes a dopant of a first conductivity type.

18. The image sensor of claim 17, further comprising: The second fin-shaped active pattern is located between the second active portion and the pixel gate electrode. The bottom surface of the pixel gate electrode is coplanar with the bottom surface of the source follower gate electrode.

19. An image sensor, comprising: A semiconductor substrate of a first conductivity type, wherein a first surface of the semiconductor substrate is opposite to a second surface of the semiconductor substrate; An isolation structure is provided in a semiconductor substrate, defining a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region in the semiconductor substrate. Each of the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region includes: a first photoelectric conversion region, a second photoelectric conversion region, a third photoelectric conversion region, and a fourth photoelectric conversion region, as well as a first floating diffusion region, a second floating diffusion region, a third floating diffusion region, and a fourth floating diffusion region, which are respectively spaced apart from the first photoelectric conversion region, the second photoelectric conversion region, the third photoelectric conversion region, and the fourth photoelectric conversion region in the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region. A plurality of transfer gate electrodes, each having a bottom surface at a height between a first surface of a semiconductor substrate and a second surface of a semiconductor substrate, the plurality of transfer gate electrodes including: a first transfer gate electrode between a first photoelectric conversion region and a first floating diffusion region, a second transfer gate electrode between a second photoelectric conversion region and a second floating diffusion region, a third transfer gate electrode between a third photoelectric conversion region and a third floating diffusion region, and a fourth transfer gate electrode between a fourth photoelectric conversion region and a fourth floating diffusion region; A shallow trench isolation pattern is adjacent to a first surface of a semiconductor substrate. The shallow trench isolation pattern defines an active portion in each of a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region, so as to provide an active portion in the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region, respectively. Multiple pixel transistors are respectively located on the active portions in the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region; Multiple color filters are located on the second surface of a semiconductor substrate, and the multiple color filters correspond to a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region, respectively. A grid, stacked with an isolation structure between the plurality of color filters; and Multiple microlenses on the multiple color filters, Each of the plurality of pixel transistors includes a fin-shaped active pattern, a pixel gate electrode intersecting the fin-shaped active pattern, and source / drain regions located on both sides of the pixel gate electrode in the active portion. In each of the plurality of pixel transistors, a fin-shaped active pattern protrudes from the active portion in each of the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region. The pixel gate electrode, first transport gate electrode, second transport gate electrode, third transport gate electrode, and fourth transport gate electrode of the plurality of pixel transistors include dopants of a first conductivity type, and The source / drain regions of the plurality of pixel transistors include dopants of a second conductivity type.

20. The image sensor according to claim 19, wherein, At least one of the plurality of pixel transistors includes a channel region between the source and drain regions in a finned active pattern, and The channel region includes dopants of the second conductivity type.

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