MIM capacitor and preparation method thereof

Abstract

The invention provides an MIM capacitor and a preparation method thereof, in the preparation method, after a lower pole plate material layer is formed and before an intermediate dielectric layer is formed, a chemical mechanical grinding process is adopted to grind and remove a part of thickness of the lower pole plate material layer so as to flatten the surface of the lower pole plate material layer; therefore, the flatness of the whole MIM capacitor is improved, the breakdown voltage of the MIM capacitor is improved, the leakage current of the device is reduced, and the TDDB failure time (service life) of the device is prolonged.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a MIM capacitor and its fabrication method. Background Technology

[0002] With the development of large-scale integrated circuits, chip area and feature size are constantly decreasing. The metal interconnect resistance and insulating layer capacitance inside the device are prone to crosstalk, and there are obstacles to development in terms of power consumption and delay. As a result, the time-dependent dielectric breakdown (TDDB) problem has gradually become one of the most serious reliability problems.

[0003] In MIM (Metal-Insulator-Metal) capacitors, high dielectric constant MIM capacitors have attracted widespread attention due to their large capacitance per unit area and small footprint. However, existing high dielectric constant MIM capacitors suffer from problems such as large leakage current, low breakdown voltage, and shortened TDDB (time to breakdown) failure (lifetime), thus limiting their wider application. Summary of the Invention

[0004] This application provides a MIM capacitor and its fabrication method, which can solve the problems of high dielectric constant MIM capacitors, such as large leakage current, low breakdown voltage, and shortened TDDB failure time (life).

[0005] On one hand, embodiments of this application provide a method for fabricating a MIM capacitor, comprising: A substrate is provided on which a pad oxide layer is formed; A lower electrode material layer is formed, the lower electrode material layer covering the gasket oxide layer; A portion of the thickness of the lower electrode material layer is removed by chemical mechanical polishing to flatten the surface of the lower electrode material layer. An intermediate dielectric layer is formed, which covers the remaining thickness of the lower electrode material layer; An upper electrode material layer is formed, which covers the intermediate dielectric layer; A first hard mask layer is formed, which covers the upper electrode material layer; The etching process involves partially etching the first hard mask layer and part of the upper electrode material layer, stopping at the surface of the intermediate dielectric layer. A second hard mask layer is formed, which covers the remaining first hard mask layer, the remaining side surface of the upper electrode material layer, and the intermediate dielectric layer. Etch a portion of the second hard mask layer, a portion of the intermediate dielectric layer, and a portion of the lower electrode material layer on the side of the upper electrode material layer and stop at the surface of the pad oxide layer; An interlayer dielectric layer is formed, which covers the remaining second hard mask layer, the remaining side surface of the intermediate dielectric layer, the remaining side surface of the lower electrode material layer, and the pad oxide layer.

[0006] Optionally, in the method for preparing the MIM capacitor, the lower electrode material layer is formed using an ALD process.

[0007] Optionally, in the method for preparing the MIM capacitor, during the process of removing a portion of the thickness of the lower electrode material layer by chemical mechanical polishing, the thickness of the lower electrode material layer removed by polishing is 50 angstroms to 150 angstroms.

[0008] Optionally, in the method for preparing the MIM capacitor, the thickness of the lower electrode material layer is 450 angstroms to 750 angstroms before the lower electrode material layer, which has a portion of its thickness, is removed by chemical mechanical polishing.

[0009] Optionally, in the method for preparing the MIM capacitor, the upper electrode material layer is formed using an ALD process.

[0010] Optionally, in the method for fabricating the MIM capacitor, the thickness of the upper electrode material layer is 400 angstroms to 600 angstroms.

[0011] Optionally, in the method for preparing the MIM capacitor, the material of the lower electrode layer is titanium nitride; the material of the intermediate dielectric layer is Al2O3; and the material of the upper electrode layer is titanium nitride.

[0012] Optionally, in the method for fabricating the MIM capacitor, the thickness of the pad oxide layer is 1000 angstroms to 10000 angstroms.

[0013] Optionally, in the method for fabricating the MIM capacitor, after forming the interlayer dielectric layer, the method further includes: A first conductive plug and a second conductive plug are formed. The first conductive plug penetrates the interlayer dielectric layer, the second hard mask layer and the first hard mask layer and is in contact with the upper electrode material layer. The second conductive plug penetrates the interlayer dielectric layer, the second hard mask layer and the intermediate dielectric layer and is in contact with the lower electrode material layer.

[0014] On the other hand, embodiments of this application also provide a MIM capacitor, including: A substrate on which a pad oxide layer is formed; A lower electrode material layer, wherein the lower electrode material layer covers a portion of the surface of the gasket oxide layer; An intermediate dielectric layer covers the lower electrode material layer, wherein, prior to the formation of the intermediate dielectric layer, a portion of the thickness of the lower electrode material layer is removed by a chemical mechanical polishing process to planarize the surface of the lower electrode material layer; An upper electrode material layer, wherein the upper electrode material layer covers a portion of the surface of the intermediate dielectric layer; A first hard mask layer covers the upper electrode material layer; A second hard mask layer covers the first hard mask layer, the side surface of the upper electrode material layer, and the intermediate dielectric layer. An interlayer dielectric layer covers the second hard mask layer, the side surface of the intermediate dielectric layer, the side surface of the lower electrode material layer, and the pad oxide layer.

[0015] The technical solution of this application has at least the following advantages: This application provides a MIM capacitor and its fabrication method. In the fabrication method, after forming the lower electrode material layer and before forming the intermediate dielectric layer, a portion of the thickness of the lower electrode material layer is removed by chemical mechanical polishing to flatten the surface of the lower electrode material layer, thereby improving the flatness of the entire MIM capacitor, which in turn improves the breakdown voltage of the MIM capacitor, reduces the leakage current of the device, and improves the TDDB failure time (lifetime) of the device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a method for preparing a MIM capacitor according to an embodiment of the present invention; Figures 2-10 This is a schematic diagram of the semiconductor structure in each process step of the fabrication of the MIM capacitor according to an embodiment of the present invention; The reference numerals in the attached figures are explained as follows: 10-Substrate, 20-Pad oxide layer, 30-Lower electrode material layer, 31-Remaining thickness of lower electrode material layer, 40-Intermediate dielectric layer, 50-Upper electrode material layer, 61-First hard mask layer, 62-Second hard mask layer, 70-Interlayer dielectric layer, 81-First conductive plug, 82-Second conductive plug. Detailed Implementation

[0018] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0022] The inventors discovered that the surface roughness of the metal lower plate of the MIM capacitor is too poor. Such local roughness will affect the overall flatness of the capacitor, resulting in increased leakage current and making the capacitor more susceptible to high voltage breakdown. This seriously affects the capacitor's TDDB. For large capacitors (thinner dielectric layer), the impact of the rough surface of the metal lower plate is even more serious, making high voltage breakdown more likely.

[0023] To address the aforementioned problems, this application provides a method for fabricating a MIM capacitor, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a MIM capacitor according to an embodiment of the present invention. The method for fabricating a MIM capacitor includes: First, perform step S1: Refer to Figure 2 , Figure 2This is a schematic diagram of the semiconductor structure after the formation of the lower electrode material layer according to an embodiment of the present invention. A substrate 10 is provided, on which a pad oxide layer 20 is formed.

[0024] Preferably, the thickness of the liner oxide layer 20 is 1000 angstroms to 10000 angstroms.

[0025] Then, proceed to step S2: Continue to refer to Figure 2 A lower electrode material layer 30 is formed, which covers the gasket oxide layer 20.

[0026] Preferably, the lower electrode material layer 30 is formed using an ALD (atomic layer deposition) process.

[0027] In this embodiment, the material of the lower electrode material layer 30 is titanium nitride.

[0028] Next, proceed to step S3: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after a portion of the thickness of the lower electrode material layer has been removed by grinding, according to an embodiment of the present invention. A chemical mechanical polishing process is used to grind and remove a portion of the thickness of the lower electrode material layer 30 in order to planarize the surface of the lower electrode material layer 30.

[0029] Preferably, the thickness of the lower electrode material layer 30 is 450 angstroms to 750 angstroms before the lower electrode material layer, which has a portion of its thickness, is removed by chemical mechanical polishing.

[0030] Preferably, during the process of removing a portion of the thickness of the lower electrode material layer using a chemical mechanical polishing process, the thickness of the lower electrode material layer removed by polishing is 50 angstroms to 150 angstroms.

[0031] Further, proceed to step S4: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the intermediate dielectric layer according to an embodiment of the present invention. The intermediate dielectric layer 40 is formed, and the intermediate dielectric layer 40 covers the remaining thickness of the lower electrode material layer 31.

[0032] In this embodiment, the intermediate dielectric layer 40 is made of Al2O3.

[0033] Preferably, the thickness of the intermediate dielectric layer 40 is 50 angstroms to 500 angstroms.

[0034] Preferably, the intermediate dielectric layer 40 can be formed by processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0035] Next, proceed to step S5: (Refer to...) Figure 5 , Figure 5This is a schematic diagram of the semiconductor structure after the formation of the upper electrode material layer according to an embodiment of the present invention. The upper electrode material layer 50 is formed, and the upper electrode material layer 50 covers the intermediate dielectric layer 40.

[0036] Preferably, the upper electrode material layer 50 is formed using an ALD (atomic layer deposition) process.

[0037] Preferably, the thickness of the upper electrode material layer 50 is 400 angstroms to 600 angstroms.

[0038] Preferably, the upper electrode material layer 50 is made of titanium nitride.

[0039] Further, proceed to step S6: Refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the first hard mask layer according to an embodiment of the present invention. The first hard mask layer 61 is formed and covers the upper electrode material layer 50.

[0040] Preferably, the first hard mask layer 61 is made of silicon nitride or silicon dioxide.

[0041] Preferably, the first hard mask layer 61 is formed using a CVD (chemical vapor deposition) process.

[0042] Next, proceed to step S7: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after etching a portion of the first hard mask layer and a portion of the upper electrode material layer according to an embodiment of the present invention. The etching of a portion of the first hard mask layer 61 and a portion of the upper electrode material layer 50 stops on the surface of the intermediate dielectric layer 40.

[0043] Preferably, a dry etching process is used to etch part of the first hard mask layer 61 and part of the upper electrode material layer 50 and stop at the surface of the intermediate dielectric layer 40.

[0044] Further, proceed to step S8: (Refer to...) Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after the formation of the second hard mask layer according to an embodiment of the present invention. The second hard mask layer 62 is formed, which covers the remaining first hard mask layer 61, the remaining side surface of the upper electrode material layer 50, and the intermediate dielectric layer 40.

[0045] Preferably, the material of the second hard mask layer 62 is silicon nitride or silicon dioxide.

[0046] Preferably, the second hard mask layer 62 is formed using a CVD (chemical vapor deposition) process.

[0047] Next, proceed to step S9: (Refer to...)Figure 9 , Figure 9 This is a schematic diagram of a semiconductor structure after etching a portion of the second hard mask layer, a portion of the intermediate dielectric layer, and a portion of the lower electrode material layer on the side of the upper electrode material layer 50. The etching of a portion of the second hard mask layer 62, a portion of the intermediate dielectric layer 40, and a portion of the remaining thickness of the lower electrode material layer 31 on the side of the upper electrode material layer 50 stops on the surface of the pad oxide layer 20.

[0048] Preferably, a dry etching process is used to etch a portion of the second hard mask layer 62, a portion of the intermediate dielectric layer 40, and a portion of the remaining thickness of the lower electrode material layer 31 on the side of the upper electrode material layer 50, and stops at the surface of the pad oxide layer 20.

[0049] Finally, proceed to step S10: (Refer to...) Figure 10 , Figure 10 This is a schematic diagram of the semiconductor structure after the formation of the first conductive plug and the second conductive plug according to an embodiment of the present invention. An interlayer dielectric layer 70 is formed, which covers the remaining second hard mask layer 62, the remaining side surface of the intermediate dielectric layer 40, the remaining side surface of the lower electrode material layer 30, and the pad oxide layer 20.

[0050] In this embodiment, the interlayer dielectric layer 70 is made of silicon dioxide.

[0051] For better options, please continue to refer to them. Figure 10 After forming the interlayer dielectric layer 70, the method for fabricating the MIM capacitor may further include: forming a first conductive plug 81 and a second conductive plug 82, wherein the first conductive plug 81 penetrates the interlayer dielectric layer 70, the second hard mask layer 62 and the first hard mask layer 61 and contacts the upper electrode material layer 50, and the second conductive plug 82 penetrates the interlayer dielectric layer 70, the second hard mask layer 62 and the intermediate dielectric layer 40 and contacts the remaining thickness of the lower electrode material layer 31.

[0052] Furthermore, after forming the first conductive plug 81 and the second conductive plug 82, the method for fabricating the MIM capacitor may further include: forming at least two independent metal interconnects, wherein one metal interconnect covers the first conductive plug 81 to electrically lead the upper electrode material layer 50 to the chip surface; and the other metal interconnect covers the second conductive plug 82 to electrically lead the lower electrode material layer 31 to the chip surface, thereby constituting the final MIM capacitor.

[0053] In this application, after the formation of the lower electrode material layer and before the formation of the intermediate dielectric layer, a chemical mechanical polishing process is used to grind away part of the thickness of the lower electrode material layer to flatten the surface of the lower electrode material layer, thereby improving the flatness of the entire MIM capacitor, thereby increasing the breakdown voltage of the MIM capacitor, reducing the leakage current of the device, and improving the TDDB failure time (lifetime) of the device.

[0054] Based on the same inventive concept, this application also provides a MIM capacitor, see reference. Figure 10 The MIM capacitor includes: Substrate 10, on which a pad oxide layer 20 is formed; Lower electrode material layer 30, which covers a portion of the surface of the gasket oxide layer 20; An intermediate dielectric layer 40 covers the lower electrode material layer 30. Before forming the intermediate dielectric layer 40, a portion of the thickness of the lower electrode material layer 30 is removed by a chemical mechanical polishing process to planarize the surface of the lower electrode material layer 30. Upper electrode material layer 50, which covers a portion of the surface of the intermediate dielectric layer 40; A first hard mask layer 61 covers the upper electrode material layer 50. The second hard mask layer 62 covers the first hard mask layer 61, the side surface of the upper electrode material layer 50, and the intermediate dielectric layer 40. Interlayer dielectric layer 70 covers the second hard mask layer 62, the side surface of the intermediate dielectric layer 40, the side surface of the lower electrode material layer 30, and the pad oxide layer 20.

[0055] Furthermore, the MIM capacitor also includes: a first conductive plug 81 and a second conductive plug 82, wherein the first conductive plug 81 penetrates the interlayer dielectric layer 70, the second hard mask layer 62 and the first hard mask layer 61 and contacts the upper electrode material layer 50, and the second conductive plug 82 penetrates the interlayer dielectric layer 70, the second hard mask layer 62 and the intermediate dielectric layer 40 and contacts the remaining thickness of the lower electrode material layer 31.

[0056] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a MIM capacitor, characterized in that, include: A substrate is provided on which a pad oxide layer is formed; A lower electrode material layer is formed, the lower electrode material layer covering the gasket oxide layer; A portion of the thickness of the lower electrode material layer is removed by chemical mechanical polishing to flatten the surface of the lower electrode material layer. An intermediate dielectric layer is formed, which covers the remaining thickness of the lower electrode material layer; An upper electrode material layer is formed, which covers the intermediate dielectric layer; A first hard mask layer is formed, which covers the upper electrode material layer; The etching process involves partially etching the first hard mask layer and part of the upper electrode material layer, stopping at the surface of the intermediate dielectric layer. A second hard mask layer is formed, which covers the remaining first hard mask layer, the remaining side surface of the upper electrode material layer, and the intermediate dielectric layer. Etch a portion of the second hard mask layer, a portion of the intermediate dielectric layer, and a portion of the lower electrode material layer on the side of the upper electrode material layer and stop at the surface of the pad oxide layer; An interlayer dielectric layer is formed, which covers the remaining second hard mask layer, the remaining side surface of the intermediate dielectric layer, the remaining side surface of the lower electrode material layer, and the pad oxide layer.

2. The method for preparing a MIM capacitor according to claim 1, characterized in that, The lower electrode material layer is formed using the ALD process.

3. The method for preparing a MIM capacitor according to claim 1, characterized in that, During the process of removing a portion of the lower electrode material layer using a chemical mechanical polishing process, the thickness of the lower electrode material layer removed is 50 angstroms to 150 angstroms.

4. The method for preparing a MIM capacitor according to claim 1, characterized in that, The thickness of the lower electrode material layer is 450 angstroms to 750 angstroms before it is ground away by a chemical mechanical polishing process to remove part of its thickness.

5. The method for preparing a MIM capacitor according to claim 1, characterized in that, The upper electrode material layer is formed using the ALD process.

6. The method for preparing a MIM capacitor according to claim 1, characterized in that, The thickness of the upper electrode material layer is 400 angstroms to 600 angstroms.

7. The method for preparing a MIM capacitor according to claim 1, characterized in that, The lower electrode material layer is made of titanium nitride; the middle dielectric layer is made of Al2O3; and the upper electrode material layer is made of titanium nitride.

8. The method for preparing a MIM capacitor according to claim 1, characterized in that, The thickness of the oxide layer on the liner is 1000 angstroms to 10000 angstroms.

9. The method for preparing a MIM capacitor according to claim 1, characterized in that, After forming the interlayer dielectric layer, the method for fabricating the MIM capacitor further includes: A first conductive plug and a second conductive plug are formed. The first conductive plug penetrates the interlayer dielectric layer, the second hard mask layer and the first hard mask layer and is in contact with the upper electrode material layer. The second conductive plug penetrates the interlayer dielectric layer, the second hard mask layer and the intermediate dielectric layer and is in contact with the lower electrode material layer.

10. A MIM capacitor, characterized in that, include: A substrate on which a pad oxide layer is formed; A lower electrode material layer, wherein the lower electrode material layer covers a portion of the surface of the gasket oxide layer; An intermediate dielectric layer covers the lower electrode material layer, wherein, prior to the formation of the intermediate dielectric layer, a portion of the thickness of the lower electrode material layer is removed by a chemical mechanical polishing process to planarize the surface of the lower electrode material layer; An upper electrode material layer, wherein the upper electrode material layer covers a portion of the surface of the intermediate dielectric layer; A first hard mask layer covers the upper electrode material layer; A second hard mask layer covers the first hard mask layer, the side surface of the upper electrode material layer, and the intermediate dielectric layer. An interlayer dielectric layer covers the second hard mask layer, the side surface of the intermediate dielectric layer, the side surface of the lower electrode material layer, and the pad oxide layer.

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