Circuit design-process co-optimization method, preparation method and circuit

Abstract

The application provides a kind of edge contact two-dimensional transistor-based circuit design-process collaborative optimization method, preparation method and circuit, by using edge contact process to significantly improve the load linearity of two-dimensional transistor, output resistance and switching stability, and optimize transistor geometric parameters according to the performance requirements of analog circuit.The method specifically includes: the optimization design of edge contact transistor, the characterization and improvement method of load performance, and its system integration and application in high-performance analog circuit module.The application provides a complete solution from transistor-level process optimization to circuit-level performance improvement, and provides a key technical path for the design and manufacture of high linearity, high stability analog and mixed signal integrated circuits based on new two-dimensional semiconductors.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device and integrated circuit design technology, and in particular to a circuit design-process co-optimization method, fabrication method and circuit based on edge-contact two-dimensional transistors. Background Technology

[0002] With the rapid development of the Internet of Things (IoT), wearable devices, and intelligent sensing systems, the demand for low-power, high-linearity, and high-stability analog front-end circuits is becoming increasingly urgent. While traditional silicon-based complementary metal-oxide-semiconductor (CMOS) technology dominates in digital circuits, it is often limited in analog circuits for these applications by challenges related to power consumption, bulk effects, and compatibility with flexible and heterogeneous integration. In recent years, two-dimensional transition metal chalcogenide (TMC) semiconductor materials (such as MoS2 and WS2) have become ideal candidate materials for building next-generation high-performance, low-power analog integrated circuits due to their atomic-level thickness, dangling-bond-free surfaces, excellent electrostatic control capabilities, and potential for compatibility with back-end processes.

[0003] However, successfully applying two-dimensional semiconductor materials to analog circuits still faces significant challenges. Analog circuits are extremely sensitive to transistor performance parameters such as transconductance linearity, output resistance, noise, and stability. Among these, the metal-semiconductor contact resistance and the quality of the contact interface are key factors affecting the performance of two-dimensional transistors, especially their driving capability and linearity. Traditional top-contact structures form a Schottky barrier on the surface of two-dimensional materials, often resulting in large contact resistance and non-ideal transmission characteristics, limiting their application in processing circuits requiring high-precision analog signals.

[0004] Therefore, how to successfully apply two-dimensional semiconductor materials to analog circuits, so as to give full play to the advantages of two-dimensional semiconductor materials in analog circuits, has become one of the problems that urgently need to be solved by those skilled in the art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a circuit design-process co-optimization method, fabrication method and circuit based on edge-contact two-dimensional transistors, to solve the problem that two-dimensional semiconductor materials cannot be maturely applied in analog circuits in the prior art.

[0007] To achieve the above and other related objectives, this invention provides a circuit design-process co-optimization method based on edge-contact two-dimensional transistors, wherein the circuit design-process co-optimization method based on edge-contact two-dimensional transistors includes at least:

[0008] The circuit containing the edge-contact two-dimensional transistor is co-optimized at both the process and design levels. After co-optimization, the device size and process parameters are determined so that the performance of the edge-contact two-dimensional transistor meets the application requirements.

[0009] At the process level, the edge contact process of the edge contact two-dimensional transistor is optimized based on the requirements of the edge contact two-dimensional transistor and / or the circuit in which the edge contact two-dimensional transistor is located.

[0010] At the design level, the geometric parameters of the edge-contact two-dimensional transistor are optimized based on the performance indicators of the circuit in which the edge-contact two-dimensional transistor is located.

[0011] Optionally, the optimized preparation process includes at least one of depth, thickness, width, length, and processing technology.

[0012] Optionally, when the performance index is the load factor of the edge-contact two-dimensional transistor, the geometric parameters of the edge-contact two-dimensional transistor are optimized so that the edge-contact two-dimensional transistor is close to an ideal current source.

[0013] Alternatively, the circuit design-process co-optimization method based on edge-contact two-dimensional transistors further includes: applying the co-optimized edge-contact two-dimensional transistors to the analog portion of the circuit, and applying hybrid-contact two-dimensional transistors or top-contact two-dimensional transistors to the digital portion of the circuit.

[0014] To achieve the above and other related objectives, the present invention also provides a method for fabricating an edge-contact two-dimensional transistor, optimized based on the aforementioned circuit design-process co-optimization method for edge-contact two-dimensional transistors. The method for fabricating the edge-contact two-dimensional transistor includes at least the following:

[0015] S11) Provide a substrate on which a two-dimensional semiconductor material layer is formed;

[0016] S12) Pattern the two-dimensional semiconductor material layer to form source / drain regions, and form edge-contact source / drain metal electrodes on the side of the two-dimensional semiconductor material layer;

[0017] S13) A gate structure is formed on the structure obtained in step S12).

[0018] Optionally, step S12) includes:

[0019] S121) Define the source / drain region, etch the two-dimensional semiconductor material layer of the source / drain region to pattern the two-dimensional semiconductor material layer and expose the side surface of the two-dimensional semiconductor material layer;

[0020] S122) The sides of the two-dimensional semiconductor material layer are cleaned by plasma treatment;

[0021] S123) Electrode material is deposited in the source and drain regions on both sides of the two-dimensional semiconductor material layer.

[0022] Alternatively, the gate structure is a top-gate structure.

[0023] Alternatively, the two-dimensional semiconductor material layer is a transition metal chalcogenide thin film prepared by chemical vapor deposition, atomic layer deposition, or transfer method.

[0024] Alternatively, after the transistor fabrication is completed in step 13), a post-annealing process is also included.

[0025] To achieve the above and other related objectives, the present invention also provides a circuit, the circuit comprising at least:

[0026] The analog circuit module includes the edge-contact two-dimensional transistors obtained after optimization using the aforementioned circuit design-process co-optimization method based on edge-contact two-dimensional transistors.

[0027] Optionally, the analog circuit module includes at least one of an operational amplifier, a comparator, and a sample-and-hold circuit.

[0028] Optionally, the edge-contact two-dimensional transistor serves as the load transistor of the inverter in the analog circuit module.

[0029] Optionally, the edge-contact two-dimensional transistor serves as the gain stage of the discrete-time comparator in the analog circuit module.

[0030] Alternatively, the circuit may further include a digital circuit module comprising a hybrid contact two-dimensional transistor and / or a top contact two-dimensional transistor.

[0031] Alternatively, the circuit is an analog-to-digital converter, including a voltage divider network, a sample-and-hold module, a comparator array, and an encoder;

[0032] The voltage divider network divides the reference voltage;

[0033] The sample-and-hold module samples the input voltage to obtain a sampled signal, wherein the analog switch uses the edge-contact two-dimensional transistor;

[0034] The comparator array compares the sampled signal with each reference provided by the voltage divider network and outputs the comparison result; wherein the load transistor of the first stage inverter of each comparator adopts the edge-contact two-dimensional transistor.

[0035] The encoder generates an encoded signal based on the comparison results output by the comparator array, including a hybrid contact two-dimensional transistor and / or a top contact two-dimensional transistor.

[0036] As described above, the circuit design-process co-optimization method, fabrication method, and circuit of the present invention have the following beneficial effects:

[0037] 1. This invention proposes a systematic and universally applicable collaborative optimization method: for the first time, the advantages of edge contact technology are systematically and collaboratively optimized with the design goals of analog circuits, and it is clear that it is applicable to a wide range of two-dimensional transition metal chalcogenide material systems, forming a portable technical solution.

[0038] 2. This invention provides a complete paradigm from device to system: it not only provides optimization methods for basic modules such as inverters and comparators, but also uses a complete ADC circuit as an example to elaborate in detail the implementation path and significant effects of the collaborative optimization method of edge-contact two-dimensional transistors in complex mixed-signal systems.

[0039] 3. This invention significantly improves the core performance of the circuit system: through edge contact technology and load optimization design, it fundamentally improves the linearity and stability of the analog circuit, and achieves a nonlinearity error of less than 0.1 LSB in the ADC embodiment.

[0040] 4. This invention provides quantifiable design guidance: by introducing quantitative indicators such as load factor, it provides engineers with clear design optimization goals and evaluation standards. Attached Figure Description

[0041] Figure 1 The diagram shows an inverter structure based on a two-dimensional material top-gate transistor according to the present invention.

[0042] Figure 2 Displayed as Figure 1 A schematic diagram of the small-signal analysis model of an inverter.

[0043] Figure 3 The diagram shows the test data for the output resistance and transconductance of edge-contact transistors and top-contact transistors.

[0044] Figure 4 The diagram shows a schematic of the edge-contact two-dimensional transistor fabrication method of the present invention, in which a two-dimensional semiconductor material layer is formed on a substrate.

[0045] Figure 5The diagram shows the etching of the source and drain regions using the edge-contact two-dimensional transistor fabrication method of the present invention.

[0046] Figure 6 The diagram shows a structure for plasma cleaning in the edge-contact two-dimensional transistor fabrication method of the present invention.

[0047] Figure 7 The diagram shows the formation of the source and drain electrodes using the edge-contact two-dimensional transistor fabrication method of the present invention.

[0048] Figure 8 The diagram shows the removal of photoresist in the edge-contact two-dimensional transistor fabrication method of the present invention.

[0049] Figure 9 The diagram shows a schematic of the seed layer formation in the edge-contact two-dimensional transistor fabrication method of the present invention.

[0050] Figure 10 The diagram shows a schematic of the formation of a gate dielectric layer using the edge-contact two-dimensional transistor fabrication method of the present invention.

[0051] Figure 11 The diagram shows a schematic of the edge-contact two-dimensional transistor fabrication method of the present invention forming a gate.

[0052] Figure 12 The diagram shows a schematic of the formation of a two-dimensional semiconductor material layer on a substrate using the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0053] Figure 13 The diagram shows the top contact formed by the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0054] Figure 14 The diagram shown illustrates the etching of the source and drain regions using the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0055] Figure 15 The diagram shows a structure for plasma cleaning in the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0056] Figure 16 The diagram shows the edge contact formation of the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0057] Figure 17 The diagram shows the removal of photoresist in the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0058] Figure 18 The diagram shows a schematic of the seed layer formation in the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0059] Figure 19The diagram shown illustrates the formation of the gate dielectric layer using the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0060] Figure 20 The diagram shows a schematic of the gate formation using the hybrid contact two-dimensional transistor fabrication method of the present invention.

[0061] Figure 21 The diagram shown is a schematic representation of the inverter of the present invention.

[0062] Figure 22 This diagram shows a comparison of load curves in an inverter when transistors with different contact processes and sizes are used as loads.

[0063] Figure 23 The diagram shows the voltage transfer characteristic curve of the NMOS inverter with edge-contact two-dimensional transistors of the present invention.

[0064] Figure 24 The diagram shows the AC small-signal test results of the NMOS inverter with edge-contact two-dimensional transistors of the present invention.

[0065] Figure 25 The diagram shown is a schematic representation of the discrete-time comparator of the present invention.

[0066] Figure 26 The diagram shown is a schematic representation of the analog-to-digital converter of the present invention.

[0067] Component designation explanation

[0068] 10-Substrate; 11-Two-dimensional semiconductor material layer; 12-Source region; 13-Drain region; 14-Source electrode; 15-Drain electrode; 16-Seed layer; 17-Gate dielectric layer; 18-Gate; 2-Photoresist; 3-Argon plasma; 50-Substrate; 51-Two-dimensional semiconductor material layer; 52a-Top contact source metal electrode; 53a-Top contact drain metal electrode; 52b-Edge contact source metal electrode; 53b-Edge contact drain metal electrode; 52-Source electrode; 53-Drain electrode; 54-Seed layer; 55-Gate dielectric layer; 56-Gate; 6-Analog-to-digital converter; 61-Voltage divider network; 62-Sample-and-hold module; 621-Sample-and-hold circuit; 63-Comparator array; 64-Encoder. Detailed Implementation

[0069] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0070] Please see Figures 1-26 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] Edge contact technology, which forms contact between a metal and the edge or end face of a two-dimensional material layer, can effectively reduce contact resistance, improve carrier injection efficiency, and provide better gate electrostatic control. Therefore, edge contact technology can be used to fabricate two-dimensional transistors. However, research on edge contact technology has largely focused on improving the device physics and fundamental electrical properties of a specific material, and has not yet systematically explored the universality of this technology across similar material families, or how to translate this device-level advantage into performance breakthroughs at the level of complex circuit systems through synergistic optimization of process and circuit design.

[0072] To address the aforementioned issues, this invention provides a circuit design-process co-optimization method based on edge-contact two-dimensional transistors. This method boasts advantages such as strong universality and systematic portability, and possesses significant theoretical value and promising practical applications.

[0073] This invention provides a circuit design-technology co-optimization (DTCO) method based on edge-contact two-dimensional transistors, comprising:

[0074] The circuit containing the edge-contact 2D transistor is co-optimized at both the process and design levels. After co-optimization, the device size and process parameters are determined so that the performance of the edge-contact 2D transistor meets the application requirements.

[0075] At the process level, the edge contact process of the edge contact two-dimensional transistor is optimized based on the requirements of the circuit in which the edge contact two-dimensional transistor is located.

[0076] At the design level, the geometric parameters of the edge-contact 2D transistor are optimized based on the performance metrics of the circuit in which the edge-contact 2D transistor is located.

[0077] Specifically, the collaborative optimization method for edge-contact two-dimensional transistors of the present invention differs from the traditional serial mode of "process first, design later". It adopts a collaborative optimization strategy to optimize at both the process level and the design level. That is, the process and design influence each other, and the performance of the edge-contact two-dimensional transistor and its circuit is optimized through multiple rounds of repeated coordination.

[0078] More specifically, at the process level, in response to the core requirements of analog circuits for high linearity, high output impedance and / or low noise, edge contact fabrication processes are selected and optimized; among them, optimized fabrication processes include, but are not limited to, depth (e.g., etching depth), thickness (e.g., deposition thickness), width, length, and processing processes (e.g., plasma cleaning, annealing), which will not be elaborated here.

[0079] More specifically, at the design level, the performance indicators of a specific device (edge-contact two-dimensional transistor) or its circuitry drive the optimization of key geometric parameters of the edge-contact two-dimensional transistor. These key geometric parameters include, but are not limited to, channel width-to-length ratio, gate length, and gate width, which will not be elaborated upon here. As an example, when the performance indicator is the load factor of the edge-contact two-dimensional transistor, the geometric parameters of the edge-contact two-dimensional transistor are optimized to make the load factor of the edge-contact two-dimensional transistor close to 1. The load factor reflects how close the load is to an ideal current source; the closer the load factor is to 1, the closer the load is to an ideal current source. It should be noted that in this invention, "close" means within a preset range of theoretical values, and the preset range can be set according to actual needs.

[0080] As another implementation of the present invention, the circuit design-process co-optimization method based on edge-contact two-dimensional transistors further includes: selecting device structures and process methods based on circuit requirements, especially the selection of contact methods. As an example, the edge-contact two-dimensional transistors obtained through co-optimization are applied to the analog section of the circuit, while hybrid-contact two-dimensional transistors or top-contact two-dimensional transistors are applied to the digital section of the circuit (if applicable) to improve the overall performance of the circuit.

[0081] Specifically, at the system level, the optimized edge-contact two-dimensional transistor is integrated into the critical path of the circuit. This circuit includes analog circuit modules, including but not limited to operational amplifiers, comparators, and sample-and-hold circuits, which will not be elaborated here. The critical path includes, but is not limited to, nodes that play a decisive role in realizing the circuit's function and performance, such as the load transistor of an inverter and the gain stage of a discrete-time comparator. In practical applications, any device that can improve circuit performance can be implemented using the optimized edge-contact two-dimensional transistor of this invention.

[0082] This invention possesses material universality, and its core processes and design concepts can be extended to two-dimensional transition metal chalcogenide material systems. This invention aims to establish a complete technology chain from contact process optimization to transistor parameter design, and then to the integration of analog circuits and even mixed-signal systems (such as ADCs). It fully leverages the advantages of edge contact processes in improving transistor linearity, load performance, and stability, providing a systematic solution for constructing high-performance two-dimensional semiconductor analog and mixed-signal integrated circuits.

[0083] Example 1

[0084] This embodiment employs the method of the present invention to perform design-process co-optimization on inverters based on two-dimensional material top-gate transistors, such as... Figure 1 As shown, the inverter consists of a pull-down driver transistor M1 and a load transistor M2, wherein the output resistance of the pull-down driver transistor M1 is r. o1 The load resistance of the inverter is R. eq The output resistance of the load transistor M2 is approximately equal to r. o2 . Figure 2 for Figure 1 Small-signal analysis model of an inverter. The optimization objective is the small-signal gain A of the inverter. v The performance indicators involved include: the transconductance g of the pull-down driver transistor. m1 The output resistor r of the pull-down driver transistor o1 , load transistor output resistance r o2 And the inverter flip-point voltage V SP The parameters for collaborative optimization include: the contact process type (edge ​​contact or top contact) between the pull-down driver transistor M1 and the load transistor M2, and the channel width W2 of the load transistor M2. The specific optimization steps are as follows:

[0085] Both the pull-down driver transistor M1 and the load transistor M2 are selected as top-gate structures, with the gate metal being gold (Au) or aluminum (Al). Based on Figure 3 Output resistance ro and transconductance g m Test data shows that the typical output resistance of an edge-contact transistor is 10. 9 On the order of Ω, with a typical transconductance of 10. -6 The S-order; the typical output resistance of the top-contact transistor is 10. 8 On the order of Ω, with a typical transconductance of 10. -5 The value is on the order of S. Therefore, the output resistance r of the load transistor M2 is on the order of S. o2 Approximately 10 at edge contact 9 Ω, approximately 10 at the top contact point 8 Ω. According to Figure 2 From the small-signal model, we know that the inverter gain formula is A v =g m1 ×(r o1 ∥r o2 ).

[0086] To maximize the gain, the transconductance g of the pull-down driver transistor needs to be increased simultaneously. m1 The output resistor r of the pull-down driver transistor o1 and the output resistance r of the load transistor o2 .Depend on Figure 3This indicates that the output resistance of the edge-contact transistor is an order of magnitude higher than that of the top-contact transistor. Although the transconductance decreases slightly, the product g m ×r o Significant improvement is achieved. Therefore, edge contact technology is preferred for simultaneously fabricating the pull-down driver transistor M1 and the load transistor M2. However, full edge contact causes a shift in the threshold voltage of the pull-down driver transistor M1 and the load transistor M2, affecting the switching point voltage V. SP The actual operating point deviates from the maximum gain point by 1.5V, which is VDD / 2. Therefore, the channel width W2 of the load transistor M2 needs to be increased to reduce its equivalent resistance and correct the switching point voltage back to 1.5V. Calculations (as shown in Table 1 below) show that the inverter with full edge contact and optimized channel width W2 of the load transistor M2 can achieve a theoretical gain of over 60 dB, significantly higher than the theoretical gain of the full top contact scheme.

[0087] Table 1 shows the theoretical gain values ​​of inverters composed of pull-down driver transistors and load transistors fabricated using different contact processes and device parameters.

[0088]

[0089] Both the pull-down driver transistor M1 and the load transistor M2 are edge-contacted according to the above method, and the width of the load transistor M2 is adjusted to make V SP =1.5V inverter. Actual gain statistics show that the gain of the full-edge contact inverter is generally higher than 30 dB (actual test results are lower than the theoretical values ​​in the table above due to static operating point offset and parasitic parameters, but the trend is consistent), while the gain of the full-top contact inverter is approximately 26 dB. Meanwhile, the flip-point deviation is controlled within ±0.1V. This embodiment demonstrates that, with gain as the optimization target, by co-optimizing the contact process (increasing the output resistance r of the pull-down drive transistor), o1 and the output resistance r of the load transistor o2 ) and transistor width (adjusting V) SP This can significantly improve the small-signal gain of the inverter while maintaining a reasonable flip point.

[0090] Example 2

[0091] like Figures 4-11 As shown, this embodiment provides a method for fabricating an edge-contact two-dimensional transistor optimized by the circuit design-process co-optimization method based on the present invention, and it is applicable to two-dimensional semiconductor materials with layered structures. The fabrication method includes:

[0092] S11) Provides a substrate 10, on which a two-dimensional semiconductor material layer 11 is formed.

[0093] Specifically, such as Figure 4 As shown, a substrate 10 is provided, on which a two-dimensional semiconductor material layer 11 is formed. As an example, the substrate 10 is made of sapphire; in practical applications, any substrate material is applicable, including but not limited to silicon, silicon oxide, polyimide, and quartz. The two-dimensional semiconductor material layer 11 is a transition metal chalcogenide thin film prepared by chemical vapor deposition, atomic layer deposition, or transfer methods. Transition metal chalcogenides include, but are not limited to, molybdenum disulfide, tungsten disulfide, molybdenum diselenide, or tungsten diselenide. The preparation method of this invention is applicable to two-dimensional semiconductor materials with layered structures (including but not limited to transition metal dichalcogenides), and will not be elaborated upon here.

[0094] S12) Pattern the two-dimensional semiconductor material layer 11 and form source and drain metal electrodes with edge contacts on the side of the two-dimensional semiconductor material layer 11.

[0095] In this example, step S12) specifically includes:

[0096] S121) Define the source / drain regions, etch the two-dimensional semiconductor material layer 11 of the source / drain regions to pattern the two-dimensional semiconductor material layer 11 and expose the side surfaces of the two-dimensional semiconductor material layer 11. For example... Figure 5 As shown, firstly, photoresist 2 is spin-coated onto the two-dimensional semiconductor material layer 11, and the source region 12 and drain region 13 are defined by photolithography. Then, the two-dimensional semiconductor material of the source region 12 and drain region 13 is selectively removed by reactive ion etching, exposing the layered edges (i.e., sides) of the two-dimensional semiconductor material layer 11; in this example, the substrate 10 of the source region 12 and drain region 13 is also partially etched, that is, the thickness of the substrate 10 of the source region 12 and drain region 13 is reduced.

[0097] S122) The sides of the two-dimensional semiconductor material layer 11 are cleaned using plasma treatment. For example... Figure 6 As shown, argon plasma 3 is used for interface cleaning. Any plasma capable of cleaning the interface of the corresponding two-dimensional semiconductor material layer to improve device performance is applicable to this invention and is not limited to this embodiment. In this example, the cleaned interface includes, but is not limited to, the side surface of the two-dimensional semiconductor material layer 11, and also includes the upper surface of the substrate 10 of the source region 12 and the drain region 13.

[0098] (S123) Electrode material is deposited in the source and drain regions on both sides of the two-dimensional semiconductor material layer 11. For example... Figure 7 As shown, as an example, in-situ deposited electrode material forms the source 14 and drain 15. In this example, the electrode material is gold. Figure 8 As shown, after removing the photoresist 2, the two-dimensional semiconductor material layer 11 serves as a channel, and the source electrode 14 and the drain electrode 15 are in contact with the two sides of the two-dimensional semiconductor material layer 11 respectively, forming source and drain metal electrodes with edge contact.

[0099] S13) A gate structure is formed on the structure obtained in step S12). In this embodiment, the gate structure is a top-gate structure, and any fabrication process and steps that can form a top-gate structure are applicable to this invention. As an example, such as Figure 9 As shown, firstly, a seed layer 16 is formed on the two-dimensional semiconductor material layer 11. As... Figure 10 As shown, a gate dielectric layer 17 is then formed on the upper surfaces of the source 14, drain 15, and seed layer 16. The material of the gate dielectric layer 17 includes, but is not limited to, one or more combinations of aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide. Figure 11 As shown, finally, a metal material is deposited on the gate dielectric layer 17 to form the gate 18.

[0100] As another implementation of the present invention, after the transistor fabrication is completed in step 13), a post-annealing process is also included to stabilize the electrical characteristics of the transistor and reduce the hysteresis effect.

[0101] The edge-contact two-dimensional transistor of the present invention can be obtained based on the above steps. To illustrate the performance of the edge-contact two-dimensional transistor obtained by the fabrication method of the present invention, corresponding devices were obtained using molybdenum disulfide and tungsten disulfide as two-dimensional semiconductor materials, respectively, based on the fabrication method of the present invention. Electrical tests show that the edge-contact transistors formed by both molybdenum disulfide and tungsten disulfide consistently exhibit smaller subthreshold swing, higher output impedance, and better current saturation characteristics than their corresponding top-contact transistors. This proves that the edge-contact process of the present invention is universally applicable to this type of layered two-dimensional semiconductor material in improving the key characteristics of analog devices.

[0102] Example 3

[0103] like Figures 12-20 As shown, this embodiment provides a method for fabricating a hybrid contact two-dimensional transistor, which is also applicable to two-dimensional semiconductor materials with layered structures. The method includes:

[0104] S21) A substrate 50 is provided, and a two-dimensional semiconductor material layer 51 is formed on the substrate 50; such as Figure 12 As shown, the specific steps are described in step S11 of embodiment two, and will not be repeated here.

[0105] S22) Top-contact source / drain metal electrodes are formed on the upper surfaces of both sides of the patterned two-dimensional semiconductor material layer 51, and edge-contact source / drain metal electrodes are formed on the side surfaces of the two-dimensional semiconductor material layer 51.

[0106] In this example, step S22) specifically includes:

[0107] S221) Define the source / drain region, and form a top contact source / drain metal electrode in the inner region of the source / drain region; etch the two-dimensional semiconductor material layer 51 and expose the side surface of the two-dimensional semiconductor material layer 51 so that the side surface of the two-dimensional semiconductor material layer 51 is aligned with the outer side surface of the top contact source / drain metal electrode. Figure 13 As shown, firstly, the source region and drain region are defined; then, through photolithography, etching, and other processes, a top-contact source metal electrode 52a and a top-contact drain metal electrode 53a are formed in the inner region of the source and drain regions (i.e., the region near the center of the device). These top-contact source metal electrodes 52a and top-contact drain metal electrodes 53a are located on the upper surface of the two-dimensional semiconductor material layer 51. Figure 14 As shown, then, photoresist 2 is spin-coated, and the two-dimensional semiconductor material layer 51 covered by the source and drain metal electrodes (52a, 53a) that are not top-contacted in the source and drain regions (outer regions) is removed by photolithography, etching and other processes, exposing the layered edge of the two-dimensional semiconductor material layer 51.

[0108] S222) Plasma treatment is used to clean the sides and the outer surfaces of the source and drain metal electrodes at the top contact of the two-dimensional semiconductor material layer 51; such as Figure 15 As shown, the specific steps are described in step S122 of Embodiment 2, and will not be repeated here.

[0109] (S223) Electrode material is deposited on the outer surfaces of the source / drain metal electrodes (52a, 53a) at the side and top contacts of the two-dimensional semiconductor material layer 51 to form edge-contact source / drain metal electrodes. For example... Figure 16 As shown, as an example, in-situ deposited electrode material forms an edge-contact source metal electrode 52b and an edge-contact drain metal electrode 53b. The top-contact source metal electrode 52a and the edge-contact source metal electrode 52b together constitute the source electrode 52, and the top-contact drain metal electrode 53a and the edge-contact drain metal electrode 53b together constitute the drain electrode 53. In this example, the electrode material is gold. Figure 17 As shown, after removing the photoresist 2, the two-dimensional semiconductor material layer 51 serves as the channel. The source electrode 52 has a folded structure and contacts the left side and the upper left side of the two-dimensional semiconductor material layer 51. The drain electrode 53 has a folded structure and contacts the right side and the upper right side of the two-dimensional semiconductor material layer 51, forming a mixed contact source and drain metal electrode (edge ​​contact + top contact).

[0110] S23) Form a gate structure on the structure obtained in step S22). Figures 18-20 As shown, a seed layer 54, a gate dielectric layer 55, and a gate 56 are formed sequentially. For specific steps, please refer to step S23 of Embodiment 2, which will not be described in detail here.

[0111] Example 4

[0112] This embodiment provides an edge-contact two-dimensional top-gate transistor (EDT) optimized using the circuit design-process co-optimization method of the present invention and fabricated using the edge-contact two-dimensional transistor fabrication method of Embodiment 2, which serves as a high-performance load. As an example, this high-performance load is used as the load transistor of an NMOS inverter; such as... Figure 21 As shown, the NMOS inverter includes a first NMOS transistor N1 and a second NMOS transistor N2 (both NMOS transistors), wherein the first NMOS transistor N1 serves as a pull-down drive transistor, and the second NMOS transistor N2 serves as a load transistor. In this example, the width-to-length ratio is optimized based on the performance index load factor η. In practical applications, this high-performance load can be applied to any circuit structure requiring good load performance, and is not limited to this embodiment.

[0113] The load factor η is used to measure the performance of the transistor as a load in an NMOS inverter. Load curves are shown for three types of transistors used as loads in an NMOS inverter. The three example load transistors are a top-contact transistor with a width-to-length ratio of 30 / 10, an edge-contact transistor with a width-to-length ratio of 30 / 10, and an edge-contact transistor with a width-to-length ratio of 100 / 10. The formula for calculating the load factor η is:

[0114] ;

[0115] Among them, I load and V load These represent the voltage and current across the load, respectively. VDD is the power supply voltage, and Ion is the current at the intersection of the output curve of the pull-down drive transistor and the load curve. The load factor η reflects how closely the load approximates an ideal current source; the closer the load factor η is to 1, the closer the load is to an ideal current source. For example... Figure 22 As shown, a is the output curve of the pull-down driver transistor N1, b is the load curve of the edge-contact two-dimensional transistor with a width-to-length ratio of 100 / 10, c is the load curve of the top-contact two-dimensional transistor with a width-to-length ratio of 30 / 10, and d is the load curve of the edge-contact two-dimensional transistor with a width-to-length ratio of 30 / 10. Calculations show that the load coefficient η calculated from the load curve b is 0.8, from the load curve c is 0.67, and from the load curve d is 0.86. It is evident that the edge-contact two-dimensional transistor obtained using the synergistic optimization method and fabrication method of this invention can significantly improve the η value, making its current-voltage characteristics closer to an ideal constant current source, exhibiting superior load performance. Using this optimized edge-contact transistor as the load transistor of an NMOS inverter can significantly improve the inverter's voltage gain, power supply rejection ratio, and linear operating range.

[0116] It should be noted that the transistor type and load factor calculation values ​​given in this embodiment are only used to demonstrate how to characterize the performance of the transistor prepared by the present invention. This method is applicable to transistors with other contact methods and sizes resulting from any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention.

[0117] Example 5

[0118] In this embodiment, the edge-contact two-dimensional transistor obtained using the collaborative optimization method of the present invention is applied in a high-performance NMOS inverter, such as... Figure 23 The figure shows the voltage transfer characteristic curve of this high-performance NMOS inverter. Figure 24 The results show the AC small-signal test results for this high-performance NMOS inverter. As a core unit in modules such as ADC comparators, this high-performance NMOS inverter, when using the edge-contact two-dimensional transistor of this invention as the load transistor, exhibits a voltage gain increase of over 30% and enhanced logic threshold stability. This verifies the effectiveness of the circuit design-process co-optimization method based on edge-contact two-dimensional transistors of this invention at the basic analog module level.

[0119] Example 6

[0120] In this embodiment, the edge-contact two-dimensional transistor obtained using the collaborative optimization method of the present invention is applied to the core gain stage (e.g., the first-stage gain) of a discrete-time comparator. Figure 25As shown in the example, the discrete-time comparator includes a first switch S1, a second switch S2, a third switch S3, a capacitor C, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6. One end of the first switch S1 is connected to the input data Vdata, and the other end is connected to the first terminal of the capacitor C, and is controlled by the inverse signal of the control signal Vctrl. One end of the second switch S2 is connected to the reference signal Vref, and the other end is connected to the first terminal of the capacitor C, and is controlled by the control signal Vctrl. The second terminal of the capacitor C... One end of the third switch S3 is connected to the gate of the third NMOS transistor N3, and the other end is connected to the gate of the fifth NMOS transistor N5. The third NMOS transistor N3 and the fourth NMOS transistor N4 form the first inverting gain stage, and the fifth NMOS transistor N5 and the sixth NMOS transistor N6 form the second inverting gain stage. The third NMOS transistor N3 and the fifth NMOS transistor N5 act as pull-down drive transistors, and the fourth NMOS transistor N4 and the sixth NMOS transistor N6 act as load transistors. One end of the third switch S3 is connected to the gate of the third NMOS transistor N3, and the other end is connected to the gate of the fifth NMOS transistor N5. It is controlled by the control signal Vctrl. During the reset phase, the control signal Vctrl is high; during the comparison phase, the control signal Vctrl is low. Either or both of the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are edge-contact two-dimensional transistors obtained using the collaborative optimization method of this invention. Their high output resistance and stable load characteristics improve the gain and resolution of the comparator.

[0121] Example 7

[0122] like Figure 26 As shown, this embodiment provides an analog-to-digital converter 6, which includes a voltage divider network 61, a sample-and-hold module 62, a comparator array 63, and an encoder 64.

[0123] like Figure 26 As shown, voltage divider network 61 divides the reference voltage Vref to obtain multiple comparison references. As an example, voltage divider network 61 is implemented using a series of resistors.

[0124] like Figure 26 As shown, the sample-and-hold module 62 samples the input voltage Vin to obtain a sampled signal. The analog switches in the sample-and-hold module 62 employ edge-contact two-dimensional transistors optimized and fabricated according to this invention. As an example, the sample-and-hold module 62 includes a sample-and-hold circuit 621 and a switch K; the sample-and-hold circuit 621 contains multiple analog switches, the specific structures of which are not detailed here; switch K is also an analog switch; some (at least one) or all of the analog switches employ the edge-contact two-dimensional transistors of this invention. Utilizing the high linearity and low leakage current characteristics of the edge-contact two-dimensional transistors of this invention, accurate sampling and holding of the input analog signal are ensured, reducing distortion at the source.

[0125] like Figure 26 As shown, the comparator array 63 includes multiple comparators for comparing the sampled signal with various comparison benchmarks provided by the voltage divider network 61 and outputting the comparison results. The load transistor of the core gain stage (e.g., the first-stage inverter) of each comparator uses an edge-contact two-dimensional transistor optimized according to this invention. As an example, the comparator array 63 includes seven comparators, outputting comparison results A0A1A2A3A4A5A6A7; the structure of each comparator can adopt the discrete-time comparator of Embodiment Six, which will not be described in detail here. Using edge-contact two-dimensional transistors with optimized aspect ratios as load transistors provides high-gain, high-resolution comparison capabilities for the entire ADC, and effectively compensates for process variations using a discrete-time reset mechanism.

[0126] like Figure 26 As shown, encoder 64 generates encoded signals based on the comparison results output by comparator array 63, including hybrid contact two-dimensional transistors and / or top contact two-dimensional transistors, which can be set according to actual needs (e.g., speed requirements). In this example, encoder 64 is an 8-3 encoder, outputting encoded signals Y0Y1Y2. As a digital logic circuit, encoder 64 requires high operating speed; as an example, the transistors in its pull-up and pull-down branches are fabricated using the hybrid contact process of Embodiment 3, which, while retaining certain contact advantages, pursues higher carrier mobility to accelerate the switching speed of the encoded logic and reduce system latency.

[0127] Furthermore, regarding the optimization of the back-end processes: after the entire ADC chip is interconnected, it is annealed in an oxygen atmosphere at 150°C for 1 hour; the specific annealing conditions can be adjusted according to actual needs. This step further stabilizes the threshold voltage and hysteresis characteristics of the edge contact transistors in analog modules such as comparators, improving the long-term operational reliability of the ADC.

[0128] Through the aforementioned cross-level (materials-process-device-module-system) synergistic optimization, the ADC in this embodiment achieves excellent static performance: a differential nonlinearity (DNL) of 0.072 LSB and an integral nonlinearity (INL) of 0.128 LSB, while consuming only 3.36 μW. This fully demonstrates the powerful effectiveness of the method of this invention in realizing high-performance, low-power mixed-signal integrated circuits.

[0129] The method of this invention can also be fully applied to other complex systems. In the analog part, edge contact transistors are used to ensure accuracy, while in the digital part, other contact processes can be flexibly selected to optimize speed, thereby achieving system-level performance optimization, and is not limited to this embodiment.

[0130] In summary, this invention provides a collaborative optimization method for edge-contact two-dimensional transistors. By employing edge-contact technology, it significantly improves the load linearity, output resistance, and switching stability of two-dimensional transistors, and optimizes transistor geometry parameters to meet the performance requirements of analog circuits. Specifically, it includes: optimized design of edge-contact transistors, methods for characterizing and improving load performance, and their system integration and application in high-performance analog circuit modules (such as inverters, comparators, and sample-and-hold circuits). This invention provides a complete solution from transistor-level process optimization to circuit-level performance improvement, offering a key technical path for the design and manufacturing of high-linearity, high-stability analog and mixed-signal integrated circuits based on novel two-dimensional semiconductors. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0131] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A circuit design-process co-optimization method based on edge-contact two-dimensional transistors, applied to two-dimensional transition metal chalcogenide material systems, characterized in that, The circuit design-process co-optimization method based on edge-contact two-dimensional transistors includes at least the following: The circuit containing the edge-contact two-dimensional transistor is co-optimized at both the process and design levels. The optimization at both levels is carried out simultaneously and influences each other. After co-optimization, the device size and process parameters are determined so that the performance of the edge-contact two-dimensional transistor meets the application requirements. At the process level, the edge contact process of the edge contact two-dimensional transistor is optimized based on the requirements of the circuit in which the edge contact two-dimensional transistor is located. At the design level, based on the load factor of the edge-contact two-dimensional transistor in the circuit, the geometric parameters of the edge-contact two-dimensional transistor are optimized so that the edge-contact two-dimensional transistor is close to an ideal current source. The load factor η satisfies: ； Among them, I load and V load VDD represents the voltage and current across the load, Ion represents the current at the intersection of the output curve of the driving transistor and the load curve, and VDD represents the power supply voltage. The load factor η reflects how close the load is to an ideal current source. The closer the load factor η is to 1, the closer the load is to an ideal current source.

2. The circuit design-process co-optimization method based on edge-contact two-dimensional transistors according to claim 1, characterized in that: The optimized fabrication process includes at least one of the following: etching depth, deposition thickness, width, length, and processing technology.

3. The circuit design-process co-optimization method based on edge-contact two-dimensional transistors according to any one of claims 1-2, characterized in that: The circuit design-process co-optimization method based on edge-contact two-dimensional transistors further includes: applying the co-optimized edge-contact two-dimensional transistors to the analog part of the circuit, and applying hybrid-contact two-dimensional transistors or top-contact two-dimensional transistors to the digital part of the circuit.

4. A method for fabricating an edge-contact two-dimensional transistor, optimized based on the circuit design-process co-optimization method for edge-contact two-dimensional transistors as described in any one of claims 1-3, characterized in that, The method for fabricating the edge-contact two-dimensional transistor includes at least the following: S11) Provide a substrate on which a two-dimensional semiconductor material layer is formed; S12) Pattern the two-dimensional semiconductor material layer to form source / drain regions, and form edge-contact source / drain metal electrodes on the side of the two-dimensional semiconductor material layer; S13) A gate structure is formed on the structure obtained in step S12).

5. The method for fabricating an edge-contact two-dimensional transistor according to claim 4, characterized in that: Step S12) includes: S121) Define the source / drain region, etch the two-dimensional semiconductor material layer of the source / drain region to pattern the two-dimensional semiconductor material layer and expose the side surface of the two-dimensional semiconductor material layer; S122) The sides of the two-dimensional semiconductor material layer are cleaned by plasma treatment; S123) Electrode material is deposited in the source and drain regions on both sides of the two-dimensional semiconductor material layer.

6. The method for fabricating an edge-contact two-dimensional transistor according to any one of claims 4-5, characterized in that: The gate structure is a top-gate structure.

7. The method for fabricating an edge-contact two-dimensional transistor according to any one of claims 4-5, characterized in that: The two-dimensional semiconductor material layer is a transition metal chalcogenide thin film prepared by chemical vapor deposition, atomic layer deposition, or transfer method.

8. The method for fabricating an edge-contact two-dimensional transistor according to any one of claims 4-5, characterized in that: After the transistor fabrication is completed, a post-annealing process is also included.

9. A circuit, characterized in that, The circuit includes at least: The analog circuit module includes an edge-contact two-dimensional transistor obtained after optimization by the circuit design-process co-optimization method based on edge-contact two-dimensional transistors as described in any one of claims 1-3.

10. The circuit according to claim 9, characterized in that: The analog circuit module includes at least one of an operational amplifier, a comparator, and a sample-and-hold circuit.

11. The circuit according to claim 9, characterized in that: The edge-contact two-dimensional transistor serves as the load transistor for the pull-up branch of the NMOS inverter in the analog circuit module.

12. The circuit according to claim 9, characterized in that: The edge-contact two-dimensional transistor serves as the gain stage of the discrete-time comparator in the analog circuit module.

13. The circuit according to any one of claims 9-12, characterized in that: The circuit also includes a digital circuit module, which includes a hybrid contact two-dimensional transistor and / or a top contact two-dimensional transistor.

14. The circuit according to claim 13, characterized in that: The circuit is an analog-to-digital converter, including a voltage divider network, a sample-and-hold module, a comparator array, and an encoder; The voltage divider network divides the reference voltage; The sample-and-hold module samples the input voltage to obtain a sampled signal, wherein the analog switch uses the edge-contact two-dimensional transistor; The comparator array compares the sampled signal with the references provided by the voltage divider network and outputs the comparison results; The load transistor of the first-stage inverter of each comparator is the edge-contact two-dimensional transistor. The encoder generates an encoded signal based on the comparison results output by the comparator array, including a hybrid contact two-dimensional transistor and / or a top contact two-dimensional transistor.

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