An anti-radiation GaN logic circuit structure and a manufacturing method thereof

Abstract

This invention provides a radiation-resistant GaN logic circuit structure and its fabrication method, belonging to the field of semiconductor technology. The circuit structure includes, from bottom to top, a substrate layer, an aluminum nitride nucleation layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization-induced hole transport layer, a gallium nitride channel layer, and a barrier layer. The device has an electrically connected 2DEG resistive region and an enhancement-mode Schottky gate GaN HEMT region. On the surface of the enhancement-mode Schottky gate GaN HEMT region, a drain ohmic electrode, a gate ohmic electrode, a source ohmic electrode, and a HEMT-side deep trench electrode are spaced apart along the source-drain direction. A resistive-side deep trench electrode connected to the gallium nitride buffer layer is disposed on the surface of the 2DEG resistive region, and the resistive-side deep trench electrode and the HEMT-side deep trench electrode are bridged. This effectively prevents hole accumulation at the bottom of the active region, alleviates threshold drift caused by the back-gate effect and fluctuations in the 2DEG resistance, and improves the device's resistance to single-event burn-out.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a radiation-resistant GaN logic circuit structure and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), as a core representative of third-generation wide-bandgap semiconductors, has broad application prospects due to its high breakdown electric field, high electron saturation drift velocity, and high temperature and radiation resistance. Among them, resistive transistor (RTL) inverters, as the basic logic unit for building all-GaN power integrated circuits, have advantages such as simple circuit structure, fast switching speed, and high integration density, and can meet the stringent requirements of aerospace-grade chips for high energy efficiency and lightweight design.

[0003] Existing gallium nitride (GaN) RTL inverters typically employ monolithic integration technology, consisting of a two-dimensional electron gas (2DEG) resistor and an enhancement-mode gallium nitride high electron mobility transistor (GaN HEMT) driver. Their typical structure is based on an insulating substrate such as sapphire or silicon carbide, where an AlGaN / GaN heterojunction is formed through epitaxial growth, utilizing spontaneous polarization and piezoelectric polarization effects to generate a high concentration of two-dimensional electron gas. The enhancement-mode GaN HEMT typically employs a p-GaN gate structure to achieve normally-off characteristics, while the 2DEG resistor's resistance value is determined through etching interruption or field plate modulation. The two are interconnected via ohmic contacts, forming the basic logic inverting unit.

[0004] However, when GaN RTL inverters operate in the intense radiation environment of space, single-event irradiation can severely threaten their reliability. High-energy particles excite transient electron-hole pairs within the device. Holes, due to their extremely low mobility and lack of effective dissipation channels, tend to accumulate at the buffer layer and heterojunction interface. On one hand, for enhancement-mode GaN HEMTs, excess holes accumulating at the buffer layer interface below the p-GaN gate can generate a positive back-gate effect, leading to negative threshold voltage drift or even device burnout. On the other hand, for 2DEG resistors, the hole charge accumulated deep in the substrate can modulate the electron concentration in the upper channel through electrostatic coupling, causing a sharp drop in resistance and compromising the inverter's logic swing and noise margin. Currently, existing radiation hardening techniques mainly focus on structural improvements of individual transistors, lacking system-level hardening solutions for resistor-transistor integrated logic units. In particular, for monolithic integrated circuits based on insulating substrates such as sapphire, the lack of longitudinal charge discharge channels means that grounding the surface electrodes alone is no longer sufficient to meet the hole discharge rate requirements under extremely high dose irradiation. The problem of deep charge accumulation has become a key bottleneck restricting the aerospace application of GaN logic circuits. Summary of the Invention

[0005] This invention provides a radiation-resistant GaN logic circuit structure and its fabrication method. It effectively prevents hole accumulation at the bottom of the active region, alleviates threshold drift and 2DEG resistance fluctuations caused by the back-gate effect, and improves the device's resistance to single-event burn-out. The technical solution is as follows:

[0006] In a first aspect, embodiments of the present invention provide a radiation-resistant GaN logic circuit structure, comprising, from bottom to top, a substrate layer, an aluminum nitride nucleation layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization-induced hole transport layer, a gallium nitride channel layer, and a barrier layer. The circuit structure has a 2DEG resistor region and an enhancement-mode Schottky gate GaN HEMT region arranged at intervals along the source-drain direction and isolated from each other. The 2DEG resistor region and the enhancement-mode Schottky gate GaN HEMT region are electrically connected. The surface of the HEMT region is provided with a drain ohmic electrode, a gate ohmic electrode, a source ohmic electrode, and an HEMT-side deep trench electrode arranged at intervals along the source-drain direction and gradually moving away from the 2DEG resistor region. The drain ohmic electrode and the source ohmic electrode are connected to the gallium nitride channel layer, the gate is connected to the barrier layer, and the HEMT-side deep trench electrode is connected to the gallium nitride buffer layer. The surface of the 2DEG resistor region is provided with a resistor-side deep trench electrode connected to the gallium nitride buffer layer, and the resistor-side deep trench electrode and the HEMT-side deep trench electrode are bridged.

[0007] Optionally, the aluminum gallium nitride polarization-induced hole transport layer is an aluminum gallium nitride layer, and the aluminum composition of the aluminum gallium nitride polarization-induced hole transport layer decreases linearly in the direction from the gallium nitride buffer layer to the gallium nitride channel layer.

[0008] Optionally, a fully isolated region formed by implanting high-energy ions is provided between the 2DEG resistor region and the enhancement-mode Schottky gate GaN HEMT region, and the fully isolated region extends longitudinally into the interior of the gallium nitride buffer layer.

[0009] Optionally, multiple resistor-side deep trench electrodes are provided that are bridged with the HEMT-side deep trench electrode, and the multiple resistor-side deep trench electrodes are arranged at intervals along a direction perpendicular to the source-drain direction.

[0010] Optionally, the 2DEG resistive region is divided into an active region and multiple field regions by a high-resistance isolation region formed by implanting high-energy ions. The high-resistance isolation region extends along the source-drain direction and longitudinally into the interior of the gallium nitride channel layer. A high-voltage resistive electrode connected to the gallium nitride channel layer is provided at the end of the active region away from the enhancement-mode Schottky gate GaN HEMT region. A resistive output electrode connected to the gallium nitride channel layer is provided at the end of the active region near the enhancement-mode Schottky gate GaN HEMT region. The resistive output electrode is bridged with the drain ohmic electrode. Multiple resistive-side deep trench electrodes are correspondingly disposed in multiple field regions.

[0011] Optionally, the 2DEG resistor region includes the active region and two field regions symmetrically disposed on both sides of the active region along a direction perpendicular to the source-drain direction, and the resistor-side deep trench electrode is disposed at the end of the field region near the active region.

[0012] Optionally, the high-voltage resistive electrode includes a first ohmic metal layer, a first interconnect metal layer, and a first top metal layer arranged from bottom to top; the output resistive electrode includes a second ohmic metal layer, a second interconnect metal layer, and a second top metal layer arranged from bottom to top; and the drain ohmic electrode includes a third ohmic metal layer and a third interconnect metal layer arranged from bottom to top. The second interconnect metal layer and the third interconnect metal layer are bridged by a first interconnect metal pillar.

[0013] Optionally, the resistor-side deep trench electrode includes a fourth ohmic metal layer and a fourth interconnect metal layer arranged from bottom to top; the HEMT-side deep trench electrode includes a fifth ohmic metal layer, a fifth interconnect metal layer, and a fifth top metal layer arranged from bottom to top; the fourth interconnect metal layer is bridged to the fifth interconnect metal layer through a second interconnect metal pillar; the gate includes a P-type gallium nitride strip, a Schottky metal layer, two gate interconnect metal pillars disposed at both ends of the Schottky metal layer perpendicular to the source-drain direction, and a gate top metal layer above the gate interconnect metal pillars, arranged from bottom to top; the source ohmic electrode includes a source ohmic metal layer arranged from bottom to top, two source interconnect metal pillars disposed at both ends of the source ohmic metal layer perpendicular to the source-drain direction, and a source top metal layer above the source interconnect metal pillars; the second interconnect metal pillar passes through the two gate interconnect metal pillars and the two source interconnect metal pillars.

[0014] Optionally, the thickness of the aluminum nitride nucleation layer ranges from 15nm to 25nm; the thickness of the gallium nitride buffer layer ranges from 2µm to 3µm; the thickness of the aluminum gallium nitride polarization-induced hole transport layer ranges from 100nm to 150nm; the thickness of the gallium nitride channel layer ranges from 200nm to 300nm; and the thickness of the barrier layer ranges from 20nm to 25nm.

[0015] In a second aspect, embodiments of the present invention provide a manufacturing method for fabricating the radiation-resistant GaN logic circuit structure described in the first aspect, comprising:

[0016] Step 1: On the epitaxial wafer, from bottom to top, grow a substrate layer, an aluminum nitride nucleation layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization induced hole transport layer, a gallium nitride channel layer, a barrier layer, and a p-type gallium nitride layer. Remove the p-type gallium nitride layer in the non-patterned area by etching to form the p-type gallium nitride strip in the gate region.

[0017] Step 2: Inject high-energy ions into the designated area, control the injection depth to penetrate the aluminum gallium nitride polarization-induced hole transport layer and reach the interior of the gallium nitride buffer layer, forming a fully isolated region that completely cuts off the electron and hole channels, so as to separate the 2DEG resistance region and the enhancement-mode Schottky gate GaN HEMT region.

[0018] Step 3: Implant high-energy ions into the 2DEG resistance region, control the implantation depth to penetrate the barrier layer and reach the gallium nitride channel layer, and form a high-resistance isolation region to separate the active region and two field regions symmetrically arranged on both sides of the active region along the direction perpendicular to the source-drain direction.

[0019] Step 4: Grow a dielectric layer on the epitaxial wafer and use two etching processes to create shallow contact holes and deep trench holes respectively: The first etching process forms shallow holes at both ends of the active region along the source-drain direction and the enhancement-mode Schottky gate GaN HEMT region down to the gallium nitride channel layer interface; The second etching process forms deep trench holes penetrating to the gallium nitride buffer layer on the outer side of the high-resistivity isolation region near the field region of the active region and on the side of the enhancement-mode Schottky gate GaN HEMT region away from the 2DEG resistor region. By depositing an ohmic metal layer and annealing at high temperature, a high-voltage resistor electrode, an output resistor electrode, a drain ohmic electrode, a source ohmic electrode, a resistor-side deep trench electrode, and a HEMT-side deep trench electrode are formed.

[0020] Step 5: Regrow the dielectric layer, and etch and deposit a Schottky metal layer over the P-type gallium nitride strip to form the gate;

[0021] Step 6: Regrow the dielectric layer, and etch and deposit interconnect metal over the high voltage electrode, the output electrode, the drain electrode, the gate electrode, the source electrode, the resistor-side deep trench electrode, and the HEMT-side deep trench electrode to achieve bridging between the resistor-side deep trench electrode and the HEMT-side deep trench electrode, as well as between the resistor output electrode and the drain electrode.

[0022] Step 7: Regrow the dielectric layer. Etch and deposit a thick layer of aluminum as the top layer metal above the high-voltage resistor, the output resistor, the gate, the source ohmic electrode, and the HEMT-side deep trench electrode. Form the top layer metal pads using photolithography lift-off to bring out the signal ports of the circuit structure and the final ports of the hole outgoing network.

[0023] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0024] Under normal operating conditions, the logic signal current of the device flows horizontally only in the 2DEG at the interface between the barrier layer and the gallium nitride channel layer. When a positive voltage higher than the threshold voltage is applied to the gate, the GaN HEMT is turned on, and the bridging node between the output resistive output electrode and the drain ohmic electrode is pulled low to near ground potential, achieving a logic low-level output. When a voltage lower than the threshold voltage or zero voltage is applied to the gate, the GaN HEMT is turned off, and the output is pulled high to near the power supply voltage through the 2DEG resistive region, achieving a logic high-level output, thereby completing the inverting logic function.

[0025] When a device operates in a high-radiation environment in space, high-energy particles incident on the device will excite a large number of transient electron-hole pairs. Electrons, due to their high mobility, can be quickly collected by external circuitry, while holes, due to their extremely low mobility and lack of effective dissipation channels, tend to accumulate at the gallium nitride buffer layer and heterojunction interface. This invention utilizes an aluminum gallium nitride polarization-induced hole transport layer, employing its built-in polarization electric field to vertically pull excess holes to this layer. Then, through a three-dimensional hole extraction network composed of deep trench electrodes on the resistive side and the HEMT side, driven by an external negative bias voltage, the holes accumulated in the aluminum gallium nitride polarization-induced hole transport layer are rapidly extracted to the outside of the device. This vertically layered charge management strategy fundamentally solves the problem of radiation-induced hole accumulation inside the device, effectively suppressing threshold voltage drift caused by the back-gate effect and the sudden drop in 2DEG resistor value, ensuring the stability of logic swing and noise margin of the logic circuit structure under irradiation conditions, and significantly improving the device's resistance to single-event burn-out. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of one side of the radiation-resistant GaN logic circuit structure provided in Embodiment 1 of the present invention;

[0028] Figure 2 yes Figure 1 A structural diagram of the other side;

[0029] Figure 3 yes Figure 1 A top-view structural diagram;

[0030] Figure 4 This is a schematic diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 1 of the present invention during fabrication step 1;

[0031] Figure 5 This is a schematic diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 1 of the present invention during fabrication step 2;

[0032] Figure 6 This is a schematic diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 1 of the present invention during fabrication step 3;

[0033] Figure 7 This is a schematic diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 1 of the present invention during fabrication step 4;

[0034] Figure 8 This is a schematic diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 1 of the present invention during fabrication step 5;

[0035] Figure 9 This is a schematic diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 1 of the present invention during fabrication step 6;

[0036] Figure 10 This is a flowchart of the manufacturing method provided in the embodiments of the present invention;

[0037] Figure 11 This is a three-dimensional structural schematic diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 2 of the present invention;

[0038] Figure 12 This is a top view schematic diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 2 of the present invention;

[0039] Figure 13 This is a three-dimensional structural diagram of the radiation-resistant GaN logic circuit structure provided in Embodiment 3 of the present invention.

[0040] In the diagram: 1-Substrate; 2-Aluminum nitride nucleation layer; 3-Gallium nitride buffer layer; 4-Aluminum gallium nitride polarization-induced hole transport layer; 5-Gallium nitride channel layer; 6-Barrier layer; 61-2DEG resistor region; 62-Enhancement-mode Schottky gate GaN HEMT region; 63-Fully isolated region; 64-Sub-isolated region; 611-High-resistivity isolated region; 612-Active region; 613-Field region; 6121-Resistor sub-region; 7-Drain ohmic electrode; 71-Third ohmic metal layer; 72-Third interconnect metal layer; 8-Gate; 81-P-type gallium nitride strip; 82-Schottky metal layer; 83-Gate interconnect metal pillar; 84-Gate top metal layer; 9-Source ohmic electrode; 91-Source ohmic metal layer; 92-Source interconnect metal pillar; 93-Source top metal layer; 10-HEMT side deep trench electrode; 10 1-Fifth Ohmic Metal Layer; 102-Fifth Interconnect Metal Layer; 103-Fifth Top Metal Layer; 11-Resistor-Side Deep Trench Electrode; 111-Fourth Ohmic Metal Layer; 112-Fourth Interconnect Metal Layer; 12-Resistor High Voltage Electrode; 121-First Ohmic Metal Layer; 122-First Interconnect Metal Layer; 123-First Top Metal Layer; 13-Resistor Output Electrode; 131-Second Ohmic Metal Layer; 132-Second Interconnect Metal Layer; 133-Second Top Metal Layer; 14-First Interconnect Metal Pillar; 15-Second Interconnect Metal Pillar; 16-Ohmic Metal Pillar. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0042] like Figures 1 to 9 As shown, based on the above-mentioned defects, this embodiment of the invention provides a radiation-resistant GaN logic circuit structure. This GaN logic circuit structure is based on the excellent radiation resistance characteristics of the GaN material system. Through innovative epitaxial structure design and device layout, a highly efficient deep carrier transport and extraction network is constructed to solve the reliability problems of existing GaN RTL inverters caused by hole accumulation in the strong radiation environment of space, such as threshold drift, resistance fluctuation and single-event burn-out.

[0043] Example 1:

[0044] Specifically, the radiation-resistant GaN logic circuit structure of this embodiment includes, from bottom to top, a substrate layer 1, an aluminum nitride nucleation layer 2, a gallium nitride buffer layer 3, an aluminum gallium nitride polarization-induced hole transport layer 4, a gallium nitride channel layer 5, and a barrier layer 6. The substrate layer 1 provides mechanical support for the entire device and can be made of insulating or semi-insulating materials such as sapphire, silicon carbide, or silicon. For example, in this embodiment, a sapphire substrate is used for the substrate layer 1, with a thickness of approximately 0.65 mm. The aluminum nitride nucleation layer 2 grows above the substrate layer 1 to alleviate lattice and thermal mismatch between the substrate and the gallium nitride material above it, improving the crystal quality of the epitaxial layer. The gallium nitride buffer layer 3 grows above the aluminum nitride nucleation layer 2 to further improve crystal quality and provide a high-resistance isolation layer to prevent leakage current. The aluminum gallium nitride polarization-induced hole transport layer 4 grows above the gallium nitride buffer layer 3, and its core function is to induce a three-dimensional hole gas (3DHG) within the layer through polarization effects, serving as a horizontal transport path for radiation-induced holes. Gallium nitride (GaN) channel layer 5 is grown above aluminum gallium nitride (AlGaN) polarization-induced hole transport layer 4, providing a conductive channel for the two-dimensional electron gas (2DEG). Barrier layer 6 is grown above GaN channel layer 5, forming a heterojunction with GaN channel layer 5, and generating a high concentration of two-dimensional electron gas at the interface using spontaneous polarization and piezoelectric polarization effects.

[0045] In the aforementioned epitaxial structure, the aluminum gallium nitride (AGaN) polarization-induced hole transport layer 4 is an AGaN layer. The aluminum composition of the AGaN polarization-induced hole transport layer 4 decreases linearly from the gallium nitride buffer layer 3 towards the gallium nitride channel layer 5. Specifically, the aluminum composition decreases linearly from 0.2 at the lower surface contacting the top of the gallium nitride buffer layer 3 to 0 at the upper surface contacting the bottom of the gallium nitride channel layer 5. The core principle of this aluminum composition gradient design is that the spatial gradient change in aluminum composition generates spontaneous polarization and piezoelectric polarization gradients along the growth direction within the layer, thereby inducing distributed negative polarization charges and forming a three-dimensional hole gas within the layer. This three-dimensional hole gas provides a high-mobility lateral transport channel for excess holes generated by irradiation, enabling holes to be quickly guided to the deep trench electrode at the edge of the device for active extraction. This design achieves physical isolation between electron flow and hole flow in vertical space: the logic signal current of the circuit structure flows horizontally only in the 2DEG at the interface between the barrier layer 6 and the gallium nitride channel layer 5, while the excess holes induced by irradiation are drawn down to the deep aluminum gallium nitride polarization induced hole transport layer 4 by the built-in electric field, and the two do not interfere with each other.

[0046] Based on the aforementioned epitaxial structure, the GaN logic circuit structure of this embodiment has 2DEG resistor regions 61 and enhancement-mode Schottky gate GaN HEMT regions 62 arranged at intervals along the source-drain direction and isolated from each other. The 2DEG resistor regions 61 and the enhancement-mode Schottky gate GaN HEMT regions 62 together constitute the basic logic unit of an RTL inverter, where the 2DEG resistor region 61 serves as the load resistor and the enhancement-mode Schottky gate GaN HEMT regions 62 serve as the driving transistor. The 2DEG resistor regions 61 and the enhancement-mode Schottky gate GaN HEMT regions 62 are electrically connected to realize logic functions.

[0047] A drain ohmic electrode 7, a gate 8, a source ohmic electrode 9, and a deep trench electrode 10 are arranged at intervals along the source-drain direction on the surface of the enhancement-mode Schottky gate GaN HEMT region 62, gradually moving away from the 2DEG resistance region 61. The drain ohmic electrode 7 and the source ohmic electrode 9 are connected to the gallium nitride channel layer 5 to introduce external circuit signals into the 2DEG channel. The gate 8 is connected to the barrier layer 6 to control the on / off state of the GaN HEMT. The deep trench electrode 10 is connected to the gallium nitride buffer layer 3 and is etched downwards through the barrier layer 6, the gallium nitride channel layer 5, and the aluminum gallium nitride polarization-induced hole transport layer 4, reaching deep into the gallium nitride buffer layer 3 to form a bulk ohmic contact with the aluminum gallium nitride polarization-induced hole transport layer 4, thus constituting a hole exit port on the GaN HEMT side. The deep trench electrode 10 is located on the side of the source ohmic electrode 9 away from the gate 8, serving as the overall hole discharge outlet for the entire circuit structure.

[0048] A resistive deep trench electrode 11, connected to the gallium nitride buffer layer 3, is disposed on the surface of the 2DEG resistive region 61. The resistive deep trench electrode 11 is also etched downwards, penetrating the barrier layer 6, the gallium nitride channel layer 5, and the aluminum gallium nitride polarization-induced hole transport layer 4, extending into the interior of the gallium nitride buffer layer 3, forming a bulk ohmic contact with the aluminum gallium nitride polarization-induced hole transport layer 4. The resistive deep trench electrode 11 and the HEMT-side deep trench electrode 10 are bridged, that is, electrically connected in parallel to the same potential through an interconnect metal.

[0049] The aforementioned deep trench electrode 11 on the resistive side and deep trench electrode 10 on the HEMT side together constitute a three-dimensional hole extraction network. During operation, a lateral electric field is established deep within the device by applying a negative bias voltage to the top metal of the deep trench electrode 10 on the HEMT side. When high-energy particles are incident on the device to excite transient electron-hole pairs, the holes are first drawn vertically to the layer by the built-in electric field of the aluminum gallium nitride polarization-induced hole transport layer 4. Subsequently, driven by the lateral electric field established by the negative bias voltage of the deep trench electrode, they are rapidly extracted to the outside of the device along the three-dimensional hole gas channel. This design not only provides an efficient extraction and transport channel for holes generated by the single-event effect, but also significantly shortens the hole residence time through active negative pressure, effectively preventing hole accumulation at the bottom of the active region, mitigating threshold voltage drift caused by the back-gate effect and fluctuations in the 2DEG resistor value, and improving the GaN RTL inverter's resistance to single-event burnout and switching stability.

[0050] Furthermore, a fully isolated region 63, formed by implanting high-energy ions, is disposed between the 2DEG resistive region 61 and the enhancement-mode Schottky gate GaN HEMT region 62. The fully isolated region 63 extends longitudinally into the gallium nitride buffer layer 3. Specifically, the fully isolated region 63 is formed by implanting high-energy nitrogen ions into a designated area. The implantation depth penetrates the aluminum gallium nitride polarization-induced hole transport layer 4 and extends into the gallium nitride buffer layer 3. By disrupting the crystal structure, a high-resistivity region is formed, thereby completely severing the electron channel and bottom hole transport channel between the 2DEG resistive region 61 and the enhancement-mode Schottky gate GaN HEMT region 62 electrically, achieving complete insulation isolation between the two functional regions. For example, the implantation depth of the fully isolated region 63 is approximately 2.5 µm, and its width is 10 µm-15 µm. The full isolation region 63 ensures the electrical independence of the 2DEG resistor region 61 and the enhanced Schottky gate GaN HEMT region 62, avoiding crosstalk and leakage between the two functional regions and guaranteeing the correctness and stability of the inverter logic function.

[0051] Furthermore, multiple resistor-side deep trench electrodes 11 are provided, which are bridged to the HEMT-side deep trench electrode 10. These multiple resistor-side deep trench electrodes 11 are arranged at intervals along a direction perpendicular to the source-drain direction. By providing multiple resistor-side deep trench electrodes 11 and distributing them at intervals along a direction perpendicular to the source-drain direction, the number and coverage of hole emission ports can be increased. This allows excess holes generated by irradiation below the 2DEG resistor region 61 to be captured by multiple deep trench electrodes nearby, shortening the lateral drift distance of holes and improving hole emission efficiency.

[0052] Furthermore, the 2DEG resistance region 61 is divided into an active region 612 and multiple field regions 613 by a high-resistance isolation region 611 formed by high-energy ion implantation. The high-resistance isolation region 611 extends along the source-drain direction and longitudinally into the interior of the gallium nitride channel layer 5. The high-resistance isolation region 611 is formed by high-energy ion implantation, and its implantation depth remains inside the gallium nitride channel layer 5 to cut off the two-dimensional electron gas at the interface between the barrier layer 6 and the gallium nitride channel layer 5, forming lateral electron isolation. At the same time, it ensures that the implantation depth does not touch the underlying aluminum gallium nitride polarization-induced hole transport layer 4, so as to retain the electrical connectivity of this layer in the horizontal direction and maintain the integrity of the deep hole transport channel. For example, the implantation depth of the high-resistance isolation region 611 is 100nm-200nm, and the width is about 5µm.

[0053] A high-voltage resistor 12, connected to the gallium nitride channel layer 5, is disposed at the end of the active region 612 furthest from the enhancement-mode Schottky gate GaN HEMT region 62, for inputting a high-voltage signal for the entire device. A resistive output electrode 13, connected to the gallium nitride channel layer 5, is disposed at the end of the active region 612 closest to the enhancement-mode Schottky gate GaN HEMT region 62. The resistive output electrode 13 is bridged with the drain ohmic electrode 7, forming the output terminal of the circuit structure, thereby connecting the 2DEG resistive region 61 and the enhancement-mode Schottky gate GaN HEMT region 62 in series to realize an RTL inverting logic structure. Exemplarily, the 2DEG resistive region 61 can be formed into a high-resistivity 2DEG channel in the kiloohm range through low-dose ion implantation. The distance between the high-voltage resistor 12 and the resistive output electrode 13 is 20µm-200µm, resulting in a resistance value of 10kΩ-100kΩ for the active region 612.

[0054] Multiple resistor-side deep trench electrodes 11 are correspondingly disposed in multiple field regions 613, thereby constructing multiple hole extraction channels around the active region 612, so that holes generated by irradiation below the active region 612 can be extracted from multiple directions nearby.

[0055] Preferably, the 2DEG resistive region 61 includes an active region 612 and two field regions 613 symmetrically arranged on both sides of the active region 612 along a direction perpendicular to the source-drain direction. A resistive-side deep trench electrode 11 is disposed at the end of each field region 613 near the active region 612. The symmetrical arrangement of the two field regions 613 on both sides of the active region 612, with a resistive-side deep trench electrode 11 disposed at the end of each field region 613 near the active region 612, is to attract as many holes generated below the active region 612 during irradiation as possible. If a deep trench electrode is disposed on only one side, the hole extraction efficiency will significantly decrease because the holes need to drift a longer lateral distance to reach the electrode. The symmetrical arrangement minimizes the distance that holes generated at any position below the active region 612 need to travel to reach the nearest deep trench electrode, thereby maximizing the hole emission efficiency.

[0056] Furthermore, the high-voltage resistive electrode 12 includes a first ohmic metal layer 121, a first interconnect metal layer 122, and a first top metal layer 123 arranged from bottom to top. The first ohmic metal layer 121 is etched downwards to the upper surface of the gallium nitride channel layer 5 and forms an ohmic contact therewith for electrical connection with the 2DEG channel; the first interconnect metal layer 122 is grown above the first ohmic metal layer 121 for electrical interconnection between layers; the first top metal layer 123 is located at the topmost layer and serves as a top metal pad for the introduction and extraction of external signals.

[0057] The resistive output electrode 13 includes a second ohmic metal layer 131, a second interconnect metal layer 132, and a second top metal layer 133 arranged from bottom to top. The second ohmic metal layer 131 is also etched downwards to the upper surface of the gallium nitride channel layer 5 to form an ohmic contact therewith; the second interconnect metal layer 132 is grown above the second ohmic metal layer 131; the second top metal layer 133 is located on the topmost layer and serves as the top pad for the output terminal of the circuit structure.

[0058] The drain ohmic electrode 7 includes a third ohmic metal layer 71 and a third interconnect metal layer 72 arranged from bottom to top. The third ohmic metal layer 71 is etched downwards to the upper surface of the gallium nitride channel layer 5 to form an ohmic contact therewith. The second interconnect metal layer 132 and the third interconnect metal layer 72 are bridged by a first interconnect metal pillar 14, that is, the resistor output electrode 13 and the drain ohmic electrode 7 are electrically connected through the first interconnect metal pillar 14, together forming the output node of the circuit structure.

[0059] Furthermore, the resistor-side deep trench electrode 11 includes a fourth ohmic metal layer 111 and a fourth interconnect metal layer 112 arranged from bottom to top. The fourth ohmic metal layer 111 is etched downwards through the barrier layer 6, the gallium nitride channel layer 5, and the aluminum gallium nitride polarization-induced hole transport layer 4, reaching deep into the gallium nitride buffer layer 3, forming a bulk ohmic contact with the aluminum gallium nitride polarization-induced hole transport layer 4, thereby directly contacting and extracting hole carriers from the deep three-dimensional hole gas. Exemplarily, the etching depth of the fourth ohmic metal layer 111 is approximately 2µm-2.5µm downwards from the surface of the barrier layer 6. The fourth interconnect metal layer 112 is located above the fourth ohmic metal layer 111 and is used for bridging connections with the interconnect metal on the HEMT side.

[0060] The HEMT-side deep trench electrode 10 includes a fifth ohmic metal layer 101, a fifth interconnect metal layer 102, and a fifth top metal layer 103 arranged from bottom to top. The structure of the fifth ohmic metal layer 101 is similar to that of the fourth ohmic metal layer 111, also etched downwards through the barrier layer 6, the gallium nitride channel layer 5, and the aluminum gallium nitride polarization-induced hole transport layer 4, extending into the gallium nitride buffer layer 3 and forming a bulk ohmic contact with the aluminum gallium nitride polarization-induced hole transport layer 4. The fifth interconnect metal layer 102 is located above the fifth ohmic metal layer 101; the fifth top metal layer 103 is located at the topmost layer, serving as the final port of the hole extraction network in the entire circuit structure, used for applying an external negative bias voltage to achieve active hole extraction.

[0061] The fourth interconnect metal layer 112 is bridged with the fifth interconnect metal layer 102 through the second interconnect metal pillar 15, thereby connecting the resistor-side deep trench electrodes 11 on both sides of the 2DEG resistor region 61 and the HEMT-side deep trench electrodes 10 on the side of the enhancement-mode Schottky gate GaN HEMT region 62 to the same potential, thus constructing a complete three-dimensional hole discharge network.

[0062] The gate 8 includes, from bottom to top, a P-type gallium nitride strip 81, a Schottky metal layer 82, two gate interconnect metal pillars 83 disposed at both ends of the Schottky metal layer 82 perpendicular to the source-drain direction, and a top gate metal layer 84 above the gate interconnect metal pillars 83. The P-type gallium nitride strip 81 is disposed above the barrier layer 6 of the gate region, and depletes the 2DEG below it through the built-in potential of the P-type gallium nitride, realizing the normally-off characteristic of the enhancement-mode GaN HEMT. The Schottky metal layer 82 and the P-type gallium nitride strip 81 form a Schottky contact, together constituting an enhancement-mode Schottky gate structure. The two gate interconnect metal pillars 83 are symmetrically disposed above both ends of the Schottky metal layer 82 perpendicular to the source-drain direction, and are used to lead the gate signal from the Schottky metal layer 82 to the top gate metal layer 84 above it, realizing the application and control of the gate voltage. For example, the thickness of the P-type gallium nitride strip 81 is approximately 100 nm.

[0063] The source ohmic electrode 9 includes a source ohmic metal layer 91 arranged from bottom to top, two source interconnect metal pillars 92 disposed at both ends of the source ohmic metal layer 91 perpendicular to the source-drain direction, and a source top metal layer 93 above the source interconnect metal pillars 92. The source ohmic metal layer 91 is etched downwards to the upper surface of the gallium nitride channel layer 5 to form an ohmic contact therewith. The two source interconnect metal pillars 92 are symmetrically disposed above the two ends of the source ohmic metal layer 91 perpendicular to the source-drain direction, and are used to lead the source signal to the source top metal layer 93 and connect to the ground signal.

[0064] It should be noted that the second interconnect metal pillar 15 passes between the two gate interconnect metal pillars 83 and the two source interconnect metal pillars 92. That is, the second interconnect metal pillar 15, used to connect the resistor-side deep trench electrode 11 and the HEMT-side deep trench electrode 10, spatially passes between the two gate interconnect metal pillars 83 and the two source interconnect metal pillars 92, bridging a long distance across the fully isolated region 63. This ingenious three-dimensional interconnect layout achieves the spatial coexistence of the deep hole discharge network and the surface logic circuit without increasing the horizontal area of ​​the device, fully utilizing the gap space between the gate and source interconnect metal pillars and improving the device's integration density.

[0065] For example, the length of the drain ohmic electrode 7, the length of the gate 8, and the length of the source ohmic electrode 9 are 100µm perpendicular to the source-drain direction, and the width is 1µm; the distance between the source ohmic electrode 9 and the gate 8 is 2µm; and the distance between the drain ohmic electrode 7 and the gate 8 is 4µm.

[0066] In this embodiment, the thickness of the aluminum nitride nucleation layer 2 ranges from 15nm to 25nm; the thickness of the gallium nitride buffer layer 3 ranges from 2µm to 3µm; the thickness of the aluminum gallium nitride polarization-induced hole transport layer 4 ranges from 100nm to 150nm; the thickness of the gallium nitride channel layer 5 ranges from 200nm to 300nm; and the thickness of the barrier layer 6 ranges from 20nm to 25nm. The thickness ranges of these layers are optimized to ensure both the crystal quality of the epitaxial layer and the electrical performance of the device, while also providing sufficient etching depth for the deep trench electrode to reach the aluminum gallium nitride polarization-induced hole transport layer 4 and the gallium nitride buffer layer 3, thus ensuring the effectiveness of the three-dimensional hole extraction network.

[0067] The working principle of the radiation-resistant GaN logic circuit structure in this embodiment is as follows:

[0068] Under normal operating conditions, the logic signal current of the device flows horizontally only in the 2DEG at the interface between the barrier layer 6 and the gallium nitride channel layer 5. When a positive voltage higher than the threshold voltage is applied to the gate 8, the GaN HEMT is turned on, and the bridging node between the output resistive output electrode 13 and the drain ohmic electrode 7 is pulled low to near ground potential, achieving a logic low-level output. When a voltage lower than the threshold voltage or zero voltage is applied to the gate 8, the GaN HEMT is turned off, and the output is pulled high to near the power supply voltage through the 2DEG resistive region 61, achieving a logic high-level output, thereby completing the inverting logic function.

[0069] When the device operates in a high-radiation environment in space, high-energy particles incident on the device will excite a large number of transient electron-hole pairs. Among them, electrons can be quickly collected by external circuits due to their high mobility, while holes, due to their extremely low mobility and lack of effective dissipation channels, tend to accumulate at the gallium nitride buffer layer 3 and the heterojunction interface. This invention uses the aluminum gallium nitride polarization-induced hole transport layer 4 to longitudinally pull excess holes to this layer using its built-in polarization electric field; then, through a three-dimensional hole extraction network composed of the resistor-side deep trench electrode 11 and the HEMT-side deep trench electrode 10, the holes accumulated in the aluminum gallium nitride polarization-induced hole transport layer 4 are quickly extracted to the outside of the device under the drive of an external negative bias voltage. This vertically layered charge management strategy fundamentally solves the problem of radiation-induced holes accumulating inside the device, effectively suppresses threshold voltage drift caused by the back-gate effect and the sudden drop in 2DEG resistance, ensures the stability of the logic swing and noise margin of the device under irradiation, and significantly improves the device's resistance to single-event burn-out.

[0070] Figure 10 This is a flowchart of the manufacturing method provided in an embodiment of the present invention. Figure 10 As shown, this embodiment of the invention also provides a manufacturing method for manufacturing such as Figures 1 to 9 The radiation-resistant GaN logic circuit structure of Example 1 shown includes the following steps:

[0071] S1. On the epitaxial wafer, a substrate layer 1, an aluminum nitride nucleation layer 2, a gallium nitride buffer layer 3, an aluminum gallium nitride polarization induced hole transport layer 4, a gallium nitride channel layer 5, a barrier layer 6, and a P-type gallium nitride layer are grown sequentially from bottom to top. The P-type gallium nitride layer in the non-patterned area is removed by etching to form a P-type gallium nitride stripe 81 in the gate region.

[0072] Combination Figure 4 As shown, specifically, a sapphire substrate is selected as the substrate layer 1 for the epitaxial wafer, with a thickness of approximately 0.65 mm. On the substrate layer 1, a 20 nm aluminum nitride nucleation layer 2, a 2 µm gallium nitride buffer layer 3, a 100 nm aluminum gallium nitride polarization-induced hole transport layer 4, a 200 nm gallium nitride channel layer 5, a 20 nm barrier layer 6, and a 100 nm p-type gallium nitride layer are sequentially grown using metal-organic chemical vapor deposition (MOCVD). The aluminum gallium nitride polarization-induced hole transport layer 4 is an aluminum composition gradient layer, with the aluminum composition linearly decreasing from 0.2 to 0 from the lower surface in contact with the top of the gallium nitride buffer layer 3 to the upper surface in contact with the bottom of the gallium nitride channel layer 5. This is used to induce three-dimensional hole gas within the layer through polarization effects, constructing a deep hole transport channel.

[0073] Subsequently, the P-type gallium nitride layer outside the gate pattern is removed by inductively coupled plasma (ICP) dry etching, leaving the P-type gallium nitride strip 81 in the gate region. The P-type gallium nitride strip 81, together with the subsequently deposited Schottky metal layer 82, constitutes the gate structure of the enhancement-mode GaN HEMT. The built-in potential of the P-type gallium nitride depletes the 2DEG in the underlying channel, achieving the normally-off enhancement-mode characteristics of the HEMT. This step achieves complete growth of the entire device epitaxial structure, laying the material foundation for subsequent device fabrication.

[0074] S2. High-energy ions are injected into a designated area, and the injection depth is controlled to penetrate the aluminum gallium nitride polarization-induced hole transport layer 4 and reach the interior of the gallium nitride buffer layer 3, forming a fully isolated region 63 that completely cuts off the electron and hole channels, so as to separate the 2DEG resistance region 61 and the enhancement-mode Schottky gate GaN HEMT region 62.

[0075] Combination Figure 5 As shown, specifically, the fully isolated region 63 serves as the boundary, with a 2DEG resistance region 61 on one side and an enhancement-mode Schottky gate GaN HEMT region 62 on the other. High-energy nitrogen ions are implanted into the fully isolated region 63 using an ion implantation method, with the implantation depth controlled to reach the interior of the gallium nitride buffer layer 3, thereby disrupting the crystal structure to form a high-resistivity region. The ion-implanted region covers the barrier layer 6, gallium nitride channel layer 5, aluminum gallium nitride polarization-induced hole transport layer 4, and part of the gallium nitride buffer layer 3 within the fully isolated region 63, thus electrically completely severing the electron channel and bottom hole transport channel between the 2DEG resistance region 61 and the enhancement-mode Schottky gate GaN HEMT region 62. For example, the implantation depth of the fully isolated region 63 is approximately 2.5 µm, and its width is 10 µm-15 µm. This step achieves complete electrical isolation between the two functional regions through deep ion implantation, avoiding signal crosstalk and charge leakage between the 2DEG resistor region 61 and the enhancement-mode Schottky gate GaN HEMT region 62, thus ensuring the correctness of the inverter's logic function.

[0076] S3. High-energy ions are injected into the 2DEG resistance region 61, and the injection depth is controlled to penetrate the barrier layer 6 and reach the gallium nitride channel layer 5 to form a high-resistance isolation region 611 to separate the active region 612 and two field regions 613 symmetrically arranged on both sides of the active region 612 along the direction perpendicular to the source and drain direction.

[0077] Combination Figure 6As shown, specifically, firstly, low-dose lattice-damage ion implantation with nitrogen ions is performed in the 2DEG resistance region 61. By precisely controlling the implantation dose, the sheet resistance is precisely adjusted, enabling the 2DEG resistance region 61 to form a high-resistivity 2DEG channel on the order of kiloohms. For example, the sheet resistance is approximately 500Ω. Subsequently, the active region 612 is defined, and a high-resistivity isolation region 611 is delineated. High-energy nitrogen ions are implanted into the high-resistivity isolation region 611 using an ion implantation method. The implantation depth is strictly controlled to reach the middle of the gallium nitride channel layer 5, destroying the 2DEG at the interface between the barrier layer 6 and the gallium nitride channel layer 5, forming lateral insulation. At the same time, it is ensured that the implantation depth does not touch the underlying aluminum gallium nitride polarization-induced hole transport layer 4 to preserve the integrity of the hole transport channel below this region. The ion implantation region is the barrier layer 6 and part of the gallium nitride channel layer 5 inside the high-resistivity isolation region 611. For example, the implantation depth of the high-resistivity isolation region 611 is 100nm-200nm, and the width is approximately 5µm.

[0078] The key to this step is to precisely control the ion implantation depth: the implantation depth must be sufficient to cut off the surface 2DEG electron channel to achieve electrical definition and lateral isolation of the active region 612; at the same time, the implantation depth cannot be too deep, and it must ensure that the electrical connectivity of the aluminum gallium nitride polarization-induced hole transport layer 4 in the horizontal direction is not disrupted, so that the irradiation-induced holes below the active region 612 can still be laterally transported to the resistive side deep trench electrode 11 in the field region 613 through the three-dimensional hole gas channel, and finally extracted to the outside of the device.

[0079] S4. A dielectric layer is grown on the epitaxial wafer, and shallow contact holes and deep trench holes are formed by two etching processes: the first etching is carried out at both ends of the active region 612 along the source-drain direction and the enhancement-mode Schottky gate GaN HEMT region 62 to the interface of the gallium nitride channel layer 5 to form shallow holes; the second etching is carried out on the outer side of the high-resistivity isolation region 611 on both sides of the active region 612 near the field region 613 and on the side of the enhancement-mode Schottky gate GaN HEMT region 62 away from the 2DEG resistor region 61 to the gallium nitride buffer layer 3 to form deep trench holes. By depositing an ohmic metal layer and annealing at high temperature, a high-voltage resistor electrode 12, a resistor output electrode 13, a drain ohmic electrode 7, a source ohmic electrode 9, a resistor-side deep trench electrode 11 and a HEMT-side deep trench electrode 10 are formed.

[0080] Combination Figure 7As shown, specifically, a silicon nitride dielectric layer is grown on the entire epitaxial wafer using plasma-enhanced chemical vapor deposition (PECVD). This dielectric layer serves as surface passivation and protection. Subsequently, two photolithography and inductively coupled plasma (ICP) dry etching processes are used to create contact holes of two different depths. The first etching forms shallow contact holes: at the two ends of the active region 612 along the source-drain direction, corresponding to the positions of the high-voltage resistor 12 and the output resistor 13, respectively, and at the source-drain regions of the enhancement-mode Schottky gate GaN HEMT region 62, corresponding to the positions of the drain ohmic electrode 7 and the source ohmic electrode 9, respectively, the dielectric layer and the barrier layer 6 are etched downwards to the interface of the gallium nitride channel layer 5 to form shallow contact holes. The second etching forms deep trench holes: in the field region 613 outside the high-resistivity isolation region 611 on both sides of the active region 612, corresponding to the position of the deep trench electrode 11 on the resistor side, and in the source ohmic electrode 9 in the enhancement-mode Schottky gate GaN HEMT region 62, on the side away from the gate 8, corresponding to the position of the deep trench electrode 10 on the HEMT side, the etching penetrates the barrier layer 6, the gallium nitride channel layer 5 and the aluminum gallium nitride polarization-induced hole transport layer 4 and enters the interior of the gallium nitride buffer layer 3 to form deep trench hole exit holes.

[0081] Subsequently, an ohmic metal layer is deposited sequentially on the epitaxial wafer. For example, the material of the ohmic metal layer is Ti / Al 300nm / 700nm. The metal in the non-patterned area is removed by photolithography lift-off and high-temperature rapid thermal annealing is performed in a nitrogen atmosphere. At the same time, a shallow contact area is formed for the resistive high voltage electrode 12, the resistive output electrode 13, the drain ohmic electrode 7, and the source ohmic electrode 9 that are in contact with the gallium nitride channel layer 5, as well as the resistive side deep trench electrode 11 and the HEMT side deep trench electrode 10 that are filled in the deep trench and have ohmic contact with the aluminum gallium nitride polarization induced hole transport layer 4.

[0082] This step, through two etching processes at different depths, simultaneously forms the surface ohmic contact electrode and the deep hole extraction electrode in the same metal deposition step, simplifying the process flow. The deep trench electrode penetrates to the aluminum gallium nitride polarization-induced hole transport layer 4 and forms a bulk ohmic contact with it, ensuring a direct electrical connection between the deep three-dimensional hole gas channel and the external circuit, providing a physical basis for effective hole extraction.

[0083] S5. Re-grow the dielectric layer by etching and depositing a Schottky metal layer 82 over the P-type gallium nitride strip 81 to form the gate 8.

[0084] Combination Figure 8As shown, specifically, a silicon nitride dielectric layer is grown again on the entire epitaxial wafer. The silicon nitride dielectric layer is etched above the P-type gallium nitride strip 81 in the gate region, and the gate metal is sequentially deposited by electron beam evaporation. For example, the gate metal material is Ni / Al 100nm / 400nm. The metal outside the gate pattern area is removed by photolithography to form a Schottky metal layer 82. The Schottky metal layer 82 and the underlying P-type gallium nitride strip 81 together constitute the gate 8 structure of the enhancement-mode GaN HEMT. A Schottky contact is formed between the Schottky metal layer 82 and the P-type gallium nitride strip 81. The built-in potential of the P-type gallium nitride is used to increase the threshold voltage of the channel below the gate, realizing the enhancement-mode normally-off operating characteristic and ensuring that the device is in the off state when the gate is zero-biased, meeting the safety requirements of aerospace-grade circuits.

[0085] S6. A dielectric layer is grown again, and interconnect metal is etched and deposited above the high voltage electrode 12, the output electrode 13, the drain ohmic electrode 7, the gate 8, the source ohmic electrode 9, the resistor-side deep trench electrode 11, and the HEMT-side deep trench electrode 10 to achieve bridging between the resistor-side deep trench electrode 11 and the HEMT-side deep trench electrode 10, as well as between the resistor output electrode 13 and the drain ohmic electrode 7.

[0086] Combination Figure 9 As shown, specifically, a thick silicon nitride dielectric layer is grown on the epitaxial wafer, and photolithography and inductively coupled plasma dry etching are used to expose the surfaces of each electrode. Specifically, the high-voltage resistor 12, the output resistor 13, the drain ohmic electrode 7, the resistor-side deep trench electrode 11, and the HEMT-side deep trench electrode 10 expose their entire surfaces; the gate electrode 8 exposes the surfaces of the Schottky metal layer 82 perpendicular to the source-drain direction at both ends to form the gate interconnect metal pillar 83; the source ohmic electrode 9 exposes the surfaces of the source ohmic metal layer 91 perpendicular to the source-drain direction at both ends to form the source interconnect metal pillar 92.

[0087] Subsequently, interconnect metal is deposited on the epitaxial wafer. For example, the interconnect metal material is Ti / Al 300nm / 700nm. The metal in the non-patterned areas is removed by photolithography lift-off to form the following interconnect structure: a first interconnect metal layer 122 on the high voltage resistor 12, a second interconnect metal layer 132 on the output resistor 13, a third interconnect metal layer 72 on the drain ohmic electrode 7, a fourth interconnect metal layer 112 on the resistor-side deep trench electrode 11, and a fifth interconnect metal layer 102 on the HEMT-side deep trench electrode 10; two gate interconnect metal pillars 83 on the gate 8 and two source interconnect metal pillars 92 on the source ohmic electrode 9; a first interconnect metal pillar 14 that physically connects the output resistor 13 and the drain ohmic electrode 7 to form the output voltage node of the circuit structure; and a second interconnect metal pillar 15 that connects the resistor-side deep trench electrode 11 and the HEMT-side deep trench electrode 10 in parallel over a long distance on both sides of the 2DEG resistor active region 612 to collect the hole charge captured by all the deep trench electrodes and construct a complete three-dimensional hole discharge network.

[0088] This step achieves two key electrical connections through the deposition of interconnect metal layers: First, the first interconnect metal pillar 14 bridges the resistive output electrode 13 with the drain ohmic electrode 7, forming the output node of the circuit structure and completing the construction of the RTL inverting logic circuit; Second, the second interconnect metal pillar 15 connects the deep trench electrodes distributed throughout the device in parallel to the same potential, forming a unified hole extraction network. The second interconnect metal pillar 15 is spatially positioned between the two gate interconnect metal pillars 83 and the two source interconnect metal pillars 92, cleverly utilizing the gap space between the gate and source interconnect metal pillars, achieving spatial coexistence of the deep hole discharge network and the surface logic circuit without increasing the device area.

[0089] S7. A dielectric layer is grown again. Thick aluminum metal is etched and deposited above the high voltage electrode 12, the output electrode 13, the gate 8, the source ohmic electrode 9, and the HEMT side deep trench electrode 10 as the top layer metal. The top layer metal pads are formed by photolithography lift-off method and used to bring out the signal ports of each circuit structure and the final port of the hole lead-out network.

[0090] Combination Figures 1 to 3As shown, specifically, a silicon nitride dielectric layer is grown integrally on the epitaxial wafer. In areas requiring external interconnection, the formed silicon nitride dielectric layer is etched up to the top surface of the interconnect metal layer. For example, 4000nm aluminum is deposited as the top layer metal, and top layer metal pads are formed in the corresponding areas using photolithography lift-off. Specifically, a first top layer metal layer 123 is formed above the high-voltage electrode 12 of the resistor as the high-voltage input terminal of the circuit structure; a second top layer metal layer 133 is formed above the output electrode 13 of the resistor as the output terminal pad of the circuit structure; a gate top layer metal layer 84 is formed above the gate interconnect metal pillar 83 of the gate 8 as the gate signal input terminal; a source top layer metal layer 93 is formed above the source interconnect metal pillar 92 of the source ohmic electrode 9 as the ground signal connection terminal; and a fifth top layer metal layer 103 is formed above the HEMT-side deep trench electrode 10 as the final port of the hole extraction network of the entire circuit structure, used for applying an external negative bias voltage to drive the active extraction of holes.

[0091] This step completes the final outlining of all signal ports and hole exit ports in the circuit structure, allowing the device to connect to external packages and circuits via the top metal pads. The dielectric layer can be made of at least one of silicon dioxide, silicon nitride, or polyimide. In the radiation-resistant GaN logic circuit structure obtained by the above fabrication method, the blank areas from the top metal layer to the top surface of barrier layer 6 are filled with a dielectric layer, serving as interlayer insulation and surface passivation.

[0092] The fabrication method provided in this embodiment completes the entire fabrication process of the radiation-resistant GaN logic circuit structure in seven steps. The core features of this method are: epitaxial growth of the hole transport layer 4 induced by aluminum gallium nitride polarization with a gradient aluminum composition, constructing a three-dimensional hole gas transport channel within the device; precise division of functional regions is achieved by forming a fully isolated region 63 and a high-resistivity isolated region 611 through two ion implantations at different depths; surface ohmic contact electrodes and deep hole extraction electrodes are simultaneously formed through two etching processes at different depths and a unified metal deposition step; and a complete three-dimensional hole discharge network is constructed while realizing the inverter logic circuit connection through the layout design of the interconnect metal layers. The entire process is compatible with standard GaN HEMT manufacturing processes, requiring no additional special equipment or materials, and exhibits good process feasibility and cost-effectiveness.

[0093] Example 2:

[0094] Combination Figure 11 , Figure 12 As shown, the radiation-resistant GaN logic circuit structure of this embodiment differs from that of Embodiment 1 in that the active region 612 of the 2DEG resistor region 61 is improved in this embodiment to further improve the hole extraction efficiency.

[0095] Specifically, high-energy ion implantation is performed in the central region of the active region 612, which is perpendicular to the source / drain direction, to form a sub-isolation region 64 that penetrates the barrier layer 6, the gallium nitride channel layer 5, the aluminum gallium nitride polarization-induced hole transport layer 4, and extends into the gallium nitride buffer layer 3. This physically divides the original single active region 612 into two parallel resistive sub-regions 6121. The two resistive sub-regions 6121 are located on opposite sides of the sub-isolation region 64 and are connected in parallel through the metal layers at the high-voltage resistive electrode 12 and the output resistive electrode 13 at both ends of the active region 612. This achieves spatial division of the active region 612 without changing the total resistance value.

[0096] Meanwhile, a resistor-side deep trench electrode 11 is added between the two sub-isolation regions. The depth of the resistor-side deep trench electrode 11 is the same as that of the two existing resistor-side deep trench electrodes 11 in the field regions 613 on both sides of the active region 612. It is etched downwards to penetrate the aluminum gallium nitride polarization-induced hole transport layer 4 to the interior of the gallium nitride buffer layer 3, and is bridged with the HEMT-side deep trench electrode 10 through interconnect metal.

[0097] Compared to Example 1, the active region 612 in Example 1 has a larger width. If heavy ion bombardment occurs at the center of the active region 612, the generated holes need to drift laterally to the resistive deep trench electrodes 11 on both sides to be extracted. The drift path is long, resulting in low hole extraction efficiency. In this example, by dividing the active region 612 into two parallel resistive sub-regions 6121 and adding a hole extraction channel in the middle, the maximum lateral drift distance of holes below the active region is shortened by half. This allows irradiation-induced holes to be quickly captured and discharged by the nearest resistive deep trench electrode 11, further alleviating the problem of irradiation-induced 2DEG resistance reduction.

[0098] Example 3:

[0099] Combination Figure 13 As shown, the radiation-resistant GaN logic circuit structure of this embodiment differs from that of Embodiment 1 in that the bottom ohmic metal structure of the resistor-side deep trench electrode 11 and the HEMT-side deep trench electrode 10 in this embodiment is improved from a large-area plate-shaped ohmic metal to an array of hexagonal or cylindrical ohmic metal pillars 16.

[0100] Specifically, within the area originally planned as a deep trench electrode, multiple independent deep holes arranged in a tight array of regular hexagons or circles are formed using photolithography and etching processes. The depth of these deep holes is the same as the depth of the ohmic metal at the deep trench electrode in Example 1. The etching penetrates downwards through the aluminum gallium nitride polarization-induced hole transport layer 4 to the interior of the gallium nitride buffer layer 3. Subsequently, ohmic metal is deposited to fill these deep holes, forming an array of ohmic metal pillars 16. The upper ends of all the ohmic metal pillars 16 in each deep trench electrode area are connected into a whole by an interconnecting metal layer, achieving electrical parallel connection.

[0101] Compared to Example 1, which employs a large-area continuous deep-groove ohmic metal plate, this method is prone to generating significant mechanical stress due to the mismatch in thermal expansion coefficients between the metal and semiconductor materials during high-temperature processes or high-current operation. This stress could lead to epitaxial layer cracking or metal-filled voids, affecting device reliability and yield. In contrast, this example uses a hexagonal or cylindrical array structure, utilizing gallium nitride and aluminum gallium nitride materials retained between the metal pillars as a supporting framework. This effectively releases the thermomechanical stress caused by deep-groove metallization, improving the device's mechanical strength and the yield of deep-hole metal filling. Furthermore, the hexagonal or cylindrical array structure increases the total contact area between the ohmic metal and the aluminum gallium nitride polarization-induced hole transport layer 4, further enhancing the lateral collection rate of deep holes while maintaining low ohmic contact resistance, thus improving hole extraction efficiency.

[0102] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0103] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A radiation hard GaN logic circuit structure, characterized by, The circuit structure comprises, from bottom to top, a substrate layer (1), an aluminum nitride nucleation layer (2), a gallium nitride buffer layer (3), an aluminum gallium nitride polarization-induced hole transport layer (4), a gallium nitride channel layer (5), and a barrier layer (6). The circuit structure has a 2DEG resistor region (61) and an enhancement-mode Schottky gate GaN HEMT region (62) arranged at intervals along the source-drain direction and insulated from each other. The 2DEG resistor region (61) and the enhancement-mode Schottky gate GaN HEMT region (62) are electrically connected. The surface of the HEMT region (62) is provided with a drain ohmic electrode (7), a gate (8), a source ohmic electrode (9), and a HEMT-side deep trench electrode (10) arranged at intervals along the source-drain direction and gradually moving away from the 2DEG resistor region (61). The drain ohmic electrode (7) and the source ohmic electrode (9) are connected to the gallium nitride channel layer (5). The gate (8) is connected to the barrier layer (6). The HEMT-side deep trench electrode (10) is connected to the gallium nitride buffer layer (3). The surface of the 2DEG resistor region (61) is provided with a resistor-side deep trench electrode (11) connected to the gallium nitride buffer layer (3). The resistor-side deep trench electrode (11) and the HEMT-side deep trench electrode (10) are bridged.

2. The radiation-hardened GaN logic circuit structure of claim 1, wherein, The aluminum gallium nitride polarization-induced hole transport layer (4) is an aluminum gallium nitride layer. In the direction from the gallium nitride buffer layer (3) toward the gallium nitride channel layer (5), the aluminum composition of the aluminum gallium nitride polarization-induced hole transport layer (4) decreases linearly.

3. The radiation-resistant GaN logic circuit structure according to claim 1, characterized in that, A fully isolated region (63) formed by implanting high-energy ions is provided between the 2DEG resistive region (61) and the enhanced Schottky gate GaN HEMT region (62), and the fully isolated region (63) extends longitudinally into the interior of the gallium nitride buffer layer (3).

4. The radiation-resistant GaN logic circuit structure according to claim 3, characterized in that, Multiple resistor-side deep trench electrodes (11) are provided that are bridged with the HEMT-side deep trench electrode (10), and the multiple resistor-side deep trench electrodes (11) are arranged at intervals along a direction perpendicular to the source-drain direction.

5. The radiation-resistant GaN logic circuit structure according to claim 4, characterized in that, The 2DEG resistive region (61) is divided into an active region (612) and multiple field regions (613) by a high-resistance isolation region (611) formed by implanting high-energy ions. The high-resistance isolation region (611) extends along the source-drain direction and extends longitudinally into the interior of the gallium nitride channel layer (5). The active region (612) is provided with a high-voltage resistive electrode (12) connected to the gallium nitride channel layer (5) at one end away from the enhancement-mode Schottky gate GaN HEMT region (62). The active region (612) is provided with a high-voltage resistive electrode (13) connected to the gallium nitride channel layer (5) at one end near the enhancement-mode Schottky gate GaN HEMT region (62). The high-voltage resistive electrode (13) is bridged with the drain ohmic electrode (7). Multiple resistive deep trench electrodes (11) are correspondingly disposed in multiple field regions (613).

6. The radiation-resistant GaN logic circuit structure according to claim 5, characterized in that, The 2DEG resistor region (61) includes the active region (612) and two field regions (613) symmetrically arranged on both sides of the active region (612) along a direction perpendicular to the source-drain direction. The resistor-side deep trench electrode (11) is disposed at the end of the field region (613) near the active region (612).

7. The radiation-resistant GaN logic circuit structure according to claim 5, characterized in that, The high-voltage resistor (12) includes a first ohmic metal layer (121), a first interconnect metal layer (122) and a first top metal layer (123) arranged from bottom to top. The output resistor (13) includes a second ohmic metal layer (131), a second interconnect metal layer (132) and a second top metal layer (133) arranged from bottom to top. The drain ohmic electrode (7) includes a third ohmic metal layer (71) and a third interconnect metal layer (72) arranged from bottom to top. The second interconnect metal layer (132) and the third interconnect metal layer (72) are bridged by a first interconnect metal pillar (14).

8. The radiation-resistant GaN logic circuit structure according to claim 7, characterized in that, The resistor-side deep trench electrode (11) includes a fourth ohmic metal layer (111) and a fourth interconnect metal layer (112) arranged from bottom to top. The HEMT-side deep trench electrode (10) includes a fifth ohmic metal layer (101), a fifth interconnect metal layer (102), and a fifth top metal layer (103) arranged from bottom to top. The fourth interconnect metal layer (112) is bridged to the fifth interconnect metal layer (102) through a second interconnect metal pillar (15). The gate (8) includes a P-type gallium nitride strip (81) and a Schottky metal layer (82) arranged from bottom to top. The source ohmic electrode (9) includes a source ohmic metal layer (91) arranged from bottom to top, two source interconnect metal pillars (92) arranged at both ends of the source ohmic metal layer (91) perpendicular to the source drain direction, and a source top metal layer (93) above the source interconnect metal pillars (92). The second interconnect metal pillar (15) passes between the two gate interconnect metal pillars (83) and the two source interconnect metal pillars (92).

9. The radiation-resistant GaN logic circuit structure according to any one of claims 1 to 8, characterized in that, The thickness of the aluminum nitride nucleation layer (2) is 15nm-25nm; the thickness of the gallium nitride buffer layer (3) is 2µm-3µm; the thickness of the aluminum gallium nitride polarization-induced hole transport layer (4) is 100nm-150nm; the thickness of the gallium nitride channel layer (5) is 200nm-300nm; and the thickness of the barrier layer (6) is 20nm-25nm.

10. A method for fabricating the radiation-resistant GaN logic circuit structure as described in claim 8, characterized in that, include: Step 1: On the epitaxial wafer, a substrate layer (1), an aluminum nitride nucleation layer (2), a gallium nitride buffer layer (3), an aluminum gallium nitride polarization induced hole transport layer (4), a gallium nitride channel layer (5), a barrier layer (6), and a P-type gallium nitride layer are grown sequentially from bottom to top. The P-type gallium nitride layer in the non-patterned area is removed by etching to form a P-type gallium nitride strip (81) in the gate area. Step 2: Inject high-energy ions into the designated area, control the injection depth to penetrate the aluminum gallium nitride polarization-induced hole transport layer (4) and reach the interior of the gallium nitride buffer layer (3), forming a fully isolated region (63) that completely cuts off the electron and hole channels, so as to separate the 2DEG resistance region (61) and the enhancement-mode Schottky gate GaN HEMT region (62). Step 3: Implant high-energy ions into the 2DEG resistance region (61), control the implantation depth to penetrate the barrier layer (6) and reach the gallium nitride channel layer (5), forming a high-resistance isolation region (611) to separate the active region (612) and two field regions (613) symmetrically arranged on both sides of the active region (612) along the direction perpendicular to the source and drain direction. Step 4: A dielectric layer is grown on the epitaxial wafer. Shallow contact holes and deep trench holes are formed by two etching processes: First, shallow holes are formed at both ends of the active region (612) along the source-drain direction and at the interface of the enhancement-mode Schottky gate GaN HEMT region (62) to the gallium nitride channel layer (5); Second, deep trench holes are formed on the outer side of the high-resistivity isolation region (611) on both sides of the active region (612) near the field region (613) and on the side of the enhancement-mode Schottky gate GaN HEMT region (62) away from the 2DEG resistor region (61). The high-voltage resistor electrode (12), the output resistor electrode (13), the drain ohmic electrode (7), the source ohmic electrode (9), the resistor-side deep trench electrode (11), and the HEMT-side deep trench electrode (10) are formed by depositing an ohmic metal layer and annealing at high temperature. Step 5: Regrow the dielectric layer, and etch and deposit a Schottky metal layer (82) over the P-type gallium nitride strip (81) to form the gate (8); Step 6: Regrow the dielectric layer by etching and depositing interconnect metal over the high voltage electrode (12), the output electrode (13), the drain ohmic electrode (7), the gate (8), the source ohmic electrode (9), the resistor-side deep trench electrode (11), and the HEMT-side deep trench electrode (10) to achieve bridging between the resistor-side deep trench electrode (11) and the HEMT-side deep trench electrode (10), as well as between the resistor output electrode (13) and the drain ohmic electrode (7). Step 7: Regenerate the dielectric layer. Etch and deposit thick aluminum metal as the top layer metal above the high voltage electrode (12), the output electrode (13), the gate (8), the source ohmic electrode (9), and the HEMT side deep trench electrode (10). Form the top layer metal pads by photolithography lift-off method to bring out the signal ports of each circuit structure and the final port of the hole lead-out network.

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