Integrated circuit device and method of manufacturing the same

Abstract

Integrated circuit devices and methods of forming integrated circuit devices are provided. The integrated circuit device may include: a first transistor on a substrate; and a second transistor on the first transistor, where the first transistor is between the substrate and the second transistor in a vertical direction perpendicular to an upper surface of the substrate, where the first transistor includes: first channel layers spaced apart from each other in the vertical direction; and a first work function layer on the first channel layer, wherein the second transistor includes: second channel layers spaced apart from each other in a vertical direction; and a second work function layer on the second channel layer, wherein the second work function layer is spaced apart from the first channel layer.

Description

Technical Field

[0001] This disclosure generally relates to the field of integrated circuit devices, and more specifically to integrated circuit devices comprising stacked transistors. Background Technology

[0002] Various structures and methods for forming integrated circuit devices have been proposed to increase integration density. For example, stacked transistor structures, which include multiple transistors stacked vertically, have been proposed. Summary of the Invention

[0003] One aspect of this disclosure is to provide an integrated circuit device with improved electrical and reliability characteristics, and a method for manufacturing the integrated circuit device. More specifically, one aspect of this disclosure is to provide an integrated circuit device comprising a stacked transistor structure including a plurality of transistors and matching work function layers therewith to improve and optimize performance. However, it will be understood that the embodiments, objectives, and benefits of this disclosure are not limited to those described above.

[0004] According to some embodiments, an integrated circuit device may include: a first transistor on a substrate; and a second transistor on the first transistor, wherein the first transistor is located between the substrate and the second transistor in a vertical direction perpendicular to the upper surface of the substrate, wherein the first transistor includes: a first channel layer spaced apart from each other in the vertical direction; and a first work function layer on the first channel layer, wherein the second transistor includes: a second channel layer spaced apart from each other in the vertical direction; and a second work function layer on the second channel layer, wherein the second work function layer is spaced apart from the first channel layer.

[0005] According to some embodiments, an integrated circuit device may include: a first transistor on a substrate; a second transistor on the first transistor; and an insulator between the first transistor and the second transistor in a vertical direction perpendicular to the upper surface of the substrate, wherein the first transistor includes: a first channel layer spaced apart from each other in the vertical direction; and a first work function layer on the first channel layer, wherein the second transistor includes: a second channel layer spaced apart from each other in the vertical direction; and a second work function layer on the second channel layer, wherein the second work function layer is spaced apart from the first channel layer by the first work function layer.

[0006] According to some embodiments, a method of forming an integrated circuit device may include: forming a first stack including a first channel layer on a substrate and a second stack including a second channel layer on the first stack, wherein the first channel layers are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the second channel layers are spaced apart from each other in a vertical direction; forming an insulator between the first stack and the second stack in a vertical direction; forming a dummy layer extending around the first channel layer, the second channel layer and the insulator; replacing the upper portion of the dummy layer on the second channel layer with a first internal work function layer; replacing the lower portion of the dummy layer on the first channel layer with a second work function layer; and forming a first external work function layer on the first internal work function layer, the insulator and the second work function layer, wherein the first external work function layer is spaced apart from the first channel layer by the second work function layer. Attached Figure Description

[0007] Figure 1 It is a cross-sectional view of an integrated circuit device according to some implementation methods.

[0008] Figure 2 This is a flowchart of a method for forming an integrated circuit device according to some implementation methods.

[0009] Figures 3 to 19 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments. Figure 3 This is a cross-sectional view of an intermediate structure during an intermediate process (including the formation of an inter-gate sacrificial layer on the stack). Figure 4 This is a cross-sectional view of the intermediate structure during the intermediate process (including the removal of a portion of the inter-gate sacrificial layer and a portion of the stack). Figure 5 and Figure 6 This is a cross-sectional view of the intermediate structure during the intermediate process (including replacing the intergate sacrificial layer with an insulator). Figure 7 It is a cross-sectional view of the intermediate structure during the intermediate process (including the removal of the sacrificial layer). Figure 8 It is a cross-sectional view of the intermediate structure during the intermediate process (including the formation of the virtual layer). Figure 9 This is a cross-sectional view of the intermediate structure during the intermediate process that includes removing the external dummy digital layer. Figure 10 It is a cross-sectional view of the intermediate structure during the intermediate process (including the formation of the first barrier layer). Figure 11 It is a cross-sectional view of the intermediate structure during the intermediate process (including the removal of the upper internal dummy layer). Figure 12 It is a cross-sectional view of the intermediate structure during the intermediate process (including the removal of the first barrier layer). Figure 13 It is a cross-sectional view of the intermediate structure in the intermediate process (including the formation of the second preliminary work function layer). Figure 14 It is a cross-sectional view of the intermediate structure during the intermediate process (including the removal of the second external preliminary work function layer). Figure 15It is a cross-sectional view of the intermediate structure during the intermediate process (including the removal of the lower internal dummy layer). Figure 16 It is a cross-sectional view of the intermediate structure in the intermediate process (including the formation of the first preliminary work function layer). Figure 17 It is a cross-sectional view of the intermediate structure during the intermediate process (including the formation of the second barrier layer). Figure 18 It is a cross-sectional view of the intermediate structure during the intermediate process (including the removal of a portion of the first preliminary work function layer). Figure 19 This is a cross-sectional view of the intermediate structure during the intermediate process (including the removal of the second barrier layer). Detailed Implementation

[0010] According to the embodiments described herein, an integrated circuit device may include a stacked transistor structure comprising a first transistor (e.g., a lower transistor) and a second transistor (e.g., an upper transistor) vertically stacked on a substrate. The first transistor may include a first channel layer (e.g., a lower channel layer) spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate. The first transistor may further include a first work function layer (e.g., a lower work function layer) on the first channel layer. The first transistor may further include a first gate insulator (e.g., a lower gate insulator) between the first work function layer and the first channel layer, and a first gate electrode (e.g., a lower gate electrode) on the first work function layer. The second transistor may include a second channel layer (e.g., an upper channel layer) spaced apart from each other in a vertical direction. The second transistor may further include a second work function layer (e.g., an upper work function layer) on the second channel layer. The second transistor may further include a second gate insulator (e.g., an upper gate insulator) between the second work function layer and the second channel layer, and a second gate electrode (e.g., an upper gate electrode) on the second work function layer. In some embodiments, each of the first channel layer and each of the second channel layer may be a nanosheet or a nanowire. The integrated circuit device may further include an insulator (also referred to as an inter-gate insulator or intermediate dielectric separator) between a first transistor (e.g., a first channel layer) and a second transistor (e.g., a second channel layer) in a vertical direction. A first work function layer may include a first internal work function layer and a first external work function layer. The first internal work function layer may be located between (adjacent) first channel layers in the first channel layer in a vertical direction. A first external work function layer may extend around the first channel layer and the first internal work function layer. The first external work function layer may be located between the insulator and the uppermost first channel layer in the first channel layer in a vertical direction. The first external work function layer may be located between the substrate and the lowermost first channel layer in the first channel layer in a vertical direction. A second work function layer may include a second internal work function layer and a second external work function layer. The second internal work function layer may be located between (adjacent) second channel layers in the second channel layer in a vertical direction. The second external work function layer may extend around the first channel layer, the first work function layer, the second channel layer, the second internal work function layer, and the insulator. The first channel layer may be spaced apart from the second work function layer. For example, the first channel layer can be separated from the second work function layer by a first work function layer. In some embodiments, the second work function layer may have an interface between the second internal work function layer and the second external work function layer. In some embodiments, the first work function layer may not have an interface between the first internal work function layer and the first external work function layer. For example, the first work function layer may be a single monolithic structure. In some embodiments, the first internal work function layer and the first external work function layer may be formed simultaneously using the same process or a series of the same processes.In some implementations, the second internal work function layer and the second external work function layer can be formed by different processes or different series of processes.

[0011] The exemplary embodiments will be described in more detail with reference to the accompanying drawings.

[0012] Figure 1 This is a cross-sectional view of an integrated circuit device 10 according to some embodiments. (Refer to...) Figure 1 The integrated circuit device 10 may include a first transistor 112 (e.g., lower transistor 112) and a second transistor 114 (e.g., upper transistor 114) formed on a substrate 100. The first transistor 112 may be located between the substrate 100 and the second transistor 114 in a vertical direction perpendicular to the upper and / or lower surfaces of the substrate 100. In some embodiments, the centers (or central portions) of the first transistor 112 and the centers (or central portions) of the second transistor 114 may be misaligned or offset (in a horizontal direction parallel to the upper and / or lower surfaces of the substrate 100). The first transistor 112 and the second transistor 114 may have different or the same conductivity type. In some embodiments, the first transistor 112 may be an N-type transistor including an N-type source / drain region (not shown), and the second transistor 114 may be a P-type transistor including a P-type source / drain region (not shown). However, the inventive concept of the types of the first transistor 112 and the second transistor 114 is not limited to the embodiments described above. For example, the first transistor 112 may be a P-type transistor including a P-type source / drain region (not shown), and the second transistor 114 may be an N-type transistor including an N-type source / drain region (not shown).

[0013] Substrate 100 may include semiconductor materials such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP, and / or may include insulating materials such as silicon oxide, silicon oxide nitride, silicon nitride, silicon carbon nitride, and / or low-k materials. In some embodiments, substrate 100 may be a bulk substrate (e.g., a silicon wafer), a semiconductor-on-insulator (SOI) substrate, or an insulating layer (e.g., a monolithic insulating layer). Low-k materials may have a dielectric constant lower than that of silicon oxide (e.g., SiO). Low-k materials may include, for example, fluorine-doped silicon oxide, organosilicon glass, carbon-doped oxide, porous silica, porous organosilicon glass, spin-coated organic polymer dielectrics, and / or spin-coated silicon-based polymer dielectrics.

[0014] The first transistor 112 may include a first channel layer 102 (e.g., a lower channel layer 102) and a first work function layer 104 (e.g., a lower work function layer 104) on the first channel layer 102. Although Figure 1Not shown, but the first transistor 112 may further include a first gate insulator (e.g., a lower gate insulator) on the first channel layer 102 and a first gate electrode (e.g., a lower gate electrode) on the first work function layer 104. For example, the first gate insulator may be located between the first channel layer 102 and the first work function layer 104. The first gate insulator, the first work function layer 104, and the first gate electrode may be collectively referred to as the first gate structure (e.g., the lower gate structure).

[0015] The first channel layers 102 may be spaced apart from each other in the vertical direction. In some embodiments, the first channel layers 102 may be spaced apart from each other at equal or substantially equal distances in the vertical direction. In some embodiments, each of the first channel layers 102 may have equal or substantially equal widths in the horizontal direction. For example, each of the first channel layers 102 may have a first width W1 in the horizontal direction. Here, "substantially" may mean a deviation of no more than 10%. For example, when element X has a width of 10 nm and the width of element Y is substantially equal to the width of element X, the width of element Y may be no less than 9 nm or no more than 11 nm.

[0016] Although not in Figure 1 As shown, however, the first gate insulator may extend around the first channel layer 102 (e.g., at least partially around the first channel layer 102). The first work function layer 104 may extend around the first gate insulator (and the first channel layer 102) (e.g., at least partially around the first gate insulator (and the first channel layer 102)). The first gate electrode may extend around the first work function layer 104 (e.g., at least partially around the first work function layer 104).

[0017] In some embodiments, the first channel layer 102 may include a semiconductor material, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the first gate insulator may include an insulator, such as silicon oxide, silicon nitride, silicon nitride, silicon carbon nitride, and / or a low-k material having a dielectric constant lower than that of silicon oxide. In some embodiments, the first work function layer 104 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer. In some embodiments, the first gate electrode may include, for example, tungsten (W), aluminum (Al), and / or copper (Cu). However, the materials in the first channel layer 102, the first gate insulator, the first work function layer 104, and the first gate electrode are not limited to the embodiments described above. In some embodiments, the first gate insulator and the first gate electrode may be omitted.

[0018] The first work function layer 104 may include a first internal work function layer 104_I and a first external work function layer 104_O. The first internal work function layer 104_I may be located between adjacent first channel layers in the first channel layer 102 in the vertical direction. The first internal work function layer 104_I may also be located between the lowermost first channel layer in the first channel layer 102 and the substrate 100 in the vertical direction. For example, the first internal work function layer 104_I may be located on the lower surface of the lowermost first channel layer in the first channel layer 102 and on the upper surface of the substrate 100. The first external work function layer 104_O may be located between the uppermost first channel layer in the first channel layer 102 and the insulator 106 (described in detail later) in the vertical direction. For example, the first external work function layer 104_O may be located on the upper surface of the uppermost first channel layer in the first channel layer 102 and on the lower surface of the insulator 106. The first external work function layer 104_O may be located on the side surface of the first channel layer 102 and on the side surface of the first internal work function layer 104_I. In some implementations, the first external work function layer 104_O may extend around the first internal work function layer 104_I and the first channel layer 102 (e.g., at least partially around the first internal work function layer 104_I and the first channel layer 102).

[0019] In some embodiments, the first internal work function layer 104_I and the first external work function layer 104_O can be integrally formed (as a single structure or a monolithic structure) to constitute the first work function layer 104. For example, the first work function layer 104 can be a single monolithic structure. The first work function layer 104 may not have an interface between the first internal work function layer 104_I and the first external work function layer 104_O. The first work function layer 104 may be in contact with the first channel layer 102 and the insulator 106.

[0020] The second transistor 114 may include a second channel layer 108 (e.g., upper channel layer 108) and a second work function layer 110 (e.g., upper work function layer 110) on the second channel layer 108. Although Figure 1 Not shown, but the second transistor 114 may further include a second gate insulator (e.g., an upper gate insulator) on the second channel layer 108 and a second gate electrode (e.g., an upper gate electrode) on the second work function layer 110. For example, the second gate insulator may be located between the second channel layer 108 and the second work function layer 110. The second gate insulator, the second work function layer 110, and the second gate electrode may be collectively referred to as the second gate structure (e.g., the upper gate structure).

[0021] The second channel layers 108 may be spaced apart from each other in the vertical direction. In some embodiments, the second channel layers 108 may be spaced apart from each other at equal or substantially equal distances in the vertical direction. In some embodiments, each of the second channel layers 108 may have equal or substantially equal widths in the horizontal direction. For example, each of the second channel layers 108 may have a second width W2 in the horizontal direction. In some embodiments, the first width W1 of the first channel layer 102 may be greater than the second width W2 of the second channel layer 108.

[0022] Although not in Figure 1 As shown, however, the second gate insulator may extend around the second channel layer 108 (e.g., at least partially around the second channel layer 108). The second work function layer 110 may extend around the second gate insulator (e.g., at least partially around the second gate insulator). The second gate electrode may extend around the second work function layer 110 (e.g., at least partially around the second work function layer 110).

[0023] In some embodiments, the second channel layer 108 may include a semiconductor material, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the second gate insulator may include an insulator, such as silicon oxide, silicon nitride, silicon nitride, silicon carbon nitride, and / or a low-k material having a dielectric constant lower than that of silicon oxide. In some embodiments, the second work function layer 110 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer. In some embodiments, the second gate electrode may include, for example, tungsten (W), aluminum (Al), and / or copper (Cu). However, the materials in the second channel layer 108, the second gate insulator, the second work function layer 110, and the second gate electrode are not limited to the embodiments described above. In some embodiments, the second gate insulator and the second gate electrode may be omitted.

[0024] The second work function layer 110 may include a second internal work function layer 110_I and a second external work function layer 110_O. The second internal work function layer 110_I may be located between adjacent second channel layers in the second channel layer 108 in the vertical direction. The second internal work function layer 110_I may also be located between the lowermost second channel layer and the insulator 106 in the second channel layer 108 in the vertical direction. For example, the second internal work function layer 110_I may be located on the lower surface of the lowermost second channel layer in the second channel layer 108 and on the upper surface of the insulator 106. The second external work function layer 110_O may be located on the upper surface of the uppermost second channel layer in the second channel layer 108. The second external work function layer 110_O may be located on the side surface of the second channel layer 108 and the side surface of the second internal work function layer 110_I. In some embodiments, the second external work function layer 110_O may be on the first external work function layer 104_O and the upper surface of the substrate 100 (may be in contact with the first external work function layer 104_O and the upper surface of the substrate 100). In some embodiments, the second external work function layer 110_O may extend around the second internal work function layer 110_I and the second channel layer 108 (e.g., at least partially surrounding the second internal work function layer 110_I and the second channel layer 108). In some embodiments, the second external work function layer 110_O may extend around the insulator 106, the first work function layer 104, and the first channel layer 102 (e.g., at least partially surrounding the insulator 106, the first work function layer 104, and the first channel layer 102). For example, the second external work function layer 110_O may be in contact with the second internal work function layer 110_I, the second channel layer 108, the insulator 106, the first external work function layer 104_O, and / or the substrate 100. In some embodiments, the second external work function layer 110_O may extend around (e.g., at least partially around) the first transistor 112 and the second transistor 114. In some embodiments, the second work function layer 110 may be spaced apart from the first channel layer 102. For example, the second work function layer 110 may be spaced apart from the first channel layer 102 by the first work function layer 104.

[0025] An insulator 106 (also referred to as inter-gate insulator 106 or intermediate dielectric separator 106) may be located between the first transistor 112 and the second transistor 114 in a vertical direction. For example, the insulator 106 may be located between the first channel layer 102 and the second channel layer 108 in a vertical direction. In some embodiments, the insulator 106 may be located on a first work function layer 104 (e.g., a first external work function layer 104_O). For example, the upper surface of the first work function layer 104 (e.g., the upper surface of the first external work function layer 104_O) may be located on the lower surface of the insulator 106 (e.g., may contact the lower surface of the insulator 106). In some embodiments, the insulator 106 may be located on a second internal work function layer 110_I. For example, the lower surface (e.g., the lowest surface) of the second internal work function layer 110_I may be located on the upper surface of the insulator 106 (e.g., may contact the upper surface of the insulator 106).

[0026] In some embodiments, the second work function layer 110 may include an interface 110_IF between the second inner work function layer 110_I and the second outer work function layer 110_O. For example, the second inner work function layer 110_I may be defined by the second outer work function layer 110_O, with the interface 110_IF therebetween. In some embodiments, the second inner work function layer 110_I may have a third width W3 in the horizontal direction. The third width W3 may be smaller than the second width W2 of the second channel layer 108. For example, the interface 110_IF of the second work function layer 110 may overlap with the second channel layer 108 in the vertical direction. For example, a portion of the second outer work function layer 110_O may protrude horizontally toward the second inner work function layer 110_I, which in the vertical direction is between adjacent second channel layers in the second channel layer 108 and / or between the lowermost second channel layer in the second channel layer 108 and the insulator 106.

[0027] Insulator 106 may be in contact with the first work function layer 104 and the second work function layer 110. For example, insulator 106 may be in contact with the first external work function layer 104_O, the second internal work function layer 110_I, and the second external work function layer 110_O. Insulator 106 may include an insulator, such as a silicon nitride (e.g., SiN). However, the material of insulator 106 is not limited to this.

[0028] In some embodiments, the first internal work function layer 104_I and the first external work function layer 104_O may include the same material (e.g., a first material). In some embodiments, the second internal work function layer 110_I and the second external work function layer 110_O may include the same material (e.g., a second material). In some embodiments, the first material of the first work function layer 104 may be different from the second material of the second work function layer 110. In some embodiments, the second internal work function layer 110_I and the second external work function layer 110_O may include different materials. For example, the second internal work function layer 110_I may include a second material, and the second external work function layer 110_O may include a third material that is different from the first material of the first work function layer 104 and the second material of the second internal work function layer 110_I.

[0029] In some embodiments, each of the first channel layer 102 and the second channel layer 108 may be a nanosheet (which may have a thickness in the vertical direction ranging from 1 nm to 100 nm) or a nanowire (which may have a circular cross-section with a diameter ranging from 1 nm to 100 nm).

[0030] Although Figure 1 The diagram shows a first transistor 112 comprising two first channel layers 102, but in some embodiments, the first transistor 112 may include one or more first channel layers 102. Although Figure 1 The second transistor 114 is shown to include three second channel layers 108, but in some embodiments, the second transistor 114 may include one, two or more than three second channel layers 108.

[0031] Although Figure 1 Not shown, but the integrated circuit device 10 may also include a mid-process (MOL) structure and a back-process (BEOL) structure. Each of the MOL and BEOL structures may include an interlayer insulating layer providing conductive lines (e.g., metal lines) and conductive path plugs (e.g., metal path plugs). Various elements of the first transistor 112 and the second transistor 114 may be (electrically) connected to one of the wires in the MOL and BEOL structures.

[0032] Furthermore, in some embodiments, a back-side power distribution network structure (BSPDNS) may be provided below or within the substrate 100. In some embodiments, some components of the BSPDNS may be provided in the substrate 100. The BSPDNS may include a back-side insulating layer in which conductive back-side wires (e.g., metal power rails) and conductive back-side contacts (e.g., back-side metal contacts) are provided. Various elements of the first transistor 112 and the second transistor 114 may be (electrically) connected to one of the conductive back-side wires.

[0033] Figure 2 This is a flowchart illustrating a method for forming an integrated circuit device according to some implementation methods. For example, Figure 2 It is formed according to some implementation methods Figure 1 The flowchart shows the method of the integrated circuit device 10.

[0034] Figures 3 to 19 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments. For example, Figures 3 to 19 This illustrates the formation according to some embodiments. Figure 1 A cross-sectional view of the method of the integrated circuit device 10 shown.

[0035] Reference Figure 1 , Figure 2 and Figure 3 The method may include forming a first stack 318 (e.g., a lower stack 318) (202) on a substrate 100. The first stack 318 may include a first channel layer 102 and a first sacrificial layer 312 (e.g., a lower sacrificial layer 312). In some embodiments, the first channel layer 102 and the first sacrificial layer 312 may be stacked alternately in the vertical direction. In some embodiments, the first sacrificial layer 312 may include a material that has etch selectivity relative to the first channel layer 102. For example, the first sacrificial layer 312 may include SiGe.

[0036] Reference Figure 1 , Figure 2 and Figure 3 An inter-gate sacrificial layer 316 (also referred to as an intermediate sacrificial layer 316) can be formed on the first stack 318 (202). The first stack 318 may be located between the inter-gate sacrificial layer 316 and the substrate 100 in a vertical direction. In some embodiments, the inter-gate sacrificial layer 316 may include SiGe.

[0037] Reference Figure 1 , Figure 2 and Figure 3 A second stack 320 (e.g., upper stack 320) can be formed on the inter-gate sacrificial layer 316 (202). The inter-gate sacrificial layer 316 can be located between the first stack 318 and the second stack 320 in the vertical direction. The second stack 320 may include a second channel layer 108 and a second sacrificial layer 314 (e.g., upper sacrificial layer 314). In some embodiments, the second channel layer 108 and the second sacrificial layer 314 may be stacked alternately in the vertical direction. In some embodiments, the second sacrificial layer 314 may include a material that has etch selectivity relative to the second channel layer 108. For example, the second sacrificial layer 314 may include SiGe.

[0038] In some embodiments, the inter-gate sacrificial layer 316 may comprise a material having etch selectivity relative to the first channel layer 102, the first sacrificial layer 312, the second channel layer 108, and the second sacrificial layer 314. For example, the inter-gate sacrificial layer 316 may comprise SiGe having a different Ge concentration than the SiGe of the first sacrificial layer 312 and the second sacrificial layer 314. However, the materials of the first sacrificial layer 312, the second sacrificial layer 314, and the inter-gate sacrificial layer 316 are not limited to the embodiments described above.

[0039] Reference Figure 1 , Figure 2 and Figure 4 A portion of the second stack 320 and a portion of the inter-gate sacrificial layer 316 can be removed (e.g., etched) to expose a portion of the first stack 318 (a portion of the upper surface of the first stack 318) (204).

[0040] Reference Figure 1 , Figure 2 , Figure 5 and Figure 6 The inter-gate sacrificial layer 316 can be removed, and an insulator 106 can be formed in the space from which the inter-gate sacrificial layer 316 has been removed. In some embodiments, the inter-gate sacrificial layer 316 can be replaced by an insulator 106 (206). For example, since the inter-gate sacrificial layer 316 can be etched selectively relative to the first channel layer 102, the first sacrificial layer 312, the second channel layer 108, and the second sacrificial layer 314, the inter-gate sacrificial layer 316 can be selectively etched without etching the first stack 318 and the second stack 320. The insulator 106 can then be formed in the space from which the inter-gate sacrificial layer 316 has been removed. In some embodiments, the shape of the insulator 106 can be the same as or substantially the same as the shape of the inter-gate sacrificial layer 316 that has been removed.

[0041] Reference Figure 1 , Figure 2 and Figure 7 The first sacrificial layer 312 and the second sacrificial layer 314 (208) can be removed.

[0042] Reference Figure 1 , Figure 2 and Figure 8A dummy layer 822 may be formed on the first channel layer 102, the second channel layer 108, the insulator 106, and the substrate 100 (e.g., a dummy layer 822 may be formed to contact the first channel layer 102, the second channel layer 108, the insulator 106, and the substrate 100) (210). The dummy layer 822 may include aluminum oxide (e.g., AlO), but the material in the dummy layer 822 is not limited thereto. In some embodiments, the dummy layer 822 may extend around (at least partially around) each of the first channel layers 102, each of the second channel layers 108, and the insulator 106. The dummy layer 822 may include an inner dummy layer 822_I and an outer dummy layer 822_O. In some embodiments, the inner dummy layer 822_I may be located between adjacent first channel layers in the first channel layer 102 in the vertical direction, between adjacent second channel layers in the second channel layer 108 in the vertical direction, between the uppermost first channel layer in the first channel layer 102 and the insulator 106 in the vertical direction, between the lowermost second channel layer in the second channel layer 108 and the insulator 106 in the vertical direction, and between the lowermost first channel layer in the first channel layer 102 and the substrate 100 in the vertical direction. The outer dummy layer 822_O may extend around the inner dummy layer 822_I, the first channel layer 102, the second channel layer 108, and the insulator 106.

[0043] Reference Figure 1 , Figure 2 and Figure 9 The outer dummy layer 822_O (212) can be removed. In some embodiments, the substrate 100, the first channel layer 102, the insulator 106, and the second channel layer 108 can be stacked alternately with the inner dummy layer 822_I in the vertical direction. Here, the inner dummy layer 822_I between the insulator 106 and the substrate 100 in the vertical direction can be referred to as the lower inner dummy layer 822_I. On the other hand, the inner dummy layer 822_I between the insulator 106 and the uppermost second channel layer in the second channel layer 108 in the vertical direction can be referred to as the upper inner dummy layer 822_I. The dummy layer 822 (e.g., the outer dummy layer 822_O) can be removed by, for example, a diluted ammonia mixture (ADM) and / or standard clean 1 (SC1).

[0044] Reference Figure 1 , Figure 2 and Figure 10A first barrier layer 1024 may be formed on the first channel layer 102 and the lower internal dummy layer 822_I (e.g., the first barrier layer 1024 may be formed to contact the first channel layer 102 and the lower internal dummy layer 822_I) (214). For example, the first barrier layer 1024 may overlap the first channel layer 102 and the lower internal dummy layer 822_I in the horizontal and / or vertical directions. The first barrier layer 1024 may be formed on the substrate 100 and extend around the first channel layer 102 and the lower internal dummy layer 822_I (e.g., at least partially surrounding the first channel layer 102 and the lower internal dummy layer 822_I). In some embodiments, the first barrier layer 1024 may be on the insulator 106. For example, the first barrier layer 1024 may overlap the insulator 106 in the horizontal direction. The first barrier layer 1024 may extend around the insulator 106 (e.g., at least partially surrounding the insulator 106). In some embodiments, a portion of the insulator 106 (e.g., the upper portion) may be exposed from the first barrier layer 1024. The upper internal dummy layer 822_I and the second channel layer 108 may also be exposed from the first barrier layer 1024. In some embodiments, a preliminary barrier layer may be formed on the substrate 100, the first channel layer 102, the second channel layer 108, and the internal dummy layer 822_I. The preliminary barrier layer may then be partially removed by a photolithography process (including, for example, forming a bottom anti-reflective coating (BARC), applying a photoresist (PR), exposure, and development) to form the first barrier layer 1024 exposing the second channel layer 108 and the upper internal dummy layer 822_I. The first barrier layer 1024 may include, but is not limited to, an organic planarization layer (OPL).

[0045] Reference Figure 1 , Figure 2 and Figure 11 The upper internal dummy layer 822_I (216) can be removed. For example, the upper internal dummy layer 822_I can be removed by an ashing process and / or a stripping process. The lower internal dummy layer 822_I can be retained because the first barrier layer 1024 protects the lower internal dummy layer 822_I.

[0046] Reference Figure 1 , Figure 2 and Figure 12 The first barrier layer 1024 (218) can be removed.

[0047] Reference Figure 1 , Figure 2 and Figure 13A second preliminary work function layer 1310 (220) can be formed on the first channel layer 102, the insulator 106, the second channel layer 108, the lower internal dummy layer 822_I, and the substrate 100. In some embodiments, the second preliminary work function layer 1310 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer. The second preliminary work function layer 1310 may include a second internal preliminary work function layer 1310_I and a second external preliminary work function layer 1310_O. The second internal preliminary work function layer 1310_I may be located between adjacent second channel layers in the second channel layer 108 in the vertical direction and between the lowermost second channel layer in the second channel layer 108 and the insulator 106 in the vertical direction. The second external preliminary work function layer 1310_O may be on (e.g., in contact with) the first channel layer 102, the lower internal dummy layer 822_I, the insulator 106, the second channel layer 108, the second internal preliminary work function layer 1310_I, and the substrate 100. For example, the second external preliminary work function layer 1310_O may extend around (e.g., at least partially around) the first channel layer 102, the lower internal dummy layer 822_I, the insulator 106, the second channel layer 108, and the second internal preliminary work function layer 1310_I.

[0048] Reference Figure 1 , Figure 2 and Figure 14 The second external preliminary work function layer 1310_O (222) can be removed. The second internal preliminary work function layer 1310_I can be retained as the second internal work function layer 110_I.

[0049] Reference Figure 1 , Figure 2 and Figure 15 This allows the removal of the lower internal virtual layer 822_I (224).

[0050] Reference Figure 1 , Figure 2 and Figure 16A first preliminary work function layer 1604 may be formed on the first channel layer 102, insulator 106, second channel layer 108, second internal work function layer 110_I, and substrate 100 (e.g., the first preliminary work function layer 1604 may be formed to contact the first channel layer 102, insulator 106, second channel layer 108, second internal work function layer 110_I, and substrate 100) (226). The first preliminary work function layer 1604 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer. In some embodiments, the first preliminary work function layer 1604 may include a material different from the material in the second preliminary work function layer 1310 (second internal work function layer 110_I). For example, the first preliminary work function layer 1604 may have physical, chemical, and / or electrical characteristics different from those of the second preliminary work function layer 1310. The first preliminary work function layer 1604 may include a first internal preliminary work function layer 1604_I and a first external preliminary work function layer 1604_O. The first internal preliminary work function layer 1604_I may be located between adjacent first channel layers in the first channel layer 102 in the vertical direction. The first external preliminary work function layer 1604_O may be located between the lowermost first channel layer in the first channel layer 102 and the substrate 100 in the vertical direction, and between the uppermost first channel layer in the first channel layer 102 and the insulator 106 in the vertical direction. The first external preliminary work function layer 1604_O may be located on (e.g., in contact with) the first channel layer 102, the first internal preliminary work function layer 1604_I, the insulator 106, the second channel layer 108, the second internal work function layer 110_I, and the substrate 100. For example, the first external preliminary work function layer 1604_O may extend around the first channel layer 102, the first internal preliminary work function layer 1604_I, the insulator 106, the second channel layer 108, and the second internal work function layer 110_I (e.g., at least partially around the first channel layer 102, the first internal preliminary work function layer 1604_I, the insulator 106, the second channel layer 108, and the second internal work function layer 110_I).

[0051] Reference Figure 1 , Figure 2 and Figure 17A second barrier layer 1726 (228) may be formed on the first channel layer 102 and the lower portion of the first preliminary work function layer 1604. For example, the second barrier layer 1726 may overlap the lower portions of the first channel layer 102, the first internal preliminary work function layer 1604_I, and the first external preliminary work function layer 1604_O in the horizontal and / or vertical directions. The second barrier layer 1726 may be formed on the substrate 100 and extend around the lower portions of the first channel layer 102, the first internal preliminary work function layer 1604_I, and the first external preliminary work function layer 1604_O (e.g., at least partially around the lower portions of the first channel layer 102, the first internal preliminary work function layer 1604_I, and the first external preliminary work function layer 1604_O). In some embodiments, the second barrier layer 1726 may be on the insulator 106. For example, the second barrier layer 1726 may overlap the insulator 106 in the horizontal direction. The second barrier layer 1726 may extend around (e.g., at least partially around) the insulator 106. In some embodiments, a portion of the insulator 106 (e.g., the upper portion) may be exposed from the second barrier layer 1726. The second internal work function layer 110_I and the second channel layer 108 may also be exposed from the second barrier layer 1726. In some embodiments, a preliminary barrier layer may be formed on the substrate 100, the first channel layer 102, the insulator 106, the second channel layer 108, the second internal work function layer 110_I, and the first preliminary work function layer 1604. The preliminary barrier layer may then be partially removed by a photolithography process (including, for example, forming a BARC, applying a PR, exposure, and development) to form the second barrier layer 1726, which exposes the upper portion of the second internal work function layer 110_I, the second channel layer 108, and the first preliminary work function layer 1604. The second barrier layer 1726 may be an organic planarization layer (OPL), but is not limited thereto.

[0052] Reference Figure 1 , Figure 2 and Figure 18 The upper portion (230) of the first preliminary work function layer 1604 can be removed (e.g., by wet etching). For example, the upper portion of the first outer preliminary work function layer 1604_O can be removed. The lower portion of the first preliminary work function layer 1604 can be retained to form a first work function layer 104 including a first inner work function layer 104_I and a first outer work function layer 104_O. In some embodiments, the upper portion of the first preliminary work function layer 1604 can be removed to expose the second channel layer 108, the second inner work function layer 110_I, the side surfaces of the insulator 106, and a portion of the upper surface of the first outer work function layer 104_O.

[0053] Reference Figure 1 , Figure 2and Figure 19 The second barrier layer 1726 (232) can be removed.

[0054] Reference Figure 1 and Figure 2 The second external work function layer 110_O can be formed on the second channel layer 108, the second internal work function layer 110_I, the insulator 106, the first work function layer 104 (e.g., the first external work function layer 104_O), and the substrate 100 (e.g., the second external work function layer 110_O can be formed to contact the second channel layer 108, the second internal work function layer 110_I, the insulator 106, the first work function layer 104 (e.g., the first external work function layer 104_O), and the substrate 100) (234). In some embodiments, the second internal work function layer 110_I can be recessed in the horizontal direction during the manufacturing process. For example, the side surface of the second internal work function layer 110_I can overlap the second channel layer 108 in the vertical direction. (See reference...) Figures 14 to 19 The described process causes the second internal work function layer 110_I to be recessed. However, the process that may cause the second internal work function layer 110_I to be recessed is not limited to the embodiments described above. After the second external work function layer 110_O is formed on the second internal work function layer 110_I, the side surface of the second internal work function layer 110_I may become the interface 110_IF between the second internal work function layer 110_I and the second external work function layer 110_O. In some embodiments, the second external work function layer 110_O may include a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer, but is not limited thereto. In some embodiments, the second internal work function layer 110_I and the second external work function layer 110_O may include the same material. However, embodiments of the inventive concept are not limited thereto. In some embodiments, the second internal work function layer 110_I may include a material different from the material in the second external work function layer 110_O (the material of the second external work function layer 110_O).

[0055] Reference Figure 1 , Figure 18 and Figure 19The removal (e.g., etching) target of the upper portion of the first preliminary work function layer 1604 (e.g., the upper portion of the first outer preliminary work function layer 1604_O) can be the same as or substantially the same as the thickness of the first preliminary work function layer 1604. In some embodiments, the removal target of the upper portion of the first preliminary work function layer 1604 may include the thickness of the first preliminary work function layer 1604 and an over-etch allowance. Unlike conventional processes, the removal (e.g., etching) target of the upper portion of the first preliminary work function layer 1604 can be smaller than the width of the second channel layer 108 in the horizontal direction. The process of removing the upper portion of the first preliminary work function layer 1604 may not form (may reduce) a path (e.g., an opening or trench) extending through the first channel layer 102 and the first work function layer 104 (or extending into the first channel layer 102 and the first work function layer 104) by over-etching, and the second work function layer 110 may be spaced apart from the first channel layer 102. For example, the second work function layer 110 can be spaced apart from the first channel layer 102 by the first work function layer 104. As a result, the integrated circuit device 10 can reduce potential wet etching damage (e.g., etching damage on the gate insulator). Furthermore, the boundary shift between the first transistor 112 and the second transistor 114 (e.g., the boundary shift between a P-type transistor and an N-type transistor) can be reduced. Consequently, the process margin of the integrated circuit device 10 can be improved (e.g., reducing or preventing losses in the first work function layer 104), and the performance of the multi-threshold voltage (Vth) structure of the integrated circuit device 10 (e.g., the Vth of the first transistor 112 and the Vth of the second transistor 114) can be improved. Additionally, since the first work function layer 104 does not need to be formed between adjacent second channel layers in the second channel layer 108 and is removed therefrom, potential unstrap defects between the second channel layers 108 can be reduced or prevented.

[0056] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of this disclosure, and therefore this disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the inventive concept to those skilled in the art. In the figures, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Unless explicitly stated otherwise, the same reference numerals may always refer to similar or identical elements.

[0057] Example embodiments are described herein with reference to cross-sectional diagrams, which are schematic illustrations of idealized embodiments and intermediate structures of the example embodiments. Accordingly, variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments herein should not be construed as limited to the specific shapes shown herein, but may include, for example, deviations in shape caused by manufacturing processes.

[0058] It should also be noted that in some alternative implementations, the functions / actions indicated in the flowchart boxes may not occur in the order shown in the flowchart. For example, depending on the functions / actions involved, two boxes shown consecutively may actually be executed substantially simultaneously, or these boxes may sometimes be executed in reverse order. Furthermore, the function of a given box in the flowchart and / or block diagram may be divided into multiple boxes, and / or the functions of two or more boxes in the flowchart and / or block diagram may be at least partially integrated. Finally, without departing from the scope of the inventive concept, other boxes may be added / inserted between the shown boxes, and / or boxes / operations may be omitted.

[0059] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0060] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0061] It will be understood that when a component is referred to as being “connected” to, “attached” to, or “in response to” or “on” another component, it can be directly connected to, directly connected to, or directly responded to or directly on the other component, or there may be intermediate components. Conversely, when a component is referred to as being “directly connected” to, “directly connected” to, or “directly responded to” or “on” another component, there are no intermediate components. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Furthermore, the symbol “ / ” (e.g., when used in the term “source / drain”) will be understood to be equivalent to the term “and / or”.

[0062] As used here, “element A overlaps with element B in direction X” (or similar language) means that there exists at least one line extending in direction X that intersects both elements A and B.

[0063] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the presented embodiments, a first element may be referred to as a second element.

[0064] As used here, "lower surface" refers to the surface facing the substrate (e.g., Figure 1 The term "upper surface" refers to the surface opposite to the lower surface of the substrate 100. Furthermore, as used herein, "lower portion" refers to the portion closer to the substrate than "upper portion".

[0065] In conjunction with the foregoing description and accompanying drawings, numerous different embodiments have been disclosed herein. It will be understood that a literal description and illustration of each combination and sub-combination of these embodiments would be excessively repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be construed as a complete written description of all combinations and sub-combinations constituting the embodiments described herein, as well as the manner and process of making and using them, and should support the claims for any such combinations or sub-combinations.

[0066] The foregoing disclosure is intended to be illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the scope of the inventive concept. Therefore, to the fullest extent permitted by law, the scope shall be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be construed as limited by the foregoing detailed description.

[0067] Cross-references to related applications

[0068] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 716,879, filed November 6, 2024, entitled “STACKED TRANSISTORS WITH MATCHED WORK FUNCTION METAL SCHEME AND METHODS OF MANUFACTURING THE SAME”, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: The first transistor on the substrate; as well as The second transistor on the first transistor, The first transistor is located between the substrate and the second transistor in a vertical direction perpendicular to the upper surface of the substrate. The first transistor includes: The first channel layers are spaced apart from each other in the vertical direction; and The first work function layer on the first channel layer The second transistor includes: The second channel layers are spaced apart from each other in the vertical direction; and The second work function layer on the second channel layer, and The second work function layer is spaced apart from the first channel layer.

2. The integrated circuit device according to claim 1, wherein the first work function layer is located between the first channel layer and the second work function layer.

3. The integrated circuit device according to claim 2, wherein the second work function layer comprises a second internal work function layer and a second external work function layer. The second internal work function layer is located between adjacent second channel layers in the second channel layer. The second external work function layer extends around the second channel layer and the second internal work function layer, and The second work function layer has an interface between the second internal work function layer and the second external work function layer.

4. The integrated circuit device according to claim 3, wherein the first work function layer comprises a first internal work function layer and a first external work function layer. The first internal work function layer is located between adjacent first channel layers in the first channel layer. The first external work function layer extends around the first channel layer and the first internal work function layer, and The first work function layer has no interface between the first internal work function layer and the first external work function layer.

5. The integrated circuit device according to claim 4, wherein the first internal work function layer and the first external work function layer are configured to form an integral structure.

6. The integrated circuit device of claim 4, wherein the interface of the second work function layer overlaps with the second channel layer in the vertical direction.

7. The integrated circuit device according to claim 6, wherein, In a horizontal direction parallel to the upper surface of the substrate, the width of at least one of the second channel layers is greater than the width of the second internal work function layer.

8. The integrated circuit device of claim 6, wherein the first internal work function layer and the first external work function layer comprise a first material.

9. The integrated circuit device of claim 8, wherein the second internal work function layer and the second external work function layer comprise a second material different from the first material.

10. The integrated circuit device of claim 8, wherein the second internal work function layer comprises a second material. The second external work function layer includes a third material, and The second material is different from the first material and the third material.

11. An integrated circuit device, comprising: The first transistor on the substrate; The second transistor on the first transistor; as well as An insulator is located between the first transistor and the second transistor in a direction perpendicular to the upper surface of the substrate. The first transistor includes: The first channel layers are spaced apart from each other in the vertical direction; and The first work function layer on the first channel layer The second transistor includes: The second channel layers are spaced apart from each other in the vertical direction; and The second work function layer on the second channel layer, and The second work function layer is separated from the first channel layer by the first work function layer.

12. The integrated circuit device of claim 11, wherein the first work function layer is in contact with the insulator.

13. The integrated circuit device of claim 11, wherein the second work function layer comprises a second internal work function layer and a second external work function layer. The second internal work function layer is located between adjacent second channel layers in the second channel layer. The second external work function layer extends around the second channel layer and the second internal work function layer, and The second work function layer has an interface between the second internal work function layer and the second external work function layer.

14. The integrated circuit device according to claim 13, wherein the first work function layer comprises a first internal work function layer and a first external work function layer. The first internal work function layer is located between adjacent first channel layers in the first channel layer. The first external work function layer extends around the first channel layer and the first internal work function layer, and The first work function layer has no interface between the first internal work function layer and the first external work function layer.

15. The integrated circuit device of claim 14, wherein the first internal work function layer and the first external work function layer are configured to form an integral structure.

16. The integrated circuit device of claim 11, wherein the first work function layer comprises a first material, and The second work function layer includes a second material that is different from the first material.

17. A method for forming an integrated circuit device, the method comprising: A first stack including a first channel layer and a second stack including a second channel layer are formed on a substrate, wherein the first channel layers are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the second channel layers are spaced apart from each other in the vertical direction. An insulator is formed between the first stack and the second stack in the vertical direction; A dummy layer is formed extending around the first trench layer, the second trench layer, and the insulator; Replace the upper portion of the dummy layer on the second channel layer with a first internal work function layer; Replace the lower portion of the dummy layer on the first channel layer with a second work function layer; as well as A first external work function layer is formed on the first internal work function layer, the insulator, and the second work function layer. The first external work function layer is separated from the first channel layer by the second work function layer.

18. The method of claim 17, wherein the first external work function layer is in contact with the first internal work function layer.

19. The method of claim 18, wherein the integrated circuit device includes an interface between the first external work function layer and the first internal work function layer.

20. The method of claim 19, wherein the first external work function layer and the first internal work function layer comprise a first material, and The second work function layer includes a second material that is different from the first material.

Images