Display panel and electronic device including the same

Abstract

The invention discloses a display panel and an electronic device comprising the same. The display panel includes a base substrate, a semiconductor pattern, an insulating layer, a gate pattern, an interlayer insulating layer, a source-drain pattern, a via layer, and a light emitting diode. The base substrate includes a first region and a second region, the second region including: a bending region that is bendable; a cover region extending from one side of the bending region and surrounding the first region; and a pad region extending from an opposite side of the bending region from the side of the bending region. The semiconductor pattern on the first region includes a semiconductor material. An insulating layer on the base substrate covers the semiconductor pattern. A gate pattern on the gate insulating layer at least partially overlaps the semiconductor pattern. The insulating layer covers the gate pattern. A first crack arrest opening and a second crack arrest opening are defined in the insulating layer. The number of first crack arrest openings is different than the number of second crack arrest openings.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0153833, filed on November 1, 2024, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a display panel configured to prevent defects caused by crack propagation and an electronic device including the display panel. Background Technology

[0003] Display panels and the electronic devices containing them typically include multiple light-emitting diodes (LEDs) to provide images to the user. Furthermore, wiring for controlling the multiple LEDs is arranged on the display panel. Summary of the Invention

[0004] During user use of electronic devices, various forms of impact may be applied to the display panel. Consequently, cracks may appear in the display panel, and if these cracks propagate to the aforementioned wiring, the wiring may become exposed. Exposed wiring is susceptible to corrosion, and this corrosion can lead to display panel malfunction.

[0005] In particular, the likelihood of failure due to crack propagation increases when cracks appear in areas with more concentrated wiring. The vulnerability of a display panel to crack propagation-induced failures can vary depending on the specific area of ​​the display panel.

[0006] The features of this disclosure provide a display panel capable of effectively preventing defects caused by crack propagation by designing crack dams in a differentiated manner according to the region, and an electronic device having the display panel.

[0007] The display panel in embodiments of this disclosure may include a substrate, a semiconductor pattern, a gate insulating layer, a gate pattern, an interlayer insulating layer, a source-drain pattern, a via layer, and a light-emitting diode. A first region and a second region may be defined in the substrate. The second region may include a curved region, a cover region, and a pad region. The curved region may be flexible. The cover region may extend from one side of the curved region and may surround the first region. The pad region may extend from the opposite side of the curved region. The semiconductor pattern may be disposed on the first region and may include a semiconductor material. The gate insulating layer may be disposed on the substrate and may cover the semiconductor pattern. The gate pattern may be disposed on the gate insulating layer, wherein at least a portion thereof overlaps with the semiconductor pattern. The interlayer insulating layer may cover the gate pattern. A plurality of first crack-stopping openings are defined in the portion of the interlayer insulating layer overlapping the cover region, and a plurality of second crack-stopping openings are defined in the portion of the interlayer insulating layer overlapping the pad region. Each of the plurality of first crack-stopping openings may extend along the outer edge of the cover region, and each of the plurality of second crack-stopping openings may extend along the outer edge of the pad region. The number of multiple first crack-stopping openings and the number of multiple second crack-stopping openings can be different from each other. A source-drain pattern can be disposed on an interlayer insulating layer, wherein at least a portion thereof is electrically connected to a semiconductor pattern. A via layer can cover the source-drain pattern, and a light-emitting diode can be disposed on the via layer.

[0008] In embodiments of this disclosure, the number of multiple second crack-prevention openings may be greater than the number of multiple first crack-prevention openings.

[0009] In embodiments of this disclosure, at least one of a plurality of third crack-stopping openings and a plurality of fourth crack-stopping openings may be defined in a gate insulating layer. The plurality of third crack-stopping openings may overlap with a first crack-stopping opening, respectively. The plurality of fourth crack-stopping openings may overlap with a second crack-stopping opening, respectively.

[0010] The display panel in embodiments of this disclosure may further include a plurality of pads, electrical components, and a plurality of spider traces. The plurality of pads may be arranged on a pad area. The electrical components may overlap with the plurality of pads. The plurality of spider traces may extend from the plurality of pads respectively and transmit signals from the electrical components to at least one of a source-drain pattern and a gate pattern. A plurality of second crack-prevention openings may be defined between the plurality of spider traces and the outer edge of the pad area.

[0011] In embodiments of this disclosure, in a plan view, a plurality of second crack-prevention openings may be spaced apart from a plurality of first crack-prevention openings across a bending region.

[0012] In embodiments of this disclosure, when the bending region is bent, a plurality of second crack-stopping openings may overlap with at least one of the first region and the covering region.

[0013] In embodiments of this disclosure, the substrate may include a first substrate layer, a second substrate layer, and a third substrate layer. The first substrate layer may include an organic material. The second substrate layer may be disposed on the first substrate layer. At least one of a plurality of fifth crack-prevention openings and a plurality of sixth crack-prevention openings may be defined in the second substrate layer. The plurality of fifth crack-prevention openings may overlap with a plurality of first crack-prevention openings, respectively. The plurality of sixth crack-prevention openings may overlap with a plurality of second crack-prevention openings, respectively. The third substrate layer may be disposed on the second substrate layer. The third substrate layer may include an organic material.

[0014] In embodiments of this disclosure, the shape formed by projecting each of the plurality of second crack blocking openings onto the substrate may include at least one of a straight shape, a curved shape, and a sawtooth shape.

[0015] The display panel in the embodiments of this disclosure may further include a functional layer disposed between a substrate and a semiconductor pattern. At least one of a plurality of seventh crack-prevention openings and a plurality of eighth crack-prevention openings may be defined in the functional layer. The plurality of seventh crack-prevention openings may overlap with a plurality of first crack-prevention openings, respectively. The plurality of eighth crack-prevention openings may overlap with a plurality of second crack-prevention openings, respectively.

[0016] The display panel in another embodiment of this disclosure may include a substrate, a semiconductor pattern, a gate insulating layer, a gate pattern, an interlayer insulating layer, a source-drain pattern, a via layer, and a light-emitting diode. A first region and a second region may be defined in the substrate. The second region may include a curved region, a cover region, and a pad region. The curved region may be flexible. The cover region may extend from one side of the curved region and may surround the first region. The pad region may extend from the opposite side of the curved region. The semiconductor pattern may be disposed on the first region and may include a semiconductor material. The gate insulating layer may be disposed on the substrate and may cover the semiconductor pattern. The gate pattern may be disposed on the gate insulating layer, wherein at least a portion thereof overlaps with the semiconductor pattern. The interlayer insulating layer may be configured to overlap with the first region and may cover the gate pattern. The interlayer insulating layer may include a plurality of first protruding members and a plurality of second protruding members. The plurality of first protruding members may be arranged to be spaced apart from each other on the cover region. The plurality of second protruding members may be arranged to be spaced apart from each other on the pad region. Each of the first protruding members may extend along at least a portion of the outer boundary of the cover region. Each of the second protruding members may extend along at least a portion of the outer boundary of the pad area. A source-drain pattern may be disposed on an interlayer insulating layer, wherein at least a portion thereof is electrically connected to the semiconductor pattern. A via layer may cover the source-drain pattern, and a light-emitting diode may be disposed on the via layer. The number of first protruding members and the number of second protruding members may differ from each other.

[0017] In embodiments of this disclosure, the number of second protruding members may be greater than the number of first protruding members.

[0018] In embodiments of this disclosure, the gate insulating layer may include at least one of a plurality of third protruding members and a plurality of fourth protruding members. The third protruding members may overlap with the first protruding members, respectively. The fourth protruding members may overlap with the second protruding members, respectively.

[0019] In another embodiment of this disclosure, the display panel may further include a plurality of pads, electrical components, and a plurality of spider traces. The plurality of pads may be arranged on a pad area. The electrical components may be electrically connected to the plurality of pads. The plurality of spider traces may extend from the plurality of pads respectively and deliver signals provided by the electrical components to at least one of a source-drain pattern and a gate pattern. A plurality of second protruding members may be disposed between the plurality of spider traces and the outer edge of the pad area.

[0020] In embodiments of this disclosure, the second protruding member may be spaced apart from the first protruding member in a plan view, separated by a curved area.

[0021] In embodiments of this disclosure, when the bending region is bent, the second protruding member may overlap with at least one of the first region and the covering region.

[0022] In embodiments of this disclosure, the substrate may include a first substrate layer, a second substrate layer, and a third substrate layer. The first substrate layer may include an organic material. The second substrate layer may be disposed on the first substrate layer. The second substrate layer may include at least one of a plurality of fifth protruding members and a plurality of sixth protruding members. The fifth protruding members may overlap with the first protruding members respectively. The sixth protruding members may overlap with the second protruding members respectively. The third substrate layer may be disposed on the second substrate layer and may include an organic material.

[0023] In embodiments of this disclosure, the shape formed by projecting each of the plurality of second protruding members onto the substrate may include at least one of a straight shape, a curved shape, and a serrated shape.

[0024] The display panel in the embodiments of this disclosure may further include a functional layer disposed between a substrate and a semiconductor pattern. The functional layer may include at least one of a plurality of seventh protruding members and a plurality of eighth protruding members. The seventh protruding members may overlap with a first protruding member, and the eighth protruding members may overlap with a second protruding member.

[0025] The electronic device in embodiments of this disclosure may include a display panel. The display panel may include a substrate, a semiconductor pattern, a gate insulating layer, a gate pattern, an interlayer insulating layer, a source-drain pattern, a via layer, and a light-emitting diode. A first region and a second region may be defined in the substrate. The second region may include a curved region, a cover region, and a pad region. The curved region may be flexible. The cover region may extend from one side of the curved region and may surround the first region. The pad region may extend from the opposite side of the curved region. The semiconductor pattern may be disposed on the first region and may include a semiconductor material. The gate insulating layer may be disposed on the substrate and may cover the semiconductor pattern. The gate pattern may be disposed on the gate insulating layer, wherein at least a portion thereof overlaps with the semiconductor pattern. The interlayer insulating layer may be configured to overlap with the first region and may cover the gate pattern. The interlayer insulating layer may include a plurality of first protruding members and a plurality of second protruding members. The plurality of first protruding members may be arranged to be spaced apart from each other on the cover region. The plurality of second protruding members may be arranged to be spaced apart from each other on the pad region. Each of the plurality of first protruding members may extend along at least a portion of the outer boundary of the cover region. Each of the plurality of second protruding members may extend along at least a portion of the outer boundary of the pad area. A source-drain pattern may be disposed on an interlayer insulating layer, wherein at least a portion thereof is electrically connected to the semiconductor pattern. A via layer may cover the source-drain pattern. A light-emitting diode may be disposed on the via layer. The number of first protruding members and the number of second protruding members may differ from each other.

[0026] In embodiments of this disclosure, a plurality of first crack-prevention openings may be defined in the portion of the interlayer insulating layer overlapping the cover area. Each of the plurality of first crack-prevention openings may extend along the outer edge of the cover area, and a plurality of second crack-prevention openings may be defined in the portion of the interlayer insulating layer overlapping the pad area. Each of the plurality of second crack-prevention openings may extend along the outer edge of the pad area. The number of first crack-prevention openings and the number of second crack-prevention openings may be different from each other.

[0027] Through embodiments of this disclosure, a display panel and an electronic device including the display panel can be provided that can effectively prevent defects caused by crack propagation by designing crack dams in a differentiated manner according to each region. Attached Figure Description

[0028] These and / or other features will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1A and Figure 1B These are perspective views and exploded views illustrating embodiments of the electronic device according to the present disclosure;

[0030] Figure 2A This is a floor plan of the display panel.

[0031] Figure 2B The illustration shows an example where the curved area is bent;

[0032] Figure 2C It is along Figure 2A A cross-sectional view of the display panel taken by line I-I';

[0033] Figure 2D yes Figure 2A A magnified view of part AA of the display panel shown in the image;

[0034] Figure 2E It is along Figure 2A A cross-sectional view of the covered area intercepted by line II-II';

[0035] Figure 2F It is along Figure 2D A cross-sectional view of the pad area intercepted by line III-III';

[0036] Figure 3A , Figure 3C , Figure 3E and Figure 3G The diagram is along Figure 2A A cross-sectional view of the covered area intercepted by line II-II';

[0037] Figure 3B , Figure 3D , Figure 3F and Figure 3H The diagram is along Figure 2D A cross-sectional view of the pad area intercepted by line III-III';

[0038] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E yes Figure 2A A magnified view of part AA of the display panel shown in the image;

[0039] Figure 5A The illustration shows a block diagram of an embodiment of an electronic device according to the present disclosure; and

[0040] Figure 5B The illustrations show embodiments of various electronic devices according to this disclosure. Detailed Implementation

[0041] Reference will now be made in detail to the illustrative embodiments illustrated in the accompanying drawings, in which the same reference numerals refer to the same elements throughout. Embodiments may have various forms and variations, but this disclosure should in no way be construed as limiting itself to the described embodiments. Rather, this disclosure should be construed as encompassing all forms, variations, equivalents, and substitutions covered by the technical concept and scope of this disclosure. Accordingly, embodiments are described below merely by reference to the accompanying drawings to illustrate the features of this disclosure.

[0042] Similar or identical reference numerals refer to similar or identical elements. Furthermore, in the drawings, the thickness, ratios, and dimensions of elements may not be to scale and may be exaggerated for the purpose of effectively illustrating the technical features associated with these elements. Therefore, this disclosure should not be limited to the thicknesses, ratios, dimensions, etc., illustrated in the drawings. The term "and / or" should include a combination of multiple listed items that can be defined by the relevant elements, or any one of multiple listed items.

[0043] Expressions such as “comprising” or “including” are intended to indicate features, numbers, steps, operations, elements, parts or combinations thereof, and should not be construed as excluding any possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, parts or combinations thereof.

[0044] Figure 1A This is a perspective view illustrating an embodiment of the electronic device DD according to the present disclosure, and Figure 1B This is an exploded view of the electronic device DD shown in the diagram.

[0045] refer to Figure 1A and Figure 1BThe electronic device DD may include a window WD, a display panel DP, and a housing HS. The electronic device DD can provide an image IM to the user. In embodiments, the electronic device DD can be any of a monitor, television, smartphone, wearable device, navigation device, in-vehicle terminal, and tablet PC. However, the shape and purpose of the electronic device DD are not limited to the foregoing examples, as long as the electronic device DD is capable of providing an image IM.

[0046] A window (WD) can be mounted on the display panel (DP) to define the appearance of the electronic device (DD) and protect the display panel (DP). The display panel (DP) provides an image (IM) to the user. A housing (HS) can contain and protect the display panel (DP).

[0047] Although not shown, the electronic device DD may further include input detection circuitry disposed between the display panel DP and the window WD. The input detection circuitry can detect user input such as touch and may include multiple input detection sensors. In embodiments of this disclosure, at least one of the window WD and the housing HS may be omitted.

[0048] Figure 2A It is a diagram. Figure 1B The diagram shows a plan view of the display panel DP. Figure 2B The illustration shows an example in which the bending region BA of the substrate BS in an embodiment of this disclosure is bent. Figure 2C It is along Figure 2A The cross-sectional view of the display panel DP taken by line I-I'.

[0049] refer to Figures 2A to 2C The display panel DP can define a display area DA and a non-display area NDA. Multiple light-emitting diodes (LEDs) can be disposed in the display area DA. The non-display area NDA can surround the display area DA and can include a first non-display area NDA1, a second non-display area NDA2, and a third non-display area NDA3.

[0050] The display panel DP may include a substrate BS, a semiconductor pattern SM, a functional layer FL, a gate insulating layer GI, a gate pattern GAT, an interlayer insulating layer ILD, a first source-drain pattern SD1, a first via layer VIA1, a second source-drain pattern SD2, a second via layer VIA2, a pixel defining layer PDL, a light-emitting diode LD, a packaging layer CL, a bending insulating layer BI, multiple pads PD, electrical components EP, and multiple spider wirings SL1 to SLn (n is a natural number greater than 1).

[0051] A first region AR1 and a second region AR2 can be defined in the substrate BS. The first region AR1 of the substrate BS can correspond to the display area DA of the display panel DP, while the second region AR2 of the substrate BS can correspond to the non-display area NDA of the display panel DP.

[0052] The first region AR1 overlaps with the area providing the image IM, and multiple light-emitting diodes (LDs) can be disposed on the first region AR1. The second region AR2 may include a coverage area CA, a curved area BA, and a pad area PA. The coverage area CA may correspond to the first non-display area NDA1, the curved area BA may correspond to the second non-display area NDA2, and the pad area PA may correspond to the third non-display area NDA3.

[0053] The coverage area CA can extend from one side of the curved area BA and can surround the first area AR1. The curved area BA can be flexible. The pad area PA can extend from the opposite side of the curved area BA.

[0054] A semiconductor pattern SM can be disposed on the first region AR1 and can include a semiconductor material. In embodiments of this disclosure, the semiconductor material may include at least one of amorphous silicon semiconductor, polycrystalline silicon semiconductor, metal oxide semiconductor, crystalline oxide semiconductor, and amorphous oxide semiconductor. In embodiments, the oxide semiconductor may include at least one of indium tin oxide (“ITO”), indium gallium zinc oxide (“IGZO”), zinc oxide (ZnO), zinc indium oxide (“ZIO”), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (“IZTO”), and zinc tin oxide (“ZTO”).

[0055] The functional layer FL can be disposed between the substrate BS and the semiconductor pattern SM. The functional layer FL may include at least one of a buffer layer BF and a barrier layer BR. In embodiments of this disclosure, the functional layer FL may be omitted.

[0056] The buffer layer BF may include at least one of inorganic and organic materials. In embodiments, the buffer layer BF may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium dioxide, aluminum oxide, and acrylic organic materials.

[0057] The barrier layer BR prevents foreign matter from diffusing into the semiconductor pattern SM. In embodiments, the barrier layer BR may include at least one of indium zinc oxide, gallium zinc oxide, and aluminum zinc oxide.

[0058] The gate insulating layer GI can be disposed on the substrate BS and can cover the semiconductor pattern SM. The gate insulating layer GI can include at least one of organic insulating materials and inorganic insulating materials. In embodiments, the gate insulating layer GI can include at least one of polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, polyacrylic acid compound, polyimide compound, fluorocarbon compound, and benzocyclobutene compound.

[0059] In embodiments of this disclosure, the gate insulating layer GI may include different layers such as a first gate insulating layer GI1 and a second gate insulating layer GI2. However, the gate insulating layer GI is not limited thereto and may further include at least one additional layer comprising or composed of an insulating material.

[0060] A gate pattern GAT may be disposed on a first gate insulating layer GI1, and at least a portion of the gate pattern GAT may overlap with a semiconductor pattern SM. The gate pattern GAT may include a metallic material. In embodiments, the gate pattern GAT may include at least one of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0061] The interlayer insulating layer (ILD) may cover the gate pattern (GAT) and may include an insulating material. In embodiments, the interlayer insulating layer (ILD) may include at least one of polysiloxane, silicon nitride, silicon oxide, and silicon oxynitride.

[0062] The first source-drain pattern SD1 may be disposed on the interlayer insulating layer ILD, and at least a portion of the first source-drain pattern SD1 may be electrically connected to the semiconductor pattern SM. The first source-drain pattern SD1 may include a metallic material. In embodiments, the first source-drain pattern SD1 may include at least one of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0063] The first via layer VIA1 may cover the first source-drain pattern SD1. The second source-drain pattern SD2 may penetrate the first via layer VIA1 and contact the first source-drain pattern SD1. The second via layer VIA2 may cover at least a portion of the second source-drain pattern SD2.

[0064] The pixel limiting layer (PDL) can be disposed on the second via layer (VIA2). A light-emitting diode (LED) aperture (L-OP) can be defined in the pixel limiting layer (PDL), and an LED (LD) can be disposed in the LED aperture (L-OP).

[0065] A light-emitting diode (LD) can be disposed on a first via layer VIA1 and a second via layer VIA2. The LD may include an anode electrode AE, an emitter layer EML, and a cathode electrode CE. The anode electrode AE ​​can be electrically connected to a semiconductor pattern SM through a first source-drain pattern SD1 and a second source-drain pattern SD2. In embodiments of this disclosure, the LD may be, but is not limited to, an organic light-emitting diode (“OLED”).

[0066] The encapsulation layer CL can cover the light-emitting diode LD to protect it from oxygen and moisture. The encapsulation layer CL may include a first encapsulation layer CL1, a second encapsulation layer CL2, and a third encapsulation layer CL3. In an embodiment, the encapsulation layer CL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0067] Each of the first encapsulation layer CL1, the second encapsulation layer CL2, and the third encapsulation layer CL3 may include at least one of organic and inorganic materials. The first encapsulation layer CL1 may cover the cathode electrode CE. The second encapsulation layer CL2 may be disposed on the first encapsulation layer CL1. The third encapsulation layer CL3 may be disposed on the second encapsulation layer CL2.

[0068] In embodiments of this disclosure, at least one of the first encapsulation layer CL1, the second encapsulation layer CL2, and the third encapsulation layer CL3 may be omitted. In another embodiment of this disclosure, the encapsulation layer CL may further include at least one additional layer comprising at least one of organic and inorganic materials.

[0069] The bending insulation layer BI may overlap with the bending region BA. The bending insulation layer BI may include an insulating material. In embodiments, the bending insulation layer BI may include at least one selected from polyacrylic acid compounds, polyimide compounds, fluorocarbon compounds, and benzocyclobutene compounds.

[0070] Multiple pads (PDs) can be set on pad area (PA). Multiple pads (PDs) can transmit signals provided by electrical component (EP) to multiple spider traces (SL1 to SLn) respectively. Electrical component (EP) can be electrically connected to multiple pads (PDs) and can overlap with multiple pads (PDs). Electrical component (EP) can provide signals for controlling multiple light-emitting diodes (LDs).

[0071] The electrical component EP may include at least one of a flexible printed circuit board (“FPCB”) and a driver chip. The driver chip can provide control signals for the light-emitting diode (LD) and may include multiple thin-film transistors.

[0072] In embodiments of this disclosure, the electrical component EP can be any of a chip-on-film (“COF”) structure, a chip-on-plastic (“COP”) structure, and a chip-on-glass (“COG”) structure. However, the electrical component EP is not limited to the foregoing examples and can be any component configured to provide signals for controlling a plurality of light-emitting diodes (LDs).

[0073] Multiple spider wirings SL1 to SLn can extend from multiple pads PD respectively, and can transmit signals from electrical components EP to at least one of the first source-drain pattern SD1 and gate pattern GAT. In embodiments of this disclosure, at least one of the second source-drain pattern SD2, the second via layer VIA2, the pixel defining layer PDL, the encapsulation layer CL, and the bending insulating layer BI can be omitted.

[0074] Figure 2D yes Figure 2A The image shows a magnified view of a portion AA of the display panel DP. Figure 2E It is along Figure 2A The cross-sectional view of section SC1 of the covered area CA intercepted by line II-II', and Figure 2F It is along Figure 2D The cross-sectional view of the pad area PA taken by line III-III' is shown in the figure.

[0075] refer to Figures 2D to 2F A plurality of first crack-stopping openings OP1 can be defined in the portion of the interlayer insulating layer (ILD) overlapping with the cover area CA, and a plurality of second crack-stopping openings OP2 can be defined in the portion of the interlayer insulating layer (ILD) overlapping with the pad area PA. Each of the first crack-stopping openings OP1 can extend along the outer edge of the cover area CA, and each of the second crack-stopping openings OP2 can extend along the outer edge of the pad area PA. The first crack-stopping openings OP1 and the second crack-stopping openings OP2 can act as crack dams to block the propagation of cracks.

[0076] In embodiments of this disclosure, at least a portion of the shape formed by projecting each of the second crack-blocking openings OP2 and each of the second protruding members PT2 onto the substrate BS can be a straight shape.

[0077] The number of first crack-stopping openings OP1 and the number of second crack-stopping openings OP2 can be different from each other. In an embodiment, the number of second crack-stopping openings OP2 can be greater than the number of first crack-stopping openings OP1. Therefore, with this disclosure, crack propagation can be blocked more effectively in the pad area PA than in the cover area CA.

[0078] In embodiments of this disclosure, a plurality of second crack-prevention openings OP2 can be defined between a plurality of spider traces SL1 to SLn and the outer edge BB of the pad area PA. Therefore, the second crack-prevention openings OP2 can prevent cracks from propagating from the outer edge BB of the pad area PA to the plurality of spider traces SL1 to SLn.

[0079] In embodiments of this disclosure, the second crack-stopping opening OP2 may be spaced apart from the first crack-stopping opening OP1 across the bending region BA in a plan view. In embodiments of this disclosure, when the bending region BA is bent, the second crack-stopping opening OP2 may overlap with at least one of the first region AR1 and the covering region CA.

[0080] refer to Figures 2D to 2F In embodiments of this disclosure, a portion of the interlayer insulating layer (ILD) may be configured to overlap with the first region AR1 and may include a plurality of first protruding members PT1 and a plurality of second protruding members PT2. In embodiments of this disclosure, the first protruding members PT1 may be disposed between two adjacent first crack-stopping openings OP1 among a plurality of first crack-stopping openings OP1, and the second protruding members PT2 may be disposed between two adjacent second crack-stopping openings OP2 among a plurality of second crack-stopping openings OP2.

[0081] A plurality of first protruding members PT1 may be arranged spaced apart from each other on a coverage area CA, and a plurality of second protruding members PT2 may be arranged spaced apart from each other on a pad area PA. Each of the first protruding members PT1 may extend along at least a portion of the outer boundary of the coverage area CA, and each of the second protruding members PT2 may extend along at least a portion of the outer boundary of the pad area PA.

[0082] In embodiments of this disclosure, the number of first protruding members PT1 and the number of second protruding members PT2 may be different from each other. In some embodiments, the number of second protruding members PT2 may be greater than the number of first protruding members PT1. That is, the number of second crack-preventing openings OP2 may be greater than the number of first crack-preventing openings OP1.

[0083] In embodiments of this disclosure, the second protruding member PT2 may be disposed between the outer edge BB of the multiple spider wirings SL1 to SLn and the pad area PA. In embodiments of this disclosure, the second protruding member PT2 may be spaced apart from the first protruding member PT1 in a plan view, separated by a bending area BA. In embodiments of this disclosure, when the bending area BA is bent, the second protruding member PT2 may overlap with at least one of the first area AR1 and the coverage area CA.

[0084] Figure 3A The diagram is along Figure 2A The cross-sectional view of the covered area CA cut by line II-II' is shown in section SC1-1. Figure 3B The diagram is along Figure 2D The cross-sectional view of the pad area PA cut by line III-III' is shown in section SC2-1.

[0085] refer to Figure 3A and Figure 3B In embodiments of this disclosure, at least one of a plurality of third crack-prevention openings OP3 and a plurality of fourth crack-prevention openings OP4 may be defined in a gate insulating layer GI-1, which includes a first gate insulating layer GI1-1 and a second gate insulating layer GI2-1. The plurality of third crack-prevention openings OP3 may overlap with a plurality of first crack-prevention openings OP1, and the plurality of fourth crack-prevention openings OP4 may overlap with a plurality of second crack-prevention openings OP2. The third crack-prevention openings OP3 and the fourth crack-prevention openings OP4 may act as crack dams configured to block crack propagation.

[0086] In embodiments of this disclosure, the gate insulating layer GI-1 may include a plurality of third protruding members PT3 and a plurality of fourth protruding members PT4. The plurality of third protruding members PT3 may overlap with a plurality of first protruding members PT1 respectively, and the plurality of fourth protruding members PT4 may overlap with a plurality of second protruding members PT2 respectively.

[0087] In embodiments of this disclosure, a third protruding member PT3 may be disposed between two adjacent third crack-prevention openings OP3 among a plurality of third crack-prevention openings OP3, and a fourth protruding member PT4 may be disposed between two adjacent fourth crack-prevention openings OP4 among a plurality of fourth crack-prevention openings OP4.

[0088] Figure 3C The diagram is along Figure 2A The cross-sectional view of the covered area CA cut by line II-II' is shown in section SC1-2. Figure 3D The diagram is along Figure 2D The cross-sectional view of the pad area PA taken by line III-III' is shown in section SC2-2.

[0089] In embodiments of this disclosure, the substrate BS-1 may include a first substrate layer BL1, a second substrate layer BL2, and a third substrate layer BL3. The first substrate layer BL1 may include an organic material. The second substrate layer BL2 may be disposed on the first substrate layer BL1 and may include an inorganic material. The third substrate layer BL3 may be disposed on the second substrate layer BL2 and may include an organic material.

[0090] refer to Figure 3C and Figure 3DIn embodiments of this disclosure, at least one of a plurality of fifth crack-stopping openings OP5 and a plurality of sixth crack-stopping openings OP6 may be defined in the second base layer BL2. The plurality of fifth crack-stopping openings OP5 may overlap with a plurality of first crack-stopping openings OP1, and the plurality of sixth crack-stopping openings OP6 may overlap with a plurality of second crack-stopping openings OP2. The fifth crack-stopping openings OP5 and the sixth crack-stopping openings OP6 may act as crack dams configured to block crack propagation.

[0091] In embodiments of this disclosure, the second base layer BL2 may include a plurality of fifth protruding members PT5 and a plurality of sixth protruding members PT6. The plurality of fifth protruding members PT5 may overlap with a plurality of first protruding members PT1 respectively, and the plurality of sixth protruding members PT6 may overlap with a plurality of second protruding members PT2 respectively.

[0092] In embodiments of this disclosure, a fifth protruding member PT5 may be disposed between two adjacent fifth crack-prevention openings OP5 among a plurality of fifth crack-prevention openings OP5, and a sixth protruding member PT6 may be disposed between two adjacent sixth crack-prevention openings OP6 among a plurality of sixth crack-prevention openings OP6.

[0093] Figure 3E The diagram is along Figure 2A The cross-sectional view of the covered area CA cut by line II-II' is shown in section SC1-3. Figure 3F The diagram is along Figure 2D The cross-sectional view of the pad area PA taken by line III-III' is shown in section SC2-3.

[0094] refer to Figure 3E and Figure 3F In embodiments of this disclosure, at least one of a plurality of seventh crack-prevention openings OP7 and a plurality of eighth crack-prevention openings OP8 may be defined in a functional layer FL-1, which includes a barrier layer BR-1 and a buffer layer BF-1. The plurality of seventh crack-prevention openings OP7 may overlap with a plurality of first crack-prevention openings OP1, and the plurality of eighth crack-prevention openings OP8 may overlap with a plurality of second crack-prevention openings OP2. The seventh crack-prevention openings OP7 and the eighth crack-prevention openings OP8 may act as crack dams configured to block crack propagation.

[0095] In embodiments of this disclosure, functional layer FL-1 may include a plurality of seventh protruding members PT7 and a plurality of eighth protruding members PT8. The plurality of seventh protruding members PT7 may overlap with a plurality of first protruding members PT1 respectively, and the plurality of eighth protruding members PT8 may overlap with a plurality of second protruding members PT2 respectively.

[0096] In embodiments of this disclosure, a seventh protruding member PT7 may be disposed between two adjacent seventh crack-preventing openings OP7 among a plurality of seventh crack-preventing openings OP7, and an eighth protruding member PT8 may be disposed between two adjacent eighth crack-preventing openings OP8 among a plurality of eighth crack-preventing openings OP8.

[0097] Figure 3G It is along Figure 2A The cross-sectional view of the covered area CA cut by line II-II' is shown in section SC1-4. Figure 3H The diagram is along Figure 2D The cross-sectional view of the pad area PA taken by line III-III' is shown in section SC2-4.

[0098] refer to Figure 3G and Figure 3H In embodiments of this disclosure, a predetermined material MT may be disposed in at least one of a plurality of first crack-prevention openings OP1, a plurality of second crack-prevention openings OP2, a plurality of third crack-prevention openings OP3, a plurality of fourth crack-prevention openings OP4, a plurality of fifth crack-prevention openings OP5, a plurality of sixth crack-prevention openings OP6, a plurality of seventh crack-prevention openings OP7, and a plurality of eighth crack-prevention openings OP8. In embodiments, the predetermined material MT may be an organic material.

[0099] Within a predetermined layer, regions containing or composed of organic materials can have lower hardness compared to regions containing or composed of inorganic materials, and can effectively absorb tensile stress caused by bending. Therefore, when a predetermined material MT, which is an organic material, is placed in a crack-prevention opening, it can more effectively block crack propagation.

[0100] Figures 4A to 4E yes Figure 2A The image shows a magnified view of a portion AA of the display panel DP.

[0101] In embodiments of this disclosure, the shape formed by projecting each of the second crack-blocking openings OP2 and each of the second protruding members PT2 onto the substrate BS may include at least one of a straight shape, a curved shape, and a sawtooth shape.

[0102] refer to Figure 4A The shape formed by projecting each of the second crack-blocking openings OP2-1 onto the substrate BS can include a curved shape. The shape formed by projecting each of the second protruding members PT2-1 onto the substrate BS can also include a curved shape. In embodiments of this disclosure, the curved shape can be a repeating arc or an elliptical arc.

[0103] refer to Figure 4B The shape formed by projecting each of the second crack-blocking openings OP2-2 onto the substrate BS can include a serrated shape. The shape formed by projecting each of the second protruding members PT2-2 onto the substrate BS can also include a serrated shape.

[0104] refer to Figure 4C The shape formed by projecting some of the second crack-preventing openings OP2-3 onto the substrate BS can include a straight shape, while the shape formed by projecting the remaining (other) second crack-preventing openings OP2-3 onto the substrate BS can include a curved shape. In embodiments of this disclosure, the arrangement of the second crack-preventing openings OP2-3 with straight shapes and the second crack-preventing openings OP2-3 with curved shapes can be freely adjusted.

[0105] refer to Figure 4C The shape formed by projecting some of the second protruding members PT2-3 onto the substrate BS can include a straight shape, while the shape formed by projecting the remaining (other) second protruding members PT2-3 onto the substrate BS can include a curved shape. In embodiments, the arrangement of the second protruding members PT2-3 with straight shapes and the second protruding members PT2-3 with curved shapes can also be freely adjusted.

[0106] refer to Figure 4D The shape formed by projecting some of the second crack-preventing openings OP2-4 onto the substrate BS can include a serrated shape, while the shape formed by projecting the remaining (other) second crack-preventing openings OP2-4 onto the substrate BS can include a curved shape. In embodiments, the arrangement of the second crack-preventing openings OP2-4 with serrated shapes and the second crack-preventing openings OP2-4 with curved shapes can be freely adjusted.

[0107] refer to Figure 4D The shape formed by projecting some of the second protruding members PT2-4 onto the substrate BS can include a serrated shape, while the shape formed by projecting the remaining (other) second protruding members PT2-4 onto the substrate BS can include a curved shape. In embodiments, the arrangement of the second protruding members PT2-4 with serrated shapes and the second protruding members PT2-4 with curved shapes can be freely adjusted.

[0108] refer to Figure 4EThe shape formed by projecting some of the second crack-preventing openings OP2-5 onto the substrate BS can include a serrated shape, while the shape formed by projecting the remaining (other) second crack-preventing openings OP2-5 onto the substrate BS can include a straight shape. In embodiments, the arrangement of the second crack-preventing openings OP2-5 with serrated shapes and the second crack-preventing openings OP2-5 with straight shapes can be freely adjusted.

[0109] refer to Figure 4E The shape formed by projecting some of the second protruding members PT2-5 onto the substrate BS can include a serrated shape, while the shape formed by projecting the remaining (other) second protruding members PT2-5 onto the substrate BS can include a straight shape. In embodiments, the arrangement of the second protruding members PT2-5 with serrated shapes and the second protruding members PT2-5 with straight shapes can also be freely adjusted.

[0110] Figure 5A The figure shows a block diagram of an embodiment of the electronic device DD according to the present disclosure.

[0111] refer to Figure 5A The electronic device DD in the embodiment may include a display panel DP, a processor PR, a memory MR, and a power module PM. The processor PR may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller.

[0112] The memory (MR) can store the data and information required for the operation of the processor (PR) or the display panel (DP). When the processor (PR) executes the application stored in the memory (MR), image data signals and / or input control signals can be transmitted to the display panel (DP), which can then process the received signals and output visual information through the display screen.

[0113] The power module PM may include a power supply module such as a power adapter or battery device, and a power conversion module configured to convert the power supplied by the power supply module to generate the power required for the operation of the electronic device DD.

[0114] At least one of the aforementioned components of the electronic device DD may be included in the display device in the above embodiments. Furthermore, some individual modules included in a single functional module may be integrated into the display device, while other modules may be provided separately from the display device. In an embodiment, the display device may include a display panel DP, while the processor PR, memory MR, and power module PM may be provided as separate devices within the electronic device DD.

[0115] Figure 5B The illustrations show embodiments of various electronic devices DD according to the present disclosure.

[0116] refer to Figure 5B The display panel DP in the embodiments of this disclosure can be applied to various electronic devices DD, such as image display electronics including smartphone APP1, tablet PC APP2, laptop computer APP3, television (“TV”) APP4, or desktop monitor APP5. The display panel DP can also be included in wearable electronic devices such as smart glasses APP6, head-mounted display APP7, or smartwatch APP8. In addition, the display panel DP can be included in in-vehicle electronic devices APP9 and APP9-1 to APP9-4, such as central information display (“CID”), instrument panel, central dashboard, instrument cluster, or rearview mirror display.

[0117] Although illustrative embodiments of the present disclosure have been described above, it will be understood by any person skilled in the art to which this disclosure pertains that various modifications and variations of the present disclosure may be made without departing from the technical spirit and scope of the present disclosure as defined in the claims. Furthermore, it should be understood that the disclosed embodiments are not intended to limit the present disclosure, and every technical spirit within the claims and their equivalents is to be construed as being included within the scope of this disclosure.

Claims

1. A display panel, comprising: The substrate includes a first region and a second region, the second region including: a bending region that is flexible; a covering region extending from one side of the bending region and surrounding the first region; and a pad region extending from the opposite side of the bending region to the side opposite to the bending region. A semiconductor pattern is disposed on the first region and includes semiconductor material; A gate insulating layer is disposed on the substrate and covers the semiconductor pattern; A gate pattern is disposed on the gate insulating layer and includes at least a portion that overlaps with the semiconductor pattern; An interlayer insulating layer covers the gate pattern; A source-drain pattern is disposed on the interlayer insulating layer and includes at least a portion electrically connected to the semiconductor pattern; Through-hole layer, covering the source-drain pattern; and A light-emitting diode is disposed on the via layer. The plurality of first crack-prevention openings, each extending along the outer edge of the covered area, are defined in the portion of the interlayer insulation layer that overlaps with the covered area. Multiple second crack-prevention openings, each extending along the outer edge of the pad area, are defined in the portion of the interlayer insulating layer that overlaps with the pad area. The number of the plurality of first crack-preventing openings and the number of the plurality of second crack-preventing openings are different from each other.

2. The display panel according to claim 1, wherein, The number of the plurality of second crack-preventing openings is greater than the number of the plurality of first crack-preventing openings.

3. The display panel according to claim 2, wherein, At least one of a plurality of third crack-preventing openings and a plurality of fourth crack-preventing openings is defined in the gate insulating layer, wherein the plurality of third crack-preventing openings overlap with the plurality of first crack-preventing openings, and the plurality of fourth crack-preventing openings overlap with the plurality of second crack-preventing openings.

4. The display panel according to claim 3, further comprising: Multiple pads are disposed on the pad area; Electrical components overlap with the plurality of pads; as well as Multiple spider wires extend from the plurality of pads and are configured to transmit signals provided by the electrical components to at least one of the source-drain pattern and the gate pattern. The plurality of second crack-prevention openings are defined between the plurality of spider wirings and the outer edge of the pad area.

5. The display panel according to claim 4, wherein, In the plan view, the plurality of second crack-preventing openings are spaced apart from the plurality of first crack-preventing openings across the bending region.

6. The display panel according to claim 4, wherein, When the bending region is bent, the plurality of second cracks prevent the opening from overlapping with at least one of the first region and the covered region.

7. The display panel according to claim 4, wherein, The substrate includes: The first base layer comprises organic materials; A second base layer is disposed on the first base layer; and A third substrate layer, disposed on the second substrate layer and comprising organic material. At least one of the plurality of fifth crack-preventing openings and the plurality of sixth crack-preventing openings is defined in the second base layer. The plurality of fifth crack-prevention openings overlap with the plurality of first crack-prevention openings, and The plurality of sixth crack-prevention openings overlap with the plurality of second crack-prevention openings, respectively.

8. The display panel according to claim 4, wherein, The shape formed by projecting each of the plurality of second crack blocking openings onto the substrate includes at least one of a straight shape, a curved shape, and a sawtooth shape.

9. The display panel according to claim 4, further comprising: A functional layer is disposed between the substrate and the semiconductor pattern. At least one of the plurality of seventh crack-preventing openings and the plurality of eighth crack-preventing openings is defined in the functional layer. The plurality of seventh crack-prevention openings overlap with the plurality of first crack-prevention openings, and The plurality of eighth crack-prevention openings overlap with the plurality of second crack-prevention openings, respectively.

10. An electronic device comprising: The display panel includes: The substrate includes a first region and a second region, the second region including: a bending region that is flexible; a covering region extending from one side of the bending region and surrounding the first region; and a pad region extending from the opposite side of the bending region to the side opposite to the bending region. A semiconductor pattern is disposed on the first region and includes semiconductor material; A gate insulating layer is disposed on the substrate and covers the semiconductor pattern; A gate pattern is disposed on the gate insulating layer and includes at least a portion that overlaps with the semiconductor pattern; An interlayer insulating layer covers the gate pattern and includes: a plurality of first protruding members spaced apart from each other on the covered area; and a plurality of second protruding members spaced apart from each other on the pad area; A source-drain pattern is disposed on the interlayer insulating layer and includes at least a portion electrically connected to the semiconductor pattern; Through-hole layer, covering the source-drain pattern; and A light-emitting diode is disposed on the via layer. Each of the first protruding members extends along at least a portion of the outer boundary of the covered area. Each of the second protruding members extends along at least a portion of the outer boundary of the pad area, and The number of the first protruding member and the number of the second protruding member are different from each other.

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