Gate tube, method of manufacturing gate tube, chip, electronic component, and electronic device

Abstract

The embodiment of the invention provides a gate tube, a method for manufacturing the gate tube, a chip, an electronic component and electronic equipment. The gate tube comprises a first electrode, a second electrode, a plurality of dielectric layers and a first isolation layer. The plurality of dielectric layers are located between the first electrode and the second electrode and include a first dielectric layer and a second dielectric layer. The second dielectric layer surrounds the first dielectric layer. The first isolation layer is disposed between the first dielectric layer and the second dielectric layer. The gate tube comprises a plurality of dielectric layers, so that the proportion of the circumference of the dielectric layers of the gate tube to the sectional area can be increased, the area of the side wall can be increased, an edge electric field can be increased, the current density of the gate tube can be increased, and the nonlinearity can be increased. By arranging the first isolation layer between the first dielectric layer and the second dielectric layer, the first dielectric layer and the second dielectric layer can be electrically isolated, and the increased fringe electric field is protected, so that the nonlinearity of the gate tube is effectively increased, and the performance of the gate tube is improved.

Description

Technical Field

[0001] The embodiments of this application generally relate to the semiconductor field, and more specifically to a gate transistor, a method for manufacturing a gate transistor, a chip, an electronic component, and an electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, the application of nonlinear semiconductor devices is becoming increasingly widespread. For example, a gate transistor, as a nonlinear device, exhibits different resistance values ​​under different voltages, and the current flowing through the gate transistor has a nonlinear relationship with the voltage applied to it. Gate transistors can be used in environments where switching is selectively performed based on voltage to mitigate leakage current or crosstalk in the application environment. Therefore, it is desirable for gate transistors to have a large degree of nonlinearity. Summary of the Invention

[0003] The embodiments of this application provide a technical solution for a gated tube with improved nonlinearity, so as to achieve improved performance of the gated tube.

[0004] According to a first aspect, a gate transistor is provided. This gate transistor can be used in any electronic device. For example, it can be used in any type of chip in an electronic device, such as a control chip, a memory chip, an analog chip, a communication chip, or a logic chip. The gate transistor includes a first electrode, a second electrode, multiple dielectric layers, and a first isolation layer. The multiple dielectric layers are located between the first and second electrodes. The multiple dielectric layers include a first dielectric layer and a second dielectric layer. The second dielectric layer surrounds the first dielectric layer. The first isolation layer is disposed between the first and second dielectric layers. By including multiple dielectric layers in the gate transistor, the ratio of the perimeter of the dielectric layers to their cross-sectional area can be increased, and the area of ​​the sidewalls can be increased, thereby increasing the edge electric field. As the edge electric field increases, the current density of the gate transistor also increases, thereby increasing the nonlinearity of the gate transistor. By disposing the first isolation layer of the gate transistor between the first and second dielectric layers in the multiple dielectric layers, the first and second dielectric layers can be electrically isolated, protecting the increased edge electric field. This protection effectively increases the current density of the selector, thereby increasing its nonlinearity and improving its performance.

[0005] In some implementations, the first isolation layer includes at least one of the following: a passivation layer, an air layer, or a combination of a passivation layer and an air layer. Therefore, the first isolation layer can be implemented with different structures according to actual needs, improving the design flexibility of the selector.

[0006] In some implementations, the thickness of the first isolation layer is less than 5 nm, or less than 2 nm, or less than 1 nm. This allows for electrical isolation between the first and second dielectric layers while maintaining a relatively small thickness. A thinner first isolation layer has a smaller, even negligible, impact on the current density of the selector. Therefore, it is possible to further and effectively increase the nonlinearity of the selector and improve its performance.

[0007] In some implementations, the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 50:1, or greater than 80:1, or greater than 100:1. This allows the first isolation layer to provide electrical isolation between the first and second dielectric layers while maintaining a relatively small cross-sectional area relative to the total cross-sectional area of ​​the multiple dielectric layers. This smaller proportion minimizes, or even negligibles, the impact of the first isolation layer on the current flowing through the selector. Therefore, it can further effectively increase the nonlinearity of the selector and improve its performance.

[0008] In some implementations, the first dielectric layer and the second dielectric layer comprise the same dielectric material. This allows the first and second dielectric layers to have identical electrical properties, further improving the performance of the selector.

[0009] In some implementations, the first or second dielectric layer comprises a single dielectric material or multiple dielectric materials. When the first or second dielectric layer comprises a single dielectric material, the manufacturing process of both layers can be simplified, thereby reducing the cost of the gate. When the first or second dielectric layer comprises multiple dielectric materials, the nonlinearity of the gate can be further improved, thus further enhancing its performance.

[0010] In some implementations, the dielectric material is selected from at least one of the following: Ta₂O₅, HfO₂, TiO₂, ZrO, SiO₂, aSi, Al₂O₃, HfSiO₄, ZrSiO₄, La₂O₃, Y₂O₃, ZnO, NiO, or MgO. Therefore, different dielectric materials can be flexibly selected according to actual needs, thereby improving the design flexibility of the selector tube.

[0011] In some implementations, the first electrode and the second electrode may be made of the same metal material or different metal materials. This increases the design flexibility of the first and second electrodes, and further enhances the design flexibility of the selector.

[0012] In some implementations, the first or second electrode comprises a metallic material or alloy thereof selected from at least one of the following: Pt, Ti, TiN, TaN, TiAl, Pd, Ir, W, Ta, or Ru. This allows for the flexible selection of different electrode materials according to actual needs, further improving the design flexibility of the selector tube.

[0013] In some implementations, the passivation layer material is selected from at least one of the following: SiNx or SiON. This allows for flexible selection of different passivation layer materials according to actual needs, further improving the design flexibility of the pass-through tube.

[0014] In some implementations, the multiple dielectric layers further include a third dielectric layer surrounding the second dielectric layer. The gate also includes a second isolation layer disposed between the second and third dielectric layers. By including the third dielectric layer in the gate, the ratio of the perimeter of the dielectric layers to the cross-sectional area can be further increased, as can the area of ​​the sidewalls, thereby further increasing the edge electric field. With the further increase of the edge electric field, the current density of the gate also increases further, thereby further increasing the nonlinearity of the gate. By disposing the second isolation layer between the second and third dielectric layers, the second and third dielectric layers can be electrically isolated, protecting the further increased edge electric field. Through this protection, the current density of the gate can be effectively increased, thereby effectively increasing the nonlinearity of the gate and effectively improving the performance of the gate.

[0015] In some implementations, the third dielectric layer has the same dielectric material as the first and second dielectric layers. This allows each of the multiple dielectric layers to have the same electrical characteristics, further improving the performance of the selector.

[0016] In some implementations, the thickness of the second isolation layer is less than 5 nm, or less than 2 nm, or less than 1 nm. This allows for electrical isolation between the second and third dielectric layers while maintaining a relatively small thickness. A thinner second isolation layer has a smaller, even negligible, impact on the current density of the selector. Therefore, it is possible to further and effectively increase the nonlinearity of the selector, thereby improving its performance.

[0017] In some implementations, in a cross-section of multiple dielectric layers parallel to the first or second electrode, the first dielectric layer, the first isolation layer, and the second dielectric layer are in one of the following shapes: concentric circles, concentric ellipses, or concentric polygons. Therefore, the first dielectric layer, the first isolation layer, and the second dielectric layer can be implemented in different shapes according to actual needs, thereby further improving the design flexibility of the pass-through.

[0018] In some implementations, the gate transistor is configured to have a non-linear relationship between the voltage between the first electrode and the second electrode and the current flowing through the gate transistor. The gate transistor according to this disclosure has a non-linear relationship between voltage and current, making it applicable to various fields, such as various types of memory chips, neuromorphic computing chips, in-memory computing chips, and integrated chips of various types.

[0019] According to a second aspect, a method for manufacturing a gate transistor is provided. The method can be executed by any one or more controllers capable of controlling the manufacturing process of the gate transistor, such as a controller, control module, or control chip from one or more of an apparatus for forming electrodes, an apparatus for depositing dielectric materials, and an etching apparatus. The method includes forming a first electrode. The method also includes forming a second electrode. The method further includes forming a plurality of dielectric layers located between the first and second electrodes. Forming the plurality of dielectric layers includes forming the first dielectric layer. Forming the plurality of dielectric layers also includes forming a second dielectric layer. The second dielectric layer surrounds the first dielectric layer. The method further includes forming a first isolation layer located between the first and second dielectric layers. By including multiple dielectric layers in the gate transistor, the ratio of the perimeter of the dielectric layers to the cross-sectional area can be increased, and the area of ​​the sidewalls can be increased, thereby increasing the edge electric field. As the edge electric field increases, the current density of the gate transistor also increases, thereby increasing the nonlinearity of the gate transistor. By arranging the first isolation layer of the gate transistor between the first and second dielectric layers in a plurality of dielectric layers, electrical isolation can be achieved between the first and second dielectric layers, protecting against the increased edge electric field. This protection effectively increases the current density of the gate transistor, thereby effectively increasing its nonlinearity and improving its performance.

[0020] In some implementations, forming the first dielectric layer includes depositing a dielectric material on the first electrode to form an initial first dielectric layer. Forming the first dielectric layer also includes etching the outer peripheral portion of the initial first dielectric layer to form the first dielectric layer. Thus, the first dielectric layer can be formed in a simple manner, resulting in lower manufacturing costs for the selector.

[0021] In some implementations, forming the first isolation layer includes forming the first isolation layer around the first dielectric layer. Forming the second dielectric layer includes forming the second dielectric layer around the first isolation layer. Forming the second electrode includes forming the second electrode on the first dielectric layer, the first isolation layer, and the second dielectric layer. Thus, the first electrode, the first dielectric layer, the first isolation layer, the second dielectric layer, and the second electrode can be formed sequentially, simplifying the manufacturing process of the selector and reducing manufacturing costs.

[0022] In some implementations, forming the second electrode includes forming the second electrode on the initial first dielectric layer before etching the outer peripheral portion of the initial first dielectric layer. Forming the first isolation layer includes forming the first isolation layer around the first dielectric layer after etching the outer peripheral portion of the initial first dielectric layer. Forming the second dielectric layer includes forming the second dielectric layer around the first isolation layer. Thus, the formed first dielectric layer, first isolation layer, and second dielectric layer can have different surface roughnesses than those described above, thereby improving the design flexibility of the gate.

[0023] In some implementations, the first isolation layer includes at least one of the following: a passivation layer, an air layer, or a combination of a passivation layer and an air layer. Therefore, the first isolation layer can be implemented with different structures according to actual needs, improving the design flexibility of the pass-through.

[0024] In some implementations, the thickness of the first isolation layer is less than 5 nm, or less than 2 nm, or less than 1 nm. This allows for electrical isolation between the first and second dielectric layers while maintaining a relatively small thickness. A thinner first isolation layer has a smaller, even negligible, impact on the current density of the selector. Therefore, it is possible to further and effectively increase the nonlinearity of the selector and improve its performance.

[0025] In some implementations, the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 50:1, or greater than 80:1, or greater than 100:1. This allows the first isolation layer to provide electrical isolation between the first and second dielectric layers while maintaining a relatively small cross-sectional area relative to the total cross-sectional area of ​​the multiple dielectric layers. This smaller proportion minimizes, or even negligibles, the impact of the first isolation layer on the current flowing through the selector. Therefore, it can further effectively increase the nonlinearity of the selector and improve its performance.

[0026] In some implementations, the first dielectric layer and the second dielectric layer comprise the same dielectric material. This allows the first and second dielectric layers to have identical electrical properties, further improving the performance of the selector.

[0027] In some implementations, the first or second dielectric layer comprises a single dielectric material or multiple dielectric materials. When the first or second dielectric layer comprises a single dielectric material, the manufacturing process of both layers can be simplified, thereby reducing the cost of the gate. When the first or second dielectric layer comprises multiple dielectric materials, the nonlinearity of the gate can be further improved, thus further enhancing its performance.

[0028] In some implementations, the dielectric material is selected from at least one of the following: Ta2O5, HfO2, TiO2, ZrO, SiO2, aSi, Al2O3, HfSiO4, ZrSiO4, La2O3, Y2O3, ZnO, NiO, or MgO. Therefore, different dielectric materials can be flexibly selected according to actual needs, improving the design flexibility of the selector tube.

[0029] In some implementations, the first electrode and the second electrode may be made of the same metal material or different metal materials. This increases the design flexibility of the first and second electrodes, and further enhances the design flexibility of the selector.

[0030] In some implementations, the first or second electrode comprises a metallic material or alloy thereof selected from at least one of the following: Pt, Ti, TiN, TaN, TiAl, Pd, Ir, W, Ta, or Ru. This allows for the flexible selection of different electrode materials according to actual needs, further improving the design flexibility of the selector tube.

[0031] In some implementations, the passivation layer material is selected from at least one of the following: SiNx or SiON. This allows for flexible selection of different passivation layer materials according to actual needs, further improving the design flexibility of the pass-through tube.

[0032] In some implementations, the method further includes forming a second isolation layer that surrounds the second dielectric layer. Forming multiple dielectric layers further includes forming a third dielectric layer that surrounds the second isolation layer. By including the third dielectric layer in the gate transistor, the ratio of the perimeter to the cross-sectional area of ​​the dielectric layer can be further increased, as can the area of ​​the sidewalls, thereby further increasing the edge electric field. With the further increase in the edge electric field, the current density of the gate transistor also increases further, thereby further increasing the nonlinearity of the gate transistor. By arranging the second isolation layer between the second and third dielectric layers, the second and third dielectric layers can be electrically isolated, protecting the further increased edge electric field. Through this protection, the current density of the gate transistor can be effectively increased, thereby effectively increasing the nonlinearity of the gate transistor and effectively improving its performance.

[0033] In some implementations, the third dielectric layer has the same dielectric material as the first and second dielectric layers. This allows each of the multiple dielectric layers to have the same electrical characteristics, further improving the performance of the selector.

[0034] In some implementations, the thickness of the second isolation layer is less than 5 nm, or less than 2 nm, or less than 1 nm. This allows for electrical isolation between the second and third dielectric layers while maintaining a relatively small thickness. A thinner second isolation layer has a smaller, even negligible, impact on the current density of the selector. Therefore, it is possible to further and effectively increase the nonlinearity of the selector, thereby improving its performance.

[0035] In some implementations, in a cross-section of multiple dielectric layers parallel to the first or second electrode, the first dielectric layer, the first isolation layer, and the second dielectric layer are in one of the following shapes: concentric circles, concentric ellipses, or concentric polygons. Therefore, the first dielectric layer, the first isolation layer, and the second dielectric layer can be implemented in different shapes according to actual needs, thereby further improving the design flexibility of the pass-through.

[0036] In some implementations, the gate transistor is configured to have a non-linear relationship between the voltage between the first electrode and the second electrode and the current flowing through the gate transistor. The gate transistor according to this disclosure has a non-linear relationship between voltage and current, making it applicable to various fields, such as various types of memory chips, neuromorphic computing chips, in-memory computing chips, and integrated chips of various types.

[0037] According to a third aspect, a chip is provided. The chip includes a gate according to the first aspect and a package. The package is configured to encapsulate the gate.

[0038] According to a fourth aspect, an electronic component is provided. The electronic component includes a chip according to a third aspect, and a circuit board. The circuit board is configured to support the chip.

[0039] According to a fifth aspect, an electronic device is provided. The electronic device includes a chip according to a third aspect and a power supply circuit. The power supply circuit is configured to supply power to the chip. Attached Figure Description

[0040] The above and other features, advantages, and aspects of the embodiments of this application will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 A schematic diagram of an example of a gate tube is shown.

[0041] Figure 2 A schematic diagram of another example of a gate tube is shown.

[0042] Figure 3 A schematic diagram of an example of a gate tube according to an embodiment of this application is shown.

[0043] Figure 4 Another schematic diagram shows an example of a gate tube according to an embodiment of this application.

[0044] Figure 5 A schematic diagram of another example of a gate according to an embodiment of this application is shown.

[0045] Figure 6 A schematic diagram of another example of a gate according to an embodiment of this application is shown.

[0046] Figure 7 A flowchart of a method for manufacturing a gate tube according to an embodiment of this application is shown.

[0047] Figure 8 A schematic diagram illustrating an example of forming a first electrode according to an embodiment of this application is shown.

[0048] Figure 9 A schematic diagram illustrating an example of forming an initial first dielectric layer according to an embodiment of this application is shown.

[0049] Figure 10 A schematic diagram illustrating an example of forming a first dielectric layer according to an embodiment of this application is shown.

[0050] Figure 11A schematic diagram illustrating an example of forming a first isolation layer according to an embodiment of this application is shown.

[0051] Figure 12 A schematic diagram illustrating an example of forming a second dielectric layer according to an embodiment of this application is shown.

[0052] Figure 13 A schematic diagram illustrating an example of forming a second electrode according to an embodiment of this application is shown.

[0053] Figure 14 A schematic diagram of another example of forming a second electrode according to an embodiment of this application is shown.

[0054] Figure 15 A schematic diagram of another example of forming a first dielectric layer according to an embodiment of this application is shown.

[0055] Figure 16 A schematic diagram of another example of forming a first isolation layer according to an embodiment of this application is shown.

[0056] Figure 17 A schematic diagram of another example of forming a second dielectric layer according to an embodiment of this application is shown. Detailed Implementation

[0057] The technical solutions of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0058] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " indicates "and / or," for example, A / B can mean A or B, or A and B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, in the description of the embodiments of this application, "plural" or "multiple" refers to two or more than two.

[0059] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.

[0060] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, “at least one” and “one or more” refer to one, two, or more than two. The term “and / or” is used to describe the relationship between related objects, indicating that three relationships may exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character “ / ” generally indicates that the preceding and following related objects are in an “or” relationship.

[0061] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "one embodiment," "some embodiments," "another embodiment," "other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0062] The numbers or values ​​used in this specification are illustrative and are intended only to facilitate understanding of the technology of the embodiments of this application, and are by no means intended to limit the scope of this application.

[0063] The gate transistor provided in this application can be applied to electronic devices such as mobile phones, tablets, wearable devices, in-vehicle devices, augmented reality (AR) / virtual reality (VR) devices, laptops, ultra-mobile personal computers (UMPCs), netbooks, and personal digital assistants (PDAs), for example, on any chip in an electronic device. This application does not impose any limitations on the type of chip on which the gate transistor is applied or the specific type of electronic device on which the chip is applied.

[0064] The following section will first provide a detailed introduction to some terms that may be involved in the embodiments of this application.

[0065] 1. Resistive random-access memory (RRAM) Resistive random access memory (RRAM) is a type of non-volatile memory that uses voltage to control the resistance state of a material, thereby enabling data storage.

[0066] 2. Phase-change random-access memory (PCRAM) Phase change memory is a non-volatile memory that realizes data storage based on the reversible phase transition between crystalline and amorphous states of chalcogenide glass materials.

[0067] 3. Ferroelectric random-access memory (FeRAM) Ferroelectric memory is a non-volatile memory that uses the polarization properties of ferroelectric crystal materials and controls the inversion of ferroelectric domains through an electric field to achieve data storage.

[0068] 4. Magnetic random-access memory (MRAM) Magnetic memory is a type of non-volatile memory that uses electron spin rather than charge to store data.

[0069] 5. 1S1R(one selector one resistor) 1S1R refers to a structure in non-volatile memory (e.g., RRAM, PCRAM, FeRAM, MRAM, etc.) based on a cross-point array architecture, which consists of a selector and memory cells connected in series.

[0070] 6. Nonlinearity Nonlinearity is used to describe the electrical current-voltage (IV) characteristics of a device. Some devices have a constant or nearly constant resistance value at different voltages, and their IV characteristics are linear, exhibiting no nonlinearity. Other devices have different resistance values ​​at different voltages, and their IV characteristics are nonlinear, exhibiting nonlinearity. For devices with nonlinear characteristics, such as gate transistors, generally, the greater the nonlinearity, the more suitable it is for the requirements of its application environment.

[0071] It should be understood that the above only lists the common meanings of these terms, and these terms may be interpreted differently depending on the specific implementation in which they are applied.

[0072] As mentioned above, it is desirable for the gate transistor to have a large degree of nonlinearity; the greater the nonlinearity, the more suitable it is for the requirements of its application environment. For example, the following example describes an application environment for the gate transistor with reference to a non-volatile memory environment.

[0073] Large-scale non-volatile memories (MRAMs) based on cross-point array architectures (e.g., RRAM, PCRAM, FeRAM, MRAM, etc.) are gaining increasing attention and use due to their high storage density and low power consumption. However, with advancements in memory technology, storage density and size are continuously decreasing, potentially leading to leakage current in these architectures. In such cases, during write (or read) operations, due to the parallel connection between memory cells, unselected cells connected to the same bit or word line as the selected cell may be affected by crosstalk voltages due to leakage current paths. Crosstalk voltages can cause unintended flips of these unselected cells, resulting in write (or read) errors. This significantly degrades memory performance, reduces the memory window, increases power consumption, and ultimately reduces the memory's competitiveness.

[0074] Therefore, it is desirable to introduce higher nonlinearity for the memory cells. In other words, when a memory cell is not selected, it is desirable to achieve a smaller current flow with a lower voltage, thereby reducing the effects of leakage current and crosstalk voltage. Furthermore, when a memory cell is selected, it is desirable to achieve a larger current flow with a higher voltage, thereby enabling precise operation of the memory cell. However, introducing nonlinearity into the memory cell itself is difficult to achieve; therefore, it is typically introduced by connecting the memory cell in series with a selector to form a 1S1R structure. The selector can have a large resistance value at a lower voltage (also called "bias"), exhibiting a high-resistance state (also called the "off state" of the selector), thereby reducing leakage current and crosstalk voltage. Furthermore, the selector can have a small resistance value at a higher voltage, exhibiting a low-resistance state (also called the "on state"), thus enabling precise selection of memory cells and precise operation (e.g., writing or reading) of the memory cell. In this case, it is desirable for the selector to have higher nonlinearity. The nonlinearity of a selector transistor can be expressed as the ratio of its "on-state" current to its "off-state" current; therefore, a high on-state current (or current density) is desirable. It should be understood that the larger voltage used for the "on-state" and the smaller voltage used for the "off-state" can be selected differently depending on the selector itself or its application environment.

[0075] Generally, gate transistors can be classified into conductive filament type gate transistors and bandgap type gate transistors based on their different conduction mechanisms. For conductive filament type gate transistors, the "on" and "off" states are achieved by whether or not a conductive filament is formed within the gate transistor. For bandgap type gate transistors, the aforementioned nonlinearity can be achieved through material type, structural shape (e.g., height and width), etc. Furthermore, because conductive filament type gate transistors have relatively low stability, bandgap type gate transistors are more commonly used.

[0076] For bandgap gates, nonlinearity is typically improved by enhancing the flatness of the thin film, reducing diffusion, or limiting the choice of dielectric material. However, this approach requires high-precision manufacturing processes, which is difficult to achieve ideally in actual production and hinders cost reduction.

[0077] In addition, there is a method to increase the nonlinearity of the gate transistor by increasing the contact area between the dielectric material of the dielectric layer and the electrode. However, this method results in a larger gate transistor size and greater manufacturing difficulty, as shown below. Figure 1 and Figure 2 As shown in the example. Figure 1 A schematic diagram of an example of a gate tube 100 is shown. Figure 2 A schematic diagram of another example of a gate 200 is shown. Figure 1 The gate transistor 100 includes electrodes 110 and 120 and a dielectric layer 130. The dielectric layer 130 has a groove shape, thereby contacting the electrode 120 on three surfaces, thus increasing the contact area between the dielectric layer and the electrode. This allows current to exist in the electrode 120 not only along the z-axis but also along the x-axis, thereby increasing the current density of the gate transistor 100 and increasing the nonlinearity of the gate transistor 100.

[0078] Figure 2 The gate transistor 200 includes electrodes 210 and 220 and a dielectric layer 230. Electrode 210 has a groove shape, and dielectric layer 230 is located in the groove of electrode 210. Dielectric layer 230 also has a groove shape, and electrode 220 is located in the groove of dielectric layer 230. Multiple surfaces of electrode 210 are in contact with dielectric layer 230, and multiple surfaces of dielectric layer 230 are in contact with electrode 220, thereby increasing the contact area between dielectric layer and electrode. This results in current flowing not only along the z-axis but also along the x-axis in electrodes 210 and 220, thereby increasing the current density of gate transistor 200 and increasing the nonlinearity of gate transistor 200.

[0079] However, Figure 1 and Figure 2The recessed structure of the gate transistors 100 and 200 requires a large space, resulting in a large gate transistor volume, which is not conducive to the miniaturization of the devices in which they are applied (e.g., the aforementioned memory). In addition, the recessed structure of the gate transistors 100 and 200 is difficult to manufacture, which is not conducive to reducing production costs.

[0080] To at least address or mitigate the aforementioned and other potential problems, embodiments of this application provide a gated transistor. The gated transistor includes a first electrode, a second electrode, multiple dielectric layers, and a first isolation layer. The multiple dielectric layers are located between the first and second electrodes. The multiple dielectric layers include a first dielectric layer and a second dielectric layer. The second dielectric layer surrounds the first dielectric layer. The first isolation layer is disposed between the first and second dielectric layers. By including multiple dielectric layers in the gated transistor, the ratio of the perimeter of the dielectric layers to their cross-sectional area can be increased, and the area of ​​the sidewalls can be increased, thereby increasing the edge electric field. As the edge electric field increases, the current density of the gated transistor also increases, thereby increasing the nonlinearity of the gated transistor. By disposing the first isolation layer of the gated transistor between the first and second dielectric layers in the multiple dielectric layers, the first and second dielectric layers can be electrically isolated, protecting the increased edge electric field. Through this protection, the current density of the gated transistor can be effectively increased, thereby effectively increasing the nonlinearity of the gated transistor and effectively improving its performance. The following refers to... Figures 3 to 6 An example of a gate tube according to this application is described.

[0081] Figure 3 A schematic diagram of an example of a gate tube 300 according to an embodiment of this application is shown. Figure 4 An embodiment according to this application is shown. Figure 3 Another schematic diagram 400 shows an example of a gate tube. Figure 3 and Figure 4The gate shown can be used in any electronic device. For example, it can be used in any type of chip in an electronic device, such as a control chip, a memory chip, an analog chip, a communication chip, or a logic chip. As an example, the chip to which gate 300 can be applied can be a non-volatile memory chip as described above. As another example, the chip to which gate 300 can be applied can be a neuromorphic computing chip (e.g., a neuromorphic computing chip based on devices such as memristors), where gate 300 can be combined with synaptic or neuronal units in the chip for selection of synaptic or neuronal units. As yet another example, the chip to which gate 300 can be applied can be a memory computing chip, where gate 300 can be used in a near-memory computing or in-memory computing architecture to achieve precise access (or selection) of the memory array. In another example, the selector 300 can be applied to an integrated chip of multiple chips (e.g., an AI product chip), and the selector can be used to precisely select a specific device or function within that chip. It should be understood that the above are merely examples of chips to which the selector 300 according to this application can be applied; depending on actual needs, the selector 300 according to this application can be applied to different application environments than those described above.

[0082] Figure 3 The diagram shown is a cross-section of the selector tube 300 parallel to the plane formed by the x-axis and z-axis. Figure 4 The diagram shows a cross-section of the selector tube 300 parallel to the plane formed by the x-axis and y-axis. (See diagram for example.) Figure 3 and Figure 4 As shown, the selector 300 includes a first electrode 310 and a second electrode 320. The selector 300 also includes multiple dielectric layers located between the first electrode 310 and the second electrode 320, and includes a first dielectric layer 331 and a second dielectric layer 332. The second dielectric layer 332 surrounds the first dielectric layer 331. The selector 300 also includes a first isolation layer 341 disposed between the first dielectric layer 331 and the second dielectric layer 332. Figure 4 As shown, in a cross-section of multiple dielectric layers parallel to the first electrode 310 or the second electrode 320, the first dielectric layer 331, the first insulating layer 341, and the second dielectric layer 332 can be one of the following shapes: concentric circles, concentric ellipses, or concentric polygons.

[0083] For example, Figure 4 Box 410 shows an example of concentric circles formed by the first dielectric layer 331, the first isolation layer 341, and the second dielectric layer 332. Figure 4Box 420 shows an example of a concentric ellipse formed by the first dielectric layer 331, the first isolation layer 341, and the second dielectric layer 332. Figure 4 Box 430 shows an example of a concentric quadrilateral formed by the first dielectric layer 331, the first isolation layer 341, and the second dielectric layer 332. Figure 4 Box 440 illustrates an example of a concentric hexagon formed by the first dielectric layer 331, the first isolation layer 341, and the second dielectric layer 332. It should be understood that... Figure 4 The examples shown are merely illustrative; depending on actual needs, the first dielectric layer 331, the first isolation layer 341, and the second dielectric layer 332 can have other shapes, such as concentric pentagons, concentric octagons, concentric dodecagons, etc. When the first dielectric layer 331, the first isolation layer 341, and the second dielectric layer 332 are concentric polygons, locally increased current can be achieved at the corners between any two adjacent sides of the polygon, thereby improving the nonlinearity of the switching transistor. Furthermore, although... Figure 4 The example concentric shapes shown all have central symmetry, but depending on actual needs (e.g., to simplify the manufacturing process and save costs), the concentric shapes formed by the first dielectric layer 331, the first isolation layer 341, and the second dielectric layer 332 may not have central symmetry. This application does not impose any restrictions on this comparison.

[0084] exist Figure 3 and Figure 4 In the example shown, the gate 300 is configured such that the voltage between the first electrode 310 and the second electrode 320 has a nonlinear relationship with the current flowing through the gate 300. For example, the gate 300 has a high degree of nonlinearity. Specifically, since the first dielectric layer 331 of the gate 300 has a sidewall adjacent to the first isolation layer 341, and the second dielectric layer 332 has a sidewall adjacent to the first isolation layer 341 and also has a sidewall away from the first isolation layer 341, the ratio of the perimeter of the dielectric layer to the cross-sectional area and the sidewall area of ​​the gate 300 according to this application are increased compared to conventional gates without such multiple layered dielectric layers parallel to the z-direction. The increased ratio and sidewall area can increase the edge electric field in the on-state of the gate, thereby increasing the current flowing through the sidewalls. As a result, the current density of the gate can be increased (this is also called the "edge perimeter effect"), thus making the gate 300 have a large degree of nonlinearity. Furthermore, the first isolation layer 341 can electrically isolate the first dielectric layer 331 and the second dielectric layer 332, thereby protecting against the increased edge electric field. This protection allows the nonlinearity of the selector to be effectively increased, thereby effectively improving the performance of the selector. For example, Table 1 below shows some examples of the nonlinearity of the selector according to this disclosure and the corresponding current density.

[0085] Table 1

[0086] In Table 1 above, the positive "+" and negative "-" voltage directions represent the positive and negative values ​​of the voltage applied to the second electrode 320 when the first electrode 310 is grounded, and vice versa. The specific values ​​of the applied positive "+" and negative "-" voltages can be determined according to the selector or the application environment. In Table 1, for selectors with the various sizes of the first electrode 310 or second electrode 320 as described above, the nonlinearity can be increased by 0.5 to 1 order of magnitude compared to conventional selectors without the multiple dielectric layers of this application. Furthermore, the selectors with the various sizes of the first electrode 310 or second electrode 320 in Table 1 can all have the same number of dielectric layers (e.g., all have a first dielectric layer and a second dielectric layer). As can be seen from Table 1, as the size of the first electrode 310 or second electrode 320 increases, the ratio of the perimeter to the cross-sectional area of ​​the dielectric layer between the first electrode 310 and the second electrode 320 decreases, resulting in a decrease in the increase in the side area relative to the cross-sectional area, and thus a decreasing trend in nonlinearity. This shows that the larger the ratio of the perimeter to the cross-sectional area of ​​the dielectric layer in the selector tube, the higher the nonlinearity of the selector tube.

[0087] In the case of the gate transistor configured as described above, to further improve the nonlinearity of the gate transistor and thus further improve its performance, in some embodiments, the thickness of the first isolation layer 341 can be less than 5 nm. In other embodiments, the thickness of the first isolation layer can be less than 2 nm. In still other embodiments, the thickness of the first isolation layer 341 can be less than 1 nm. For example, the thickness of the first isolation layer 341 can be 0.5 nm. For example, this extremely small thickness can be formed by growing a passivation layer material of several atomic periods using an ALD process, but it is not limited to this. Therefore, the thickness of the first isolation layer 341 can be very small, thus making its effect on the current density of the gate transistor 300 small, or even negligible. This allows the nonlinearity of the gate transistor 300 to be effectively increased, thereby effectively improving its performance.

[0088] Furthermore, to further increase the nonlinearity of the selector and improve its performance, in some embodiments, the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 50:1. In other embodiments, the thickness ratio is greater than 80:1. In still other embodiments, the thickness ratio is greater than 100:1. For example, when the thickness of the first dielectric layer or the second dielectric layer is 50 nm, the thickness ratio can be greater than 100:1. Thus, while the first isolation layer 341 provides electrical isolation between the first dielectric layer 331 and the second dielectric layer 332, the cross-sectional area of ​​the first isolation layer 341 is relatively small compared to the total cross-sectional area of ​​the multiple dielectric layers. This results in a smaller, even negligible, impact on the current flowing through the selector. This effectively increases the nonlinearity of the selector 300 and improves its performance. In this paper, the term “thickness” refers to the thickness along the x-axis, and the term “cross-sectional area” refers to the cross-sectional area in a plane parallel to the plane formed by the x-axis and y-axis.

[0089] Furthermore, in order to effectively increase the nonlinearity of the gate tube 300 by setting the first isolation layer 341 as described above, in order to improve the design flexibility of the first isolation layer 341 and thus improve the design flexibility of the gate tube 300, in some embodiments, the first isolation layer 341 may include at least one of the following: a passivation layer, an air layer, or a combination of a passivation layer and an air layer. Figure 3 and Figure 4 An example is shown where the first isolation layer 341 includes a passivation layer. In some embodiments, the material of the passivation layer is selected from at least one of the following: SiNx or SiON. Thus, different passivation layer materials can be flexibly selected according to actual needs, thereby further improving the design flexibility of the selector 300.

[0090] Figure 5 An example is shown where the first isolation layer includes an air layer. Figure 5 A schematic diagram of another example of a gate 500 according to an embodiment of this application is shown. Figure 5 Box 510 shows a view of a cross-section of the selector tube 500 parallel to the plane formed by the x-axis and z-axis. Figure 5 Box 520 shows a cross-section of the selector tube 500 parallel to the plane formed by the x-axis and y-axis. Figure 5 The gate tube 500 shown is Figure 3 and Figure 4 The only difference is that Figure 5 The first isolation layer 541 of the selector 500 is an air layer. It should be understood that, although... Figure 5 Box 520 only shows an example of the first dielectric layer 331, the first isolation layer 541, and the second dielectric layer 332 forming concentric circles. However, the first dielectric layer 331, the first isolation layer 541, and the second dielectric layer 332 can also form other shapes, such as the concentric ellipses or concentric polygons described above. It should be understood that the example of the first isolation layer including a combination of a passivation layer and an air layer can be used in conjunction with... Figure 3 and Figure 5 The gates 300 and 500 shown are similar.

[0091] With the first isolation layer configured as described above, in some embodiments, the first dielectric layer 331 and the second dielectric layer 332 of the selector 300 or 500 can be configured to include the same dielectric material. This allows the first dielectric layer 331 and the second dielectric layer 332 to have the same electrical characteristics, thereby further improving the performance of the selector 300 or 500. Furthermore, in some embodiments, the first dielectric layer 331 or the second dielectric layer 332 includes a single dielectric material. In this case, the manufacturing process of the first dielectric layer 331 and the second dielectric layer 332 can be simplified, thereby reducing the cost of the selector 300 or 500. In other cases, the first dielectric layer 331 or the second dielectric layer 332 can include multiple dielectric materials. For example, these multiple dielectric materials can be stacked along the z-axis direction. In this case, the nonlinearity of the selector can be further improved, further enhancing the performance of the selector. Furthermore, in some embodiments, the dielectric material of the first dielectric layer 331 or the second dielectric layer 332 may be selected from at least one of the following: Ta2O5, HfO2, TiO2, ZrO, SiO2, aSi, Al2O3, HfSiO4, ZrSiO4, La2O3, Y2O3, ZnO, NiO, or MgO. Thus, different dielectric materials can be flexibly selected according to actual needs (e.g., process space, or electrical requirements), thereby improving the design flexibility of the selector tube 300 or 500. For example, the thickness of the first dielectric layer or the second dielectric layer may be in the range of 4 nm to 10 nm, but is not limited to this.

[0092] Furthermore, with the first isolation layer 341, the first dielectric layer 331, and the second dielectric layer 332 configured as described above, in some embodiments, the first electrode 310 and the second electrode 320 of the selector 300 or 500 may comprise the same metal material or different metal materials. This increases the design flexibility of the first and second electrodes, thereby further enhancing the design flexibility of the selector 300 or 500. In some embodiments, the first electrode 310 or the second electrode 320 may comprise a metal material or an alloy thereof selected from at least one of the following: Pt, Ti, TiN, TaN, TiAl, Pd, Ir, W, Ta, or Ru. This allows for the flexible selection of different electrode materials according to actual needs, further improving the design flexibility of the selector 300 or 500.

[0093] In some embodiments, the dielectric materials of the first dielectric layer 331 and the second dielectric layer 332 can be arbitrarily combined with the metal materials or alloys of the first electrode 310 and the second electrode 320, thereby further improving the design flexibility and versatility of the selector. In other embodiments, specific combinations of dielectric materials and metal materials or alloys can be selected from the above-mentioned dielectric materials and metal materials or alloys according to actual needs, such as through simulation, so that the selector 300 or 500 can more accurately have the desired performance. This application does not impose any limitations on this.

[0094] In addition, although Figures 3 to 5 The illustrated gate includes only two dielectric layers and one isolation layer, but the gate of this application is not limited to this. For example, to further increase the nonlinearity of the gate, the multiple dielectric layers of the gate according to this application may include more dielectric layers, and the gate according to this application may correspondingly include more isolation layers. Figure 6 A schematic diagram of another example of a gate 600 according to an embodiment of this application is shown. Figure 6 In, relative to Figure 3 The gate tube 300 shown is... Figure 6 The multiple dielectric layers of the gate 600 shown also include a third dielectric layer 633, which surrounds the second dielectric layer 332. Furthermore, Figure 6 The gate 600 shown also includes a second isolation layer 642, which is disposed between the second dielectric layer 332 and the third dielectric layer 633. In a plane parallel to the plane formed by the x-axis and y-axis, the first dielectric layer 331, the first isolation layer 341, the second dielectric layer 332, the second isolation layer 642, and the third dielectric layer 633 of the gate 600 can form a structure similar to... Figure 4 The concentric circles, concentric ellipses, or concentric polygons shown.

[0095] Furthermore, in some embodiments, the third dielectric layer 633 may have the same dielectric material as the first dielectric layer 331 and the second dielectric layer 332. For example, the third dielectric layer 633 may have the dielectric materials listed above. This allows each of the plurality of dielectric layers in the gate transistor to have the same electrical characteristics, thereby further improving the performance of the gate transistor. Furthermore, the second isolation layer 642 may be disposed similarly to the first isolation layer 341. In some embodiments, the thickness of the second isolation layer 642 may be less than 5 nm. In other embodiments, the thickness of the second isolation layer 642 may be less than 2 nm. In still other embodiments, the thickness of the second isolation layer 642 may be less than 1 nm. Thus, similar to the first isolation layer 341, the second isolation layer 642 can further effectively improve the nonlinearity of the gate transistor while achieving electrical isolation between the second dielectric layer 332 and the third dielectric layer 633, thereby further effectively improving the performance of the gate transistor. It should be understood that the thickness of the second isolation layer 642 may be set to be the same as or different from the thickness of the first isolation layer 341.

[0096] Furthermore, in some embodiments, the thickness ratio of the second isolation layer 642 to the first dielectric layer 331, the second dielectric layer 332, or the third dielectric layer 633 is greater than 50:1. In other embodiments, the thickness ratio of the second isolation layer 642 to the first dielectric layer 331, the second dielectric layer 332, or the third dielectric layer 633 is greater than 80:1. In still other embodiments, the thickness ratio of the second isolation layer 642 to the first dielectric layer 331, the second dielectric layer 332, or the third dielectric layer 633 is greater than 100:1. This allows the cross-sectional area of ​​the second isolation layer 642 to be relatively small relative to the total cross-sectional area of ​​the multiple dielectric layers, thus minimizing, or even negligible, the impact of the second isolation layer 642 on the current flowing through the selector. This effectively increases the nonlinearity of the selector, thereby effectively improving its performance. Furthermore, the second isolation layer 642 includes at least one of the following: a passivation layer, an air layer, or a combination of a passivation layer and an air layer. The material of the passivation layer can be selected from at least one of the following: SiNx or SiON. This further improves the design flexibility of the pass-through. It should be understood that the structure (passivation layer, air layer, or a combination of passivation layer and air layer) and material of the second isolation layer 642 can be the same as or different from the structure and material of the first isolation layer 341.

[0097] above Figures 3 to 6The gate tube shown is merely an example. Depending on actual needs, the multiple layers of the gate tube according to this application may include three or more dielectric layers. Correspondingly, the gate tube may include two or more isolation layers located between the dielectric layers. More dielectric layers and more isolation layers can be arranged similarly to the above, and this application does not impose any limitations on this. Furthermore, the specific values ​​of thickness and proportion shown above, as well as the specific materials listed above, are merely examples. Depending on actual needs, the gate tube may have different values ​​and materials than those described above. See below for reference. Figures 7 to 17 Examples of methods for manufacturing a gate tube according to embodiments of this application are described below. Figures 7 to 17 Manufacturing process is shown Figure 3 The example of the gate 300 shown should be understood. Figures 7 to 17 The method is also suitable for manufacturing any other gate tubes, such as gate tubes 500, 600, or other gate tubes that include more dielectric layers and isolation layers.

[0098] Figure 7 A flowchart of a method 700 for manufacturing a gate transistor 300 according to an embodiment of this application is shown. The execution subject of the method 700 may be any one or more controllers capable of controlling the manufacturing process of the gate transistor, such as controllers, control modules, or control chips among one or more of the following: devices for forming electrodes, devices for depositing dielectric materials, and devices for etching.

[0099] like Figure 7 As shown, a first electrode is formed at box 710. As an example, this first electrode 310 can be formed, for example, by processes such as PVD or ALD. A second electrode is formed at box 720. As an example, this second electrode 320 can be formed, for example, by processes such as PVD or ALD. Multiple dielectric layers are formed at box 730. These multiple dielectric layers are located between the first electrode and the second electrode. Forming multiple dielectric layers at box 730 includes: forming a first dielectric layer at box 731. Forming multiple dielectric layers at box 730 also includes: forming a second dielectric layer at box 732, the second dielectric layer surrounding the first dielectric layer. A first insulating layer is formed at box 740, the first insulating layer being located between the first dielectric layer and the second dielectric layer. It should be understood that... Figure 7 The order of boxes 710-740 shown is merely an example; in actual manufacturing, boxes 710-740 can be arranged in the same order as... Figure 7 The different orders shown are used for execution. For example, Figures 8 to 13 An example of the process for manufacturing the gate tube 300 is shown. Figure 8 , Figure 9 Combination Figures 14 to 17 Another example of the process for manufacturing the gate tube 300 is shown.

[0100] Figure 8 A schematic diagram of an example of forming a first electrode 310 according to an embodiment of this application is shown. Figure 8 Corresponding to Figure 7 Box 710 in Figure 8 In the process, the first electrode 310 is formed. During execution... Figure 7 Following block 710, block 731 can be executed to form the first dielectric layer. Block 731 may include, for example: Figure 9 The schematic diagram 731-1 shows the formation of the first initial first dielectric layer 910, and Figure 10 The first dielectric layer 331 is formed as shown in schematic diagram 731-2. Figure 9 A schematic diagram 731-1 illustrates an example of forming an initial first dielectric layer 910 according to an embodiment of this application. The initial first dielectric layer 910 is formed by depositing (e.g., in any deposition manner) dielectric material on the first electrode 310. Figure 10 Schematic diagram 731-2 illustrates an example of forming a first dielectric layer 331 according to an embodiment of this application. The outer peripheral portion of the first initial dielectric layer 910 is etched (e.g., by photolithography, but not limited thereto) to form the first dielectric layer 331.

[0101] After the first dielectric layer 331 is formed, execution can be performed. Figure 7 The frame 740 forms the first isolation layer. Figure 11 A schematic diagram illustrating an example of forming a first isolation layer 341 according to an embodiment of this application is shown. Figure 11 As shown, in Figure 7 At frame 740, a first isolation layer 341 is formed around the first dielectric layer 331. In one example, the first isolation layer 341 can be formed by depositing a passivation layer around the first dielectric layer 331 using an ALD process. In another example, the first isolation layer 341 can be formed by first depositing a passivation layer material on all areas of the first electrode 310 except for the area where the first dielectric layer 331 is located, and then etching the outer peripheral portion. In yet another example, the first isolation layer 341 can be formed using a lateral deposition process (e.g., 3D structure filling).

[0102] After the first isolation layer 341 is formed, execution can proceed. Figure 7 The frame 732 forms the second dielectric layer. Figure 12 A schematic diagram illustrating an example of forming a second dielectric layer 332 according to an embodiment of this application is shown. Figure 12 As shown, a second dielectric layer 332 is formed around the first isolation layer 341. The second dielectric layer 332 can be formed by any deposition method. After the second dielectric layer 332 is formed, the following can be performed: Figure 7 The frame 740 forms the second electrode 320. Figure 13A schematic diagram illustrating an example of forming a second electrode 320 according to an embodiment of this application is shown. Figure 13 As shown, a second electrode 320 is formed on the first dielectric layer 331, the first insulating layer 341, and the second dielectric layer 332. Therefore, a [missing information - likely a specific material or structure] can be manufactured. Figure 3 The gate tube 300 is shown.

[0103] Furthermore, in the gated tube where it is desired to form a first isolation layer including an air layer (e.g., Figure 5 In the case of the gate tube 500 shown, or a gate tube including a first isolation layer consisting of an air layer and a passivation layer, it can be obtained by etching all or part of it. Figure 13 The passivation layer of the first isolation layer 341 shown is implemented. Furthermore, it should be understood that more isolation layers and more dielectric layers can be formed by repeating the above-described formation process of the first isolation layer and the second dielectric layer. For example, the method according to this disclosure may further include: forming a second isolation layer surrounding the second dielectric layer 332; and forming a third dielectric layer surrounding the second isolation layer. Thus, a material such as... Figure 6 The gate tube 600 is shown. Furthermore, gate tubes comprising three or more dielectric layers and two or more isolation layers can also be manufactured similarly to those described above.

[0104] The above describes one example of the process for manufacturing a gate tube. The following describes another example of the process for manufacturing a gate tube. In this other example, firstly... Figure 8 and Figure 9 As shown, in Figure 7 The first electrode 310 is formed at frame 710, and... Figure 7 An initial first dielectric layer 910 is formed at frame 731. Then, execution... Figure 7 The frame 720 forms the second electrode 320. Figure 14 A schematic diagram 720' shows another example of forming a second electrode according to an embodiment of this application. (See diagram 720') Figure 14 As shown, a second electrode 320 is formed on the initial first dielectric layer 910. After the second electrode 320 is formed, it is possible to... Figure 7 The outer peripheral portion of the initial first dielectric layer 910 is etched at frame 731 (e.g., by a chemical etching process, etc.) to form the first dielectric layer 331. For example, the etching time can be controlled according to the etching rate to obtain a first dielectric layer with a desired thickness. Figure 15 Schematic diagram 731-2' shows another example of forming a first dielectric layer according to an embodiment of this application. Figure 15 In this process, the first dielectric layer 331 is formed. Afterwards, execution can proceed. Figure 7 The frame 740 forms the first isolation layer 341. Figure 16A schematic diagram 740' shows another example of forming a first isolation layer according to an embodiment of this application. (See diagram 740') Figure 6 As shown, a first isolation layer 341 is formed around the first dielectric layer 331. Afterwards, execution can be performed. Figure 7 The frame 732 forms the second dielectric layer 332. Figure 17 A schematic diagram 732' of another example of forming a second dielectric layer 332 according to an embodiment of this application is shown. Figure 17 As shown, a second dielectric layer 322 is formed. Therefore, it is possible to manufacture... Figure 3 The gate tube 300 is shown. Furthermore, it should be understood that, based on the above example process, gate tubes comprising more dielectric layers and more corresponding isolation layers can also be manufactured, for example, Figure 6 The gate tube 600 shown or other gate tubes including three or more dielectric layers and two or more isolation layers.

[0105] The gate transistor manufactured according to the method described in this application comprises multiple dielectric layers, which can increase the ratio of the perimeter to the cross-sectional area of ​​the dielectric layers and increase the area of ​​the sidewalls, thereby increasing the edge electric field. As the edge electric field increases, the current density of the gate transistor also increases, thereby increasing the nonlinearity of the gate transistor. By arranging a first isolation layer of the gate transistor between the first and second dielectric layers, the first and second dielectric layers can be electrically isolated, protecting the increased edge electric field. Through this protection, the current density of the gate transistor can be effectively increased, thereby effectively increasing the nonlinearity of the gate transistor and effectively improving its performance.

[0106] Furthermore, in some embodiments, the first isolation layer includes at least one of the following: a passivation layer, an air layer, or a combination of a passivation layer and an air layer. In some embodiments, the material of the passivation layer is selected from at least one of the following: SiNx or SiON. In some embodiments, the thickness of the first isolation layer is less than 5 nm, or the thickness of the first isolation layer is less than 2 nm, or the thickness of the first isolation layer is less than 1 nm. In some embodiments, the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 50:1, or the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 80:1, or the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 100:1.

[0107] In some embodiments, the first dielectric layer and the second dielectric layer comprise the same dielectric material. In some embodiments, the first dielectric layer or the second dielectric layer comprises a single dielectric material or multiple dielectric materials. In some embodiments, the dielectric material is selected from at least one of the following: Ta2O5, HfO2, TiO2, ZrO, SiO2, aSi, Al2O3, HfSiO4, ZrSiO4, La2O3, Y2O3, ZnO, NiO, or MgO. In some embodiments, the first electrode and the second electrode comprise the same metallic material or different metallic materials. In some embodiments, the first electrode or the second electrode comprises a metallic material or an alloy thereof selected from at least one of the following: Pt, Ti, TiN, TaN, TiAl, Pd, Ir, W, Ta, or Ru. In some embodiments, the third dielectric layer has the same dielectric material as the first dielectric layer and the second dielectric layer. In some embodiments, the thickness of the second isolation layer is less than 5 nm, or the thickness of the second isolation layer is less than 2 nm, or the thickness of the second isolation layer is less than 1 nm.

[0108] In some embodiments, in a cross-section of the plurality of dielectric layers parallel to the first electrode or the second electrode, the first dielectric layer, the first insulating layer, and the second dielectric layer are in one of the following shapes: concentric circles, concentric ellipses, or concentric polygons. In some embodiments, the gate is configured such that the voltage between the first electrode and the second electrode has a non-linear relationship with the current flowing through the gate. For example, the gate 300 has a high degree of non-linearity. It should be understood that the gate manufactured according to the above method of this disclosure has the above-mentioned reference. Figures 3 to 6 The advantages described will not be repeated here.

[0109] Based on the above embodiments, embodiments of this application also provide a chip. The chip includes a gate transistor according to any of the embodiments described above, and includes a package. The package is configured to encapsulate the gate transistor.

[0110] Based on the above embodiments, embodiments of this application also provide an electronic component. This electronic component includes a chip according to any of the embodiments described above, and includes a circuit board. The circuit board is configured to support the chip. In one example, the circuit board is a printed circuit board. Alternatively, the circuit board may also be a flexible circuit board disposed on a substrate.

[0111] Based on the above embodiments, embodiments of this application also provide an electronic device. This electronic device includes a chip according to any of the embodiments described above, and includes a power supply circuit. The power supply circuit is configured to supply power to the chip. In one example, the electronic device may be a terminal device such as a mobile phone, tablet computer, or computer. The power supply circuit may be a circuit built into the terminal device, connected to a battery, and supplying power from the battery directly or through conversion to the chip. Alternatively, the power supply circuit may be an external power adapter, etc. It is understood that the electronic device disclosed herein is not limited to terminal devices, but may also be a server, base station, or other electronic devices using the chip.

[0112] This disclosure can be a method, apparatus, system, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of this disclosure.

[0113] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0114] Various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A selection tube, characterized in that, include: First electrode; Second electrode; Multiple dielectric layers are located between the first electrode and the second electrode, wherein the multiple dielectric layers include: First dielectric layer; and A second dielectric layer surrounds the first dielectric layer; and A first isolation layer is disposed between the first dielectric layer and the second dielectric layer.

2. The selection tube according to claim 1, characterized in that, The first isolation layer includes at least one of the following: a passivation layer, an air layer, or a combination of a passivation layer and an air layer.

3. The selection tube according to claim 1 or 2, characterized in that, The thickness of the first isolation layer is less than 5 nm, or the thickness of the first isolation layer is less than 2 nm, or the thickness of the first isolation layer is less than 1 nm.

4. The selection tube according to any one of claims 1-3, characterized in that, The thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 50:1, or the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 80:1, or the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 100:

1.

5. The selection tube according to any one of claims 1-4, characterized in that, The first dielectric layer and the second dielectric layer comprise the same dielectric material.

6. The selection tube according to any one of claims 1-5, characterized in that, The first dielectric layer or the second dielectric layer may include a single dielectric material or multiple dielectric materials.

7. The selection tube according to claim 5 or 6, characterized in that, The medium material is selected from at least one of the following: Ta2O5, HfO2, TiO2, ZrO, SiO2, aSi, Al2O3, HfSiO4, ZrSiO4, La2O3, Y2O3, ZnO, NiO, or MgO.

8. The selection tube according to any one of claims 1-7, characterized in that, The first electrode and the second electrode may be made of the same metal material or different metal materials.

9. The selection tube according to claim 8, characterized in that, The first electrode or the second electrode comprises a metallic material or an alloy thereof selected from at least one of the following: Pt, Ti, TiN, TaN, TiAl, Pd, Ir, W, Ta, or Ru.

10. The selection tube according to any one of claims 2-9, characterized in that, The material of the passivation layer is selected from at least one of the following: SiNx or SiON.

11. The selection tube according to any one of claims 1-10, characterized in that, The plurality of dielectric layers also include: A third dielectric layer surrounds the second dielectric layer. The gate tube further includes: A second isolation layer is disposed between the second dielectric layer and the third dielectric layer.

12. The selection tube according to claim 11, characterized in that, The third dielectric layer has the same dielectric material as the first dielectric layer and the second dielectric layer.

13. The selection tube according to claim 11 or 12, characterized in that, The thickness of the second isolation layer is less than 5 nm, or the thickness of the second isolation layer is less than 2 nm, or the thickness of the second isolation layer is less than 1 nm.

14. The selection tube according to any one of claims 1-13, characterized in that, In a cross-section of the plurality of dielectric layers parallel to the first electrode or the second electrode, the first dielectric layer, the first insulating layer, and the second dielectric layer are in one of the following shapes: concentric circles, concentric ellipses, or concentric polygons.

15. The selection tube according to any one of claims 1-14, characterized in that, The gate is configured such that the voltage between the first electrode and the second electrode has a non-linear relationship with the current flowing through the gate.

16. A method for manufacturing a gate tube, characterized in that, include: Form the first electrode; Form a second electrode; Forming a plurality of dielectric layers, the plurality of dielectric layers being located between the first electrode and the second electrode, wherein forming the plurality of dielectric layers includes: Forming the first dielectric layer; and A second dielectric layer is formed, the second dielectric layer surrounding the first dielectric layer; and A first isolation layer is formed, which is located between the first dielectric layer and the second dielectric layer.

17. The method according to claim 16, characterized in that, Forming the first dielectric layer includes: Depositing a dielectric material on the first electrode to form an initial first dielectric layer; and The outer peripheral portion of the initial first dielectric layer is etched to form the first dielectric layer.

18. The method according to claim 17, characterized in that, The formation of the first isolation layer includes: The first isolation layer is formed around the first dielectric layer. The formation of the second dielectric layer includes: A second dielectric layer is formed around the first isolation layer. The formation of the second electrode includes: The second electrode is formed on the first dielectric layer, the first isolation layer, and the second dielectric layer.

19. The method according to claim 17, characterized in that, Forming the second electrode includes: Before etching the outer peripheral portion of the initial first dielectric layer, the second electrode is formed on the initial first dielectric layer. The formation of the first isolation layer includes: After etching the outer peripheral portion of the initial first dielectric layer, the first isolation layer is formed around the first dielectric layer. The formation of the second dielectric layer includes: The second dielectric layer is formed around the first isolation layer.

20. The method according to any one of claims 16-19, characterized in that, The thickness of the first isolation layer is less than 5 nm, or the thickness of the first isolation layer is less than 2 nm, or the thickness of the first isolation layer is less than 1 nm.

21. The method according to any one of claims 16-20, characterized in that, The thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 50:1, or the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 80:1, or the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 100:

1.

22. The method according to any one of claims 16-21, characterized in that, The method further includes: A second isolation layer is formed, which surrounds the second dielectric layer. The formation of multiple dielectric layers also includes: A third dielectric layer is formed, which surrounds the second isolation layer.

23. A chip, characterized in that, include: The gate tube according to any one of claims 1-15; as well as The package is configured to encapsulate the gate.

24. An electronic component, characterized in that, include: The chip according to claim 23; as well as A substrate is configured to support the chip.

25. An electronic device, characterized in that, include: The chip according to claim 23; as well as The power supply circuit is configured to supply power to the chip.

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