Wafer warping prediction method and device, equipment and storage medium

Abstract

The invention provides a wafer warping prediction method and device, equipment and a storage medium. The method comprises the steps that a finite element warping prediction model of a wafer to be predicted is determined, and at least one metal interconnection layer is arranged on the wafer to be predicted; for any metal interconnection layer in the at least one metal interconnection layer, obtaining the equivalent internal stress of the metal interconnection layer; and predicting a target warping value corresponding to the wafer to be predicted according to the equivalent internal stress corresponding to each metal interconnection layer and the finite element warping prediction model.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing and testing technology, and in particular to a method, apparatus, device and storage medium for predicting wafer warpage. Background Technology

[0002] In semiconductor manufacturing, wafer warpage is a significant factor affecting the performance and yield of semiconductor devices. With the increasing integration density of semiconductor devices, multilayer metal interconnect structures and various materials are being used. However, differences in the coefficient of thermal expansion (CTE) between different materials and the accumulation of internal stress among various materials can lead to varying degrees of wafer warpage during processing. Currently, a common approach is to combine Timoshenko's two-layer theory with finite element analysis, using the stress-free temperature of the equivalent redistribution layer (RDL) to predict wafer warpage. However, this method struggles to accurately reflect the impact of actual internal stress states on warpage when dealing with high-density metal ratios, multilayer interconnect structures, and complex combinations of dielectric materials, particularly in assessing the overall warpage changes caused by stress mismatches between different materials. Summary of the Invention

[0003] This application provides a method, apparatus, device, and storage medium for predicting wafer warpage, which solves the problem that existing technologies struggle to assess the impact of dielectric and metallic materials on warpage in multilayer metal interconnect structures.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides a method for predicting wafer warpage, comprising: determining a finite element warpage prediction model for a wafer to be predicted, wherein at least one metal interconnect layer is disposed on the wafer to be predicted; obtaining the equivalent internal stress of any metal interconnect layer among the at least one metal interconnect layer; and predicting the target warpage value corresponding to the wafer to be predicted based on the equivalent internal stress corresponding to each metal interconnect layer and the finite element warpage prediction model.

[0005] This application provides a wafer warpage prediction device, comprising: a determination module for determining a finite element warpage prediction model of a wafer to be predicted, wherein at least one metal interconnect layer is disposed on the wafer to be predicted; and a prediction module for obtaining the equivalent internal stress of any one of the at least one metal interconnect layer; and predicting the target warpage value corresponding to the wafer to be predicted based on the equivalent internal stress corresponding to each metal interconnect layer and the finite element warpage prediction model.

[0006] This application provides a wafer warpage prediction device, comprising: Memory is used to store executable instructions or computer programs. When a processor executes computer-executable instructions or computer programs stored in the memory, it implements the prediction method provided in the embodiments of this application.

[0007] This application provides a computer-readable storage medium storing a computer program or computer-executable instructions for implementing the prediction method provided in this application when executed by a processor.

[0008] This application provides a computer program product, including a computer program or computer executable instructions, which, when executed by a processor, implements the prediction method provided in this application.

[0009] The embodiments of this application have the following beneficial effects: First, by constructing a finite element warpage prediction model and calculating the equivalent internal stress for each metal interconnect layer, the influence of different materials and structures on wafer warpage during actual manufacturing can be more accurately reflected. Furthermore, by substituting the equivalent internal stress as an input parameter into the finite element model for warpage prediction, the error problem caused by neglecting internal stress differences in the traditional stress-free temperature equivalence method can be avoided, thereby improving the accuracy of warpage prediction. This method is particularly suitable for complex structures with high-density metal distribution or mismatched thermal expansion coefficients of multiple materials, solving the problem that existing technologies struggle to assess the influence of dielectric and metallic materials on warpage in multilayer metal interconnect structures. Attached Figure Description

[0010] Figure 1 This is an exemplary flowchart illustrating a wafer warpage prediction method provided in this application embodiment. Figure 1 ; Figure 2 This is an exemplary flowchart illustrating a wafer warpage prediction method provided in this application embodiment. Figure 2 ; Figures 3-6 This is an exemplary layout diagram of the metal sublayer provided in the embodiments of this application; Figure 7 This is an exemplary schematic diagram illustrating the conservation of deflection provided in an embodiment of this application; Figure 8 This is an exemplary flowchart illustrating a wafer warpage prediction method provided in this application embodiment. Figure 3 ; Figure 9 This is an exemplary structural schematic diagram of a wafer warpage prediction device provided in an embodiment of this application; Figure 10 This is an exemplary structural diagram of a wafer warpage prediction device provided in an embodiment of this application.

[0011] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] Terms used in some descriptions, such as metal interconnect layer, internal stress, finite element model, and warpage value, are core technical concepts of this application and require explanation to ensure consistent understanding. The following is a detailed explanation of the relevant terms: 1) Metal interconnect layer: This can refer to the metal structure layer formed on the wafer for circuit connection. It can include metal wiring materials and dielectric filling materials. Its thickness, distribution and material properties directly affect the overall deformation behavior of the wafer.

[0014] 2) Internal Stress: During the manufacturing process, unbalanced forces within the material caused by processes such as material deposition, heat treatment, or cooling act on the wafer surface, causing warping or bending deformation. Different materials (such as metals and dielectrics) have different internal stress states, and their combined effect determines the overall degree of wafer warping.

[0015] 3) Finite Element Model (FEM): A numerical computation-based method that simulates the distribution of physical fields (such as stress, strain, temperature, etc.) within a structure by discretizing a complex structure into multiple small elements (mesh). In this application, the finite element warpage prediction model is used to predict the warpage of wafers under various internal stress conditions.

[0016] 4) Warpage Value: Used to quantify the degree of warpage of a wafer under specific conditions, usually expressed as the maximum displacement or curvature. In this application, by modeling the equivalent internal stress of each metal interconnect layer and inputting it into the finite element model, the target warpage value of the entire wafer to be predicted can be obtained.

[0017] 5) Equivalent Internal Stress: This can refer to the equivalent internal stress of a wafer in the back-end of line (BEOL) process, based on Timoshenko's layered beam theory (or Timoshenko's two-layer theory), which treats the wafer as a substrate layer plus an equivalent redistribution layer (RDL). In this application, the equivalent RDL can refer to any one of the at least one metal interconnect layer on the wafer to be predicted, and the metal interconnect layer includes a metal sublayer and a dielectric sublayer. Based on this, the contribution of each metal sublayer and dielectric sublayer to the warpage of the wafer to be predicted is calculated separately. Then, through the principle of deflection conservation, these contributions are combined into an equivalent internal stress value to replace the actual complex multi-material stress state, thereby simplifying the finite element analysis process and improving prediction accuracy. Here, this equivalent internal stress value is also the equivalent internal stress of the aforementioned equivalent RDL, or the equivalent internal stress corresponding to the metal interconnect layer. The subsequent equivalent deflection, equivalent Young's modulus, etc., all refer to the parameters corresponding to the metal interconnect layer, which will not be elaborated on in detail later.

[0018] 6) Deflection Coefficient: A parameter used to characterize the effect of unit internal stress on wafer warpage. This deflection coefficient is determined by the wafer's basic geometric parameters (such as diameter and thickness), the material's elastic modulus, and the layout characteristics of the metal or dielectric layers. By calculating the deflection coefficients of the metal and dielectric sublayers, the equivalent internal stress can be further derived.

[0019] 7) Representative Volume Element (RVE): A microscopic representative unit used in multi-scale modeling to estimate the equivalent mechanical properties of composite materials. In this application, RVE can be used to model the periodic structure of the metal interconnect layer to obtain the equivalent elastic modulus (or equivalent Young's modulus) and coefficient of thermal expansion, thereby supporting macroscopic warpage prediction.

[0020] 8) Coefficient of Thermal Expansion (CTE): The proportionality of a material's length or volume change when the temperature changes. In wafer warpage prediction, due to the significant difference in CTE between metals and dielectric materials, thermal stress becomes one of the important factors leading to warpage.

[0021] 9) Stress-free temperature: refers to the temperature at which a material is free of residual stress. In existing technologies, the stress-free temperature equivalent method is often used to approximate the wafer warpage problem, but this method is difficult to accurately reflect the actual stress state of multilayer heterogeneous materials.

[0022] As described in the background section, existing technologies that predict wafer warpage using the stress-free temperature equivalence method often neglect the differences in internal stress among various materials (such as metal and dielectric materials) in the metal interconnect layer and their cumulative effect on warpage, leading to significant prediction errors, especially in wafer structures with high-density metal ratios. Furthermore, traditional methods struggle to effectively assess the impact of different dielectric materials on wafer warpage, failing to meet the needs of complex wafer structures for manufacturing risk control and process optimization during the design phase.

[0023] To address the aforementioned technical problems, this application proposes a method for predicting wafer warpage. The core of this method lies in introducing an equivalent computational mechanism for the internal stress of the metal sublayer and dielectric sublayer, combined with a finite element warpage prediction model. This method can more accurately assess the combined impact of different materials on wafer warpage, significantly improving prediction accuracy, thereby enabling early identification of manufacturing risks and optimization of process paths during the wafer design stage.

[0024] The technical solution of this application will be described in detail below with reference to the accompanying drawings and embodiments.

[0025] See Figure 1 This is an exemplary flowchart illustrating a method for predicting wafer warpage provided in this application. The following will be combined with... Figure 1 The steps shown are explained as follows: Figure 1 As shown, the prediction method may include the following steps 101 to 103.

[0026] Step 101: Determine the finite element warpage prediction model of the wafer to be predicted, wherein at least one metal interconnect layer is disposed on the wafer to be predicted.

[0027] It should be noted that the method for predicting wafer warpage can be executed by a computer system or simulation platform, which includes, but is not limited to, simulation software based on finite element analysis, data processing servers, etc. In this application, the wafer to be predicted can refer to a wafer in the BEOL stage of any integrated circuit manufacturing process. In the BEOL stage, the main tasks include the fabrication of metal interconnect layers (such as forming wires, contact holes, vias, etc.), the deposition and planarization of insulating layers (dielectrics), and the formation of the final passivation layer and pads on the wafer.

[0028] In practical implementation, at least one metal interconnect layer can be deployed on the wafer to be predicted, and each metal interconnect layer can contain a metal sublayer and a dielectric sublayer. The metal materials and dielectric materials used in different metal interconnect layers can be the same or different. The wafer-level finite element warpage prediction model is a computer simulation model used to simulate and analyze the mechanical, thermal, and electrical behavior of the entire semiconductor wafer during manufacturing, packaging, or testing. Its main idea is to discretize a real wafer containing multiple complex thin-film structures (such as metal interconnect layers) in a computer using mathematical methods. For example, it can be divided into millions or even billions of simple, interconnected micro-units (such as hexahedral or tetrahedral units) to form a mesh system. Then, by solving physical equations (such as mechanical equilibrium equations, heat conduction equations, etc.), the response of the wafer under external loads (such as temperature changes, mechanical forces, etc.) can be predicted. The composition of this finite element warpage prediction model can be summarized in the following four aspects. Firstly, the geometry mainly includes: a substrate and a stack of thin film layers, wherein the substrate can be a silicon substrate; the stack of thin film layers can include layers formed in the front-end process (FEOL) stage (e.g., shallow trench isolation, gate stack, etc.) and the BEOL stage (e.g., metal interconnect layers, etc.). Secondly, material properties, each material is endowed with precise temperature-dependent mechanical and thermal properties, wherein the aforementioned material and thermal properties can include elastic modulus (or Young's modulus), Poisson's ratio, coefficient of thermal expansion, etc. Thirdly, loads and boundary conditions, to define the physical environment in which the finite element warp prediction model exists, wherein the loads can include: thermal loads, internal stress loads, mechanical loads, etc. The boundary conditions can be constraints on the displacement of the wafer in certain directions (e.g., simulating the support points of the wafer on the carrier). Fourthly, the physical field and solution objective, to define the specific problem to be analyzed, wherein the physical field can include internal stress / strain fields, displacement / warp fields, etc. In this embodiment of the application, the warpage prediction model is used to predict the warpage of the entire wafer based on the equivalent internal stress of the metal interconnect layer, so as to analyze the degree of influence of the equivalent internal stress of the metal interconnect layer on the warpage of the wafer.

[0029] In this embodiment, before calculating the target warpage of the wafer to be predicted, it is first necessary to obtain the wafer's geometry, material properties, loads (internal stress loads), boundary conditions, physical field, and solution objective according to the method described above, in order to establish a wafer-level finite element warpage prediction model for subsequent use. This finite element warpage prediction model includes a sub-finite element model corresponding to each metal interconnect layer, which is used to simulate the corresponding metal interconnect layer. In other words, the sub-finite element model is used to equivalently represent the corresponding metal interconnect layer, which can then be applied to predict wafer warpage.

[0030] Step 102: For any one of the at least one metal interconnect layers, obtain the equivalent internal stress of the metal interconnect layer.

[0031] It should be noted that after obtaining the finite element warp prediction model as described above, since the calculation method of the equivalent internal stress of each metal interconnect layer and the calculation method of the warp value of the wafer to be predicted under the equivalent internal stress are the same, in this embodiment of the application, only the calculation method of the equivalent internal stress of a metal interconnect layer and the calculation method of the warp value of the wafer to be predicted under the equivalent internal stress are used as examples for explanation. That is, for any metal interconnect layer provided on the wafer to be predicted, the equivalent internal stress of the metal interconnect layer can be obtained.

[0032] In some embodiments, such as Figure 2 As shown, obtaining the equivalent internal stress of the metal interconnect layer in step 102 may include steps 201 to 203.

[0033] Step 201: Obtain the first deflection generated under the internal stress of the metal sublayer.

[0034] It should be noted that the metal sublayer can refer to the conductive material layer of the metal interconnect layer, which can be made of highly conductive metals such as copper (Cu) and aluminum (Al), and can be used to realize electrical connections between different regions on the wafer to be predicted. During the manufacturing process, this metal sublayer will generate certain residual internal stress, i.e., metal internal stress. This metal internal stress will affect the overall warpage of the wafer to be predicted due to the mismatch in thermal expansion coefficients, and can be obtained through finite element simulation calculations or experimental testing.

[0035] In some embodiments, step 201 may include: obtaining the metal deflection coefficient of the metal sublayer, and determining the product of the metal deflection coefficient and the metal internal stress as the first deflection.

[0036] It should be noted that the metal deflection coefficient can be a quantitative parameter representing the degree of bending of the wafer under test when a unit area or unit volume of metal material is subjected to internal metal stress. It reflects the ability of the metal material to influence the overall warpage of the wafer under specific process conditions. The first deflection can be the displacement of a certain position on the surface of the wafer under test relative to the original plane under the action of internal metal stress in the metal sublayer. It is an important indicator for measuring the degree of deformation of the wafer under test and directly affects the yield of the wafer. Therefore, in this application, the product of the metal deflection coefficient and the internal metal stress can be used as the first deflection.

[0037] In some embodiments, an optional method for obtaining the metal deflection coefficient of the metal sublayer may include: obtaining a first basic parameter of the wafer to be predicted; the first basic parameter includes the diameter, a first thickness, and the Young's modulus of the substrate of the wafer to be predicted; obtaining a second basic parameter of the metal sublayer; the second basic parameter includes a second thickness of the metal interconnect layer and a first volume and the Young's modulus of the metal sublayer on the wafer to be predicted; and obtaining the metal deflection coefficient based on the diameter, the first thickness, the Young's modulus of the substrate, the second thickness, the first volume, and the Young's modulus of the metal. Specifically, obtaining the metal deflection coefficient based on the diameter, the first thickness, the Young's modulus of the substrate, the second thickness, the first volume, and the Young's modulus of the metal may include: determining the quotient of a first value and a second value as the metal deflection coefficient; wherein the first value is obtained based on the diameter, the first volume, the first thickness, and the second thickness; and the second value is obtained based on the first thickness, the second thickness, the Young's modulus of the substrate, and the Young's modulus of the metal.

[0038] Here, the first basic parameter can refer to the geometric parameters and material property data of the substrate of the wafer to be predicted. Specifically, the geometric parameters can include parameters that determine the geometry of the wafer to be predicted, such as diameter and a first thickness. The first thickness can refer to the thickness of the substrate of the wafer to be predicted. The material property data can include the Young's modulus of the substrate, which can be the elastic modulus of the substrate. It is a parameter that measures the material's resistance to elastic deformation; simply put, it describes how "hard" or "rigid" the material is. For example, assuming the substrate of the wafer to be predicted is a silicon (Si) substrate, the Young's modulus of the substrate is used to measure the silicon (Si) substrate's resistance to elastic deformation. In practice, the Young's modulus of the substrate can be directly measured using high-precision experimental equipment or obtained by consulting published authoritative experimental measurement data.

[0039] Here, the second fundamental parameter can be a key parameter used to describe the physical and geometric properties of the metal sublayers in the metal interconnect layer. The second thickness can refer to the thickness of the metal interconnect layer, which is the thickness of the mixture between the metal sublayer and the dielectric sublayer. The first layout can represent the spatial distribution of the metal material on the wafer to be predicted, such as linewidth, line spacing, fill rate, etc., which affect the degree of local stress concentration. For example, as... Figure 3 and Figure 4 The examples show uniformly distributed signal transmission lines and non-uniformly distributed non-signal transmission lines, respectively. For example... Figure 5 and Figure 6 The images show a uniformly distributed power supply network and a non-uniformly distributed power supply network, respectively.

[0040] In practical applications, the first volume can refer to the total volume of the metal sublayer, which can be determined based on the proportion of the metal sublayer to the metal interconnect layer. Specifically, the first volume is the volume of the metal interconnect layer multiplied by the proportion of the metal sublayer to the metal interconnect layer. The Young's modulus of the metal can be used to measure the ability of the metal sublayer to resist elastic deformation, and it can refer to the intrinsic Young's modulus of the metallic material (such as pure copper (Cu)). In practical applications, this Young's modulus can be obtained directly through experiments (such as nanoindentation).

[0041] In this application, after obtaining the first basic parameter and the second basic parameter, the metal deflection coefficient is calculated based on the diameter, the first thickness, and the Young's modulus of the substrate in the first basic parameter, and the first layout, the second thickness, the first volume, and the Young's modulus of the metal in the second basic parameter. Specifically, the quotient of the first value and the second value can be determined as the metal deflection coefficient; wherein, the first value is obtained based on the diameter, the first volume, the first thickness, and the second thickness; and the second value is obtained based on the first thickness, the second thickness, the Young's modulus of the substrate, and the Young's modulus of the metal.

[0042] The first deflection and the metal deflection coefficient mentioned above can be expressed by the following formulas (1) and (2).

[0043] (1).

[0044] (2).

[0045] in, The first deflection; The deflection coefficient of the metal; This refers to internal stress within the metal. The diameter of the wafer to be predicted; This is the first volume; The second thickness; The first thickness; It is the sum of the first thickness and the second thickness; Young's modulus of the metal; The Young's modulus of the substrate.

[0046] In the above formulas (1) and (2), the first value can be: The second value can be... .

[0047] Step 202: Obtain the second deflection generated under the internal stress of the medium in the medium sublayer.

[0048] It should be noted that the dielectric sublayer can refer to an insulating material layer covering the aforementioned metal sublayer to isolate the metal circuitry, prevent short circuits, and provide some mechanical support. This dielectric sublayer can be made of a low dielectric constant material, such as polyimide (PI), polyethylene terephthalate (PET), silicon oxide, or silicon nitride. The dielectric sublayer has a significantly different coefficient of thermal expansion from the metal sublayer, introducing additional internal stress (i.e., dielectric internal stress), which in turn affects the predicted wafer warpage. This dielectric internal stress can be obtained through finite element simulation calculations or experimental testing.

[0049] In this application, the calculation method for the second deflection of the dielectric sublayer is similar to that for the first deflection described above. Specifically, step 202 may include obtaining the dielectric deflection coefficient of the dielectric sublayer and determining the product of the dielectric deflection coefficient and the dielectric internal stress as the second deflection; wherein, the dielectric deflection coefficient is obtained based on the first basic parameters of the wafer to be predicted and the third basic parameters of the dielectric sublayer; the first basic parameters include the diameter, first thickness, and substrate Young's modulus of the wafer to be predicted; the third basic parameters include the second thickness of the metal interconnect layer and the second volume and dielectric Young's modulus of the dielectric sublayer on the wafer to be predicted.

[0050] The dielectric deflection coefficient has the same meaning as the metal deflection coefficient and can be understood by reference, so it will not be repeated here. The first basic parameter has been explained in detail above and will not be repeated here. The third basic parameter can refer to a key parameter used to describe the physical and geometric properties of the dielectric sublayer in the metal interconnect layer. The second layout can represent the three-dimensional geometric distribution, shape, and spatial arrangement of the insulating material (i.e., dielectric material) used to isolate and support metal wires (such as copper wires) in the wafer during the back-end process. The second volume can refer to the total volume of the dielectric sublayer, which can be the product of the volume of the metal interconnect layer and the proportion of the dielectric sublayer to the metal interconnect layer. The dielectric Young's modulus can refer to the intrinsic Young's modulus of the dielectric, which can also be obtained through experimental measurement (such as nanoindentation).

[0051] In this application, the aforementioned second deflection and the medium deflection coefficient can be expressed by the following formulas (3) to (4).

[0052] (3) (4) in, This is the second deflection; The deflection coefficient of the medium; This refers to the internal stress of the medium. The diameter of the wafer to be predicted; For the second volume; The second thickness; The first thickness; It is the sum of the first thickness and the second thickness; The Young's modulus of the medium; The Young's modulus of the substrate.

[0053] Based on the above formulas (1) to (4), the first deflection of the wafer to be predicted under the internal stress of the metal and the first deflection under the internal stress of the medium can be calculated for later use.

[0054] Step 203: Obtain the equivalent internal stress based on the first deflection, the second deflection, and the equivalent deflection coefficient, wherein the equivalent deflection coefficient is used to reflect the degree of warping of the metal interconnect layer under unit internal stress.

[0055] In some embodiments, step 203 may include: determining the quotient of the sum of the first deflection and the second deflection and the equivalent deflection coefficient as the equivalent internal stress; wherein the equivalent deflection coefficient is obtained based on the diameter of the wafer to be predicted, the first thickness, the Young's modulus of the substrate, and the second thickness and equivalent Young's modulus of the metal interconnect layer.

[0056] It should be noted that, according to the law of deflection conservation, such as Figure 7 As shown, under the action of the equivalent internal stress of the metal interconnect layer, the resulting equivalent deflection should be equal to the sum of the first deflection generated under the action of the metal internal stress of the metal sublayer and the second deflection generated under the action of the dielectric internal stress of the dielectric sublayer. Based on this, after calculating the first deflection, the second deflection, and the equivalent deflection coefficient, the equivalent internal stress of the metal interconnect layer can be obtained. Specifically, it can be expressed by formulas (5) to (8).

[0057] (5) (6) (7) (8) in, This represents the equivalent deflection corresponding to the metal interconnect layer. It is the equivalent deflection coefficient; Equivalent internal stress; This is the equivalent Young's modulus corresponding to the metal interconnect layer.

[0058] In this application, the equivalent Young's modulus can be calculated based on the finite element analysis of the representative volume element (RVE) theory, specifically according to the following formula (9).

[0059] (9).

[0060] in, This represents the volume of the representative volume element (RVE) of the metal interconnect layer. The equivalent stress of the RVE in the metal interconnect layer; The equivalent strain of the RVE for the metal interconnect layer.

[0061] In practical applications, the equivalent stress and equivalent strain of the RVE in the metal interconnect layer can be calculated as follows: First, the RVE is set to an average strain period type. Then, a given strain is applied to a specified direction of the RVE (including thermal strain, displacement load, etc.), while keeping other directions free. Finally, the stress corresponding to each sampling point in the RVE is calculated. and strain The equivalent stress and equivalent strain of RVE can be obtained by averaging, as shown in formulas (10) and (11).

[0062] (10).

[0063] (11).

[0064] Step 103: Predict the target warpage value of the wafer to be predicted based on the equivalent internal stress corresponding to each metal interconnect layer and the finite element warpage prediction model.

[0065] It should be noted that the wafer to be predicted can be divided into multiple grids. In this case, after obtaining the equivalent internal stress of each metal interconnect layer, step 103 may include: first, applying the equivalent internal stress corresponding to each metal interconnect layer to the corresponding sub-finite element model in the finite element warpage prediction model to obtain the sub-strain corresponding to each grid; then, obtaining the deformation pattern of the wafer to be predicted under each equivalent internal stress based on each sub-strain; finally, calculating the target warpage value under each equivalent internal stress based on the deformation pattern.

[0066] It should be noted that the grid can refer to dividing the wafer to be predicted into several small regions with regular geometric shapes, which are the basic units for finite element simulation calculations. The grid can be rectangular, triangular or other forms, and the specific division method depends on the structural complexity of the wafer and the accuracy requirements of the simulation.

[0067] In this application, the finite element warpage prediction model includes a sub-finite element model corresponding to each metal interconnect layer. When the obtained equivalent internal stresses are applied to the corresponding sub-finite element models, deformation will occur on the wafer to be predicted. The warpage value corresponding to this deformation is the target warpage value. During calculation, firstly, after applying the obtained equivalent internal stresses to the corresponding sub-finite element models, a sub-strain value corresponding to each mesh is obtained. Then, the sub-strain values ​​corresponding to each mesh are fitted to form the deformation graph (or deformation function). Afterward, the target warpage value corresponding to the wafer to be predicted under each equivalent internal stress is calculated based on the deformation graph. Specifically, the displacement data or curvature data of each sampling point in the deformation graph can be analyzed; the maximum displacement value or maximum curvature is extracted as the target warpage value.

[0068] In this embodiment, by considering the internal stress generated by the metal sublayer and dielectric sublayer of each metal interconnect layer, the equivalent internal stress of each metal interconnect layer is obtained. By taking each equivalent internal stress into account in the prediction of the warpage of the wafer to be predicted, the comprehensive impact of the entire metal interconnect layer on the warpage of the wafer to be predicted can be calculated more accurately, thereby improving the accuracy of the warpage prediction of the wafer to be predicted. This avoids the errors caused by considering only a single layer, thereby improving the accuracy of warpage prediction, and further optimizing the process path and reducing manufacturing risks.

[0069] In summary, the wafer warpage prediction method provided in this application can solve the problem that the stress-free temperature equivalent method in the prior art is difficult to accurately predict the warpage of high-density metal ratio wafers during the manufacturing process of multilayer metal interconnect structures by introducing equivalent internal stress. At the same time, the stress-free temperature equivalent method is also difficult to assess the influence of different dielectric material stress states on wafer warpage.

[0070] To understand this application, as Figure 8 As shown in the figure, this application provides a flowchart of a method for predicting wafer warpage. Specifically, the implementation process may include the following steps 801 to 806.

[0071] Step 801: Determine the finite element warp prediction model for the wafer to be predicted.

[0072] Step 802: For any metal interconnect layer deployed on the wafer to be predicted, obtain the first deflection under the internal stress of the metal sublayer corresponding to the metal interconnect layer and the second deflection under the internal stress of the dielectric sublayer corresponding to the metal interconnect layer.

[0073] Step 803: Obtain the equivalent deflection coefficient corresponding to the metal interconnect layer.

[0074] Step 804: Obtain the equivalent internal stress corresponding to the metal interconnect layer based on the first deflection, the second deflection, and the equivalent deflection coefficient.

[0075] Step 805: Obtain the equivalent internal stress corresponding to each metal interconnect layer.

[0076] Step 806: Apply the equivalent stress corresponding to each metal interconnect layer to the corresponding sub-finite element model in the finite element warpage prediction model to predict the target warpage value of the wafer to be predicted.

[0077] It should be noted that the various technical features appearing in steps 801 to 806 above have been described in detail above and can be understood with reference to the above description, and will not be repeated one by one.

[0078] This application also provides a wafer warpage prediction device, specifically, as shown in the embodiments. Figure 9 As shown, the prediction device 900 may include: a determination module 901 and a prediction module 902, wherein...

[0079] The determining module 901 can be used to determine the warpage prediction model of the wafer to be predicted, wherein at least one metal interconnect layer is disposed on the wafer to be predicted.

[0080] The prediction module 902 can be used to obtain the equivalent internal stress of any metal interconnect layer in the at least one metal interconnect layer; and predict the target warpage value of the wafer to be predicted based on the equivalent internal stress corresponding to each metal interconnect layer and the finite element warpage prediction model.

[0081] In some embodiments, the prediction module 902 may be specifically used to: obtain a first deflection generated under the internal stress of the metal sublayer; obtain a second deflection generated under the internal stress of the dielectric sublayer; and obtain the equivalent internal stress based on the first deflection, the second deflection, and the equivalent deflection coefficient, wherein the equivalent deflection coefficient is used to reflect the degree of warpage generated by the metal interconnect layer under unit internal stress.

[0082] In some embodiments, the prediction module 902 is further configured to: obtain the metal deflection coefficient of the metal sublayer, and determine the product of the metal deflection coefficient and the metal internal stress as the first deflection.

[0083] In some embodiments, the prediction module 902 is further configured to: obtain a first basic parameter of the wafer to be predicted; the first basic parameter includes the diameter, a first thickness, and the Young's modulus of the substrate of the wafer to be predicted; obtain a second basic parameter of the metal sublayer; the second basic parameter includes a second thickness of the metal interconnect layer and a first volume and the Young's modulus of the metal sublayer on the wafer to be predicted; and obtain the metal deflection coefficient based on the diameter, the first thickness, the Young's modulus of the substrate, the second thickness, the first volume, and the Young's modulus of the metal.

[0084] In some embodiments, the prediction module 902 is further configured to: determine the quotient of a first value and a second value as the metal deflection coefficient; wherein the first value is obtained based on the diameter, the first volume, the first thickness and the second thickness; and the second value is obtained based on the first thickness, the second thickness, the Young's modulus of the substrate and the Young's modulus of the metal.

[0085] In some embodiments, the prediction module 902 is further configured to: obtain the dielectric deflection coefficient of the dielectric sublayer, and determine the product of the dielectric deflection coefficient and the dielectric internal stress as the second deflection; wherein the dielectric deflection coefficient is obtained based on a first basic parameter of the wafer to be predicted and a third basic parameter of the dielectric sublayer; the first basic parameter includes the diameter, first thickness, and substrate Young's modulus of the wafer to be predicted; the third basic parameter includes the second thickness of the metal interconnect layer and the second volume and dielectric Young's modulus of the dielectric sublayer on the wafer to be predicted.

[0086] In some embodiments, the prediction module 902 is further configured to: determine the quotient of the sum of the first deflection and the second deflection and the equivalent deflection coefficient as the equivalent internal stress; wherein the equivalent deflection coefficient is obtained based on the diameter of the wafer to be predicted, the first thickness, the Young's modulus of the substrate, and the second thickness and the equivalent Young's modulus of the metal interconnect layer.

[0087] In some embodiments, the wafer to be predicted is divided into multiple grids; the prediction module 902 is further specifically used to: apply the equivalent internal stress corresponding to each metal interconnect layer to the corresponding sub-finite element model in the finite element warpage prediction model to obtain the sub-strain corresponding to each grid; the sub-finite element model is used to simulate the corresponding metal interconnect layer; obtain the deformation pattern of the wafer to be predicted under each equivalent internal stress according to each sub-strain; calculate the target warpage value under each equivalent internal stress according to the deformation pattern.

[0088] In some embodiments, the prediction module 902 is further specifically used to: fit the sub-strain corresponding to each of the grids to form the deformation pattern; analyze the displacement data or curvature data of each sampling point in the deformation pattern; and extract the maximum displacement value or maximum curvature as the target warping value.

[0089] It should be noted that the prediction device provided in this application embodiment is a device for implementing the aforementioned prediction method. The technical features mentioned here have been described in detail above and can be understood with reference to the foregoing description, and will not be repeated here.

[0090] like Figure 10 As shown in the illustration, this application provides a wafer warpage prediction device 1000, which may include: a memory 1001 for storing computer-executable instructions or computer programs; and a processor 1002 for executing the computer-executable instructions or computer programs stored in the memory to implement the prediction method provided in this application. The processor 1002 may be, but is not limited to, a central processing unit (CPU). The memory 1001 may be a read-only memory (ROM), random access memory (RAM), flash memory, etc.

[0091] This application provides a computer program product, including a computer program or computer executable instructions, which, when executed by a processor, implements the prediction method provided in this application.

[0092] This application provides a computer-readable storage medium storing a computer program or computer-executable instructions for implementing the prediction method provided in this application when executed by a processor.

[0093] It should be noted that the descriptions of the above embodiments of storage media, devices, equipment, and products are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of storage media, devices, equipment, and products in this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0094] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for predicting wafer warpage, characterized in that, include: A finite element warpage prediction model for a wafer to be predicted is determined, wherein at least one metal interconnect layer is disposed on the wafer to be predicted; For any one of the at least one metal interconnect layers, obtain the equivalent internal stress of the metal interconnect layer; The target warpage value of the wafer to be predicted is predicted based on the equivalent internal stress corresponding to each metal interconnect layer and the finite element warpage prediction model.

2. The method according to claim 1, characterized in that, The metal interconnect layer includes a metal sublayer and a dielectric sublayer; obtaining the equivalent internal stress of the metal interconnect layer includes: The first deflection generated under the internal stress of the metal sublayer is obtained; A second deflection is obtained under the dielectric internal stress of the dielectric sublayer; The equivalent internal stress is obtained based on the first deflection, the second deflection, and the equivalent deflection coefficient, wherein the equivalent deflection coefficient is used to reflect the degree of warpage of the metal interconnect layer under unit internal stress.

3. The method according to claim 2, characterized in that, The process of obtaining the first deflection generated under the internal stress of the metal sublayer includes: The metal deflection coefficient of the metal sublayer is obtained, and the product of the metal deflection coefficient and the internal stress of the metal is determined as the first deflection.

4. The method according to claim 3, characterized in that, Obtaining the metal deflection coefficient of the metal sublayer includes: Obtain the first basic parameters of the wafer to be predicted; the first basic parameters include the diameter, first thickness, and Young's modulus of the substrate of the wafer to be predicted; Obtain the second basic parameters of the metal sublayer; the second basic parameters include the second thickness of the metal interconnect layer and the first volume and Young's modulus of the metal sublayer on the wafer to be predicted. The metal deflection coefficient is obtained based on the diameter, the first thickness, the Young's modulus of the substrate, the second thickness, the first volume, and the Young's modulus of the metal.

5. The method according to claim 4, characterized in that, The step of obtaining the metal deflection coefficient based on the diameter, the first thickness, the Young's modulus of the substrate, the second thickness, the first volume, and the Young's modulus of the metal includes: determining the quotient of a first value and a second value as the metal deflection coefficient; wherein the first value is obtained based on the diameter, the first volume, the first thickness, and the second thickness; and the second value is obtained based on the first thickness, the second thickness, the Young's modulus of the substrate, and the Young's modulus of the metal.

6. The method according to claim 2, characterized in that, The process of obtaining the second deflection generated under the internal stress of the dielectric sublayer includes: The dielectric deflection coefficient of the dielectric sublayer is obtained, and the product of the dielectric deflection coefficient and the internal stress of the dielectric is determined as the second deflection; The dielectric deflection coefficient is obtained based on the first basic parameter of the wafer to be predicted and the third basic parameter of the dielectric sublayer; the first basic parameter includes the diameter, first thickness, and Young's modulus of the substrate of the wafer to be predicted; the third basic parameter includes the second thickness of the metal interconnect layer and the second volume and Young's modulus of the dielectric sublayer on the wafer to be predicted.

7. The method according to any one of claims 2 to 6, characterized in that, The step of obtaining the equivalent internal stress based on the first deflection, the second deflection, and the equivalent deflection coefficient includes: The equivalent internal stress is determined by the quotient of the sum of the first deflection and the second deflection and the equivalent deflection coefficient; wherein the equivalent deflection coefficient is obtained based on the diameter of the wafer to be predicted, the first thickness, the Young's modulus of the substrate, and the second thickness and equivalent Young's modulus of the metal interconnect layer.

8. The method according to claim 7, characterized in that, The wafer to be predicted is divided into multiple grids; the prediction of the target warpage value of the wafer to be predicted based on the equivalent internal stress corresponding to each metal interconnect layer and the finite element warpage prediction model includes: The equivalent internal stress corresponding to each metal interconnect layer is applied to the corresponding sub-finite element model in the finite element warpage prediction model to obtain the sub-strain corresponding to each mesh; the sub-finite element model is used to simulate the corresponding metal interconnect layer. Based on each sub-strain, obtain the deformation pattern of the wafer to be predicted under each of the aforementioned equivalent internal stresses; The target warpage value is calculated based on the deformation image under each of the equivalent internal stresses.

9. The method according to claim 8, characterized in that, The step of obtaining the deformation pattern of the wafer to be predicted under each equivalent internal stress based on each sub-strain includes: fitting the sub-strain corresponding to each grid to form the deformation pattern; Correspondingly, the step of calculating the target warpage value under each equivalent internal stress based on the deformation image includes: analyzing the displacement data or curvature data of each sampling point in the deformation image; and extracting the maximum displacement value or maximum curvature as the target warpage value.

10. A device for predicting wafer warpage, characterized in that, include: A determination module is used to determine the finite element warpage prediction model of the wafer to be predicted, wherein at least one metal interconnect layer is disposed on the wafer to be predicted; And a prediction module, used for For any one of the at least one metal interconnect layers, obtain the equivalent internal stress of the metal interconnect layer; The target warpage value of the wafer to be predicted is predicted based on the equivalent internal stress corresponding to each metal interconnect layer and the finite element warpage prediction model.

11. A wafer warpage prediction device, characterized in that, include: Memory is used to store executable instructions or computer programs. And a processor, configured to execute computer-executable instructions or computer programs stored in the memory, to implement the prediction method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, It stores computer-executable instructions or computer programs thereon, which are used to implement the prediction method according to any one of claims 1 to 9 when executed by a processor.

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