Mini LED test method, system and computer

Abstract

The invention relates to the technical field of semiconductors, and provides a Mini LED test method and system and a computer, and the method comprises the steps: obtaining a wafer outer ring threshold value, a first forward voltage interval and a second forward voltage interval; testing the wafer through the probe group to obtain a plurality of voltage test data and a plurality of crystal grain coordinates; selecting a plurality of first re-measured crystal grains based on the wafer outer ring threshold value and the plurality of crystal grain coordinates; selecting a plurality of second retest grains from the plurality of first retest grains based on the first forward voltage interval and the plurality of voltage test data; determining a reference probe from the plurality of probes, and testing the plurality of second retest crystal grains to obtain a plurality of voltage retest data; and obtaining the wafer yield based on the plurality of voltage remeasurement data and the second forward voltage interval. By adopting the method, automatic processing is carried out on probe pricking deviation or grain spacing abnormity, the false yield is corrected in time, and material waste is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a Mini LED testing method, system, and computer. Background Technology

[0002] Wafer processing involves several steps, including wafer mounting, dicing, cleaving, film flipping, and testing. Wafer mounting involves attaching the entire wafer to a white film, providing stable support and ensuring precise alignment in subsequent automated production processes. Dicing typically uses wafer laser cutting technology, where a high-repetition-rate picosecond or femtosecond laser beam passes through the wafer surface and focuses at a predetermined depth inside the substrate. Its nonlinear absorption effect forms a continuous, homogeneous internal modification layer in the focal area. The structure of this internal modification layer changes, and its strength is significantly reduced, while the front and back sides of the wafer remain intact. Cleaving completely separates the still-connected chip array into individual chips. Film flipping involves transferring the entire wafer, still attached to the original dicing white film, to a dedicated blue film that is easy for the chips to pick up. Testing involves obtaining basic electrical characteristic data of the chip using probes.

[0003] However, during the wafer flipping process, the spacing between the wafer dies is prone to shift. Due to the abnormal spacing, during multi-channel synchronous testing, the position of the probes in contact with the dies in some or a single channel may shift, failing to form an effective electrical connection. This leads to abnormal test data, and the system misjudges the dies with the probes misaligned as defective dies. Consequently, the calculated wafer yield is lower than expected, and false defects are likely to occur. Intact dies are also judged as defective and scrapped, resulting in a significant loss of raw materials.

[0004] Existing technologies can issue alarms for probe misalignment or data anomalies, but these alarms are reactive and lack automatic handling of die spacing anomalies. After an alarm, manual intervention is required, resulting in a slow response. When probe misalignment occurs, there is a lack of dynamic adjustment of the test tasks. All dies handled by the channel with the offset probe are subject to mistesting or missed testing, resulting in invalid batch test data. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a Mini LED testing method, system, and computer. This invention proactively selects chips requiring retesting and uses a reference probe for retesting, dynamically adjusting testing tasks after an alarm is triggered to proactively compensate for defects. This invention aims to solve the technical problem in existing technologies of lacking automatic processing for probe misalignment or abnormal chip spacing, making it difficult to promptly correct false yields.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: A Mini LED testing method includes the following steps: Obtain the outer edge threshold of the wafer, the first positive voltage range, and the second positive voltage range; The wafer is tested by a probe group to obtain several voltage test data and several grain coordinates of several grains in the wafer. The probe group includes several probes. Based on the wafer outer ring threshold and several grain coordinates, several first retest grains are selected from several grains; Based on the first positive voltage range and several voltage test data, several second retest grains are selected from several first retest grains; Based on the number of probes and the probe arrangement rules of the probe group, a reference probe is determined from several probes, and several second retesting dies are tested through the reference probe to obtain several voltage retesting data. Based on several voltage retest data and the second positive voltage range, the wafer yield is obtained.

[0007] Furthermore, prior to the step of selecting a plurality of first retest grains from the plurality of grains based on the wafer outer edge threshold and the plurality of grain coordinates, the method further includes: Several voltage test data points located within the first positive voltage range are established as several NG test data points; The NG rate is calculated based on several of the NG test data and all of the voltage test data. Obtain the NG rate threshold, and based on the NG rate threshold and the NG rate, determine whether to issue an alarm signal.

[0008] Furthermore, the step of selecting a plurality of first retest grains from the plurality of grains based on the wafer outer edge threshold and the plurality of grain coordinates includes: The outer edge region of the wafer is determined based on the outer edge threshold. Based on the grain coordinates, it is determined whether the grain is located within the outer ring region of the wafer. If the grain is not located within the outer ring region of the wafer, then the grain is established as the first retest grain.

[0009] Furthermore, the step of selecting a plurality of second retest grains from a plurality of first retest grains includes: The first retest grains corresponding to the NG test data are established as the second retest grains.

[0010] Furthermore, the minimum voltage value of the first positive voltage range is greater than the maximum voltage value of the second positive voltage range. Following the step of selecting the plurality of first retest grains corresponding to the plurality of NG test data as the plurality of second retest grains, the method further includes: Several voltage test data points located outside the first positive voltage range and the second positive voltage range are established as several test data points to be judged; Several test data points to be judged that are less than the minimum voltage value of the second positive voltage range are established as several abnormal test data points, and several test data points to be judged that are greater than the minimum voltage value of the second positive voltage range are established as several selected test data points, and the several selected test data points correspond to several selected grains. Acquire several optical test data and several optical test thresholds for several selected grains, and based on the several optical test data and several optical test thresholds, determine several second retest grains from the several selected grains.

[0011] Furthermore, the plurality of probes correspond to a plurality of test channels. Following the step of selecting a plurality of second retest grains from a plurality of first retest grains based on the first forward voltage range and a plurality of voltage test data, the method further includes: Based on the aforementioned test channels, the plurality of second retest grains are divided into a plurality of channel grain groups; Obtain a channel threshold, compare the number of grains in the channel grain group with the channel threshold, and select several grain groups to be inspected from several channel grain groups. The CCD is used to inspect several probes corresponding to several groups of grains to be inspected to determine whether probe misalignment has occurred. If probe misalignment occurs, an alarm signal is issued.

[0012] Furthermore, the step of testing several second retest grains using the reference probe specifically includes: Obtain the hardware coordinates of the second retest die, and move the probe group based on the hardware coordinates so that the reference probe is aligned with the second retest die for testing.

[0013] Furthermore, before the step of obtaining the wafer yield based on several voltage retest data and the second positive voltage range, the method further includes: The retest NG rate is calculated based on several voltage retest data and all voltage test data. Based on the NG rate threshold and the retest NG rate, determine whether to retest.

[0014] A Mini LED testing system, employing the Mini LED testing method described in the above technical solution, the system comprising: The acquisition module is used to acquire the wafer outer ring threshold, the first positive voltage range, and the second positive voltage range; The testing module is used to test the wafer through a probe group to obtain several voltage test data and several grain coordinates of several grains in the wafer. The probe group includes several probes. The first selection module is used to select a number of first retest grains from the number of grains based on the wafer outer ring threshold and a number of grain coordinates. The second selection module is used to select a number of second retesting grains from a number of first retesting grains based on the first positive voltage range and a number of voltage test data. The retest module is used to determine a reference probe from a number of probes according to the number of probes and the probe arrangement rules of the probe group, and to test a number of second retest dies through the reference probe to obtain a number of voltage retest data. The yield module is used to obtain the wafer yield based on several voltage retest data and the second positive voltage range.

[0015] A computer includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the MiniLED testing method as described above.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: By using the wafer outer ring threshold to screen the position of the grains, grains with epitaxial problems on the outer ring are no longer retested, improving retesting efficiency and reducing the time and material consumption of the testing process; by combining the first positive voltage range and the second positive voltage range to perform layered judgment on the voltage test data, grains whose voltage test data can directly reflect probe offset or grain spacing abnormalities are preferentially screened out, thus identifying a portion of the second retested grains, while those that cannot directly reflect probe offset or grain spacing abnormalities but whose test data are not judged as abnormal are excluded. The aforementioned die is further screened using optical data to identify another portion of the second retest dies. Finally, all the second retest dies are retested using the reference probe. Based on the hardware coordinates of the die, its accurate position is located. This not only avoids the errors in the first and second tests caused by the presence of offset probes in the probe group, but also enables effective testing of dies with abnormal spacing, obtaining their true test data. This prevents false defects and avoids the wafer being incorrectly scrapped due to false defects failing to meet yield standards. By calculating the true and accurate yield of the wafer, material waste is greatly reduced. Attached Figure Description

[0017] Figure 1 This is a flowchart of the Mini LED testing method in the first embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the abnormal grain spacing in the first embodiment of the present invention; Figure 3 This is a schematic diagram of probe offset in the first embodiment of the present invention; Figure 4 This is a structural block diagram of the Mini LED testing system in the second embodiment of the present invention; Explanation of key component symbols: 100. Grain; 110. Anomaly test channel; 200. Probe test point; The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0018] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0019] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] Please see Figure 1 The Mini LED testing method in the first embodiment of the present invention includes the following steps: Step S10: Obtain the wafer outer ring threshold, the first positive voltage range, and the second positive voltage range; Preferably, the outer edge threshold of the wafer is 20, the first positive voltage range is 4V~8V, and the second positive voltage range is 1.8V~2.4V.

[0022] Step S20: Test the wafer with a probe group to obtain several voltage test data and several grain coordinates of several grains in the wafer. The probe group includes several probes. Preferably, the probe group includes eight probes, each including a left sub-probe and a right sub-probe, for testing the electrical characteristics at both ends of the die. (See also...) Figure 2 The probe measurement points 200 are located at both ends of the grain 100, specifically aligned with the electrodes at both ends of the grain 100. Theoretically, the grains are arranged with uniform and regular spacing. However, the actual arrangement of the grains is affected by the large-scale transfer of the grains 100 from the white film to the blue film during the film-changing process, and the surface cleaning. This film-changing process directly causes changes in the spacing between the grains, resulting in problems such as offset, uneven spacing, and misalignment. When the offset is significant, it will lead to poor contact between the probes of one or more channels and the electrodes at both ends of the grain 100, or even open circuits. Because an effective and stable electrical connection cannot be formed, abnormal test data will occur. Please refer to [link / reference needed]. Figure 3During long-term automated production, hardware equipment may wear out, and the probe may become misaligned. When the probe becomes misaligned, the channel where the probe misaligns becomes an abnormal test channel 110 during the simultaneous testing of the wafer through multiple channels. In the abnormal test channel 110, a batch of probe test points 200 become misaligned, resulting in a batch of abnormal data. Both of the above situations are manifested as abnormal test data.

[0023] Step S30: Based on the outer edge threshold of the wafer and several grain coordinates, select several first retest grains from the several grains; Before step S30, the method further includes: S310: Establish a plurality of voltage test data located within the first positive voltage range as a plurality of NG test data; S320: Calculate the NG rate based on several of the NG test data and all of the voltage test data; S330: Obtain the NG rate threshold, and based on the NG rate threshold and the NG rate, determine whether to issue an alarm signal.

[0024] Preferably, the NG rate is obtained by dividing the number of NG dies by the total number of dies on the wafer. The NG rate threshold is 5%. The first positive voltage range is the voltage range obtained by testing under the open-circuit state of the dies. When the voltage test data falls within the first positive voltage range, it means that due to abnormal die spacing or probe offset, the probe test point 200 falls outside the two electrodes of the die 100, and the open-circuit voltage test result is directly obtained. That is, several dies 100 corresponding to several NG test data need to be retested directly, and an alarm signal can be issued to remind the operator.

[0025] Step S30 further includes: S340: Determine the outer edge region of the wafer based on the outer edge threshold; S350: Based on the grain coordinates, determine whether the grain is located within the outer ring region of the wafer. If the grain is not located within the outer ring region of the wafer, then establish the grain as the first retest grain.

[0026] Preferably, all the grains 100 in the outer ring region of the wafer are affected by epitaxy due to actual production process issues, and therefore do not participate in the calculation and retesting, which helps to shorten the retesting time and improve the retesting efficiency.

[0027] Step S40: Based on the first positive voltage range and several voltage test data, select several second retest grains from several first retest grains; Understandably, after the first screening based on the position of the grain 100, a second screening is performed based on the test data of the grain 100. Based on the first positive voltage range, the corresponding grain 100 that can reflect the open circuit condition in the voltage test data is directly determined. The second retested grain is a grain with abnormal grain spacing or a grain that was tested by the offset probe in the first test.

[0028] Step S40 includes: S410: The first retest grains corresponding to the plurality of NG test data are established as the second retest grains.

[0029] Preferably, a subset of grains that need to be retested can be identified first.

[0030] The minimum voltage value of the first positive voltage range is greater than the maximum voltage value of the second positive voltage range. Following step S410, the method further includes: S4110: Establish several voltage test data located outside the first positive voltage range and the second positive voltage range as several test data to be judged; S4120: Several test data to be judged that are less than the minimum voltage value of the second positive voltage range are established as several abnormal test data, and several test data to be judged that are greater than the minimum voltage value of the second positive voltage range are established as several selected test data, and the several selected test data correspond to several selected grains. S4130: Obtain several optical test data and several optical test thresholds of several selected grains, and based on the several optical test data and several optical test thresholds, determine several second retest grains from the several selected grains.

[0031] Preferably, several voltage test data points located outside the first and second positive voltage ranges indicate that the corresponding grains may be substandard, or that the grain spacing offset is not significant, or that the probe offset for testing the grain is not significant and is less than the minimum voltage value of the second positive voltage range. That is, grains 100 with test voltages less than 1.8V are substandard, and their test data is abnormal, so they are not directly included in the retest. By comparing and analyzing data from other test items, usable grains are selected again from the chosen grains for retesting; that is, a portion of the grains 100 are selected again to be used for the second retest. Understandably, multi-layer screening improves the accuracy of selecting retest grains and avoids misjudging qualified grains as defective grains.

[0032] In step S40, the plurality of probes correspond to the plurality of test channels. Following step S40, the method further includes: S420: Based on the plurality of test channels, the plurality of second retest grains are divided into a plurality of channel grain groups; S430: Obtain the channel threshold, compare the number of chips in the channel chip group with the channel threshold, and select a number of chip groups to be inspected from a number of channel chip groups. S440: The CCD is used to check several probes corresponding to several groups of grains to be checked to determine whether probe offset occurs. If probe offset occurs, an alarm signal is issued.

[0033] Preferably, traditional methods lack identification, automatic adjustment, and inspection and maintenance methods for probe offset. In this embodiment, all the second retested dies are grouped according to the test channels, and it is checked whether there are certain test channels corresponding to a large number of dies 100 that need to be retested, thereby selecting the abnormal test channels 200, and then checking whether the probes corresponding to the abnormal test channels 200 have offset risks. If probe offset is identified, an alarm is issued for immediate maintenance.

[0034] Step S50: Based on the number of probes and the probe arrangement rules of the probe group, a reference probe is determined from several probes, and several second retesting dies are tested through the reference probe to obtain several voltage retesting data. Preferably, for the 8-channel probe group, the probe located in the middle section is selected as the reference probe, specifically, the probe corresponding to the 4th channel is selected as the reference probe.

[0035] Step S50 includes: S510: Obtain the hardware coordinates of the second retest die, and move the probe group based on the hardware coordinates so that the reference probe is aligned with the second retest die for testing.

[0036] Preferably, the second retest die is automatically screened and automatically retested. The second retest die is accurately tested without offset according to the precise hardware position to obtain its true test results, thereby avoiding misjudgment of the quality of the second retest die and avoiding false defective products.

[0037] Step S60: Based on several voltage retest data and the second positive voltage range, obtain the wafer yield.

[0038] Since the flipping process transfers the granules 100 to the blue film, there is a risk of granule spacing misalignment during the flipping process. Furthermore, in the subsequent granule sorting process, due to the extensibility of the blue film, the granules 100 are continuously picked out, and the position of the remaining granules 100 on the blue film continues to change. Before each sorting test, there is a possibility that the granule spacing misalignment will lead to abnormal test data. In the production process, there are multiple testing steps, and each testing step is prone to false defects, resulting in a low yield calculation result, which can easily lead to rework and scrap, resulting in a waste of a lot of manpower, material resources and raw materials. In actual testing, the NG rate of test data caused by granule misalignment is 1% to 7%, causing a loss in production line yield. Through the method of the present invention, the overall yield can be improved by 1.2%.

[0039] Understandably, targeted secondary retesting effectively identifies and recovers "false" defects caused by poor contact, avoiding the misjudgment and scrapping of perfectly good chips, reducing raw material loss, and directly lowering the "false kill" rate. By adopting a mode of full test recording combined with fixed-point single-channel retesting, only a few NG positions are retested. Compared with overall retesting, this greatly saves testing time and machine time, and does not require modification or upgrade of expensive probe stations, testing machines, and other hardware equipment. It is achieved only through software logic and process optimization, resulting in low implementation cost and high return on investment. This method is flexible and can effectively absorb process fluctuations caused by inconsistent incoming material arrangement, enhancing the production line's fault tolerance to incoming material fluctuations.

[0040] Before step S60, the method further includes: S610: Calculate the retest NG rate based on several voltage retest data and all voltage test data; S620: Based on the NG rate threshold and the retest NG rate, determine whether to retest.

[0041] Please see Figure 4 The Mini LED testing system provided in the second embodiment of the present invention applies the Mini LED testing method described in the first embodiment above, and the system includes: The acquisition module 10 is used to acquire the wafer outer ring threshold, the first positive voltage range, and the second positive voltage range; Test module 20 is used to test the wafer through a probe group to obtain several voltage test data and several grain coordinates of several grains in the wafer. The probe group includes several probes. The first selection module 30 is used to select a number of first retest grains from the number of grains based on the wafer outer ring threshold and a number of grain coordinates. The first selected module 30 includes: The first unit is used to establish a plurality of voltage test data located within the first positive voltage range as a plurality of NG test data. The second unit is used to calculate the NG rate based on several of the NG test data and all of the voltage test data; The third unit is used to obtain the NG rate threshold and, based on the NG rate threshold and the NG rate, determine whether to issue an alarm signal; The fourth unit is used to determine the outer edge region of the wafer based on the outer edge threshold. The fifth unit is used to determine whether the grain is located within the outer ring region of the wafer based on the grain coordinates. If the grain is not located within the outer ring region of the wafer, the grain is established as the first retest grain.

[0042] The second selection module 40 is used to select a number of second retesting grains from a number of first retesting grains based on the first positive voltage range and a number of voltage test data. In the second selection module 40, the minimum voltage value of the first forward voltage range is greater than the maximum voltage value of the second forward voltage range, and the plurality of probes correspond to a plurality of test channels. The second selection module 40 includes: The sixth unit is used to identify several first retest grains corresponding to several NG test data as several second retest grains.

[0043] The sixth unit is specifically used for: Several voltage test data points located outside the first positive voltage range and the second positive voltage range are established as several test data points to be judged; Several test data points to be judged that are less than the minimum voltage value of the second positive voltage range are established as several abnormal test data points, and several test data points to be judged that are greater than the minimum voltage value of the second positive voltage range are established as several selected test data points, and the several selected test data points correspond to several selected grains. Acquire several optical test data and several optical test thresholds for several selected grains, and based on the several optical test data and several optical test thresholds, determine several second retest grains from the several selected grains.

[0044] The seventh unit is used to divide a plurality of second retest grains into a plurality of channel grain groups based on a plurality of the test channels; The eighth unit is used to obtain the channel threshold, compare the number of chips in the channel chip group with the channel threshold, and select a number of chip groups to be inspected from a number of channel chip groups. The ninth unit is used to check several probes corresponding to several groups of grains to be checked by CCD to determine whether probe offset occurs. If probe offset occurs, an alarm signal is issued.

[0045] The retest module 50 is used to determine a reference probe from a plurality of probes according to the number of probes and the probe arrangement rules of the probe group, and to test a plurality of second retest dies through the reference probe to obtain a plurality of voltage retest data. The retest module 50 includes: The tenth unit is used to obtain the hardware coordinates of the second retest die, and move the probe group based on the hardware coordinates so that the reference probe is aligned with the second retest die for testing.

[0046] The yield module 60 is used to obtain the wafer yield based on several voltage retest data and the second positive voltage range.

[0047] The yield module 60 includes: The eleventh unit is used to calculate the retest NG rate based on several of the voltage retest data and all of the voltage test data; The twelfth unit is used to determine whether to retest based on the NG rate threshold and the retest NG rate.

[0048] The third embodiment of the present invention provides a computer, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the Mini LED testing method as described in the first embodiment.

[0049] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0050] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A Mini LED testing method, characterized in that, Includes the following steps: Obtain the outer edge threshold of the wafer, the first positive voltage range, and the second positive voltage range; The wafer is tested by a probe group to obtain several voltage test data and several grain coordinates of several grains in the wafer. The probe group includes several probes. Based on the wafer outer ring threshold and several grain coordinates, several first retest grains are selected from several grains; Based on the first positive voltage range and several voltage test data, several second retest grains are selected from several first retest grains; Based on the number of probes and the probe arrangement rules of the probe group, a reference probe is determined from several probes, and several second retesting dies are tested through the reference probe to obtain several voltage retesting data. Based on several voltage retest data and the second positive voltage range, the wafer yield is obtained.

2. The Mini LED testing method according to claim 1, characterized in that, Before the step of selecting a plurality of first retest grains from the plurality of grains based on the wafer outer edge threshold and the plurality of grain coordinates, the method further includes: Several voltage test data points located within the first positive voltage range are established as several NG test data points; The NG rate is calculated based on several of the NG test data and all of the voltage test data. Obtain the NG rate threshold, and based on the NG rate threshold and the NG rate, determine whether to issue an alarm signal.

3. The Mini LED testing method according to claim 1, characterized in that, The step of selecting several first retest grains from several grains based on the wafer outer edge threshold and several grain coordinates includes: The outer edge region of the wafer is determined based on the outer edge threshold. Based on the grain coordinates, it is determined whether the grain is located within the outer ring region of the wafer. If the grain is not located within the outer ring region of the wafer, then the grain is established as the first retest grain.

4. The Mini LED testing method according to claim 2, characterized in that, The step of selecting a plurality of second retest grains from a plurality of first retest grains includes: The first retest grains corresponding to the NG test data are established as the second retest grains.

5. The Mini LED testing method according to claim 4, characterized in that, The minimum voltage value of the first positive voltage range is greater than the maximum voltage value of the second positive voltage range. Following the step of selecting the plurality of first retest grains corresponding to the plurality of NG test data as the plurality of second retest grains, the method further includes: Several voltage test data points located outside the first positive voltage range and the second positive voltage range are established as several test data points to be judged; Several test data points to be judged that are less than the minimum voltage value of the second positive voltage range are established as several abnormal test data points, and several test data points to be judged that are greater than the minimum voltage value of the second positive voltage range are established as several selected test data points, and the several selected test data points correspond to several selected grains. Acquire several optical test data and several optical test thresholds for several selected grains, and based on the several optical test data and several optical test thresholds, determine several second retest grains from the several selected grains.

6. The Mini LED testing method according to claim 1, characterized in that, The plurality of probes correspond to a plurality of test channels. Following the step of selecting a plurality of second retest grains from a plurality of first retest grains based on the first forward voltage range and a plurality of voltage test data, the method further includes: Based on the aforementioned test channels, the plurality of second retest grains are divided into a plurality of channel grain groups; Obtain a channel threshold, compare the number of grains in the channel grain group with the channel threshold, and select several grain groups to be inspected from several channel grain groups. The CCD is used to inspect several probes corresponding to several groups of grains to be inspected to determine whether probe misalignment has occurred. If probe misalignment occurs, an alarm signal is issued.

7. The Mini LED testing method according to claim 1, characterized in that, The specific steps of testing several second retest grains using the reference probe are as follows: Obtain the hardware coordinates of the second retest die, and move the probe group based on the hardware coordinates so that the reference probe is aligned with the second retest die for testing.

8. The Mini LED testing method according to claim 2, characterized in that, Before the step of obtaining the wafer yield based on several voltage retest data and the second positive voltage range, the method further includes: The retest NG rate is calculated based on several voltage retest data and all voltage test data. Based on the NG rate threshold and the retest NG rate, determine whether to retest.

9. A Mini LED testing system, employing the Mini LED testing method as described in any one of claims 1 to 8, characterized in that, The system includes: The acquisition module is used to acquire the wafer outer ring threshold, the first positive voltage range, and the second positive voltage range; The testing module is used to test the wafer through a probe group to obtain several voltage test data and several grain coordinates of several grains in the wafer. The probe group includes several probes. The first selection module is used to select a number of first retest grains from the number of grains based on the wafer outer ring threshold and a number of grain coordinates. The second selection module is used to select a number of second retesting grains from a number of first retesting grains based on the first positive voltage range and a number of voltage test data. The retest module is used to determine a reference probe from a number of probes according to the number of probes and the probe arrangement rules of the probe group, and to test a number of second retest dies through the reference probe to obtain a number of voltage retest data. The yield module is used to obtain the wafer yield based on several voltage retest data and the second positive voltage range.

10. A computer comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the Mini LED testing method as described in any one of claims 1 to 8.

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