Defect testing method of semiconductor device and semiconductor device

Abstract

The embodiment of the invention discloses a defect test method of a semiconductor device and the semiconductor device. The method comprises the following steps: testing a first test value of an off-state drain current of a transistor in the semiconductor device; hot carrier injection stress is applied to a transistor in the semiconductor device so as to excite instantaneous electronic defects of the lining layer in the shallow trench isolation structure; testing a second test value of an off-state drain current of a transistor in the semiconductor device; and judging whether the lining layer has electronic defects or not by comparing the change conditions of the drain current in the off state before and after the hot carrier injection stress is applied. According to the embodiment of the invention, rapid, efficient and sensitive detection of the instantaneous electronic defect of the lining layer in the shallow trench isolation structure is realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a defect testing method for semiconductor devices and a semiconductor device. Background Technology

[0002] In advanced semiconductor manufacturing processes, shallow trench isolation (STI) technology is widely used to achieve electrical isolation between adjacent active regions. To suppress silicon losses in the active region and improve device performance, a thin liner layer, typically made of silicon nitride (SiN) and referred to as "liner SiN," is usually deposited on the sidewalls and bottom of the STI trench. However, during the operation of a PMOS transistor, electrons can easily gain sufficient energy under a high electric field to form hot electrons, which are then trapped by the liner layer at the top of the STI structure, creating transient electronic defects such as electron traps at the interface or within the transistor. These electronic defects can trigger hot electron-induced punch-through (HEIP), leading to an abnormal increase in leakage current when the transistor is off. This problem is particularly pronounced after high-temperature operating life testing (HTOL), manifesting as threshold voltage drift and an increase in standby current (also known as off-state drain current), severely impacting the long-term reliability of the device.

[0003] Currently, HTOL testing is the primary method for assessing the impact of such electronic defects on device reliability. However, traditional HTOL testing has several limitations: First, the testing cycle is as long as approximately 1000 hours, and packaging time must be taken into account, which significantly slows down process development. Second, once a failure occurs, complex electrical fault analysis (EFA) and other methods are required to locate the electronic defect, which is cumbersome and costly. Third, devices with different channel width-to-length ratios (W / L) are affected by HEIP to varying degrees, with smaller devices being more sensitive, making it difficult to trace the failure mechanism. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a defect testing method and semiconductor device for semiconductor devices, aiming to overcome the technical bottlenecks of long testing cycle, difficult positioning and low efficiency of traditional HTOL testing, and to achieve rapid, efficient and sensitive detection of transient electronic defects in the inner liner of shallow trench isolation (STI) structures.

[0005] According to a first aspect of the embodiments of this application, a defect testing method for a semiconductor device is provided, the semiconductor device including a shallow trench isolation structure having an inner liner layer, the defect testing method comprising:

[0006] The first test value of the off-state drain current of the transistor in the semiconductor device is tested;

[0007] Hot carrier injection stress is applied to the transistors in the semiconductor device to excite transient electronic defects in the liner layer of the shallow trench isolation structure;

[0008] A second test value for the off-state drain current of the transistor in the semiconductor device;

[0009] By comparing the changes in the off-state drain current before and after applying hot carrier injection stress, it can be determined whether there are electronic defects in the inner liner.

[0010] Optionally, applying hot carrier injection stress to the transistors in the semiconductor device includes:

[0011] A specific bias voltage is applied to the gate and drain of the transistor in the semiconductor device to make the transistor operate in the saturation region.

[0012] Optionally, the specific bias voltage is set to a voltage range that maximizes the number of electron-hole pairs generated.

[0013] Optionally, determining whether there are electronic defects in the inner liner by comparing the changes in the off-state drain current before and after applying hot carrier injection stress includes:

[0014] Calculate the difference or multiple of change between the first test value and the second test value. If the difference or multiple of change exceeds a preset threshold, it is determined that the inner lining layer has an electronic defect.

[0015] If the difference or change factor does not exceed a preset threshold, the inner liner is determined to have no electronic defects.

[0016] Optionally, before testing the first test value of the off-state drain current of the transistor in the semiconductor device, the defect testing method further includes:

[0017] Dedicated test structures are fabricated on semiconductor wafers, the test structures comprising one or more types of transistors;

[0018] Transistors of the same type are connected in parallel in the test structure to form one or more parallel transistor arrays, so as to measure the change of the off-state drain current before and after applying hot carrier injection stress to each parallel transistor array.

[0019] Optionally, the one or more types of transistors have the same channel width but different channel lengths; or the one or more types of transistors have different channel widths but the same channel length.

[0020] Optionally, the measurement of the change in the off-state drain current before and after applying hot carrier injection stress to each parallel transistor array includes:

[0021] For each parallel transistor array, test the first test value of the off-state drain current of the parallel transistor array;

[0022] Hot carrier injection stress is applied to the parallel transistor array to excite transient electronic defects in the liner layer of the shallow trench isolation structure;

[0023] The second test value of the off-state drain current of the parallel transistor array is tested.

[0024] Optionally, determining whether there are electronic defects in the inner liner by comparing the changes in the off-state drain current before and after applying hot carrier injection stress includes:

[0025] When the channel widths of one or more types of transistors are the same but the channel lengths are different, for each parallel transistor array, the difference or change factor between the first test value and the second test value is calculated respectively.

[0026] If the difference or change factor increases as the channel length of the parallel transistor array decreases, it is determined that there is an electronic defect in the inner liner of the transistor of the semiconductor device.

[0027] Optionally, determining whether there are electronic defects in the inner liner by comparing the changes in the off-state drain current before and after applying hot carrier injection stress includes:

[0028] When the channel widths of one or more types of transistors are different but the channel lengths are the same, for each parallel transistor array, the difference or change factor between the first test value and the second test value is calculated respectively.

[0029] If the difference or change factor increases as the channel width of the parallel transistor array decreases, it is determined that there is an electronic defect in the inner liner of the transistor of the semiconductor device.

[0030] According to a second aspect of the present application, a semiconductor device is provided, wherein the liner layer of the shallow trench isolation structure of the semiconductor device is subjected to defect testing according to the defect testing method described above.

[0031] The unexpected technical effect of this application is as follows: First, a first test value of the off-state drain current of a transistor in a semiconductor device is measured. Hot carrier injection stress is applied to the transistor in the semiconductor device to excite transient electronic defects in the inner liner of the shallow trench isolation structure. Second, a second test value of the off-state drain current of the transistor in the semiconductor device is measured. By comparing the changes in the off-state drain current before and after the application of hot carrier injection stress, it is determined whether electronic defects exist in the inner liner. Thus, by measuring the change in the transistor's off-state drain current before and after hot carrier injection stress, rapid detection of transient electronic defects in the inner liner of the shallow trench isolation structure is achieved. Electronic defect screening can be completed at the wafer level in just seconds to minutes, significantly shortening the defect testing cycle and greatly improving defect testing efficiency. Simultaneously, the HEIP physical mechanism is used to convert microscopic electronic defects into macroscopically measurable transistor off-state drain current degradation signals, possessing high sensitivity and failure prediction capabilities, avoiding the complex defect location analysis process after transistor failure.

[0032] Furthermore, the embodiments of this application complete the test at the wafer level under non-destructive conditions, which will not cause permanent damage such as large-area thermal damage or metal melting of the device. This avoids the problem of local overheating and burning of defect areas due to severe leakage or breakdown of the device in traditional HTOL testing. As a result, the true microstructure at the defect can be completely preserved, which is conducive to subsequent accurate failure location and mechanism research through physical analysis methods (such as TEM, EDS, EFA, etc.).

[0033] Furthermore, a dedicated test structure is fabricated on a semiconductor wafer. The test structure contains one or more types of transistors. Transistors of the same type are connected in parallel within the test structure to form one or more parallel transistor arrays. The channel widths of the one or more types of transistors are the same, but the channel lengths are different, or the channel widths of the one or more types of transistors are different, but the channel lengths are the same. The change in the off-state drain current before and after applying hot carrier injection stress to each parallel transistor array is measured. In this way, by introducing a systematic variable design of channel width and channel length, a quantitative response model for electronic defect sensitivity is constructed, upgrading defect identification from qualitative judgment to quantitative analysis and enhancing the reliability of electronic defect testing. Attached Figure Description

[0034] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0035] Figure 1A The image shown is a cross-sectional schematic diagram of a shallow trench isolation structure in a semiconductor device in the related art;

[0036] Figure 1BThe diagram shows a top view and a cross-sectional view along the AA' direction of a semiconductor device in the related technology.

[0037] Figure 1C The image shows a top view and a cross-sectional view along the BB' direction of a semiconductor device in the related art;

[0038] Figure 1D The figure shown is a comparison of the distribution of the drain current in the off-state of semiconductor devices before and after high-temperature operating life test in related technologies.

[0039] Figure 1E The figure shown is a graph showing the relationship between transistor size and threshold voltage drift in semiconductor devices in related technologies.

[0040] Figure 2 The diagram shown is a schematic flowchart of an exemplary defect testing method for a semiconductor device according to an embodiment of this application.

[0041] Figure 3 The figure shown is an exemplary graph showing the relationship between the number of electron-hole pairs generated and the gate voltage according to an embodiment of this application.

[0042] Figure 4 The figure shown is a comparison of the relationship between gate voltage and drain current before and after applying hot carrier injection stress, according to an embodiment of this application.

[0043] Figure 5 The diagram shown is a flowchart illustrating another exemplary defect testing method for a semiconductor device according to an embodiment of this application.

[0044] Figure 6 The diagram shown is an exemplary test structure according to an embodiment of this application;

[0045] Figure 7 The diagram shown is a schematic representation of an exemplary test structure configuration according to an embodiment of this application.

[0046] Figure 8 The diagram shows a configuration of another exemplary test structure according to an embodiment of this application;

[0047] Figure 9 The diagram shows a comparison of the drain current in the off-state of an exemplary parallel transistor array with the same channel length but different channel widths after hot carrier injection stress is applied, according to an embodiment of this application. Detailed Implementation

[0048] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0049] This application may be presented in various forms, some of which will be described below.

[0050] Figure 1A A cross-sectional schematic diagram of a shallow trench isolation structure for semiconductor devices in related technologies is shown. For example... Figure 1A As shown, the semiconductor device 100 includes an active area (AA) formed on a substrate, and adjacent active areas are electrically isolated by a shallow trench isolation structure 110. The shallow trench isolation structure 110 includes trenches etched into the substrate, with a thin oxide layer and an inner liner layer (e.g., silicon nitride, liner SiN) 111 sequentially formed on the sidewalls and bottom of the trench, filled with a dielectric material (e.g., silicon dioxide), and planarized by a chemical mechanical polishing process. Above the active areas, a gate stack structure spans the trench region, the gate stack structure including a gate oxide layer and a polysilicon gate, and isolated by a sidewall structure; the source and drain are located within the active areas on either side of the gate.

[0051] Figure 1B A top view and a cross-sectional schematic diagram along the AA' direction of a semiconductor device 100 in the related art are shown. Figure 1C A top view and a cross-sectional view along the BB' direction of the semiconductor device 100 are shown. Specifically, Figure 1B The diagram shows a schematic of the conventional hot electron-induced punch-through (HEIP) model. In this model, hot electrons are mainly generated in the high-electric-field region near the drain side of the transistor channel. Some high-energy hot electrons, after gaining sufficient energy, are injected into the gate oxide layer and captured by inherent defects or traps, forming transient electron traps 112. The formation of transient electron traps 112 leads to threshold voltage drift and gate control capability degradation, thereby triggering unintended conduction behavior between the source and drain, i.e., the punch-through effect. This mechanism is related to the gate dielectric quality, channel length, and electric field distribution characteristics. Defects are spatially relatively uniformly distributed and do not have obvious location locality. Figure 1C The diagram shows a schematic of the shallow trench isolation-induced hot electron-induced penetration (STI-induced HEIP) model. Figure 1BUnlike the previously shown model, this model reveals that at advanced process nodes, the inner liner 111 on the top or sidewall of the shallow trench isolation structure 110 becomes the primary site for hot electron trapping. Due to the electric field concentration effect at the edge of the active region, and the high electron trap density of the silicon nitride material in the inner liner 111, under high drain voltage operating conditions, a large number of hot electrons are trapped by the inner liner 111 located above or near the active region boundary of the STI region, thus forming transient electron traps 112 at the silicon / silicon nitride interface or within the silicon nitride body. These transient electron traps 112 cause local potential distortion, weakening the gate's electrical control over the channel edge region, ultimately leading to a significant increase in leakage current in the transistor's off state, manifesting as hot electron-induced punch-through. Especially in narrow-width or small-size devices, the ratio of the active region edge length to the total channel width increases, making the impact of STI-related defects more prominent, exhibiting a clear channel width effect.

[0052] Figure 1D The image shows a comparison of the distribution of the drain current in the off-state of a semiconductor device before and after a high-temperature operating life test in related technologies. For example... Figure 1D As shown, after undergoing aging stress (such as HTOL testing), the off-state drain current of some devices increased significantly. In one batch of samples, the off-state drain current increased by an order of magnitude or more compared to the initial state, exhibiting a clear tail extension distribution characteristic. This phenomenon indicates that some devices experience degraded turn-off performance due to defect activation during stress (such as the trapping of hot electrons by the inner liner in shallow trench isolation structures), leading to an abnormal increase in off-state drain current. This degradation behavior of the off-state drain current is closely related to the hot electron-induced punch-through (HEIP) effect, especially in devices with process defects or high interface state density, reflecting the existence of early failure risk in traditional reliability testing.

[0053] Figure 1E The figure shown is a graph depicting the relationship between transistor size and threshold voltage shift (VT shift) in semiconductor devices in related technologies. Figure 1E As shown, with the same transistor channel length (L), the threshold voltage drift increases significantly as the transistor channel width (W) decreases. This indicates that the smaller the transistor channel width (W), the stronger the perturbation of the electric field at the edge of the active region by the STI structure, and the more prominent the ability of the inner liner to trap hot electrons, leading to intensified interface state generation and a more significant negative threshold voltage drift. This channel width dependence further corroborates the strong correlation between the HEIP failure mechanism and STI silicon nitride electronic defects.

[0054] In summary, during the operation of a PMOS transistor, electrons readily gain sufficient energy under a high electric field to form hot electrons, which are then trapped by the inner liner at the top of the STI structure, creating transient electronic defects such as electron traps at the interface or within the transistor. These defects trigger hot electron-induced punch-through (HEIP), leading to an abnormal increase in drain current during the transistor's off-state. This problem becomes particularly pronounced after High Temperature Operating Life (HTOL) testing, manifesting as threshold voltage drift and an increase in standby current (also known as off-state drain current), severely impacting the long-term reliability of the device. Currently, HTOL testing is primarily used to assess the impact of these defects on device reliability. However, traditional HTOL testing has many limitations: First, the testing cycle is as long as about 1,000 hours, and packaging time must be taken into account, which seriously slows down the process development progress; second, once a failure occurs, it is necessary to locate the electronic defect through complex electrical fault analysis (EFA) and other means, which is cumbersome and costly; third, devices with different channel width-to-length ratios (W / L) are affected by HEIP to varying degrees, with small-sized devices being more sensitive, making it difficult to trace the failure mechanism.

[0055] Based on this, this application provides a defect testing method and a semiconductor device to overcome the technical bottlenecks of long testing cycles, difficult positioning, and low efficiency of traditional HTOL testing, and to achieve rapid, efficient, and sensitive detection of transient electronic defects in the inner liner of shallow trench isolation (STI) structures.

[0056] Figure 2 The diagram illustrates a flow chart of an exemplary defect testing method for a semiconductor device according to an embodiment of this application. The semiconductor device includes a transistor formed on a substrate, the transistor being electrically isolated by a shallow trench isolation structure, the shallow trench isolation structure having an inner liner layer (e.g., a silicon nitride layer, SiN liner) on its sidewalls and top. Figure 2 As shown, the defect testing methods include:

[0057] In step S210, a first test value of the off-state drain current of the transistor in the semiconductor device is tested.

[0058] In some embodiments, before applying hot carrier injection (HCI) stress to the target transistor in the semiconductor device, a turn-off voltage (e.g., gate voltage Vg = 0 V) ​​is first applied to the gate of the target transistor, with the drain and source grounded or floating. The drain current flowing from the drain to the source in the turn-off state is measured and recorded as the first test value Ioff_initial. The first test value Ioff_initial reflects the leakage current level of the transistor in the initial state and serves as a benchmark for subsequent comparisons.

[0059] In step S220, hot carrier injection stress is applied to the transistors in the semiconductor device to excite transient electronic defects in the liner layer of the shallow trench isolation structure.

[0060] In some embodiments, a specific bias voltage is applied to the gate and drain of a transistor in a semiconductor device to operate it in the saturation region, thereby forming a high electric field region near the drain end of the channel and generating high-energy hot carriers to excite transient electronic defects in the liner layer of the shallow trench isolation structure. The specific bias voltage is set to a voltage range that maximizes the generation of electron-hole pairs (IEHP). This voltage range is determined by the peak position in the curve of electron-hole pair generation (IEHP) versus gate voltage (Vg). Figure 3 The figure shown is a graph illustrating the relationship between the number of electron-hole pairs generated and the gate voltage (Vg) according to an embodiment of this application. Figure 3As shown, as the gate voltage Vg gradually increases, the channel conduction capability strengthens and the drain current rises. However, under a fixed high drain voltage Vd (e.g., Vd = 1.5 × Vcc, where Vcc is the device's nominal power supply voltage, and Vs = Vb = 0 V, where Vs is the source voltage and Vb is the body voltage), the number of electron-hole pairs generated does not monotonically increase with the gate voltage Vg. Instead, it reaches its maximum value within a specific voltage range (e.g., between gate voltage Vg1 and gate voltage Vg2). Specifically, the number of electron-hole pairs generated peaks when the gate voltage Vg is approximately 1 / 2 Vd to 2 / 3 Vd, indicating that the number of electron-hole pairs generated per unit time is the highest at this point. This phenomenon stems from the synergistic effect of channel electric field distribution and carrier transport behavior: when the gate voltage Vg is too low, the channel is not fully open, the carrier concentration is low, and the generation of hot carriers is limited; when the gate voltage Vg approaches or exceeds the drain voltage Vd, the channel tends to be in the linear region, the drain electric field weakens, and the collisional ionization efficiency decreases; while in the range where the gate voltage Vg is approximately 1 / 2Vd to 2 / 3Vd, the transistor is in a strong saturation state, with a high-intensity transverse electric field at the drain and a moderate longitudinal electric field, which is conducive to carriers obtaining sufficient energy to induce collisional ionization, thereby efficiently generating electron-hole pairs. Therefore, in a preferred embodiment, the specific bias voltage applied to the gate of the transistor in the semiconductor device is 1 / 2 to 2 / 3 times the specific bias voltage applied to the drain of the transistor in the semiconductor device. Applying hot carrier injection stress under these conditions for a certain period of time (e.g., 10 s) can maximize the generation density of hot electrons and their injection probability into the inner liner of the top or sidewall of the shallow trench isolation (STI) structure, effectively activating the potential electron traps therein and simulating the hot electron-induced punch-through (HEIP) effect that occurs during actual high temperature working life (HTOL) testing.

[0061] In step S230, a second test value of the off-state drain current of the transistor in the semiconductor device is tested.

[0062] In some embodiments, after removing the hot carrier injection stress applied in step S220 and allowing the device to return to a steady state, the same measurement procedure as in step S210 is performed again: the gate is placed in the off state (e.g., gate voltage Vg = 0 V), and the off-state drain current of the transistor under the same conditions is measured and recorded as the second test value Ioff_stress. The second test value Ioff_stress reflects the change in leakage current caused by the activation of electronic defects in the inner liner under the action of hot carrier stress.

[0063] In step S240, the presence of electronic defects in the inner liner is determined by comparing the changes in the off-state drain current before and after the application of hot carrier injection stress.

[0064] In some embodiments, the difference or multiple of the first test value Ioff_initial and the second test value Ioff_stress is calculated (when the difference between the first test value Ioff_initial and the second test value Ioff_stress is large, the multiple is expressed in terms of order of magnitude). If the difference or multiple exceeds a preset threshold, it is determined that there is an electronic defect in the liner of the shallow trench isolation structure in the semiconductor device; if the difference or multiple does not exceed the preset threshold, it is determined that there is no defect in the liner of the shallow trench isolation structure in the semiconductor device. Figure 4 The figure shown is a comparison of the gate voltage and drain current before and after applying hot carrier injection stress, according to an embodiment of this application. Figure 4 As shown, with gate voltage Vg=0V, the first measured value of the off-state drain current Ioff_initial before applying hot carrier injection stress is approximately 10. -12 A, the second measured value of the off-state drain current, Ioff_stress, after applying hot carrier injection stress is approximately 10. -8 A, the difference between the two is four orders of magnitude, which intuitively confirms the significant amplification effect of the defect state on the drain current of the turn-off state; this order of magnitude jump directly corresponds to the increase in the interface trap density of the inner liner of the shallow trench isolation structure in semiconductor devices, providing a quantifiable failure criterion for process monitoring.

[0065] It is understood that, in the embodiments of this application, by measuring the change of the transistor turn-off drain current before and after hot carrier injection stress, the instantaneous electronic defects of the inner liner in the shallow trench isolation structure are rapidly detected. Electronic defect screening can be completed at the wafer level in just a few seconds to a few minutes, which greatly shortens the test cycle and significantly improves the efficiency of defect testing. At the same time, the microscopic electronic defects are converted into macroscopically measurable transistor turn-off drain current degradation signals by utilizing the HEIP physical mechanism, which has high sensitivity and failure prediction capabilities, avoiding the complex localization analysis process after failure.

[0066] It is understood that the embodiments of this application complete the test at the wafer level under non-destructive conditions, which will not cause permanent damage such as large-area thermal damage or metal melting of the device. This avoids the problem of local overheating and burning of defect areas due to severe leakage or breakdown of the device in traditional HTOL testing. As a result, the true microstructure at the defect can be completely preserved, which is conducive to subsequent accurate failure location and mechanism research through physical analysis methods (such as TEM, EDS, EFA, etc.).

[0067] In some embodiments, one or more dedicated parallel transistor arrays are fabricated on a semiconductor wafer. A systematic variable design of channel width and channel length is introduced to construct a quantitative response model for electronic defect sensitivity. This model is used to test the change in off-state drain current of devices with the same channel width but different channel lengths, or different channel widths but the same channel length. By analyzing the correlation between changes in channel width or channel length and the change in off-state drain current before and after applying hot carrier injection stress, defect identification is upgraded from qualitative judgment to quantitative analysis. This enhances the reliability of electronic defect judgment in the inner liner of shallow trench isolation structures and improves the sensitivity of detecting minute defects. Figure 5 The diagram shown is a schematic flowchart of another exemplary defect testing method for a semiconductor device according to an embodiment of this application. Figure 5 As shown, the defect testing methods include:

[0068] In step S510, a dedicated test structure is fabricated on a semiconductor wafer, the test structure comprising one or more types of transistors.

[0069] In one embodiment, the test structure is a wafer-level test key, integrated into the dicing lane or a dedicated monitoring area, without occupying core circuit area. The test structure includes one or more types of transistors, each type having a specific channel width (W) and channel length (L). In some embodiments, the one or more types of transistors have the same channel width but different channel lengths; or the one or more types of transistors have different channel widths but the same channel length. Figure 6 The diagram shown is an exemplary test structure according to an embodiment of this application. Figure 6 As shown, the test structure includes three types of transistors, for example, all three types of transistors have the same channel length but different channel widths: high channel width (e.g., 10 μm channel width, 0.13 μm channel length) transistor 601, medium channel width (e.g., 5 μm channel width, 0.13 μm channel length) transistor 602, and low channel width (e.g., 2 μm channel width, 0.13 μm channel length) transistor 603. The three types of transistors are arranged in an array to form a standardized test transistor array that can be read in parallel. Each type of transistor occupies the same wafer area; the high channel width transistor 601 is smaller in number due to its larger size, while the low channel width transistor 603 is more compact and denser. By designing various systematic combinations of channel width and channel length, the influence of device size effects on HEIP (hot electron-induced punch-through) sensitivity can be systematically studied.

[0070] In step S520, transistors of the same type are connected in parallel in the test structure to form one or more parallel transistor arrays.

[0071] In some embodiments, for each type of transistor, multiple individual devices are connected in parallel via metal interconnects to form an independently addressable parallel transistor array. The design purpose of the parallel transistor array is twofold: firstly, to increase the strength of the off-state drain current signal of the parallel transistor array, facilitating accurate measurement of weak drain current changes; secondly, given a fixed area for the dedicated test structure on the semiconductor wafer, increasing the number of small-sized devices connected in parallel can improve the statistical capture probability of local defects.

[0072] In step S530, the change in the off-state drain current before and after applying hot carrier injection stress to each parallel transistor array is measured.

[0073] In some embodiments, for each parallel transistor array, the off-state drain current of the parallel transistor array is tested and denoted as the first test value Ioff_initial. Subsequently, hot carrier injection stress is applied to the parallel transistor array to excite transient electronic defects in the liner layer of the shallow trench isolation structure. The off-state drain current of the parallel transistor array is tested again after stress, and denoted as the second test value Ioff_stress. Figure 6 For example, the first test value Ioff_initial and the second test value Ioff_stress of the off-state drain current of the high-channel-width transistor 601 array, the medium-channel-width transistor 602 array, and the low-channel-width transistor 603 array were tested respectively.

[0074] In step S540, the presence of electronic defects in the inner liner is determined by comparing the changes in the off-state drain current before and after the application of hot carrier injection stress.

[0075] In some embodiments, when the channel widths of the one or more types of transistors are the same but the channel lengths are different, for each parallel transistor array, the difference or change factor of the first test value Ioff_initial and the second test value Ioff_stress is calculated. If the difference or change factor increases as the channel length of the parallel transistor array decreases, it is determined that there is an electronic defect in the inner liner of the transistor of the semiconductor device. Figure 7 The diagram illustrates an exemplary test structure configuration according to an embodiment of this application. Figure 7As shown, the test structure includes three types of transistor arrays. The three parallel transistor arrays have the same channel width, but their channel lengths decrease sequentially. Transistors 701, 702, and 703 correspond to different types of transistor arrays, with the same channel width and sequentially decreasing channel lengths. It should be noted that, for convenience, Figure 7 Only one example transistor of each type is shown, and each type of crystal may include multiple example transistors connected in parallel. When hot carrier injection stress is applied to these parallel transistor arrays, by comparing the change in off-state drain current before and after stress application, it can be observed that the change in off-state drain current gradually increases as the channel length decreases. This is because a shorter channel length results in a higher electric field strength near the drain, leading to higher hot electron generation efficiency; simultaneously, the shallow trench isolation (STI) edge has a larger proportion relative to the channel region in short-channel devices, making the impact of electronic defects in the liner layer on device performance more significant. Therefore, for each parallel transistor array, the difference or factor of change between the first and second test values ​​is calculated; if the change in off-state drain current (difference or factor of change) increases as the channel length decreases, it indicates the presence of electronic defects in the liner layer of the shallow trench isolation structure.

[0076] In some embodiments, when the channel widths of the one or more types of transistors are different but the channel lengths are the same, for each parallel transistor array, the difference or change factor of the first test value Ioff_initial and the second test value Ioff_stress is calculated. If the difference or change factor increases as the channel width of the parallel transistor array decreases, it is determined that there is an electronic defect in the inner liner of the transistor of the semiconductor device. Figure 8 The diagram illustrates another exemplary configuration of a test structure according to an embodiment of this application. Figure 8 As shown, the test structure includes three types of transistor arrays. The three parallel transistor arrays have the same channel length, but their channel widths decrease sequentially. Transistors 801, 802, and 803 correspond to different types of transistor arrays, with the same channel length and sequentially decreasing channel widths. It should be noted that, for convenience, Figure 8Only one example transistor of each type is shown, and each type may contain multiple transistors connected in parallel. When hot carrier injection stress is applied to these parallel transistor arrays, comparing the changes in the off-state drain current before and after stress application reveals that the change in off-state drain current gradually increases as the channel width decreases. This is because a narrower channel width means a larger proportion of the active region edge relative to the total channel area, and electronic defects in the shallow trench isolation (STI) liner primarily affect the active region edge. The STI edge effect is more pronounced in narrow-width devices, and the impact of liner electronic defects on device performance is more significant. Therefore, for each parallel transistor array, the difference or factor of change between the first and second test values ​​is calculated; if the change in off-state drain current (difference or factor of change) increases with decreasing channel width, it further indicates the presence of electronic defects in the liner of the shallow trench isolation structure.

[0077] Figure 9 The diagram shows a comparison of the drain current in the off-state of an exemplary parallel transistor array with the same channel length but different channel widths after applying hot carrier injection stress, according to an embodiment of this application. Figure 9 As shown in the figure, the drain current response curves of parallel transistor arrays formed by three types of transistors with the same channel length and channel widths of 0.6 μm, 1 μm, and 6 μm, respectively, are as a function of gate voltage after stress. When the channel width is reduced from 6 μm to 0.6 μm, the change in the off-state drain current of the parallel transistor array after stress reaches three orders of magnitude. Therefore, the smaller the channel width, the larger the off-state drain current of the parallel transistor array. This phenomenon confirms that narrow-channel devices are more sensitive to defects in the shallow trench isolation liner.

[0078] Understandably, this systematic analysis method based on channel size variations can effectively distinguish the HEIP effect caused by electronic defects in the liner of shallow trench isolation structures from leakage current variations caused by process fluctuations or other non-systematic factors. When a clear correlation is observed between the change in off-state drain current and channel size (channel width or channel length), it can be confirmed that electronic defects exist in the liner of the shallow trench isolation structure, thus providing clear guidance for process improvement.

[0079] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A defect testing method for a semiconductor device, the semiconductor device comprising a shallow trench isolation structure having an inner liner layer, the defect testing method comprising: The first test value of the off-state drain current of the transistor in the semiconductor device is tested; Hot carrier injection stress is applied to the transistors in the semiconductor device to excite transient electronic defects in the liner layer of the shallow trench isolation structure; A second test value for the off-state drain current of the transistor in the semiconductor device; By comparing the changes in the off-state drain current before and after applying hot carrier injection stress, it can be determined whether there are electronic defects in the inner liner.

2. The defect testing method according to claim 1, wherein, Applying hot carrier injection stress to the transistors in the semiconductor device includes: A specific bias voltage is applied to the gate and drain of the transistor in the semiconductor device to make the transistor operate in the saturation region.

3. The defect testing method according to claim 2, wherein, The specific bias voltage is set to the voltage range that maximizes the number of electron-hole pairs generated.

4. The defect testing method according to claim 1, wherein, The method of determining whether there are electronic defects in the inner liner by comparing the changes in the off-state drain current before and after applying hot carrier injection stress includes: Calculate the difference or multiple of change between the first test value and the second test value. If the difference or multiple of change exceeds a preset threshold, it is determined that the inner lining layer has an electronic defect. If the difference or change factor does not exceed a preset threshold, the inner liner is determined to have no electronic defects.

5. The defect testing method according to claim 1, wherein, Before testing the first test value of the off-state drain current of the transistor in the semiconductor device, the defect testing method further includes: Dedicated test structures are fabricated on semiconductor wafers, the test structures comprising one or more types of transistors; Transistors of the same type are connected in parallel in the test structure to form one or more parallel transistor arrays, so as to measure the change of the off-state drain current before and after applying hot carrier injection stress to each parallel transistor array.

6. The defect testing method according to claim 5, wherein, One or more types of transistors have the same channel width but different channel lengths; or one or more types of transistors have different channel widths but the same channel length.

7. The defect testing method according to claim 6, wherein, The measurement of the change in off-state drain current before and after applying hot carrier injection stress to each parallel transistor array includes: For each parallel transistor array, test the first test value of the off-state drain current of the parallel transistor array; Hot carrier injection stress is applied to the parallel transistor array to excite transient electronic defects in the liner layer of the shallow trench isolation structure; The second test value of the off-state drain current of the parallel transistor array is tested.

8. The defect testing method according to claim 7, wherein, The method of determining whether there are electronic defects in the inner liner by comparing the changes in the off-state drain current before and after applying hot carrier injection stress includes: When the channel widths of one or more types of transistors are the same but the channel lengths are different, for each parallel transistor array, the difference or change factor between the first test value and the second test value is calculated respectively. If the difference or change factor increases as the channel length of the parallel transistor array decreases, it is determined that there is an electronic defect in the inner liner of the transistor of the semiconductor device.

9. The defect testing method according to claim 7, wherein, The method of determining whether there are electronic defects in the inner liner by comparing the changes in the off-state drain current before and after applying hot carrier injection stress includes: When the channel widths of one or more types of transistors are different but the channel lengths are the same, for each parallel transistor array, the difference or change factor between the first test value and the second test value is calculated respectively. If the difference or change factor increases as the channel width of the parallel transistor array decreases, it is determined that there is an electronic defect in the inner liner of the transistor of the semiconductor device.

10. A semiconductor device, wherein the defect testing method according to any one of claims 1 to 9 is used to perform defect testing on the inner liner of the shallow trench isolation structure of the semiconductor device.

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