Package substrate and semiconductor package including same

Abstract

A package substrate and a semiconductor package are provided. The package substrate may include: a base layer including a first surface and a second surface opposite to the first surface; the distribution structure is positioned in the base body layer; a bump pad connected to the distribution structure and located on the first surface of the base layer; a connection terminal attached to the bump pad, and a melting point of the connection terminal is a first temperature; and a metal protective layer located on a surface of the connection terminal and including tin, a melting point of the metal protective layer being a second temperature, where the first temperature is lower than the second temperature.

Description

Technical Field

[0001] This disclosure relates to a packaging substrate, a semiconductor package including the packaging substrate, and a method for manufacturing the semiconductor package, and more specifically, to a packaging substrate with attached connection terminals. Background Technology

[0002] In response to the rapid development of the electronics industry and user demands, electronic devices are being further miniaturized and multifunctionalized, and have greater capacity. Therefore, highly integrated semiconductor chips are required. Consequently, a semiconductor package is being designed that includes a highly integrated semiconductor chip with an increased number of connection terminals for input / output (I / O), while ensuring connection reliability. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a packaging substrate including connection terminals with low melting points and a semiconductor package including the packaging substrate can be provided.

[0004] According to some embodiments of this disclosure, a packaging substrate can be provided, and the packaging substrate may include: a substrate layer including a first surface and a second surface opposite to the first surface; a through-path extending from the first surface of the substrate layer to the second surface of the substrate layer; a first distribution structure located on the first surface of the substrate layer and including a first distribution pattern and a first interlayer insulating layer surrounding the first distribution pattern; a first bump pad located on and connected to the first distribution pattern of the first distribution structure, the first bump pad being spaced apart from the substrate layer, and the first distribution structure being located between the first bump pad and the substrate layer; a first passivation layer located on and surrounding the first bump pad, the first passivation layer including openings overlapping the first bump pad in a vertical direction; and a first connection terminal located on the first distribution structure. The first connection terminal comprises tin (Sn) and has a melting point of a first temperature in the opening of a passivation layer and located on the first bump pad; and a metal protective layer located on the surface of the first connection terminal, the metal protective layer comprising Sn and having a melting point of a second temperature, wherein the first temperature is lower than the second temperature.

[0005] According to some embodiments of this disclosure, a packaging substrate may be provided, and the packaging substrate may include: a substrate layer including a first surface and a second surface opposite to the first surface; a through-path extending from the first surface of the substrate layer to the second surface of the substrate layer; a first distribution structure located on the first surface of the substrate layer and including a first distribution pattern and a first interlayer insulating layer surrounding the first distribution pattern; and a first bump pad located on and connected to the first distribution pattern of the first distribution structure, the first bump pad being spaced apart from the substrate layer, and the first distribution structure being located on the first bump pad. Between the substrate layer; a first passivation layer, the first passivation layer being located on the first distribution structure and surrounding the first bump pad, the first passivation layer including openings that overlap with the first bump pad in the vertical direction; a first connection terminal, the first connection terminal being located in the openings of the first passivation layer and on the first bump pad, the first connection terminal comprising tin (Sn) and having a first hardness; a metal compound layer, the metal compound layer being located on the surface of each of the first connection terminals; and a metal protective layer, the metal protective layer being located on the surface of the first connection terminal and on the metal compound layer, and having a second hardness greater than the first hardness, wherein the melting point of the first bump pad is lower than the melting point of the metal protective layer.

[0006] According to some embodiments of this disclosure, a semiconductor package may be provided, and the semiconductor package may include a package substrate, the package substrate including: a substrate layer including a first surface and a second surface opposite to the first surface; a first distribution structure located on the first surface of the substrate layer; a second distribution structure located on the second surface of the substrate layer; a through-path penetrating the substrate layer and connecting the first distribution structure to the second distribution structure; a first bump pad located below the lower surface of the first distribution structure; a second bump pad located on the upper surface of the second distribution structure; and a first passivation layer surrounding the first bump pad and including openings overlapping the first bump pad in a vertical direction. The semiconductor package may further include: a main substrate, wherein the package substrate is located on an upper surface of the main substrate, and the main substrate includes substrate bump pads located on the upper surface of the main substrate; substrate connection terminals, the substrate connection terminals being located between the package substrate and the main substrate, and configured to electrically connect, physically connect, and respectively connect the first bump pads of the package substrate to the substrate bump pads of the main substrate, the melting point of the substrate connection terminals being a first temperature; metal protective layer fragments, the metal protective layer fragments being located inside each of the substrate connection terminals, and the melting point of the metal protective layer fragments being a second temperature higher than the first temperature; a semiconductor chip, the semiconductor chip being located on an upper surface of a second distribution structure of the package substrate; chip connection terminals, the chip connection terminals being located between the package substrate and the semiconductor chip, and configured to electrically connect, physically connect, and respectively connect the second bump pads of the package substrate to the chip pads of the semiconductor chip; and a molding layer, the molding layer being located on the package substrate and surrounding the semiconductor chip.

[0007] According to some embodiments of this disclosure, a method of manufacturing a semiconductor package may include: manufacturing a package substrate, the package substrate including a substrate layer, a first distribution structure disposed on a first surface of the substrate layer, a first bump pad disposed on the first distribution structure, and a second distribution structure disposed on a second surface of the substrate layer opposite to the first surface; and mounting a semiconductor chip onto the second distribution structure of the package substrate, wherein manufacturing the package substrate includes: attaching a first connection terminal to the first bump pad; forming a protective layer on the first distribution structure such that at least a portion of the surface of the first connection terminal is exposed; forming a metal protective layer on the first connection terminal with a melting point higher than the melting point of the first connection terminal; and removing the protective layer.

[0008] In embodiments of this disclosure, each of the first connection terminals comprises approximately 30% to approximately 60% wt% tin, and each of the metal protective layer fragments comprises approximately 95% to approximately 99% wt% tin.

[0009] In embodiments of this disclosure, each of the first connecting terminals has a first hardness and a first tensile strength, and each of the metal protective layer fragments has a second hardness greater than the first hardness and a second tensile strength greater than the first tensile strength.

[0010] In embodiments of this disclosure, the manufacturing method further includes attaching the packaging substrate to a host substrate by applying heat to the packaging substrate, wherein, during the attachment of the packaging substrate to the host substrate, the metal protective layer of the packaging substrate is fused with the first connection terminal to become a substrate connection terminal configured to electrically and physically connect the packaging substrate to the host substrate.

[0011] In embodiments of this disclosure, during the process of attaching the packaging substrate to the main substrate, a portion of the metal protective layer is not fused with the first connection terminal and remains inside the substrate connection terminal.

[0012] In embodiments of this disclosure, each of the first connection terminals comprises approximately 30% to approximately 60% wt% tin, and each of the metal protective layers comprises approximately 95% to approximately 99% wt% tin.

[0013] In embodiments of this disclosure, a metal compound layer is formed on the surface of the first connection terminal during the attachment process.

[0014] In embodiments of this disclosure, during the formation of the metal protective layer, when a portion of the surface of the first connecting terminal comes into contact with the protective layer, the metal protective layer is not formed at the portion of the protective layer that comes into contact with the first connecting terminal.

[0015] The aspects of the embodiments of this disclosure and the problems solved by the embodiments of this disclosure are not limited to the aspects and problems described above, and those skilled in the art can clearly understand other aspects of the embodiments of this disclosure not mentioned and the problems solved by the embodiments of this disclosure through the following description. Attached Figure Description

[0016] The embodiments can be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A This is a schematic cross-sectional view of the packaging substrate according to an embodiment; Figure 1BThis is a schematic cross-sectional view of the packaging substrate according to an embodiment; Figure 2 yes Figure 1A A schematic enlarged view of part EX in the packaging substrate; Figure 3 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate according to an embodiment; Figure 4 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate according to an embodiment; Figure 5 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate according to an embodiment; Figure 6 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate according to an embodiment; Figure 7 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate according to an embodiment; Figure 8 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate according to an embodiment; Figure 9 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate according to an embodiment; Figure 10 This is a cross-sectional view of a semiconductor package according to an embodiment; Figure 11 This is a schematic flow chart of a process for manufacturing a semiconductor package according to an embodiment; Figures 12A to 12F This is a cross-sectional view showing a method for manufacturing a semiconductor package according to an embodiment; Figure 13 This is a schematic flowchart of the process of a testing method for a semiconductor package according to an embodiment; Figures 14A to 14B This is a partial diagram illustrating a testing method for a semiconductor package according to an embodiment; Figure 15 This is a cross-sectional view illustrating a test method for a semiconductor package according to an embodiment; Figure 16 This is a cross-sectional view of a semiconductor package according to an embodiment. Detailed Implementation

[0017] Non-limiting exemplary embodiments of this disclosure are described below and illustrated in the accompanying drawings to provide a more complete explanation of the disclosure to those skilled in the art. The exemplary embodiments may be modified in various different ways, and the scope of this disclosure is not limited to the exemplary embodiments. Rather, various changes in form and detail may be made to the embodiments of this disclosure without departing from the spirit and scope thereof.

[0018] It will be understood that when a component or layer is referred to as being "on" another component or layer, "connected to" or "joined to" another component or layer, it may be directly on, directly connected to or directly joined to the other component or layer, or there may be intermediate components or layers. Conversely, when a component or layer is referred to as being "directly on" another component or layer, "directly connected to" or "directly joined to" another component or layer, there are no intermediate components or layers.

[0019] Figure 1A and Figure 1B These are schematic cross-sectional views of the packaging substrates 100 and 100R according to the embodiments. Figure 2 yes Figure 1A A schematic enlarged view of a portion EX in the packaging substrate 100.

[0020] refer to Figure 1A and Figure 2 The packaging substrate 100 may include a substrate layer 110, a through-path 110_V, a first distribution structure 121, a second distribution structure 122, a first bump pad 130, a second bump pad 160, a first connection terminal 140, and a metal protective layer 150. In some embodiments, the packaging substrate 100 may include a printed circuit board (PCB) or module substrate on which semiconductor chips are mounted.

[0021] In the following text, unless otherwise defined, a direction parallel to the upper surface of the substrate layer 110 may be defined as a first horizontal direction (e.g., the X direction), a direction perpendicular to the upper surface of the substrate layer 110 may be defined as a vertical direction (e.g., the Z direction), and a direction perpendicular to both the first horizontal direction (e.g., the X direction) and the vertical direction (e.g., the Z direction) may be defined as a second horizontal direction (e.g., the Y direction). A horizontal direction may be defined as including both the first horizontal direction (e.g., the X direction) and / or the second horizontal direction (e.g., the Y direction).

[0022] The substrate layer 110 may include a first surface 110_1 and a second surface 110_2 opposite to each other, and each of the first surface 110_1 and the second surface 110_2 of the substrate layer 110 may be a plane. The substrate layer 110 may generally be in the shape of a flat plate or a panel. For example, referring to FIG1, the first surface 110_1 of the substrate layer 110 may be referred to as the lower surface of the substrate layer 110, and the second surface 110_2 of the substrate layer 110 may be referred to as the upper surface of the substrate layer 110.

[0023] The substrate layer 110 may include at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the substrate layer 110 may include at least one material selected from prepreg, polyimide, flame retardant 4 (FR-4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine (BT), Thermount, cyanate ester, and liquid crystal polymer.

[0024] The substrate layer 110 may further include a through-path 110_V. The through-path 110_V can penetrate the substrate layer 110 and can extend from a first surface 110_1 of the substrate layer 110 to a second surface 110_2 of the substrate layer 110. The through-path 110_V can electrically connect the first distribution structure 121 to the second distribution structure 122. For example, a first portion of the through-path 110_V can contact a first distribution pattern 121_P of the first distribution structure 121, and a second portion of the through-path 110_V can contact a second distribution pattern 122_P of the second distribution structure 122.

[0025] For example, after forming a through hole extending from a first surface 110_1 of the substrate layer 110 to a second surface 110_2 of the substrate layer 110, a through passage 110_V can be conformally formed on the side surface of the through hole. For example, the through passage 110_V can be formed by using an electroplating process.

[0026] The first distribution structure 121 may be disposed on the first surface 110_1 of the substrate layer 110. The first distribution structure 121 may include multiple distribution layers. For example, the first distribution structure 121 may include four to eight distribution layers. However, the number of layers in the first distribution structure 121 is not limited thereto.

[0027] The thickness of the first distribution structure 121 can vary depending on the number of distribution layers included in the first distribution structure 121. In some embodiments, the thickness of the first distribution structure 121 can be from approximately 100 μm to approximately 1000 μm.

[0028] Each of the plurality of distribution layers of the first distribution structure 121 may include a corresponding first distribution pattern 121_P and a corresponding first interlayer insulating layer 121_D surrounding the first distribution pattern 121_P. The first distribution pattern 121_P may include a first distribution line 121_L extending horizontally on the first interlayer insulating layer 121_D and a first distribution path 121_V extending vertically (e.g., the Z direction) from the first distribution line 121_L. In some embodiments, the first interlayer insulating layer 121_D of each of the plurality of distribution layers of the first distribution structure 121 may be integrally formed (e.g., forming a body) without boundary surfaces therein.

[0029] For example, the first interlayer insulation layer 121_D can insulate the first distribution lines 121_L arranged in different distribution layers from each other. The first distribution path 121_V can penetrate the first interlayer insulation layer 121_D to be electrically connected to the first distribution lines 121_L arranged in different distribution layers.

[0030] The second distribution structure 122 can be formed on the second surface 110_2 of the substrate layer 110. The second distribution structure 1221 may include multiple distribution layers. For example, the second distribution structure 122 may include four to eight distribution layers. However, the number of layers in the second distribution structure 122 is not limited thereto.

[0031] The thickness of the second distribution structure 122 can vary depending on the number of distribution layers included in the second distribution structure 122. In some embodiments, the number of distribution layers in the second distribution structure 122 may be the same as or different from the number of distribution layers in the first distribution structure 121. In some embodiments, the thickness of the second distribution structure 122 may be from approximately 100 μm to approximately 1000 μm.

[0032] Each of the plurality of distribution layers of the second distribution structure 122 may include a corresponding second distribution pattern 122_P and a corresponding second interlayer insulating layer 122_D surrounding the second distribution pattern 122_P. The second distribution pattern 122_P may include a second distribution line 122_L extending horizontally on the second interlayer insulating layer 122_D and a second distribution path 122_V extending from the second distribution line 122_L in a vertical direction (e.g., the Z direction). In some embodiments, the second interlayer insulating layer 122_D of each of the plurality of distribution layers of the second distribution structure 122 may be integrally formed (e.g., forming a body) without a boundary surface therein.

[0033] For example, the second interlayer insulation layer 122_D can insulate the second distribution lines 122_L arranged in different distribution layers from each other. The second distribution path 122_V can penetrate the second interlayer insulation layer 122_D to be electrically connected to the second distribution lines 122_L arranged in different distribution layers.

[0034] In some embodiments, the first distribution pattern 121_P and the second distribution pattern 122_P may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), or alloys thereof. In some embodiments, the first interlayer insulating layer 121_D and the second interlayer insulating layer 122_D may include polypropylene glycol (PPG). However, the materials of the first interlayer insulating layer 121_D and the second interlayer insulating layer 122_D are not limited thereto.

[0035] The first bump pad 130 may be disposed on the first distribution structure 121 and electrically connected to the first distribution pattern 121_P of the first distribution structure 121. For example, the first bump pad 130 may be separate from the substrate layer 110 and may be disposed on the first distribution structure 121. The first bump pad 130 may be disposed on the lower surface of the first distribution structure 121.

[0036] The second bump pad 160 can be disposed on the second distribution structure 122 and electrically connected to the second distribution pattern 122_P of the second distribution structure 122. The second bump pad 160 can be separated from the substrate layer 110 and can be disposed on the second distribution structure 122. The second bump pad 160 can be disposed on the upper surface of the second distribution structure 122.

[0037] In some embodiments, the first bump pad 130 may be referred to as the lower bump pad, and the second bump pad 160 may be referred to as the upper bump pad. In some embodiments, the first bump pad 130 may be a portion of the first distribution pattern 121_P, and the second bump pad 160 may be a portion of the second distribution pattern 122_P. For example, the first bump pad 130 may include a portion of the first distribution line 121_L disposed in the lowest distribution layer, and the second bump pad 160 may include a portion of the second distribution line 122_L disposed in the highest distribution layer.

[0038] For example, the first bump pad 130 and the second bump pad 160 may include conductive materials such as Cu, Al, silver (Ag), Sn, gold (Au), Ni, lead (Pb), Ti, or alloys thereof.

[0039] At least one first passivation layer 130_P may be located on the lower surface of the first distribution structure 121 and may surround the first bump pad 130. The first passivation layer 130_P may include an opening that overlaps with the first bump pad 130 in a vertical direction (e.g., the Z direction). The lower surface of the first bump pad 130 may be exposed to the outside through the opening of the first passivation layer 130_P.

[0040] In some embodiments, the thickness of the first passivation layer 130_P may be greater than the thickness of each first bump pad 130. The side surface of the first passivation layer 130_P may be aligned (e.g., coplanar) with the side surface of the first distribution structure 121 in the vertical direction (e.g., the Z direction). In some embodiments, the width of each opening of the first passivation layer 130_P may be less than the width of each first bump pad 130.

[0041] The second passivation layer 160_P may be disposed on the second distribution structure 122 and may surround the second bump pad 160. In some embodiments, the second passivation layer 160_P may include openings that overlap with the second bump pad 160 in a vertical direction (e.g., the Z direction). The upper surface of the second bump pad 160 may be exposed to the outside through the openings of the second passivation layer 160_P. The side surfaces of the second passivation layer 160_P may be aligned (e.g., coplanar) with the side surfaces of the second distribution structure 122 in a vertical direction (e.g., the Z direction). In some embodiments, the width of each opening of the second passivation layer 160_P may be smaller than the width of each second bump pad 160.

[0042] The first connection terminals 140 may be disposed below the first bump pads 130. For example, each first connection terminal 140 may be disposed inside an opening of the first passivation layer 130_P and may contact the corresponding first bump pad 130. For example, each first connection terminal 140 may contact the sidewall of the first passivation layer 130_P that defines the opening of the first passivation layer 130_P.

[0043] Each first connection terminal 140 may include a first surface 140_1 and a second surface 140_2. The first surface 140_1 of the first connection terminal 140 may include a portion of the first connection terminal 140 that contacts one of the first bump pad 130 and the first passivation layer 130_P, and the second surface 140_2 of the first connection terminal 140 may include other portions of the first connection terminal 140.

[0044] The first connection terminal 140 can be configured to electrically and physically connect the package substrate 100 and an external device on which the package substrate 100 is mounted. For example, the first connection terminal 140 may include solder balls or solder bumps. For example, the first connection terminal 140 may include low-melting-point solder balls or low-melting-point solder bumps having a relatively low melting point.

[0045] Each metal protective layer 150 may be disposed on the second surface 140_2 of the corresponding first connection terminal 140. For example, each metal protective layer 150 may cover the second surface 140_2 of the first connection terminal 140 corresponding to the metal protective layer 150. In some embodiments, the first surface 140_1 of the first connection terminal 140 may contact the first bump pad 130 and / or the first passivation layer 130_P, and the second surface 140_2 of the first connection terminal 140 may contact the metal protective layer 150. In some embodiments, the first connection terminal 140 and the metal protective layer 150 may be collectively referred to as a bump.

[0046] In some embodiments, the first connection terminal 140 may include solder balls with a diameter of approximately 100 μm to approximately 600 μm. For example, the maximum width of each first connection terminal 140 may be approximately 100 μm to approximately 600 μm. In this disclosure, the width of each first connection terminal 140 may refer to the length of each first connection terminal 140 in the horizontal direction (e.g., the X direction or the Y direction).

[0047] For example, each metal protective layer 150 may be conformally formed on the second surface 140_2 of the first connection terminal 140 corresponding to the metal protective layer 150. For example, the first connection terminal 140 may be completely covered by the metal protective layer 150 and may not be exposed to the outside.

[0048] In some embodiments, the thickness of each metal protective layer 150 may be from approximately 3 μm to approximately 10 μm. In this disclosure, the surface of the metal protective layer 150 that contacts the first connection terminal 140 may be referred to as the inner surface, the surface of the metal protective layer 150 exposed to the outside may be referred to as the outer surface, and the distance from the inner surface to the outer surface of the metal protective layer 150 may be referred to as the thickness of the metal protective layer 150. In this disclosure, conformally forming of the metal protective layers 150 may refer to the uniform thickness of each metal protective layer 150.

[0049] Each of the first connecting terminal 140 and the metal protective layer 150 may include Sn as a constituent material. The melting point of each first connecting terminal 140 may be a first temperature, and the melting point of each metal protective layer 150 may be a second temperature. For example, the first temperature may be lower than the second temperature. The melting point of each metal protective layer 150 may be higher than the melting point of the first connecting terminal 140. In some embodiments, the first temperature may be from approximately 140 degrees Celsius to approximately 180 degrees Celsius, and the second temperature may be from approximately 200 degrees Celsius to approximately 240 degrees Celsius.

[0050] In some embodiments, each first connecting terminal 140 may have a first hardness, and each metal protective layer 150 may have a second hardness. The first hardness may be less than the second hardness. For example, because the hardness of the metal protective layer 150 may be higher than the hardness of the first connecting terminal 140, the deformation of the metal protective layer 150 due to external force may be less than the deformation of the first connecting terminal 140 due to external force. In some embodiments, at the temperature during the aging test, the first hardness may be approximately 60% to approximately 75% of the second hardness.

[0051] In some embodiments, each first connecting terminal 140 may have a first tensile strength, and each metal protective layer 150 may have a second tensile strength. The first tensile strength may be less than the second tensile strength. For example, because the tensile strength of the metal protective layer 150 may be higher than that of the first connecting terminal 140, the fragmentation of the metal protective layer 150 due to external force may be less than that of the first connecting terminal 140 due to external force. In some embodiments, at the temperature during the aging test, the first tensile strength may be approximately 50% to approximately 75% of the second tensile strength.

[0052] For example, each first connection terminal 140 may include a solder alloy containing approximately 30% to approximately 60% Sn. Each metal protective layer 150 may include a solder alloy containing approximately 96% to approximately 99% Sn. For example, the first connection terminal 140 may include a tin-bismuth (Sn-Bi) based solder alloy, and the metal protective layer 150 may include a tin-silver-copper (SAC) based solder alloy.

[0053] Because the melting point of the first connection terminal 140 attached to the packaging substrate 100 may be relatively low, attachment reliability can be improved during the mounting of the packaging substrate 100 onto an external device. However, in aging tests used to test the performance of the packaging substrates of the comparative embodiments, the first connection terminal of the packaging substrate melts, causing deformation of its appearance and contamination of the aging test equipment. In the packaging substrate 100 according to the embodiments of the present disclosure, because the melting point of the metal protective layer 150 surrounding the surface of the first connection terminal 140 is higher than the melting point of the first connection terminal 140, contamination of the aging test equipment can be suppressed even when the first connection terminal 140 melts. In addition, by using a metal protective layer 150 with higher tensile strength and higher hardness than the first connection terminal 140, the packaging substrate 100 according to the embodiments of the present disclosure can suppress the occurrence of scratches, cracks, and other phenomena in the first connection terminal 140 and the metal protective layer 150.

[0054] refer to Figure 1B The packaging substrate 100R may include a substrate layer 110R, a distribution structure 120R, a first bump pad 130R, a second bump pad 160R, a first connection terminal 140, and a metal protective layer 150. In some embodiments, the packaging substrate 100 may include an intermediate substrate or a redistribution layer (RDL).

[0055] The substrate layer 110R may have a multilayer structure, wherein the distribution structure 120R is arranged on each layer. For example, the substrate layer 110R may include an insulating material, such as a photosensitive imaging dielectric (PID) resin. In this case, the substrate layer 110R may also include inorganic fillers.

[0056] The distribution structure 120R can be arranged in the substrate layer 110R. The distribution structure 120R can include distribution lines 120_L extending horizontally from the upper or lower surface of each substrate layer 110R and distribution paths 120_V extending vertically (e.g., the Z direction) from the distribution lines 120_L. For example, the distribution paths 120_V can penetrate at least a portion of the substrate layer 110R and electrically connect multiple distribution lines 120_L located at different vertical heights to each other.

[0057] In some embodiments, at least one distribution line 120_L of the distribution structure 120R may be arranged on a first surface 110R_1 of the substrate layer 110R, and at least another distribution line 120_L of the distribution structure 120R may be arranged on a second surface 110R_2 of the substrate layer 110R (e.g., within or on the second surface 110R_2). The distribution structure 120R may be electrically connected to an external device on which the packaging substrate 100R is mounted, and may also be electrically connected to an external device mounted on the packaging substrate 100R.

[0058] The distribution structure 120R may include conductive materials such as Cu, Al, Ag, Sn, Au, Ni, Pb, Ti or alloys thereof.

[0059] A first bump pad 130R may be disposed on a first surface 110R_1 of the substrate layer 110R (e.g., within or on the first surface 110R_1), and a second bump pad 160R may be disposed on a second surface 110R_2 of the substrate layer 110R (e.g., within or on the second surface 110R_2). The first bump pad 130R and the second bump pad 160R may be electrically connected to the distribution structure 120R. In some embodiments, the first bump pad 130R may be referred to as a lower bump pad, and the second bump pad 160R may be referred to as an upper bump pad.

[0060] The first connection terminals 140 can be disposed below the first bump pads 130R. A metal protective layer 150 can be located on the surface of the first connection terminals 140. For example, the first connection terminals 140 and the metal protective layer 150 can be respectively positioned with reference... Figure 1A The first connection terminal 140 and the metal protective layer 150 described are substantially the same.

[0061] Figure 3 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate 100a according to an embodiment. Figure 4 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate 100b according to an embodiment. Figure 5This is a schematic enlarged cross-sectional view of a portion of the packaging substrate 100c according to an embodiment.

[0062] The components constituting package substrates 100a, 100b, and 100c described below, as well as the materials used in these components, can be found in reference [reference]. Figure 2 The components and materials described are essentially the same or similar. Therefore, for ease of description, the main focus is on... Figure 3 , Figure 4 and Figure 5 The packaging substrates 100a, 100b, and 100c described above are respectively... Figure 2 The differences between the packaging substrates 100 in the middle.

[0063] Let's refer to each other. Figure 3 and Figure 1A The packaging substrate 100a may include a substrate layer 110, a through-path 110_V, a first distribution structure 121, a second distribution structure 122, a first bump pad 130, a second bump pad 160, a first connection terminal 140, and a metal protective layer 150a.

[0064] The first connection terminal 140 can be attached to a first bump pad 130 disposed below the lower surface of the first distribution structure 121. The first connection terminal 140 can be attached to a corresponding first bump pad 130. The first connection terminal 140 may include a low-melting-point solder ball or a low-melting-point solder bump.

[0065] Each metal protective layer 150a can be disposed on the second surface 140_2 of the corresponding first connection terminal 140. For example, each metal protective layer 150a can cover the second surface 140_2 of the first connection terminal 140 corresponding to the metal protective layer 150a. The first connection terminal 140 can be completely covered by the metal protective layer 150a and can be not exposed to the outside.

[0066] The melting point of the metal protective layer 150a may be higher than that of the first connecting terminal 140. The tensile strength and hardness of the metal protective layer 150a may be greater than those of the first connecting terminal 140. The weight ratio of Sn included in each metal protective layer 150a may be greater than the weight ratio of Sn included in each first connecting terminal 140.

[0067] For example, the thickness of the metal protective layer 150a can increase with distance from the first passivation layer 130_P. For example, the thickness of the metal protective layer 150a may not be constant.

[0068] For example, each metal protective layer 150a may have a relatively larger thickness at the lower part of the first connection terminal 140 compared to the thickness of the portion of the metal protective layer 150a located on the side of each first connection terminal 140. Therefore, the degree of deformation of the metal protective layer 150a due to the external force applied at the lower part of the first connection terminal 140 may be relatively small.

[0069] Let's refer to each other. Figure 4 and Figure 1A The packaging substrate 100b may include a substrate layer 110, a through-path 110_V, a first distribution structure 121, a second distribution structure 122, a first bump pad 130, a second bump pad 160, a first connection terminal 140, and a metal protective layer 150b.

[0070] A metal protective layer 150b may be disposed on the surface of a first connection terminal 140 respectively attached to a first bump pad 130. The metal protective layer 150b and the first passivation layer 130_P may be separated from each other in the vertical direction (e.g., the Z direction), thereby forming a gap G between each metal protective layer 150b and each first passivation layer 130_P. The gap G may be annular in shape surrounding the first connection terminal 140. In some embodiments, the length of the gap G in the vertical direction (e.g., the Z direction) may be from approximately 10 μm to approximately 70 μm.

[0071] For example, a portion of each first connection terminal 140 may be exposed to the outside through a gap G. For example, the gap G may be disposed at a portion of the second surface 140_2 of each first connection terminal 140, thus exposing a portion of the second surface 140_2 to the outside. For example, the gap G may be disposed at a portion of the second surface 140_2 of the first connection terminal 140, and a metal protective layer 150b may be formed on the remaining portion of the second surface 140_2. For example, in the process of forming the metal protective layer 150b, a portion of the second surface 140_2 of the first connection terminal 140 may be protected by the protective layer (e.g., Figure 12D The protective layer PL is covered, and gaps G in which no metal protective layer 150b is formed can be formed.

[0072] The metal protective layer 150b may be conformally formed on the second surface 140_2 of the first connection terminal 140. For example, each metal protective layer 150b may have a constant thickness. In some embodiments, the thickness of each metal protective layer 150b may be from about 3 μm to about 10 μm.

[0073] Let's refer to each other. Figure 5 and Figure 1AThe packaging substrate 100c may include a substrate layer 110, a through-path 110_V, a first distribution structure 121, a second distribution structure 122, a first bump pad 130, a second bump pad 160, a first connection terminal 140, and a metal protective layer 150c.

[0074] A metal protective layer 150c may be disposed on the surface of the first connection terminal 140, which is respectively attached to the first bump pad 130. The metal protective layer 150c may be separated from the first passivation layer 130_P in the vertical direction (e.g., the Z direction), thereby forming a gap G. For example, a portion of the surface of the first connection terminal 140 may be exposed to the outside through the gap G. For example, the gap G may be an annular shape with a constant length in the vertical direction (e.g., the Z direction).

[0075] The thickness of the metal protective layer 150c can increase with distance from the first passivation layer 130_P. For example, the thickness of the metal protective layer 150c formed on the first connection terminal 140 may not be constant. For example, each metal protective layer 150c may have a relatively larger thickness in the portion of the metal protective layer 150c disposed below the lower portion of each first connection terminal 140 compared to the portion disposed on the side of each first connection terminal 140.

[0076] Figure 6 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate 100d according to an embodiment.

[0077] The components constituting the packaging substrate 100d described below, as well as the materials used in those components, can be found in the reference above. Figure 2 The components and materials described are essentially the same or similar. Therefore, for ease of explanation, the main focus is on describing... Figure 6 The packaging substrate 100d is the same as described above. Figure 2 The difference between the packaging substrates 100.

[0078] Let's refer to each other. Figure 6 and Figure 1A The packaging substrate 100d may include a substrate layer 110, a through-path 110_V, a first distribution structure 121, a second distribution structure 122, a first bump pad 130, a second bump pad 160, a first connection terminal 140', a metal compound layer 145, and a metal protective layer 150.

[0079] The first bump pad 130 can be electrically connected to the first distribution structure 121 and can be formed below the lower surface of the first distribution structure 121. Each first connection terminal 140' can be disposed inside an opening of the first passivation layer 130_P and can contact the corresponding first bump pad 130.

[0080] Each first connection terminal 140' may include a first surface 140'_1 and a second surface 140'_2. For example, the first surface 140'_1 of the first connection terminal 140' may include a portion that contacts one of the first bump pad 130 and the first passivation layer 130_P, and the second surface 140'_2 of the first connection terminal 140' may include other portions that do not contact the first bump pad 130.

[0081] Each metal compound layer 145 may be disposed on the second surface 140'_2 of the corresponding first connection terminal 140'. For example, the area of ​​each metal compound layer 145 may be smaller than the area of ​​the second surface 140'_2 of each first connection terminal 140', so that each metal compound layer 145 may not completely cover the second surface 140'_2 of the first connection terminal 140'.

[0082] In some embodiments, during the process of attaching the first connection terminal 140' to the first bump pad 130, a metal compound layer 145 can be formed on the second surface 140'_2 of the first connection terminal 140' by utilizing a chemical reaction between the first connection terminal 140' and the first bump pad 130. For example, the metal compound layer 145 may include gold (Au) as a constituent material.

[0083] A metal protective layer 150 may be disposed on the second surface 140'_2 of the first connecting terminal 140' and the metal compound layer 145. For example, the metal protective layer 150 may surround the first connecting terminal 140' and the metal compound layer 145. The metal compound layer 145 may be disposed between the metal protective layer 150 and the first connecting terminal 140'. For example, the metal compound layer 145 may be completely covered by the metal protective layer 150 and may not be exposed to the outside.

[0084] For example, each metal protective layer 150 may be conformally formed on the second surface 140'_2 of the first connection terminal 140' corresponding to the metal protective layer 150. In some embodiments, the thickness of each metal protective layer 150 may be from approximately 3 μm to approximately 10 μm.

[0085] In some embodiments, the first connection terminal 140' may include a low-melting-point solder ball or a low-melting-point solder bump. A portion of the surface of each first connection terminal 140' may have an edge. For example, a portion of the second surface 140'_2 of each first connection terminal 140' may have an edge. For example, the first connection terminal 140' may be in the shape of a sphere with a portion of it cut off. For example, in the process of attaching the first connection terminal 140' to the first bump pad 130, a portion of the second surface 140'_2 of the first connection terminal 140' may have an edge by utilizing the chemical reaction between the first connection terminal 140' and the first bump pad 130.

[0086] The melting point of the metal protective layer 150 may be higher than that of the first connecting terminal 140'. The tensile strength and hardness of the metal protective layer 150 may be greater than those of the first connecting terminal 140'. The weight ratio of Sn included in each metal protective layer 150 may be greater than the weight ratio of Sn included in each first connecting terminal 140'.

[0087] For example, the melting point of each first connection terminal 140' may be from approximately 140°C to approximately 180°C, and the melting point of each metal protective layer 150 may be from approximately 200°C to approximately 240°C. At the temperature at which the aging test is performed, the hardness of each first connection terminal 140' may be from approximately 60% to approximately 75% of the hardness of each metal protective layer 150. At the temperature at which the aging test is performed, the tensile strength of each first connection terminal 140' may be from approximately 50% to approximately 75% of the tensile strength of each metal protective layer 150. Each first connection terminal 140' may include a solder alloy containing approximately 30% to approximately 60% Sn. Each metal protective layer 150 may include a solder alloy containing approximately 96% to approximately 99% Sn.

[0088] The metal compound layer 145 may have a first reflectivity, and the metal protective layer 150 may have a second reflectivity. For example, the first reflectivity may be greater than the second reflectivity. Additionally, the reflectivity of the metal compound layer 145 may be higher than that of the metal protective layer 150 and the first connection terminal 140'. In other words, when the same light is incident on each of the metal compound layer 145 (e.g., a metal compound film) and the metal protective layer 150, the metal compound layer 145 may reflect more light than the metal protective layer 150.

[0089] During the performance of appearance testing to determine whether bumps are attached to the package substrate 100d, when the metal compound layer 145 is exposed to the outside, it can reflect a significant amount of light. Therefore, in the comparative embodiment, the reliability of the appearance test is reduced. The metal compound layer 145 can be covered by the metal protective layer 150 and cannot be exposed to the outside. Therefore, in the package substrate 100d of the embodiments of this disclosure, the metal compound layer 145 can be covered by the metal protective layer 150, which reduces the amount of light reflected during testing and improves the reliability of the appearance test.

[0090] Figure 7 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate 100e according to an embodiment. Figure 8 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate 100f according to an embodiment. Figure 9 This is a schematic enlarged cross-sectional view of a portion of the packaging substrate 100g according to an embodiment.

[0091] The components constituting the package substrates 100e, 100f, and 100g, as well as the materials used in these components, will be described below with reference to [reference]. Figure 6 The components and materials described are essentially the same or similar. Therefore, for ease of description, the main focus is on... Figure 7 , Figure 8 and Figure 9 The packaging substrates 100e, 100f, and 100g are respectively compared with those described above. Figure 6 The difference between the 100d packaging substrates.

[0092] Let's refer to each other. Figure 7 and Figure 1A The packaging substrate 100e may include a substrate layer 110, a through-path 110_V, a first distribution structure 121, a second distribution structure 122, a first bump pad 130, a second bump pad 160, a first connection terminal 140', a metal compound layer 145, and a metal protective layer 150e.

[0093] The first connection terminal 140' can be attached to the first bump pad 130 disposed on the lower surface of the first distribution structure 121, and can be disposed inside the opening of the first passivation layer 130_P. The first connection terminal 140' may include a low-melting-point solder ball or a low-melting-point solder bump.

[0094] Each metal protective layer 150e may be disposed on the second surface 140'_2 of the first connection terminal 140' and the metal compound layer 145. The second surface 140'_2 of the first connection terminal 140' and the metal compound layer 145 may be covered by the metal protective layer 150e and may not be exposed to the outside.

[0095] The metal protective layer 150e can become thicker as it moves away from the first passivation layer 130_P. For example, the thickness of the metal protective layer 150e may not be constant.

[0096] For example, each metal protective layer 150e may have a relatively larger thickness at the lower part of the first connecting terminal 140' compared to the thickness of the portion of the metal protective layer 150e on the side of each first connecting terminal 140'. Therefore, the degree of deformation of the metal protective layer 150e due to the external force applied to the lower part of the first connecting terminal 140' may be relatively small.

[0097] Let's refer to each other. Figure 8 and Figure 1A The packaging substrate 100f may include a substrate layer 110, a through-path 110_V, a first distribution structure 121, a second distribution structure 122, a first bump pad 130, a second bump pad 160, a first connection terminal 140', a metal compound layer 145, and a metal protective layer 150f.

[0098] A metal protective layer 150f may be disposed on the second surface 140'_2 of the first connecting terminal 140' and the metal compound layer 145. The metal protective layer 150f and the first passivation layer 130_P may be separated from each other in the vertical direction (e.g., the Z direction), thereby forming a gap G between each metal protective layer 150f and each first passivation layer 130_P. The gap G may be annular in shape around the first connecting terminal 140'. In some embodiments, the length of the gap G in the vertical direction (e.g., the Z direction) may be from approximately 10 μm to approximately 70 μm.

[0099] For example, a portion of each first connection terminal 140' may be exposed to the outside through a gap G. For example, the gap G may be disposed at a portion of the second surface 140'_2 of each first connection terminal 140', thus exposing a portion of the second surface 140'_2 to the outside. In some embodiments, a portion of the metal compound layer 145 may be disposed in the gap G, thereby being exposed to the outside.

[0100] The metal protective layer 150f may be conformally formed on the second surface 140'_2 of the first connection terminal 140'. For example, each metal protective layer 150f may have a constant thickness. In some embodiments, the thickness of each metal protective layer 150f may be from approximately 3 μm to approximately 10 μm.

[0101] Let's refer to each other. Figure 9 and Figure 1AThe packaging substrate 100g may include a substrate layer 110, a through-path 110_V, a first distribution structure 121, a second distribution structure 122, a first bump pad 130, a second bump pad 160, a first connection terminal 140', a metal compound layer 145, and a metal protective layer 150g.

[0102] A metal protective layer 150g can be disposed on a second surface 140'_2 of a first connection terminal 140' respectively attached to a first bump pad 130. The metal protective layer 150g can be separated from the first passivation layer 130_P in the vertical direction (e.g., the Z direction) and can form a gap G. For example, a portion of the surface of the first connection terminal 140' can be exposed to the outside through the gap G. For example, the gap G can be an annular shape with a constant length in the vertical direction (e.g., the Z direction).

[0103] The thickness of the metal protective layer 150g can increase with distance from the first passivation layer 130_P. For example, the thickness of the metal protective layer 150g formed on the first connection terminal 140' may not be constant. For example, each metal protective layer 150g may have a relatively larger thickness in the portion disposed below the lower portion of each first connection terminal 140' compared to the portion disposed on the side of each first connection terminal 140'.

[0104] Figure 10 This is a cross-sectional view of the semiconductor package 1000 according to an embodiment.

[0105] refer to Figure 10 The semiconductor package 1000 may include a package substrate 100, a semiconductor chip 200 and a molding layer ML. The package substrate 100 includes a first connection terminal 140 and a metal protective layer 150.

[0106] The packaging substrate 100 may include: a substrate layer 110, including a first surface 110_1 and a second surface 110_2 opposite to the first surface 110_1; a first distribution structure 121 located on the first surface 110_1 of the substrate layer 110; a second distribution structure 122 located on the second surface 110_2 of the substrate layer 110; a through-path 110_V electrically connected to the first distribution structure 121 and the second distribution structure 122; a first bump pad 130 located on the lower surface of the first distribution structure 121; and a second bump pad 160 located on the upper surface of the second distribution structure 122.

[0107] The first connection terminal 140 can be attached to the first bump pad 130 of the package substrate 100, and the metal protective layer 150 can be located on the surface of the first connection terminal 140. The melting point of the first connection terminal 140 can be lower than the melting point of the metal protective layer 150. The hardness of the first connection terminal 140 can be lower than the hardness of the metal protective layer 150. The tensile strength of the first connection terminal 140 can be less than the tensile strength of the metal protective layer 150.

[0108] The packaging substrate 100 may include the components described above. Figure 1A , Figure 1B as well as Figures 2 to 9 One of the following packaging substrates: 100, 100R, 100a, 100b, 100c, 100d, 100e, 100f, and 100g.

[0109] Semiconductor chip 200 may be located on the second distribution structure 122 of package substrate 100. Semiconductor chip 200 may include an active surface and a passive surface opposite to the active surface. Semiconductor chip 200 may be disposed on the second surface 110_2 of the substrate layer 110 of package substrate 100, such that the active surface faces package substrate 100. For example, semiconductor chip 200 may be disposed on package substrate 100 with its orientation downwards.

[0110] Semiconductor chip 200 may include, for example, semiconductor materials such as silicon (Si) and germanium (Ge). Alternatively, semiconductor chip 200 may include compound semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphate (InP). Semiconductor chip 200 may include doped wells, which are conductive regions. Semiconductor chip 200 may have various device isolation structures, such as shallow trench isolation (STI) structures.

[0111] Semiconductor devices comprising multiple independent components of various types can be formed on the active surface of semiconductor chip 200. Multiple independent components can be included in the conductive regions of semiconductor chip 200.

[0112] The semiconductor device may also include a conductive distribution or conductive plugs that electrically connect multiple independent devices to conductive regions of the semiconductor chip 200. Additionally, each of the multiple independent devices may be electrically isolated from another adjacent independent device by an insulating layer.

[0113] In some embodiments, semiconductor chip 200 may include logic devices. For example, semiconductor chip 200 may include a central processing unit chip, a graphics processing unit chip, or an application processor (AP). In some other embodiments, when semiconductor package 1000 includes a plurality of semiconductor chips 200, one of the plurality of semiconductor chips 200 may include a central processing unit chip, a graphics processing unit chip, or an AP chip, and other semiconductor chips among the plurality of semiconductor chips 200 may include memory semiconductor chips with memory devices.

[0114] For example, the memory device may include, for instance, non-volatile memory devices such as flash memory, phase-change random access memory (RAM) (PRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and resistive RAM (RRAM). In some embodiments, the memory device may include volatile memory devices such as dynamic RAM (DRAM) and static RAM (SRAM).

[0115] In some embodiments, the semiconductor chip 200 may further include chip pads 210. Chip pads 210 may be electrically connected to conductive regions of multiple individual devices via a distribution pattern of the semiconductor chip 200. For example, chip pads 210 may include a conductive material, such as Al.

[0116] Chip connection terminals 220 can be disposed between the semiconductor chip 200 and the package substrate 100. Each chip connection terminal 220 can be disposed between the second bump pad 160 of the package substrate 100 and the chip pad 210 of the semiconductor chip 200. The semiconductor chip 200 can be physically and electrically connected to the package substrate 100 through the chip connection terminals 220. However, the embodiments are not limited to this, and the semiconductor chip 200 can be physically and electrically connected to the package substrate 100 using hybrid bonding, direct bonding, conductive adhesive films, etc.

[0117] A molding layer ML may be disposed on the package substrate 100 and may surround the semiconductor chip 200. The side surfaces of the molding layer ML may be aligned (e.g., coplanar) with the side surfaces of the substrate layer 110 of the package substrate 100 in the vertical direction (e.g., the Z direction). The upper surface of the molding layer ML may be coplanar with the upper surface of the semiconductor chip 200. For example, the upper surface of the semiconductor chip 200 may be exposed to the outside.

[0118] In some embodiments, the molding layer ML may include epoxy resin, polyimide resin, etc. The molding layer ML may include, for example, an epoxy molding compound (EMC).

[0119] Figure 11 This is a schematic flowchart of the process of manufacturing a semiconductor package according to an embodiment, S100. Figures 12A to 12FThis is a cross-sectional view illustrating a method for manufacturing a semiconductor package in sequence according to an embodiment.

[0120] refer to Figure 11 The semiconductor package manufacturing method S100 may include: an operation S110 of mounting a semiconductor chip 200 on a second distribution structure 122 of a package substrate 100; an operation S120 of attaching a first connection terminal 140 to a first bump pad 130 of the package substrate 100; an operation S130 of forming a protective layer PL on a first distribution structure 131 of the package substrate 100; an operation S140 of forming a metal protective layer 150 on the first connection terminal 140; and an operation S150 of removing the protective layer PL.

[0121] refer to Figure 12A It can be used to prepare the packaging substrate 100.

[0122] The package substrate 100 may include: a substrate layer 110; a first distribution structure 121 located on a first surface 110_1 of the substrate layer 110; a second distribution structure 122 located on a second surface 110_2 of the substrate layer 110; a through-path 110_V passing through the substrate layer to electrically connect the first distribution structure 121 to the second distribution structure 122; a first bump pad 130 located below the lower surface of the first distribution structure 121; a second bump pad 160 located on the upper surface of the second distribution structure 122; a first passivation layer 130_P disposed below the lower surface of the first distribution structure 121 and surrounding the first bump pad 130, and including an opening overlapping the first bump pad 130 in a vertical direction (e.g., the Z direction); and a second passivation layer 160_P located on the upper surface of the second distribution structure 122 and surrounding the second bump pad 160.

[0123] The substrate layer 110 may include a first surface 110_1 and a second surface 110_2 opposite to the first surface 110_1. Depending on the orientation in which the substrate layer 110 is arranged, the first surface 110_1 of the substrate layer 110 may be referred to as the lower surface of the substrate layer 110, and the second surface 110_2 of the substrate layer 110 may be referred to as the upper surface of the substrate layer 110.

[0124] Figure 12B It shows Figure 11 The operation S110 involves mounting the semiconductor chip 200 onto the upper surface of the second distribution structure 122. (See reference...) Figure 12B The semiconductor chip 200 can be mounted on the packaging substrate 100 such that the chip pad 210 of the semiconductor chip 200 corresponds to the second bump pad 160 of the packaging substrate 100.

[0125] The chip pads 210 of the semiconductor chip 200 can be physically and electrically connected to the second bump pads 160 via chip connection terminals 220. The semiconductor chip 200 can be mounted on the substrate layer 110 in a downward orientation, such that the active surface of the semiconductor chip 200 faces the substrate layer 110.

[0126] Subsequently, a molding layer ML can be formed on the second surface 110_2 of the substrate layer 110 to surround (e.g., cover) the semiconductor chip 200. The upper part of the molding layer ML can be removed until the upper surface of the semiconductor chip 200 is exposed.

[0127] In embodiments of this disclosure, the semiconductor chip 200 may be mounted on the second distribution structure 122 before the first connection terminal 140 and the metal protective layer 150 are formed on the first bump pad 130. However, it is not limited to this. After the first connection terminal 140 and the metal protective layer 150 are formed on the first bump pad 130, the semiconductor chip 200 may be mounted on the second distribution structure 122.

[0128] Figure 12C It shows Figure 11 The operation S120 involves attaching the first connection terminal 140 to the substrate layer 110. (See reference...) Figure 12C The first connection terminal 140 can be attached to the first bump pad 130.

[0129] The first connection terminal 140 may include solder balls or solder bumps having a relatively low melting point. For example, the melting point of the first connection terminal 140 may be from about 140 degrees Celsius to about 180 degrees Celsius. For example, the first connection terminal 140 may include a solder alloy containing about 30% to about 60% Sn. For example, the first connection terminal 140 may include a tin-bismuth (Sn-Bi) based solder alloy.

[0130] For example, after the first connection terminal 140 is mounted on the first bump pad 130, the first connection terminal 140 can be attached to the first bump pad 130 by using a reflow process.

[0131] In some embodiments, when the first bump pad 130 comprises gold, during the process of attaching the first connection terminals 140 to the first bump pad 130 using a reflow process, the first connection terminals 140 may chemically react with the first bump pad 130. For example, the first connection terminals 140 may chemically react with the first bump pad 130, and a metal compound layer may be formed on the surface of the first connection terminals 140 (e.g., Figure 6The metal compound layer 145 in the middle). For example, the first connection terminal 140 can chemically react with the first bump pad 130, and the second surface 140'_2 of each first connection terminal 140 (e.g., Figure 6 A portion of the second surface 140'_2) may have corners.

[0132] Figure 12D It shows Figure 11 The operation S130 involves forming a protective layer PL on the first passivation layer 130_P. (See reference...) Figure 12D The protective layer PL can be formed on the upper surface of the first passivation layer 130_P.

[0133] The protective layer PL may cover the upper surface of the first passivation layer 130_P and a portion of the side surface of the first connection terminal 140. The protective layer PL may include an ultraviolet (UV) band. For example, the thickness of the protective layer PL may be from approximately 30 μm to approximately 150 μm.

[0134] Figure 12E It shows Figure 11 Operation S140 involves forming a metal protective layer 150 on the first connection terminal 140. (See reference...) Figure 12E It can be on the second surface of the first connection terminal 140 (e.g., Figure 2 A metal protective layer 150 is formed on the second surface 140_2.

[0135] A metal protective layer 150 may be formed on the exposed surface of each first connection terminal 140. The metal protective layer 150 may be formed on the surface of each first connection terminal 140 such that the thickness of the metal protective layer 150 is approximately 3 μm to approximately 10 μm.

[0136] In some embodiments, when the protective layer PL contacts the first connection terminal 140, the metal protective layer 150 is not formed on the portion of the surface of the first connection terminal 140 that contacts the protective layer PL. For example, when the protective layer PL contacts a portion of the side surface of the first connection terminal 140, the metal protective layer 150 may be separated from the upper surface of the first passivation layer 130_P in the vertical direction (e.g., the Z direction). For example, when the protective layer PL contacts the side surface of the first connection terminal 140, the protective layer may be disposed between the metal protective layer 150 and the first passivation layer 130_P.

[0137] The melting point of the metal protective layer 150 may be higher than that of the first connecting terminal 140. The melting point of the metal protective layer 150 may be from approximately 200 degrees Celsius to approximately 240 degrees Celsius. The metal protective layer 150 may comprise from approximately 96% to approximately 99% by weight Sn. The metal protective layer 150 may comprise a tin-silver-copper (SAC) based solder alloy. The hardness of the metal protective layer 150 may be greater than that of the first connecting terminal 140. The tensile strength of the metal protective layer 150 may be greater than that of the first connecting terminal 140.

[0138] In some embodiments, when a metal compound layer is formed on the surface of the first connection terminal 140 (e.g., Figure 6 When the metal compound layer 145 is in place, the metal protective layer 150 can be formed to cover the metal compound layer 145 on the first connection terminal 140. For example, such as Figure 6 As shown, the metal compound layer 145 can be covered by the metal protective layer 150 and may not be exposed to the outside. The metal compound layer 145 may be disposed between the metal protective layer 150 and the first connection terminal 140.

[0139] The reflectivity of each metal protective layer 150 and each first connection terminal 140 can be less than the reflectivity of each metal compound layer 145. For example, when the same light is incident, each metal protective layer 150 can reflect less light than each metal compound layer 145.

[0140] In some embodiments, a metal protective layer 150 can be formed on the surface of the first connection terminal 140 using a sputtering process. In some embodiments, the metal protective layer 150 can be conformally formed on the exposed surface of the first connection terminal 140. In some embodiments, the thickness of the metal protective layer 150a can increase with distance from the first passivation layer 130_P.

[0141] Figure 12F It shows Figure 11 The operation S150 involves removing the protective layer PL. (Refer to...) Figure 12F The protective layer PL can be removed from the substrate layer 110.

[0142] In some embodiments, the protective layer PL can be removed from the first passivation layer 130_P without damaging the first passivation layer 130_P and the first connection terminal 140 by irradiating the protective layer PL with ultraviolet light to weaken the adhesion of the protective layer PL.

[0143] In some embodiments, when the protective layer PL contacts a portion of the side surface of each first connection terminal 140, and the protective layer PL is removed from the first passivation layer 130_P, as... Figure 4As shown, a gap G can be formed between each metal protective layer 150 and the first passivation layer 130_P.

[0144] Figure 13 This is a schematic flowchart of the process of the test method S1000 for semiconductor packages according to an embodiment. Figure 14A and Figure 14B This is a diagram illustrating a portion of the testing method S1000 for a semiconductor package according to an embodiment. Figure 15 This is a cross-sectional view showing a portion of a test method S1000 for a semiconductor package according to an embodiment.

[0145] refer to Figure 13 The semiconductor package testing method S1000 may include: operation S100' of manufacturing a semiconductor package 1000 including a metal protective layer 150; operation S200 of performing an appearance test on the semiconductor package 1000 using an imaging device Ca (e.g., a sensor, such as a camera); and operation S300 of performing an aging test on the semiconductor package 1000 using an aging tester BT.

[0146] Operation S100' of manufacturing a semiconductor package 1000 including a metal protective layer 150 may include, according to the above reference... Figures 12A to 12F The described semiconductor package manufacturing method S100 is an operation for manufacturing a semiconductor package 1000.

[0147] Figure 14A and Figure 14B It shows Figure 13 The operation S200 involves performing an appearance test on the semiconductor package 1000 using the imaging device Ca. (See reference...) Figure 14A and Figure 14B The device can perform an appearance test on the semiconductor package 1000. For example, the appearance of the semiconductor package 1000 can be photographed using an imaging device Ca, and it can be confirmed whether the semiconductor package 1000 is abnormal. For example, the imaging device Ca may include part of an automated vision (AVI) system.

[0148] In some embodiments, the imaging device Ca can photograph the first connection terminal 140 of the semiconductor package 1000. For example, by photographing the lower part of the semiconductor package 1000, it can be identified whether the first connection terminal 140 has detached from or is missing from the first bump pad 130. The imaging device Ca can also photograph the first connection terminal 140 disposed on the first surface 110_1 of the substrate layer 110 of the semiconductor package 1000. Subsequently, the photograph taken by the imaging device Ca can be used to identify whether the first connection terminal 140 is attached to the first bump pad 130.

[0149] refer to Figure 6The first connection terminal 140 and the first bump pad 130, both having relatively low melting points, can chemically react with each other, and a metal compound layer 145 can be formed on the surface of the first connection terminal 140. Therefore, the metal compound layer 145 can be photographed using imaging equipment Ca without the presence of a metal protective layer 150. The reflectivity of the metal compound layer 145 can be higher than that of the metal protective layer 150 and the first connection terminal 140.

[0150] For example, the imaging device Ca can determine the location where the metal compound layer 145 is not attached by photographing the large amount of light reflected by the metal compound layer 145, and can determine the semiconductor package 1000 where the first connection terminal 140 is properly attached as a defective product. Therefore, when performing an appearance test on the semiconductor package of the comparative embodiment without the metal protective layer 150, it is difficult to confirm whether the first connection terminal 140 is properly attached to the first bump pad 130 due to the metal compound layer 145.

[0151] In the case where the semiconductor package 1000 includes a metal protective layer 150 with a reflectivity lower than that of the metal compound layer 145, the metal compound layer 145 can be covered by the metal protective layer 150 and is not exposed to the outside. Therefore, even when the appearance of the semiconductor package 1000 is photographed using imaging equipment Ca, the metal protective layer 150 reflects relatively little light, thus confirming whether the first connection terminal 140 is properly attached to the first bump pad 130. Therefore, by using the metal protective layer 150, the reliability of the appearance test of the semiconductor package 1000 can be improved.

[0152] Figure 15 The operation S300 of performing an aging test on a semiconductor package 1000 using an aging tester BT is shown. The aging test can test the performance of the semiconductor package 1000 under high-temperature environmental conditions. For example, the test temperature for performing the aging test can be approximately 125 degrees Celsius.

[0153] The aging tester BT may include an aging board BB and a slot S, which is mounted on the aging board BB and includes a semiconductor package 1000 mounted thereon. When the semiconductor package 1000 is mounted on the slot S, the slot S may include pins SP electrically connected to the semiconductor package 1000. However, the slot S may include spring pins or clamps instead of pins SP.

[0154] In the semiconductor package of the comparative embodiment without the metal protective layer 150, the first connection terminal 140, having a relatively low melting point, can directly contact the socket S. Therefore, some of the first connection terminals 140 may melt at the test temperature during the aging test and may contaminate the socket S.

[0155] In the semiconductor package 1000 of the embodiments of this disclosure, the first connection terminal 140 may be located inside the metal protective layer 150 with a melting point higher than that of the first connection terminal 140. Therefore, the first connection terminal 140 will not directly contact the slot S. Thus, even if the first connection terminal 140 melts, contamination of the slot S can be suppressed.

[0156] In a comparative embodiment of the semiconductor package without a metal protective layer 150, the flexible first connection terminal 140, due to its relatively low hardness and tensile strength, may come into direct contact with the pins SP of the socket S. Therefore, cracks and scratches may appear on the surface of the first connection terminal 140 during aging tests.

[0157] In the semiconductor package 1000 of the embodiments of this disclosure, a metal protective layer 150, which is relatively harder than the first connection terminal 140 due to its higher hardness and tensile strength, can surround the first connection terminal 140 and can suppress and prevent scratches and cracks from appearing on the first connection terminal 140. Because fewer scratches and cracks appear on the surface of the metal protective layer 150, which is relatively harder than the first connection terminal 140, the reliability of the semiconductor package 1000 can be improved when it is attached to an external device.

[0158] Figure 16 This is a cross-sectional view of the semiconductor package 2000 according to an embodiment.

[0159] refer to Figure 16 The semiconductor package 2000 may include a package substrate 100, a main substrate 300 configured to mount the package substrate 100, a semiconductor chip 200 configured to mount on the package substrate 100, and a molding layer ML.

[0160] The semiconductor package 2000 may further include: a substrate connection terminal 140_R that electrically connects the package substrate 100 and physically connects it to the main substrate 300; a metal protective layer fragment 150_P disposed inside the substrate connection terminal 140_R; and a chip connection terminal 220 that electrically connects the package substrate 100 and physically connects it to the semiconductor chip 200.

[0161] The main substrate 300 may include external means for mounting the package substrate 100 thereon. The main substrate 300 may include substrate bump pads 310 on its upper surface (e.g., in or on its upper surface), and may also include an internal distribution of electrically connected substrate bump pads 310. For example, various semiconductor devices other than the package substrate 100 may be mounted on the main substrate 300. The main substrate 300 can electrically connect the package substrate 100 to the semiconductor devices mounted on the main substrate 300.

[0162] The packaging substrate 100 disposed on the upper surface of the main substrate 300 may include a substrate layer 110, a first distribution structure 121, a second distribution structure 122, a through path 110_V, a first bump pad 130, a second bump pad 160, a first passivation layer 130_P, and a second passivation layer 160_P.

[0163] Most of the components of the packaging substrate 100 and the materials constituting the components may be substantially the same as or similar to the components and materials described above. Therefore, for ease of description, repeated descriptions are unnecessary.

[0164] The substrate connection terminal 140_R can be disposed between the substrate bump pad 310 of the main substrate 300 and the first bump pad 130 of the package substrate 100. In some embodiments, the metal protective layer fragment 150_P can be disposed in the substrate connection terminal 140_R.

[0165] The melting point of each metal protective layer fragment 150_P may be higher than the melting point of each substrate connection terminal 140_R. The tensile strength and hardness of each metal protective layer fragment 150_P may be higher than the tensile strength and hardness of each substrate connection terminal 140_R. For example, each substrate connection terminal 140_R may include approximately 30% to approximately 60% Sn, while each metal protective layer fragment may include approximately 95% to approximately 99% Sn.

[0166] After applying low-melting-point solder paste to the substrate bump pads 310 of the main substrate 300, heat can be applied to the package substrate 100 on which first connection terminals (e.g., first connection terminals 140 in FIG. 1) and a metal protective layer (e.g., metal protective layer 150 in FIG. 1) are formed, and the package substrate 100 can be attached to the main substrate 300. For example, by applying a reflow process, the low-melting-point solder paste on the substrate bump pads 310 of the main substrate 300, the first connection terminals of the package substrate 100, and the metal protective layer can be fused together. The fused low-melting-point solder paste, the first connection terminals, and the metal protective layer can be referred to as substrate connection terminals 140_R.

[0167] For example, during the application of heat to the package substrate 100, the metal protective layer (e.g., metal protective layer 150 in FIG. 1) may diffuse, melt, and disappear into the first connection terminal (e.g., first connection terminal 140 in FIG. 1). However, embodiments of this disclosure are not limited thereto, and in some embodiments, some metal protective layers may not diffuse with the first connection terminal to maintain their shape, and thus may become metal protective layer fragments 150_P.

[0168] The semiconductor chip 200 can be located on the second distribution structure 122 of the packaging substrate 100. Chip connection terminals 220 can be arranged between the semiconductor chip 200 and the packaging substrate 100. Each chip connection terminal 220 can be arranged between the second bump pad 160 of the packaging substrate 100 and the chip pad 210 of the semiconductor chip 200.

[0169] In some embodiments, the weight ratio of Sn included in each chip connection terminal 220 may be less than the weight ratio of Sn included in each substrate connection terminal 140_R.

[0170] A molding layer ML may be disposed on the package substrate 100 and may surround the semiconductor chip 200. The side surfaces of the molding layer ML may be aligned (e.g., coplanar) with the side surfaces of the substrate layer 110 of the package substrate 100 in the vertical direction (e.g., the Z direction). The upper surface of the molding layer ML may be coplanar with the upper surface of the semiconductor chip 200. For example, the upper surface of the semiconductor chip 200 may be exposed to the outside.

[0171] Although non-limiting exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging substrate, the packaging substrate comprising: A substrate layer, the substrate layer including a first surface and a second surface opposite to the first surface; A through-path extending from the first surface of the substrate layer to the second surface of the substrate layer; A first distribution structure is located on the first surface of the substrate layer and includes a first distribution pattern and a first interlayer insulating layer surrounding the first distribution pattern; The first bump pad is located on and connected to the first distribution pattern of the first distribution structure. The first bump pad is spaced apart from the substrate layer. The first distribution structure is located between the first bump pad and the substrate layer. A first passivation layer is located on the first distribution structure and surrounds the first bump pad, the first passivation layer including an opening that overlaps with the first bump pad in a vertical direction; a first connection terminal located on the first side of the substrate and on the first bump pad a passivation layer in the opening of the passivation layer and on the first bump pad, the first connection terminal comprising tin, and a melting point of the first connection terminal being a first temperature; as well as A metal protective layer, located on the surface of the first connection terminal, comprising tin, and having a melting point at a second temperature. Wherein, the first temperature is lower than the second temperature.

2. The packaging substrate according to claim 1, wherein, The first connecting terminal has a first hardness, and The metal protective layer has a second hardness greater than the first hardness.

3. The packaging substrate according to claim 1, wherein, The first connecting terminal has a first tensile strength, and The metal protective layer has a second tensile strength greater than the first tensile strength.

4. The packaging substrate according to claim 1, wherein, The first connection terminal comprises 30% to 60% tin, and The metal protective layer comprises 95% to 99% tin.

5. The packaging substrate according to claim 1, wherein, The thickness of the metal protective layer is 3 μm to 10 μm.

6. The packaging substrate according to claim 5, wherein, The maximum width of the first connection terminal is 100μm to 600μm.

7. The packaging substrate according to claim 1, wherein, The metal protective layer is conformally disposed on the surface of the first connection terminal that does not contact the first bump pad or the first passivation layer.

8. The packaging substrate according to claim 1, wherein, The thickness of the metal protective layer increases in the direction away from the first passivation layer.

9. The packaging substrate according to claim 1, wherein, The metal protective layer is spaced apart from the first bump pad in the vertical direction, and a gap exists between the metal protective layer and the first bump pad in the vertical direction. A portion of the first connection terminal is exposed to the outside through the gap.

10. The packaging substrate according to claim 9, wherein, The thickness of the metal protective layer increases in the direction away from the first passivation layer.

11. The packaging substrate according to claim 1, wherein, The first temperature is between 140 degrees Celsius and 180 degrees Celsius, and The second temperature is between 200 and 240 degrees Celsius.

12. The packaging substrate according to claim 1, wherein, The width of the opening in the first passivation layer is smaller than the horizontal width of the first bump pad, and The opening is defined by the sidewall of the first passivation layer, and the sidewall contacts the first connection terminal.

13. A packaging substrate, the packaging substrate comprising: A substrate layer, the substrate layer including a first surface and a second surface opposite to the first surface; A through-path extending from the first surface of the substrate layer to the second surface of the substrate layer; A first distribution structure is located on the first surface of the substrate layer and includes a first distribution pattern and a first interlayer insulating layer surrounding the first distribution pattern; The first bump pad is located on and connected to the first distribution pattern of the first distribution structure. The first bump pad is spaced apart from the substrate layer. The first distribution structure is located between the first bump pad and the substrate layer. A first passivation layer is located on the first distribution structure and surrounds the first bump pad, the first passivation layer including an opening that overlaps with the first bump pad in a vertical direction; A first connection terminal is located in the opening of the first passivation layer and on the first bump pad, the first connection terminal comprising tin and having a first hardness; A metal compound layer is located on the surface of the first connection terminal; as well as A metal protective layer is located on the surface of the first connecting terminal and the metal compound layer, and has a second hardness greater than the first hardness. The melting point of the first bump pad is lower than that of the metal protective layer.

14. The packaging substrate according to claim 13, wherein, The reflectivity of the metal protective layer is less than that of the metal compound layer.

15. The packaging substrate according to claim 13, wherein, The metal compound layer is located between the first connection terminal and the metal protective layer.

16. The packaging substrate according to claim 15, wherein, The metal protective layer is located on the metal compound layer, so that the metal compound layer is not exposed to the outside.

17. The packaging substrate according to claim 13, wherein, The metal protective layer is separated from the first bump pad in the vertical direction, and a gap exists between the metal protective layer and the first bump pad in the vertical direction. A portion of the first connection terminal is exposed to the outside through the gap.

18. The packaging substrate according to claim 17, wherein, A portion of the metal compound layer is exposed to the outside through the gap.

19. The packaging substrate according to claim 13, wherein, The portion of the surface of the first connecting terminal that does not contact the substrate layer has corners.

20. A semiconductor package, the semiconductor package comprising: A packaging substrate, the packaging substrate comprising: a substrate layer including a first surface and a second surface opposite to the first surface; a first distribution structure located on the first surface of the substrate layer; a second distribution structure located on the second surface of the substrate layer; a through-path penetrating the substrate layer and connecting the first distribution structure to the second distribution structure; a first bump pad located below the lower surface of the first distribution structure; a second bump pad located on the upper surface of the second distribution structure; and a first passivation layer surrounding the first bump pad and including openings overlapping the first bump pad in a vertical direction. A main substrate, wherein the packaging substrate is located on the upper surface of the main substrate, and the main substrate includes substrate bump pads located on the upper surface of the main substrate. A substrate connection terminal is located between the package substrate and the main substrate and is configured to electrically connect and physically connect the first bump pad of the package substrate to the substrate bump pad of the main substrate, wherein the melting point of the substrate connection terminal is a first temperature. Metal protective layer fragments, the metal protective layer fragments being located inside the substrate connection terminals, and the melting point of the metal protective layer fragments being a second temperature higher than the first temperature; A semiconductor chip, the semiconductor chip being located on the upper surface of the second distribution structure of the packaging substrate; A chip connection terminal, located between the packaging substrate and the semiconductor chip, and configured to electrically connect and physically connect the second bump pad of the packaging substrate to the chip pad of the semiconductor chip; and A molding layer is located on the packaging substrate and surrounds the semiconductor chip.

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