Substrate and method of embedding semiconductor die

Abstract

The invention relates to a substrate and a method of embedding a semiconductor die. Particular implementations of a substrate may include: a semiconductor material; a redistribution layer coupled to the first largest planar surface of the semiconductor material; and a hollow through-hole extending completely through the thickness of the semiconductor material from the second largest planar surface of the semiconductor material, the hollow through-hole being directly coupled with the redistribution layer.

Description

Technical Field

[0001] This document covers semiconductor packaging in general. More specific implementations relate to power semiconductor packaging. Background Technology

[0002] Semiconductor packages are designed to provide mechanical support and protection for one or more semiconductor dies included within the package. Other semiconductor packages are used to prevent damage to the semiconductor die from electrostatic discharge. Still other semiconductor packages are used to help prevent damage to the semiconductor die included within the package from shock, vibration, or humidity. Summary of the Invention

[0003] A specific embodiment of a substrate may include: a semiconductor material; a redistribution layer coupled to a first maximum planar surface of the semiconductor material; and a hollow via extending completely through the thickness of the semiconductor material from a second maximum planar surface, the hollow via being directly coupled to the redistribution layer.

[0004] The substrate may be implemented in one, all, or any of the following ways: The redistribution layer may include at least one thick copper layer.

[0005] The redistribution layer may include at least one dielectric layer and at least one layer of either a solderable metal or a sinterable metal.

[0006] Semiconductor materials can be made thinner from their initial thickness.

[0007] The semiconductor material can be silicon carbide.

[0008] The semiconductor material can be silicon.

[0009] The substrate may include an oxide layer between the redistribution layer and the semiconductor material.

[0010] The substrate may include an oxide layer located on the second largest planar surface of the semiconductor material.

[0011] The substrate may include a back metal layer coupled to a second maximum planar surface of the semiconductor material.

[0012] Specific implementations of a method for embedding a semiconductor die may include: providing a silicon substrate having a first oxide layer thereon; forming at least one opening in the first oxide layer; etching a cavity into the silicon substrate at the at least one opening in the first oxide layer; forming a second oxide layer in the cavity; forming a thick copper layer on the first oxide layer and on the second oxide layer; and patterning a hard copper layer. The method may include: sintering at least one semiconductor die to the thick copper layer in the cavity; filling the gap between the at least one semiconductor die and the thick copper layer in the cavity with polyimide; forming a photosensitive polymer layer over the at least one semiconductor die, the thick copper layer, and the first oxide layer; and patterning the photosensitive polymer layer to form a plurality of openings therein. The method may include: forming a first copper layer in the plurality of openings; and forming a second copper layer over the photosensitive polymer layer and the first copper layer.

[0013] Specific implementations of the method for embedding semiconductor dies may include one, all, or any of the following: The formation of the first copper layer and the formation of the second copper layer can occur simultaneously.

[0014] The method may include forming a seed layer on a second oxide layer prior to forming a thick copper layer.

[0015] The method may include baking the polyimide.

[0016] The method may include coupling one of the redistribution layer or another semiconductor die to a second copper layer.

[0017] Specific implementations of a method for embedding a semiconductor die may include: providing a silicon substrate having an oxide layer thereon; forming a thick copper layer on the oxide layer; patterning the thick copper layer; applying a first photosensitive polyimide over the thick copper layer; and patterning the first photosensitive polyimide to form an opening therein. The method may include: performing one of the following in the opening: sintering or bonding the semiconductor die; forming the first copper layer on the first photosensitive polyimide and the semiconductor die; and applying a second photosensitive polyimide over the first copper layer. The method may also include: patterning the second photosensitive polyimide; forming a second copper layer on the second photosensitive polyimide; and coupling a redistribution layer or another semiconductor die to the second copper layer.

[0018] Specific implementations of the method for embedding semiconductor dies may include one, all, or any of the following: The method may include forming a seed layer on an oxide layer before forming a thick copper layer.

[0019] The method may include filling the space around the semiconductor die with polyimide before forming the first copper layer.

[0020] Forming the first copper layer may also include simultaneously forming vias and traces.

[0021] Forming the first copper layer may also include first forming vias and then forming traces.

[0022] Forming a second copper layer may also include one of the following: simultaneously forming vias and traces; or first forming vias and then forming traces.

[0023] The above and other aspects, features and advantages will become apparent to those skilled in the art from the detailed description and accompanying drawings, as well as from the claims. Attached Figure Description

[0024] Specific embodiments will be described below in conjunction with the accompanying drawings, in which similar reference numerals denote similar elements, and: Figure 1 This is a cross-sectional view of a specific implementation of a silicon substrate; Figure 2 It has a redistribution layer formed on it. Figure 1 A cross-sectional view of a silicon substrate; Figure 3 It has a redistribution layer and a back metal layer formed on it. Figure 1 A cross-sectional view of a silicon substrate; Figure 4 It is a perspective view of a silicon substrate mounted to a frame, a set of silicon substrates packaged in a shipping package for shipment, and a cross-sectional view of a set of silicon substrates arranged in a shipping package. Figure 5 This is a cross-sectional view of a specific implementation of a silicon substrate; Figure 6 It is after a redistribution layer forms on it. Figure 5 A cross-sectional view of a silicon substrate; Figure 7 This occurs after the hollow through-hole is formed. Figure 6 A cross-sectional view of a silicon substrate; Figure 8 This is a cross-sectional view of a specific implementation of a silicon substrate; Figure 9 It lies in the formation of a cavity within it and the subsequent formation of a thick copper layer thereon. Figure 8 A cross-sectional view of a silicon substrate; Figure 10 This occurs after the semiconductor die is coupled into the cavity and sintered. Figure 9 A cross-sectional view of a silicon substrate; Figure 11 It lies in the patterned photosensitive polymer layer on top of it. Figure 10 A cross-sectional view of a silicon substrate; Figure 12 It is after the second copper layer is formed on it. Figure 11 A cross-sectional view of a silicon substrate; Figure 13 This is a cross-sectional view of a specific implementation of a silicon substrate; Figure 14 It is after a patterned thick copper layer is formed on it. Figure 13 A cross-sectional view of a silicon substrate; Figure 15 It is due to the formation of a patterned photosensitive polyimide layer on it. Figure 14 A cross-sectional view of a silicon substrate; Figure 16 It is the process of sintering a patterned thick copper layer onto a semiconductor die. Figure 15 A cross-sectional view of a silicon substrate; Figure 17 This occurs after the interconnects adjacent to the semiconductor die are formed. Figure 16 A cross-sectional view of the silicon substrate; and Figure 18 This is after the formation of a second patterned photosensitive polyimide layer and a second copper layer on top. Figure 17 A cross-sectional view of a silicon substrate. Detailed Implementation

[0025] This disclosure, its aspects, and specific embodiments are not limited to the specific components, assembly processes, or methodological elements disclosed herein. Many additional components, assembly processes, and / or methodological elements known in the art for the intended power semiconductor package will be readily apparent and can be used with specific embodiments of this disclosure. Therefore, for example, although specific embodiments are disclosed, such embodiments and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, methodological element, step, etc., known in the art for such power semiconductor package and implementation components and methods, conforming to the intended operation and methods.

[0026] Power semiconductor packages typically include a substrate to which one or more semiconductor dies are attached. The substrate includes traces for routing electrical signals and dielectric or other non-conductive / insulating layers that help electrically isolate the layer including the traces from other package components, circuit boards, or other motherboards to which the power semiconductor package is attached. Examples of substrates are direct-bonded copper (DBC) substrates, which may contain a single copper layer bonded to an electrically insulating layer or two copper layers bonded to each largest planar side of the electrically insulating layer. One challenge among many substrate types is that the coefficients of thermal expansion differ between the material of the electrically insulating layer and the material of the one or more semiconductor dies bonded to the substrate. Furthermore, the need for good thermal properties that allow one or more semiconductor dies to be cooled during operation (especially when the die is a power semiconductor die) may also limit the type of electrically insulating material that can be used. Finally, the cost of the material used for the electrically insulating material may be high enough that the higher thermal properties of the material may be offset by the total cost. For example, alumina (Al₂O₃) has a relatively low cost and a thermal conductivity of 25 W / m*K. In contrast, aluminum nitride (AlN) is expensive and has a much higher thermal conductivity of 170 W / m*K. Silicon nitride (Si3N4) substrates are also expensive, but have a thermal conductivity of 90 W / m*K. HPS substrates (alumina doped with ZrO2) are more expensive than alumina itself and have a similar thermal conductivity of 25 W / m*K, but offer better reliability. Direct-bonded copper substrates with an electrically insulating layer made of any of the aforementioned materials do exhibit high current carrying capacity, high breakdown voltage, and high thermal conductivity compared to other insulators, but are considerably more expensive.

[0027] This document discloses the use of silicon combined with an oxide layer or other electrically insulating material layer thereon as a material for an electrically insulating layer in a substrate. Given its large-scale availability and low cost, silicon is now used as the primary substrate for a variety of semiconductor dies. Silicon has a higher thermal conductivity than alumina (120 W / m*K) and a substantially similar coefficient of thermal expansion to that of semiconductor dies using silicon as their substrate material. The coefficient of thermal expansion of silicon is also close to that of semiconductor dies using silicon carbide as their substrate material. Silicon can also provide reasonably high breakdown voltages when the oxide / other electrically insulating material layer is sufficiently thick. Other advantages of using silicon include the ability to embed dies using a variety of existing silicon manufacturing processes, and a wide selection of solderable or sinterable metals for forming conductive layers on the front or back side of the silicon layer. While the various embodiments disclosed herein involve the use of silicon as a substrate, these embodiments can also be used as interposers in a variety of packaging designs, thereby leveraging silicon interposers to help construct the three-dimensional structure of semiconductor packages in combination with other substrate types.

[0028] refer to Figure 1An embodiment of a silicon substrate 2 having an oxide (SiO2 in this specific embodiment) layer 4 thereon is illustrated. The silicon substrate 2 can be a full-thickness substrate, meaning its thickness typically varies with the substrate size. For example, a silicon substrate with a diameter of 300 mm would have a thickness between about 775 micrometers and about 925 micrometers, determined by the need to prevent excessive sagging or warping of the substrate during ordinary semiconductor processing operations. However, in various embodiments, the silicon substrate can be a thinned substrate, meaning its thickness is less than what is typically determined for its size. The oxide layer can be thick to help ensure the desired breakdown voltage of the silicon substrate is achieved. In various embodiments, the oxide layer thickness can be between about 0.1 micrometers and about 5 micrometers. Low-voltage applications of tens of volts allow for the use of oxide layers near the lower end of the thickness range, while applications at very high voltages exceeding 2000 V can employ oxide layer thicknesses at the upper end of that range. While the use of oxide layers is illustrated herein, in various specific implementations, other dielectric materials (such as spin-coated glass, low-k dielectric materials, nitrides, borosilicate glass (BPSG), organic dielectrics, polyimide, benzocyclobutene, combinations of Si3N4 and SiO2, metal oxides, tantalum oxide, hafnium oxide, aluminum oxide, or any other dielectric material, as non-limiting examples) may be used to achieve the desired breakdown voltage.

[0029] refer to Figure 2 This illustrates the effect after a redistribution layer 6 is formed on it. Figure 1 The silicon substrate 2. The formation process of the redistribution layer includes initially forming thick copper traces 8 on the oxide layer 4. In various embodiments, the thickness of these thick copper traces may be between about 12 micrometers and about 35 micrometers. In various embodiments, the process of forming the thick copper traces 8 includes applying a copper adhesion layer to the oxide layer 4. As a non-limiting example, the copper adhesion layer may include one or more tantalum layers, titanium layers, titanium nitride layers, titanium tungsten layers, chromium layers, any combination thereof, or other material layers designed to promote adhesion of the thick copper traces 8 to the oxide layer 4. In various embodiments, sputtering, chemical vapor deposition, or electroless deposition may be used to form the adhesion layer. In various embodiments, a copper seed layer is applied on the copper adhesion layer. In various embodiments, sputtering, electroless deposition, or electroplating may be used to form the copper seed layer.

[0030] After the copper seed layer is formed, the surface is now ready to form a thick copper layer, from which the thick copper traces are formed. The thick copper layer can be formed using electroplating, lamination, sputtering, or evaporation processes. However, in some embodiments, without using a seed layer, copper foil can be applied / bonded / adhered / sintered / soldered to an adhesion layer, where the copper foil has the desired thickness. After forming the thick copper layer, a patterned layer is formed on top of the thick copper layer using photolithography, screen printing, stencil printing, dispensing, or another process that forms a trace pattern on the thick copper layer. The thick copper layer is then etched to form the thick copper traces 8 (the patterned trace layer). In other method embodiments, the use of a patterned layer may be omitted, and milling, laser cutting, or waterjet cutting can be used instead to form the thick copper traces 8. In the case of using a laser, a protective layer can be placed on top of the thick copper layer to help protect the resulting thick copper traces 8 from slag generated during the laser process. A washing process is then used to remove the protective layer to remove the slag and expose the thick copper traces 8.

[0031] While the use of thick copper has been illustrated so far, the use of aluminum for forming thick traces is also possible. Aluminum can also be formed using any of the processes described previously, consistent with the deposition of aluminum on the corresponding surface of the oxide layer or trace. The corresponding aluminum removal process can include any of the methods described previously, consistent with aluminum removal.

[0032] After forming the thick copper trace 8, a dielectric material 10 is applied over the thick copper trace 8. A wide variety of materials can be used, including, as non-limiting examples, spin-coated glass, BPSG, polyimide, photodefined polyimide, photodefined polymer, low-k dielectric materials, silicon dioxide, silicon oxynitride, any combination thereof, or any other type of dielectric material capable of covering the thick copper trace 8 and forming a generally flat surface. Processes used to form the dielectric material may include lamination, spraying, curtain coating, or spin coating, depending on the specific material used. In some implementations, a planarization process may be used on the dielectric material 10 to planarize the surface after the dielectric material 10 is applied / formed thereon. After applying / forming the dielectric material 10, a set of openings 12, 14 are formed in the dielectric material 10. If the dielectric material 10 is a photodefined polymer, a photolithography process can be used to directly produce the openings 12, 14. If the dielectric material is not optically definable, in some embodiments, a patterned layer is formed on the dielectric material 10 and an etching process is used to create the openings 12, 14. In yet another embodiment, a laser or waterjet cutting process may be used to form / mill the openings 12, 14 in the dielectric material 10.

[0033] After forming openings 12 and 14, a conductive material is used to fill the openings 12 and 14 to form a second set of traces 16 with corresponding vias 18. In some embodiments, the conductive material may be copper, and a planar process may be used to simultaneously form the vias 18 and the second set of traces 16. In other embodiments, the vias 18 may be formed first, and then a patterning process may be used to form the traces, similar to the patterning process used to form thick copper traces 8 using a non-planar process. In various embodiments, other metals including gold, silver, aluminum, gold alloys, silver alloys, aluminum alloys, copper, copper alloys, or any combination thereof may be used. In various embodiments, additional layers of traces and vias may also be formed to form an interconnect stack that produces a redistributed layer consisting of layers of conductive and non-conductive materials. The resulting layer allows electrical signals to move from the thick copper layer 8 to the second set of traces 16 and vice versa, depending on how the substrate is electrically connected to one or more semiconductor dies. In various specific implementations, a metal cap containing cobalt or another metal / metal stack designed to prevent copper from diffusing into the organic dielectric material can be used. Figure 2 The resulting substrate 26 is illustrated.

[0034] Figure 3 An example is shown of a silicon substrate 2 after another oxide layer 20 and a back metal layer 22 have been formed thereon. In this embodiment, the silicon substrate 2 has been thinned using grinding, polishing, or other thinning processes, and an oxide layer 20 has been formed therein. The material of the oxide layer 20 can be any dielectric material compatible with the back metal material disclosed herein. The back metal layer 22 may include one or more metal layers, and in various embodiments may include an adhesion layer. In some embodiments, if the back metal layer 22 is electroplated, a seed layer may also be present.

[0035] The resulting substrates / interposers 24 and 26 are now ready for use in a variety of semiconductor package types, which, as non-limiting examples, may include power modules, integrated power modules, leaded packages, leadless packages, inverters, power conversion equipment, or any other semiconductor package type employing a substrate or interposer. These packages may be single-sided or double-sided cooled. In various semiconductor package implementations, a heat sink may also be coupled to the back metal layer 22. Furthermore, substrates 24 and 26 can be used in wafer-level packaging operations, where they are diced together with one or more semiconductor dies to which they have been bonded. Substrates 24 and 26 can also be used in chip-level packaging operations, where substrates 24 and 26 have been diced into smaller portions having semiconductor dies attached to them. Where substrates 24 and 26 have been pre-diced to the desired size, substrates 24 and 26 can be used in chip-level packaging processes where no further dicing of substrates 24 and 26 is performed.

[0036] Either substrate 24 or 26, formed at the substrate / panel / wafer level, can be stored and transported to a subsequent location for additional processing. (Reference) Figure 4 The substrate 28 in the form of a silicon wafer has been mounted onto the frame 30 using the dicing tape 32. Since the substrate 28 is mounted onto the frame 30, a certain number of substrates can be packaged into the shipping package 34. Figure 4 The figure on the right shows a cross-sectional view of the contents of a shipping package 34 comprising a stack of 25 frames with 26 interlayers between the frames to prevent contact between the dicing tape and the top side of each substrate, and six foam spacers 36 at the top and bottom to ensure the frames do not move. A wide variety of shipping techniques, shipping packages, and other transport systems can be employed when shipping substrates, as disclosed herein, to other locations for additional semiconductor packaging operations.

[0037] refer to Figure 5 Another specific embodiment of a silicon substrate 38 having an oxide layer 40 thereon is illustrated. Figure 6 Examples of using and Figures 1 to 3 The silicon substrate 38 is formed after a redistribution layer 42 is formed thereon, similar to those thick copper traces 44 and second set of traces 46 illustrated in the specific embodiment of the substrate. At this point, the substrate 38 is ready for additional processing. This processing begins by thinning the material of the substrate 38 to a desired thickness using any thinning process disclosed herein. After thinning, an oxide (or other dielectric material disclosed herein) layer 48 is grown / formed on a second maximum planar surface 50 of the substrate 38, opposite to a first maximum planar surface 52 on which the redistribution layer 42 has already been formed. The oxide layer 48 is then patterned by forming a patterned layer on the oxide layer 48 using photolithography or other patterning processes disclosed herein, and the oxide layer 48 is etched to expose the material of the silicon substrate 38. Figure 7 In the illustrated embodiment, a second patterning layer is then formed, which outlines the location of the through-silicon via 54 before etching. As illustrated, the through-silicon via 54 is etched to have sloping sidewalls that create a larger opening on the second maximum planar side 50 of the silicon substrate 38 and a narrower opening where the through-silicon via 54 meets the thick copper trace 44. This etching with sloping sidewalls can be achieved using appropriate adjustments to the etching chemistry and chamber conditions, and the thick copper trace 44 acts as an etching stop for the through-silicon via 54.

[0038] After etching the silicon, a copper adhesion layer comprising any of the materials previously disclosed in this document is applied. In some embodiments, a copper barrier layer may also be formed into the through-silicon via 54 and the exposed silicon. In various embodiments, the copper barrier layer may comprise nickel or nickel-vanadium. In some method embodiments, a seed layer is then applied over the barrier layer. In other method embodiments, a thick copper layer 56 is then electroplated into the through-silicon via 54 and over other exposed areas of the silicon to form traces 58. The thickness of the thick copper layer 56 may be any thickness previously disclosed in this document. Figure 7 As illustrated, the resulting through-silicon via 54 is hollow because the ends of the via are not closed. This ability to keep the through-silicon via 54 hollow prevents damage to the via during operation, particularly the high-temperature / ampere cycling that has been observed to cause copper pumping, which leads to the cracking of the copper contained within the solid through-silicon via. The ability of the resulting substrate 60 to allow electrical connections to both sides of the substrate 60 through the through-silicon via 54 makes this substrate design particularly suitable for use as an interposer in semiconductor packaging designs. The electrical connection can be any of a wide variety of electrical connector types (including, as non-limiting examples, wire bonding, bonding leads, clamps, wires, flexible connectors, or any other type of electrical connector). The conductive material used for the electrical connector can be any of a wide variety of materials (including, as non-limiting examples, gold, gold alloys, silver, silver alloys, aluminum, aluminum alloys, copper, copper alloys, nickel, nickel alloys, any combination thereof, or any other type of conductive material or alloy). In various embodiments, because thick copper traces exist on both sides of the silicon substrate 38, the substrate 60 can be an efficient alternative to a directly bonded copper substrate. In various embodiments, through-silicon vias 54 can be connected to fan-out wiring formed by the traces 58. This will allow various active and / or passive components to be coupled / bonded to both sides of the substrate 60, although from a processing perspective, this will occur after the semiconductor package / substrate has been cut into package-sized portions.

[0039] The various other substrate embodiments disclosed herein can be formed using various methods for forming substrates / intermediates. References Figure 8 An example is illustrated of a silicon substrate 62 including an oxide layer 64 formed thereon. While an oxide layer 64 is illustrated, any other dielectric / non-conductive material disclosed herein may be used in various substrate embodiments. Reference Figure 9The diagram illustrates a silicon substrate 62 after a cavity 66 has been formed into the thickness / material of the silicon substrate 62. In various implementations, the cavity 66 is formed by first forming a patterned layer over an oxide layer 64, and then etching the oxide to expose the surface of the silicon substrate. The patterned layer is then removed, and the oxide layer 64 is used as the patterned layer during the etching process used to remove the silicon and form the cavity 66. As illustrated, the etching process of the cavity 66 forms beveled edges, indicating that the etching is more isotropic than anisotropic. Various etching processes, including wet etching or dry etching, can be used to etch the cavity 66 to achieve the desired cavity shape. The use of beveled sidewalls helps to achieve a more uniform formation of subsequent layers. While the use of etching has been disclosed, in some implementations, laser or milling processes can be used to form the cavity 66, which can simultaneously cut through both the oxide and silicon and avoid the need for the formation of a patterned layer.

[0040] After cavity 66 is formed, another oxide layer 68 is formed over the exposed silicon in cavity 66. This oxide layer 68 can be formed using any of the methods disclosed herein and can be specifically shaped as a conformal layer. However, in other embodiments, the oxide layer 68 may not be used; instead, a barrier layer and / or a seed layer may be applied to the exposed silicon. With the two oxide layers 64, 66 in place, a patterned layer is then formed at a desired height to facilitate the formation of a thick copper layer 70 together with the copper trace portion 72 into the cavity. Figure 9 In the illustrated embodiments, any seed layer and / or barrier layer as previously disclosed in this document is applied over the exposed oxide layers 64, 66, and then an electroplating process is used to form any thick copper layer 72 and corresponding copper trace portions 72 as disclosed herein. In other embodiments, any of the other disclosed methods for forming thick copper layers may be used to form the thick copper layer. After forming the thick copper layer 70 and any corresponding copper trace portions 72, the patterning layer is then removed. Various thick copper structures extending into the surfaces of oxide layers 64, 66, extending from the surfaces of oxide layers 64, 66, and forming traces only on the surfaces of oxide layers 64, 66 can be formed using the principles disclosed in this document.

[0041] Although Figure 9 The illustrated method embodiments disclose the use of copper; however, in other method embodiments, the use of any other metal or metal alloy disclosed herein may be used, applied using any of the corresponding methods for forming that metal. In some method embodiments, multiple metal layers of different or the same type may also be utilized.

[0042] refer to Figure 10The illustration shows a silicon substrate 62 in which a semiconductor die 74 is bonded. In this embodiment, the semiconductor die 74 is placed into the cavity 66 on the thick copper layer 72 and then sintered directly or using a sintering material compatible with forming a bond between the surface of the semiconductor die 74 and the thick copper layer 70. In other embodiments, the semiconductor die 74 can be soldered to the thick copper layer 70 by dispensing solder material onto the semiconductor die 74 or the thick copper layer 70 or both, and then heating the silicon substrate 62 to melt the solder and form the desired bond. A wide variety of solder materials can be used (including, as non-limiting examples, lead-tin solder, lead-silver-tin solder, tin-silver solder, tin-copper solder, tin, any combination thereof, or another solder material compatible with any metal layer on the semiconductor die and the thick copper layer or other metal layer in the bottom of the cavity 66), depending on the material of the semiconductor die 74 and the desired processing conditions and bonding. In a specific implementation using solder, a solder-adhesive metal layer may first be formed on the thick copper layer 70. As a non-limiting example, this solder-adhesive metal may be titanium, tungsten titanate, tantalum, titanium nitride, chromium, any combination thereof, or another metal or material that promotes adhesion between a particular solder and the specific metal type to which the solder is attached. Other materials / bonding systems (as non-limiting examples include die attachment films, adhesives, die attachment binders, friction mating, mechanical mating, or any other system / method for attaching a semiconductor die to a cavity) may be used to attach the semiconductor die to the thick copper layer 70.

[0043] Figure 10 This illustration demonstrates how, after the semiconductor die 74 has been bonded to the thick metal layer 70, the edge gaps around the semiconductor die 74 and the thick metal layer 70 in the cavity 66 can be filled with a filler material. In this embodiment, the filler material can be a polyimide material 76, which is dispensed using an inkjet printing method, a dot-matrix dispensing method, or other precise dispensing method, followed by a baking operation to cure the polyimide material 76 in the edge gaps. In other embodiments, other materials (including, as non-limiting examples, polymers, resins, molding compounds, or other electrically insulating materials that can be cured using corresponding curing methods) can be used to fill the edge gaps.

[0044] refer to Figure 11 This illustrates a silicon substrate 62 where a photopolymer layer 78 is spin-coated over a semiconductor die 74, oxide layers 64 and 68, a thick copper layer 70, and a copper trace portion 72, followed by exposure and development to form an opening 80 over a desired portion of the semiconductor die 74 and / or the copper trace portion 72. In this embodiment, a curing process is used to cure the photopolymer layer 78, thus preparing to hold the photopolymer layer in place during subsequent operations. Although in Figure 11The method exemplifies the use of spin coating of photosensitive polymers, but any other method disclosed herein that is consistent with the specific polymer / resin material used to form the polymer layer may be employed to form the polymer layer.

[0045] Figure 12 This illustrates the process after copper traces 82 and vias 84 are formed into openings 80 of the photopolymer layer 78. Figure 11 The silicon substrate 62. The formation of copper traces 82 and vias 84 can be achieved by first forming a seed layer on the photosensitive polymer layer 78 using a sputtering process, followed by electroplating. In this method, vias and traces can be formed simultaneously in a planar manner. After electroplating, a patterned layer can be formed on the copper traces 82 using a photolithography process, followed by an etching process to complete the formation of the copper traces 82. However, in other implementations, a planarization step can be used before the photolithography process to produce smoother copper traces. When using other metals, appropriate deposition, via filling, and trace formation operations can be performed for those metals. In various implementations, vias can be formed first using a metal different from or the same as the traces (depending on the process used). At this point, the resulting substrate 86 is ready for further semiconductor processing operations. For example, one or more additional redistribution layers can be formed on the copper traces 82 (the second copper layer) to form an interconnect stack. One or more additional semiconductor dies may also be coupled to copper trace 82 and exposed or further embedded in an additional redistribution layer via a molding compound. In various semiconductor packages, multiple substrates 86 may be included in a stacked or otherwise bonded configuration within a multi-chip module. Finally, any of the processing methods disclosed for any of the operations disclosed herein may be used to thin the substrate 86 and / or add back metal.

[0046] refer to Figure 13 This illustrates a specific embodiment of a silicon substrate 88 having an oxide layer 90 thereon. While the use of an oxide layer is illustrated in this embodiment, any dielectric material previously disclosed may be used. In this embodiment, a patterned layer of thick copper traces 92 is then formed over the oxide layer 90. This patterned layer begins with the deposition of a bond and / or seed layer, followed by electroplating / forming a thick copper layer using any of the layer types and formation / deposition methods disclosed herein for various layers. The patterned layer is then formed over the thick copper layer, and then any etching / removal process disclosed herein is performed to remove the thick copper layer from the exposed areas to form the thick copper traces 92. Milling / laser processes may also be used to form the thick copper traces without etching. If a laser process is used, a protective coating may be formed over the thick copper layer to retain slag thereon, which can then be removed by washing or another cleaning process. The resulting structure is... Figure 14The example shown illustrates a thick copper trace 92 that exposes a portion of the oxide layer 90.

[0047] refer to Figure 15 An example is shown of a silicon substrate 88 after a photosensitive polyimide (PSPI) layer 94 has been vacuum-laminated over a thick copper trace 92 and an oxide layer 90. Because polyimide is photoconfinable, after this layer has been conformally formed on the surface of the silicon substrate 88, exposure and development of the reactive PSPI material are performed to create an opening 96. Figure 16 An example is shown of a silicon substrate 88 after a semiconductor die 98 has been bonded to an opening 96 on a thick copper trace 92. Bonding can be performed using any die bonding method disclosed herein, including sintering and soldering.

[0048] refer to Figure 17 This illustration shows a silicon substrate 88 after a precise filling operation of the gap between the opening 96 and the semiconductor die 98 using any of the filling materials and processes disclosed herein. A baking / curing process is then used to stabilize the filling material. A via 100 and a copper trace (second copper layer) 102 are then formed to form an electrical connection with the thick copper trace 92. The via 100 and copper trace 102 can be formed using any of the methods disclosed herein for forming copper layers. In various specific embodiments using deposition and formation methods consistent with those metals, other metals / conductive materials besides copper can be used for the via 100 and / or trace 102.

[0049] Figure 18 An example is illustrated of a silicon substrate 88 after applying another photodefined polyimide / photodefined polymer layer over via 100 and trace 102 using any of the methods disclosed herein, and forming thereon / therein a second set of vias 104 and a third set of copper traces 106. Additional conductive and non-conductive layers may be formed to perform additional circuitry to another semiconductor die coupled to trace 102. In this way, a semiconductor die 98 is embedded in the resulting substrate 108. The substrate 108 can then be used in packaging operations to form any of the previously disclosed semiconductor package types that include multi-chip modules. The substrate 108 may also be thinned and / or have a back metallized. With substrates 86 and 108 having metal / conductive layers on both sides, they can be effectively used to mount active and / or passive components to both sides of the substrate after any dicing that may be required.

[0050] In this document, the semiconductor die that can be used can be any of a wide variety of semiconductor dies (including, as non-limiting examples, power semiconductor dies, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar junction transistors (IGBTs), hybrid devices, rectifiers, random access memory, high electron mobility transistors, image sensors, wide-bandgap (WBG) semiconductor devices, hybrid devices, or any other semiconductor die / device type). Any of a wide variety of semiconductor substrate types can be used for packaging semiconductor dies using the semiconductor package designs disclosed in this document, including (as non-limiting examples) silicon, silicon carbide, gallium arsenide, gallium nitride, silicon-on-insulator, ruby, sapphire, or any other semiconductor material type. A wide variety of semiconductor package configurations can be formed using the principles disclosed herein.

[0051] Various semiconductor packages implemented using the various substrates disclosed herein can be cooled from one or both sides of the package (double-sided cooling). Moreover, the methods disclosed herein for embedding semiconductor dies can be used to embed multiple semiconductor dies in multiple layers of the same substrate or in a combination of multiple substrates.

[0052] Where the above description relates to specific embodiments and implementation components, sub-components, methods, and sub-methods of semiconductor packaging, it will be readily apparent that numerous modifications can be made without departing from the substance, and that these embodiments, implementation components, sub-components, methods, and sub-methods can be applied to other semiconductor packages.

Claims

1. A substrate, the substrate comprising: Semiconductor materials; A redistribution layer coupled to a first maximum planar surface of the semiconductor material; and A hollow via extends completely through the thickness of the semiconductor material from the second largest planar surface of the semiconductor material, and the hollow via is directly coupled to the redistribution layer.

2. The substrate of claim 1, wherein the redistribution layer comprises at least one thick copper layer.

3. The substrate of claim 1, wherein the redistribution layer comprises at least one dielectric layer and at least one layer of solderable or sinterable metal.

4. The substrate of claim 1, wherein the semiconductor material is thinned from an initial thickness.

5. The substrate according to claim 1, wherein the semiconductor material is silicon carbide.

6. The substrate according to claim 1, wherein the semiconductor material is silicon.

7. The substrate according to claim 6, further comprising: An oxide layer is provided between the redistribution layer and the semiconductor material.

8. The substrate according to claim 6, further comprising: An oxide layer is located on the second largest planar surface of the semiconductor material.

9. The substrate according to claim 1, further comprising: A back metal layer coupled to the second maximum planar surface of the semiconductor material.

10. A method for embedding a semiconductor die, the method comprising: A silicon substrate is provided, wherein the silicon substrate includes a first oxide layer; At least one opening is formed in the first oxide layer; Etching a cavity into the silicon substrate at at least one opening in the first oxide layer; A second oxide layer is formed in the cavity; A thick copper layer is formed on the first oxide layer and on the second oxide layer; Pattern the thick copper layer; At least one semiconductor die is sintered to the thick copper layer in the cavity; The cavity is filled with polyimide to fill the gap between the at least one semiconductor die and the thick copper layer; A photosensitive polymer layer is formed on the at least one semiconductor die, the thick copper layer, and the first oxide layer; The photosensitive polymer layer is patterned to form a plurality of openings in the photosensitive polymer layer; A first copper layer is formed in the plurality of openings; as well as A second copper layer is formed on top of the photosensitive polymer layer and the first copper layer.

11. The method of claim 10, wherein the formation of the first copper layer and the formation of the second copper layer occur simultaneously.

12. The method according to claim 10, further comprising: A seed layer is formed on the second oxide layer before the thick copper layer is formed.

13. The method according to claim 10, further comprising: The polyimide is baked.

14. The method according to claim 10, further comprising: The redistribution layer or another semiconductor die is coupled to the second copper layer.

15. A method for embedding a semiconductor die, the method comprising: A silicon substrate is provided, wherein the silicon substrate includes an oxide layer; A thick copper layer is formed on the oxide layer; Pattern the thick copper layer; A first photosensitive polyimide is applied over the thick copper layer; The first photosensitive polyimide is patterned to form openings in the first photosensitive polyimide; Sintering or welding semiconductor dies in the opening; A first copper layer is formed on the first photosensitive polyimide and the semiconductor die; A second photosensitive polyimide is applied over the first copper layer; Pattern the second photosensitive polyimide; A second copper layer is formed on the second photosensitive polyimide; as well as The redistribution layer or another semiconductor die is coupled to the second copper layer.

16. The method according to claim 15, further comprising: A seed layer is formed on the oxide layer before the thick copper layer is formed.

17. The method according to claim 15, further comprising: Before the first copper layer is formed, the space around the semiconductor die is filled with polyimide.

18. The method of claim 15, wherein forming the first copper layer further comprises simultaneously forming vias and traces.

19. The method of claim 15, wherein forming the first copper layer further comprises first forming a via and then forming a trace.

20. The method of claim 15, wherein forming the second copper layer further comprises: Simultaneously forming through-holes and traces; or First, a through hole is formed, and then a trace is formed.

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