Semiconductor packaging structure and circuit assembly
By setting up a stacked structure on the substrate to adjust the stress, the warpage control problem of large-size chip packaging structure was solved, and the packaging process yield and heat dissipation effect were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI SUIYUAN TECH CO LTD
- Filing Date
- 2026-02-04
- Publication Date
- 2026-05-08
AI Technical Summary
Existing large-size chip packaging structures have poor warpage control, which affects the packaging process and heat dissipation.
A stacked structure is used to adjust the substrate stress, including a first structure and a second structure stacked together. The first structure is fixedly connected to the substrate, and the second structure is detachably connected to the first structure. By adjusting the stress magnitude and thermal expansion coefficient of the stacked structure, the warpage matching degree is improved, and the second structure is removed after packaging to increase the heat dissipation space.
It effectively improves the warpage control of large-size chip packaging structures, increases packaging process yield and heat dissipation performance, and reduces packaging difficulty.
Smart Images
Figure CN122003158A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and circuit assembly. Background Technology
[0002] As the integration density of heterogeneous chip structures increases, chip power consumption and package size also grow larger. When chips are mounted on substrates to form packages, substrate warpage defects can occur. The larger the chip size, the greater the substrate warpage, impacting the yield of the entire packaging manufacturing process. Furthermore, the mounting process between the package structure and the PCB circuit board presents increasing challenges.
[0003] Existing warp control structures for large-size chip packaging have poor warp control performance, which affects the packaging process and heat dissipation, becoming a technical problem that urgently needs to be solved in the industry. Summary of the Invention
[0004] This invention provides a semiconductor packaging structure and circuit assembly to solve the problem that existing warp control structures for large-size chips have poor warp control effects, affecting the packaging process and heat dissipation.
[0005] To address the aforementioned technical problems, the present invention adopts the following technical solution: This invention provides a semiconductor packaging structure, comprising: substrate; A stacked structure disposed on one side of a substrate, the stacked structure being used to adjust the stress of the substrate; the stacked structure forming at least one cavity. Semiconductor devices disposed within the cavity, with the semiconductor devices and the stacked structure spaced apart; The stacked structure includes a first structure and a second structure stacked together. The first structure is fixedly connected to the substrate, and the second structure is detachably connected to the first structure.
[0006] Optionally, the first structure is disposed between the substrate and the second structure; Along the thickness direction of the substrate, the projections of the first structure and the second structure at least partially overlap.
[0007] Optionally, the semiconductor packaging structure also includes: An adhesive layer is used to fix the first structure to the substrate; and / or, The first structure and the second structure are detachably connected via the connecting structure.
[0008] Optionally, the connection structure may include temporary bonding adhesive and / or mechanical fasteners.
[0009] Optionally, the first structure includes at least one first metal ring; The second structure includes a metal cap and / or at least one second metal ring.
[0010] Optionally, in the case where the stacked structure includes one metal cap and at least one second metal ring: A metal cap is disposed on the side of at least one second metal ring away from the substrate; and / or, Along the thickness direction of the substrate, the metal cap at least partially covers the second metal ring; and / or, Along the thickness direction of the substrate, the projection of the metal cover at least partially covers the projection of the semiconductor device.
[0011] Optionally, the stress magnitude of the laminated structure can be adjusted by the contact area between the first metal ring and the second metal ring, the contact area between two adjacent second metal rings, and / or the contact area between the second metal ring and the metal cap. And / or, the stress magnitude of the laminated structure is adjusted by the thermal expansion coefficients and / or thicknesses of the first and second structures.
[0012] Optionally, the materials of the first metal ring and the second metal ring include metal; And / or, the coefficient of thermal expansion of the first metal ring is different from that of the second metal ring; And / or, in the case where the second structure includes at least two layers of second metal rings, the coefficients of thermal expansion of adjacent layers of second metal rings are different; And / or, along a direction parallel to the substrate, the width of the metal ring is ≥1mm and ≤50mm; And / or, the minimum distance between the semiconductor device and the stacked structure is ≥0.5mm and ≤50mm.
[0013] Optionally, along the thickness direction of the substrate, the thickness of the stacked structure is greater than the thickness of the semiconductor device; And / or, the second structure of the stacked structure includes a metal cap, and the semiconductor package structure also includes a spacer disposed between the semiconductor device and the metal cap.
[0014] Secondly, this embodiment provides a circuit component, including: the semiconductor packaging structure provided in any of the items in the first aspect.
[0015] Optionally, the circuit components also include: Circuit board; A semiconductor package structure is disposed on at least one side of a circuit board, and the stacked structure of the semiconductor package structure is used to adjust the stress of the substrate to match the stress of the semiconductor package structure.
[0016] Optionally, the second structure of the stacked structure of the semiconductor package structure is used to be removed after the stress of the substrate of the semiconductor package structure is matched with the stress of the circuit board.
[0017] The semiconductor packaging structure provided in this invention, by distributing a stacked structure around a semiconductor device and spaced apart from it, includes a first structure and a second structure stacked on top of each other. This allows for the reasonable adjustment of the number and thermal expansion coefficients of the first and second structures, thereby adjusting the stress of the stacked structure and preventing substrate warping. It also effectively improves the matching degree between the warping direction of the semiconductor packaging structure and the circuit board it is mounted on, thus increasing the yield of the semiconductor packaging structure's mounting process. Furthermore, by providing a detachable connection between the second structure and the first structure, the second structure can be easily removed after the semiconductor packaging structure is mounted on the circuit board, effectively increasing the heat dissipation space of the semiconductor device. Even for large-sized semiconductor packaging structures, the warping control effect is significantly improved, and the heat dissipation effect of the semiconductor packaging structure is also enhanced. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an embodiment of the present invention; Figure 2 This is a top view of a semiconductor packaging structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a stacked structure of a semiconductor packaging structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a stacked structure of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 9This is a top view of yet another semiconductor packaging structure provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a stacked structure of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of a stacked structure of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of another semiconductor packaging structure provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of a circuit component provided in an embodiment of the present invention. Detailed Implementation
[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0022] Based on the above-mentioned technical problems, this embodiment proposes the following solutions: Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an embodiment of the present invention. Figure 2 This is a top view of a semiconductor packaging structure provided in an embodiment of the present invention. (Combined with...) Figure 1 and Figure 2The semiconductor packaging structure 10 provided in this embodiment of the invention includes: a substrate 1; a stacked structure 2 disposed on one side of the substrate 1, the stacked structure 2 being used to adjust the stress of the substrate 1; the stacked structure 2 forming at least one cavity Ho1; a semiconductor device 3 disposed in the cavity Ho1, the semiconductor device 3 being disposed at a distance from the stacked structure 2; the stacked structure 2 includes a first structure 21 and a second structure 22 stacked together, the first structure 21 being fixedly connected to the substrate 1, and the second structure 22 being detachably connected to the first structure 21.
[0023] Specifically, substrate 1 can be a glass substrate, a silicon substrate, or a sapphire substrate, etc. Semiconductor device 3 can include a semiconductor chip. Because substrate 1 is relatively thin, when semiconductor device 3 is disposed on one side of substrate 1, the uneven stress on substrate 1 can easily cause warping defects. By providing a stacked structure 2 on one side of substrate 1, the stacked structure 2 can adjust the stress on substrate 1, thereby enhancing the anti-warping effect of substrate 1.
[0024] Because there is a certain distance between the semiconductor device 3 and the stacked structure 2, there is sufficient electrical distance between the stacked structure 2 and the semiconductor device 3, which improves the insulation safety.
[0025] The stacked structure 2 includes a first structure 21 and a second structure 22 stacked together, such that the first structure 21 can be fixedly connected to the substrate 1. The second structure 22 is detachably connected to the first structure 21, so that when the second structure 22 and the first structure 21 are connected, they can jointly provide greater stress, thereby effectively improving the warpage problem of the larger semiconductor device 3, improving the flatness of the substrate 1, and improving the packaging performance of the semiconductor device 3.
[0026] Furthermore, since the stacked structure 2 includes at least one first structure 21 and at least one second structure 22, the number of the first structure 21 and the second structure 22, the coefficient of thermal expansion, etc. of the stacked structure 2 can be reasonably set as needed, and the stress of the stacked structure 2 can be adjusted so that the stress of the substrate 1 matches the stress of the semiconductor device 3. Also, after the semiconductor packaging structure 10 is placed on the circuit board 20, the warping direction of the semiconductor packaging structure 10 matches the warping direction of the circuit board 20, thereby improving the overall warping problem of the circuit board 20.
[0027] Since the second structure 22 and the first structure 21 are detachably connected, after the semiconductor device 3 is packaged, or after the semiconductor package structure 10 is mounted on the circuit board 20, the stacked structure 2 provided on the semiconductor package structure 10 matches the stress of the semiconductor package structure 10 with the stress of the circuit board 20, and then the semiconductor package structure 10 is placed on the circuit board 20, thereby reducing the process difficulty of mounting the semiconductor package structure 10 on the circuit board 20.
[0028] Since the first structure 21 and the second structure 22 of the stacked structure 2 are detachably connected, after the stress of the semiconductor package structure 10 is matched with the stress of the circuit board 20 and the mounting is completed, the second structure 22 can be removed to provide a larger heat dissipation space for the semiconductor device 3, thereby achieving both anti-warping of the substrate 1 and heat dissipation of the semiconductor device 3.
[0029] The semiconductor packaging structure 10 provided in this embodiment, by disposing a stacked structure 2 around the semiconductor device 3 and spaced apart from it, includes a first structure 21 and a second structure 22 stacked together. This allows the stacked structure 2 to be configured with appropriate quantities and thermal expansion coefficients of the first and second structures 21 and 22, thereby adjusting the stress level and preventing warping of the substrate 1. It also effectively improves the matching degree of the warping direction between the semiconductor packaging structure 10 and the circuit board 20 it is mounted on, thus increasing the mounting yield of the semiconductor packaging structure 10. Furthermore, by detachably connecting the second structure 22 to the first structure 21, the second structure 22 can be removed after the semiconductor packaging structure 10 is mounted on the circuit board 20, effectively increasing the heat dissipation space of the semiconductor device 3. This significantly improves the warping control effect even for large-sized semiconductor packaging structures 10 and enhances the heat dissipation performance of the semiconductor packaging structure 10.
[0030] Optionally, based on the above embodiments, see also... Figure 1 The first structure 21 is disposed between the substrate 1 and the second structure 22; along the thickness direction of the substrate 1, the projection of the first structure 21 and the projection of the second structure 22 at least partially overlap.
[0031] Optional, Figure 3 This is a schematic diagram of yet another semiconductor packaging structure provided in an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 3 The semiconductor packaging structure 10 may also include an adhesive layer 4, through which the first structure 21 is fixedly connected to the substrate 1.
[0032] Specifically, adhesive layer 4 serves an adhesive function. Adhesive layer 4 fixes the first structure 21 to the substrate 1, thereby improving the warpage problem of the substrate 1. For example, adhesive layer 4 can be an adhesive, which can be applied as a whole layer or applied by dispensing, without any limitation.
[0033] And / or, Figure 4 This is a schematic diagram of yet another semiconductor packaging structure provided in an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 4 The semiconductor packaging structure 10 may also include a connection structure 5, through which the first structure 21 and the second structure 22 are detachably connected.
[0034] Specifically, the connecting structure 5 is the structure that connects the second structure 22 to the first structure 21. For example, the connecting structure 5 can be a detachable mother-daughter structure combination, a screw and nut structure combination, a removable adhesive layer, etc.
[0035] Optional, Figure 5 This is a schematic diagram of yet another semiconductor packaging structure provided in an embodiment of the present invention. Based on the above embodiments, and in conjunction with… Figure 4 and Figure 5 The connection structure 5 may include temporary bonding adhesive 51 and / or mechanical connector 52.
[0036] Specifically, when the connecting structure 5 includes temporary bonding adhesive 51, it facilitates the connection between the second structure 22 and the first structure 21. Furthermore, when the first structure 21 is multi-layered, adjacent first structures 21 on both sides can be connected, or two adjacent layers of the second connecting structure 5 can be connected. The mechanical connector 52 may include metal screws. Through holes may be provided in the first structure 21 and the second structure 22, allowing the first structure 21 and the second structure 22 to be connected via mechanical connectors 52 such as metal screws.
[0037] When the second structure 22 is to be removed, the temporary bonding adhesive 51 can be removed by heating, or the second structure 22 can be removed by mechanical disassembly after the mechanical connector 52 is disassembled.
[0038] Optional, Figure 6 This is a schematic diagram of a stacked structure of a semiconductor packaging structure provided in an embodiment of the present invention. Figure 7 This is a schematic diagram of a stacked structure of another semiconductor packaging structure provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of another semiconductor packaging structure provided in an embodiment of the present invention. Figure 9 This is a top view of yet another semiconductor packaging structure provided in an embodiment of the present invention. Based on the above embodiments, and in conjunction with… Figures 6 to 9 The first structure 21 includes at least one first metal ring H1; the second structure 22 includes a metal cap G1 and / or at least one second metal ring H2.
[0039] Specifically, the second metal rings H2 are detachably connected to each other via connecting structure 5. The second metal rings H2 and the metal cover G1 are detachably connected via connecting structure 5. At least one layer of first metal rings H1 is detachably connected to the second metal rings H2 via connecting structure 5. Adjacent layers of first metal rings H1 can be connected via connecting structure 5 or via adhesive layer 4, without any limitation.
[0040] It should be noted that, Figure 8An exemplary case is shown where the first structure 21 includes a first metal ring H1 and the second structure 22 includes a metal cap G1. Figure 6 and Figure 7 An exemplary illustration shows a first structure 21 comprising a first metal ring H1 and a second structure 22 comprising at least two second metal rings H2, without any limitation herein.
[0041] Optional, Figure 10 This is a schematic diagram of a stacked structure of another semiconductor packaging structure provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of a stacked structure of another semiconductor packaging structure provided in an embodiment of the present invention. Based on the above embodiments, and combined with… Figure 10 and Figure 11 In the case where the stacked structure 2 includes a metal cover G1 and at least one second metal ring H2: the metal cover G1 is disposed on the side of the at least one second metal ring H2 away from the substrate 1; and / or, along the thickness direction Z of the substrate 1, the metal cover G1 at least partially covers the second metal ring H2; and / or, along the thickness direction Z of the substrate 1, the projection of the metal cover G1 at least partially covers the projection of the semiconductor device 3.
[0042] Specifically, the metal cover G1 is disposed on the side of at least one second metal ring H2 away from the substrate 1, facilitating the attachment of the second metal ring H2 to the adjacent first metal ring H1. This arrangement provides sufficient space for the metal cover G1 to be disposed on the side of the second metal ring H2 away from the substrate 1. Because the metal cover G1 has a large area, the stress adjustment capability of the second structure 22 on the substrate 1 is further increased, further improving the anti-warping capability of the second structure 22 on the substrate 1.
[0043] Along the thickness direction Z of substrate 1, the metal cover G1 at least partially covers the second metal ring H2, so that the contact area between the metal cover G1 and the metal ring effectively adjusts the stress direction of substrate 1. In turn, according to the size and other requirements of semiconductor device 3, the stress of substrate 1 is reasonably adjusted, further improving the stress magnitude of substrate 1, thereby improving the packaging effect of semiconductor packaging structure 10, improving the stress matching degree between semiconductor packaging structure 10 and circuit board 20, thereby improving the yield of the mounting process of semiconductor packaging structure 10 on circuit board 20, and thus improving the overall anti-warping effect and heat dissipation effect of circuit board 20.
[0044] The metal cover G1 is positioned such that its projection at least partially covers the projection of the semiconductor device 3 along the thickness direction Z of the substrate 1. This allows the metal cover G1 to adjust for warpage around the semiconductor device 3, further improving the flatness of the substrate 1 and thus enhancing the packaging effect of the semiconductor device 3. This configuration allows the larger metal cover G1 to withstand greater stress, making it suitable for improving warpage prevention in large-size semiconductor packaging structures 10. Since the metal cover G1, as the second structure 22, is detachably connected to the first structure 21, it can be removed after the semiconductor device 3 packaging structure is mounted onto the circuit board 20, effectively improving the heat dissipation of the semiconductor device 3.
[0045] Optionally, based on the above embodiments, see also... Figure 6 , Figure 7 , Figure 10 and Figure 11 The stress magnitude of the laminated structure 2 is adjusted by the contact area between the first metal ring H1 and the second metal ring H2, the contact area between two adjacent second metal rings H2, and / or the contact area between the second metal ring H2 and the metal cap G1.
[0046] Specifically, the contact area between the first metal ring H1 and the second metal ring H2 can adjust the stress level of the laminated structure 2. The contact area between two adjacent second metal rings H2 can adjust the stress level of the laminated structure 2. The contact area between the second metal ring H2 and the metal cap G1 can adjust the stress level of the laminated structure 2.
[0047] And / or, based on the above embodiments, continue to refer to... Figures 1 to 11 The stress magnitude of the laminated structure 2 is adjusted by the thermal expansion coefficient and / or thickness of the first structure 21 and the second structure 22.
[0048] Specifically, the materials of the first structure 21 and the second structure 22 can be different. The coefficient of thermal expansion of the first structure 21 may be the same as or different from that of the second structure 22. The coefficients of thermal expansion of the first structure 21 and the second structure 22 can be adjusted according to the warpage direction so that the stress generated by the first structure 21 and the second structure 22 matches the stress of the semiconductor device 3 packaged onto the substrate 1, thereby improving the flatness of the substrate 1 and thus enhancing the anti-warpage effect. The thickness of the first structure 21 and the second structure 22 can also be adjusted according to the warpage direction so that the stress generated by the first structure 21 and the second structure 22 matches the stress of the semiconductor device 3 packaged onto the substrate 1, thereby improving the flatness of the substrate 1 and thus enhancing the anti-warpage effect.
[0049] Optionally, based on the above embodiments, see also... Figures 6 to 11 The materials of the first metal ring H1 and the second metal ring H2 include metals.
[0050] Specifically, the first metal ring H1 and the second metal ring H2 can be made of materials with different coefficients of thermal expansion, and the materials should have a high elastic modulus. The first metal ring H1 and the second metal ring H2 are preferably made of metallic materials. This arrangement facilitates further improvement of the flatness of the substrate 1, thereby enhancing the anti-warping effect.
[0051] And / or, the coefficient of thermal expansion of the first metal ring H1 is different from that of the second metal ring H2.
[0052] Specifically, this configuration allows the thermal expansion coefficients of the first metal ring H1 and the second metal ring H2 to be set according to the warp direction of the substrate 1 or the circuit board 20. This ensures that the stress direction of the stacked structure 2 is opposite to that of the substrate 1 and matches the stress direction of the circuit board 20. Consequently, the flatness of the substrate 1 is improved, and the stress of the stacked structure 2 matches the stress direction of the circuit board 20. This not only improves the flatness of the substrate 1 but also ensures that the overall curvature of the semiconductor packaging structure 10 is consistent with the curvature of the circuit board 20, thereby increasing the mounting yield of the semiconductor packaging structure 10.
[0053] And / or, in the case where the second structure 22 includes at least two layers of second metal rings H2, the coefficients of thermal expansion of adjacent layers of second metal rings H2 are different.
[0054] For example, when substrate 1 is warped in a "crying face" shape, and a "smiling face" bend is needed in the stacked structure, the warp of substrate 1 can be pulled upwards to achieve the desired warp direction and flatness. The first metal ring H1 of the stacked structure can be made of a material with a lower coefficient of thermal expansion, the second metal ring H2 can be made of a material with a higher coefficient of thermal expansion, and so on, with the upper second metal ring H2 having a higher coefficient of thermal expansion than the lower second metal ring H2. Furthermore, by adjusting the contact area between adjacent second metal rings H2, the thickness of the second metal ring H2, and the coefficient of thermal expansion of the second metal ring H2, stacked structures 2 with different flatness can be achieved, thereby matching the warp direction and flatness of the back side of substrate 1 with the warp direction and flatness of circuit board 20.
[0055] And / or, Figure 12 This is a schematic diagram of yet another semiconductor packaging structure provided in an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 12 Along the direction X parallel to substrate 1, the width L1 of the metal ring is ≥1mm and ≤50mm.
[0056] Specifically, the width L1 of the metal ring ranges from 1mm to 50mm. The preferred width L1 is 3mm to 20mm. This design ensures sufficient stress on the metal ring, facilitating anti-warping effects for semiconductor package structures 10 of different sizes.
[0057] And / or, the minimum distance L2 between the semiconductor device 3 and the stacked structure 2 is ≥0.5mm and ≤50mm.
[0058] Specifically, the minimum distance L2 between the semiconductor device 3 and the stacked structure 2 ranges from 0.5mm to 50mm. The preferred range for the minimum distance L2 between the semiconductor device 3 and the stacked structure 2 is 1.5mm to 10mm. This arrangement ensures that the distance between the semiconductor device 3 and the stacked structure 2 is greater than the creepage distance, while also allowing the semiconductor device 3 to meet the tolerances of the packaging process during mounting, thus satisfying the packaging effect of the semiconductor package structure 10.
[0059] Optionally, based on the above embodiments, see also... Figure 12 Along the thickness direction Z of substrate 1, the thickness D1 of the stacked structure 2 is greater than the thickness D2 of semiconductor device 3.
[0060] Specifically, this configuration makes the stacked structure 2 more resistant to warping, and also ensures that the height of the semiconductor device 3 is lower than the height of the stacked structure 2, even with the metal cover G1 included in the stacked structure 2, thus further guaranteeing the electrical distance between the semiconductor device 3 and the stacked structure 2.
[0061] And / or, Figure 13 This is a schematic diagram of yet another semiconductor packaging structure provided in an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 13 The second structure 22 of the stacked structure 2 includes a metal cover G1, and the semiconductor package structure 10 also includes a gasket 6, which is disposed between the semiconductor device 3 and the metal cover G1.
[0062] Specifically, the gasket can serve as a buffer, an insulator, and a support. By placing the gasket between the semiconductor device 3 and the metal cover G1, the metal cover G1 and the semiconductor device 3 can be fixedly supported by the gasket, improving the stability of the semiconductor device 3 and the metal cover G1, avoiding damage to the semiconductor device 3 caused by pressure in the direction of the metal cover G1, and thus improving the lifespan of the semiconductor package structure 10.
[0063] Based on the same inventive concept, this embodiment provides a circuit component 100. The circuit component 100 provided in this embodiment includes the semiconductor package structure 10 provided in any of the above embodiments, and has the beneficial effects of the semiconductor package structure 10 provided in any of the above embodiments, which will not be described again here.
[0064] Optional, Figure 14 This is a schematic diagram of a circuit component provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 14 The circuit assembly 100 further includes: a circuit board 20; a semiconductor package structure 10 disposed on at least one side of the circuit board 20, wherein the stacked structure 2 of the semiconductor package structure 10 is used to adjust the stress of the substrate 1 to match the stress of the semiconductor package structure 10.
[0065] Specifically, the warp direction of the semiconductor package structure 10 matches the warp direction of the circuit board 20, improving the warp matching degree between the semiconductor package structure 10 and the circuit board 20, and increasing the yield of the semiconductor package structure 10 packaged onto the circuit board 20. After the semiconductor device 3 is packaged onto the substrate 1, if the substrate 1 exhibits a "crying face" warp, the stacked structure needs to be made to have a "smiling face" bend. This pulls the warped substrate 1 upwards, achieving the desired warp direction and flatness.
[0066] For example, when the circuit board 20 warps in a "smiley face" shape, the semiconductor package structure 10 needs to be bent in a "smiley face" shape so that the bending direction of the semiconductor package structure 10 is consistent with the warping direction of the circuit board 20, which facilitates mounting or soldering the semiconductor package structure 10 on the circuit board 20.
[0067] Optionally, based on the above embodiments, see also... Figure 14 The second structure 22 of the stacked structure 2 of the semiconductor package structure 10 is used to be removed after the stress of the substrate 1 of the semiconductor package structure 10 matches the stress of the circuit board 20.
[0068] Specifically, after the stress on the substrate 1 of the semiconductor packaging structure 10 matches the stress on the circuit board 20, the second structure 22 can be removed, which can improve the heat dissipation of the semiconductor device 3 and reduce the thickness of the semiconductor packaging structure 10 on the circuit board 20, which is beneficial to the miniaturization and thinning design of the circuit assembly 100.
[0069] It should be noted that, Figure 14 The example shown is of 30 solder balls, but no limitation is made here.
[0070] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.
Claims
1. A semiconductor packaging structure, characterized in that, include: substrate; A stacked structure disposed on one side of the substrate, the stacked structure being used to adjust the stress of the substrate; the stacked structure forming at least one cavity; The semiconductor device disposed within the cavity is spaced apart from the stacked structure. The stacked structure includes a first structure and a second structure stacked together. The first structure is fixedly connected to the substrate, and the second structure is detachably connected to the first structure.
2. The semiconductor packaging structure according to claim 1, characterized in that, The first structure is disposed between the substrate and the second structure; Along the thickness direction of the substrate, the projection of the first structure and the projection of the second structure at least partially overlap.
3. The semiconductor packaging structure according to claim 1 or 2, characterized in that, The semiconductor packaging structure further includes: An adhesive layer is used to fix the first structure to the substrate; and / or, A connection structure is provided, wherein the first structure and the second structure are detachably connected via the connection structure.
4. The semiconductor packaging structure according to claim 3, characterized in that, The connection structure includes temporary bonding adhesive and / or mechanical fasteners.
5. The semiconductor packaging structure according to claim 1 or 2, characterized in that, The first structure includes at least one first metal ring; The second structure includes a metal cap and / or at least one second metal ring.
6. The semiconductor packaging structure according to claim 5, characterized in that, In the case where the stacked structure includes one metal cap and at least one second metal ring: The metal cap is disposed on the side of the at least one second metal ring away from the substrate; and / or, Along the thickness direction of the substrate, the metal cap at least partially covers the second metal ring; and / or, Along the thickness direction of the substrate, the projection of the metal cover at least partially covers the projection of the semiconductor device.
7. The semiconductor packaging structure according to claim 6, characterized in that, The stress magnitude of the laminated structure is adjusted by the contact area between the first metal ring and the second metal ring, the contact area between two adjacent second metal rings, and / or the contact area between the second metal ring and the metal cap. And / or, the stress magnitude of the laminated structure is adjusted by the coefficients of thermal expansion and / or thickness of the first and second structures.
8. The semiconductor packaging structure according to claim 5, characterized in that, The materials of the first metal ring and the second metal ring include metals; And / or, the coefficient of thermal expansion of the first metal ring is different from that of the second metal ring; And / or, in the case where the second structure includes at least two layers of second metal rings, the coefficients of thermal expansion of adjacent layers of second metal rings are different; And / or, along a direction parallel to the substrate, the width of the metal ring is ≥1mm and ≤50mm; And / or, the minimum distance between the semiconductor device and the stacked structure is ≥0.5mm and ≤50mm.
9. The semiconductor packaging structure according to claim 5, characterized in that, Along the thickness direction of the substrate, the thickness of the stacked structure is greater than the thickness of the semiconductor device; And / or, the second structure of the stacked structure includes a metal cap, and the semiconductor package structure further includes a spacer disposed between the semiconductor device and the metal cap.
10. A circuit assembly, characterized in that, include: The semiconductor packaging structure according to any one of claims 1 to 9.
11. The circuit assembly according to claim 10, characterized in that, Also includes: Circuit board; The semiconductor package structure is disposed on at least one side of the circuit board, and the stacked structure of the semiconductor package structure is used to adjust the stress of the substrate to match the stress of the semiconductor package structure.
12. The circuit assembly according to claim 10 or 11, characterized in that, The second structure of the stacked structure of the semiconductor package is used to be removed after the stress of the substrate of the semiconductor package is matched with the stress of the circuit board of the circuit assembly.