Package substrate and semiconductor package including the same

Abstract

A package substrate includes: a core having a first surface and a second surface opposite the first surface in a vertical direction, the first surface and the second surface being substantially flat, the core including glass and a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in a vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulating layer structure on the first bonding layer and partially covering the first wiring structure; and a first protective layer on the first insulating layer structure and covering a portion of an upper surface of the first wiring structure.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0156874, filed with the Korean Intellectual Property Office on November 7, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The example embodiment relates to a packaging substrate and a semiconductor package including the packaging substrate. Background Technology

[0003] As the area of ​​the packaging substrate increases, warping occurs within the packaging substrate, necessitating methods to increase the stiffness of the core. Summary of the Invention

[0004] One aspect is to provide a packaging substrate with enhanced electrical properties.

[0005] On the other hand, it provides a semiconductor package with enhanced electrical properties.

[0006] According to one or more exemplary embodiments, a packaging substrate is provided, comprising: a core having a first surface and a second surface opposite to the first surface in a vertical direction, the first and second surfaces being substantially planar, the core including glass and a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending vertically from the first surface through the core, the through electrode being spaced horizontally from the first recess; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer located on the first insulating layer structure and covering a portion of the upper surface of the first wiring structure.

[0007] According to another aspect of one or more example embodiments, a packaging substrate is provided, comprising: a core including glass, the core having a first surface and a second surface opposite to the first surface in a vertical direction, and a first recess in the first surface; a first bonding layer in the first recess, the first bonding layer comprising a first organic insulating material; a second bonding layer contacting the first surface of the core and an upper surface of the first bonding layer, the second bonding layer comprising a second organic insulating material different from the first organic insulating material; a through electrode extending vertically from the first surface through the core, the through electrode being spaced horizontally from the first recess; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer located on the first insulating layer structure and covering a portion of the upper surface of the first wiring structure.

[0008] According to another aspect of one or more example embodiments, a semiconductor package is provided, comprising: a package substrate including a core, a first bonding layer, a through electrode, a first wiring structure, a first insulating layer structure, and a first protective layer, the core comprising glass and having a first surface and a second surface opposite to the first surface in a vertical direction, the first and second surfaces being substantially flat, and the core including a first recess in the first surface, the first bonding layer contacting the first surface of the core and filling the first recess, the through electrode extending vertically from the first surface through the core, the through electrode being spaced horizontally from the first recess, the first wiring structure on the first bonding layer and contacting the through electrode, the first insulating layer structure on the first bonding layer and at least partially covering the first wiring structure, and the first protective layer on the first insulating layer structure and covering an upper surface of a first portion of the first wiring structure; a semiconductor chip on the package substrate, the semiconductor chip including conductive pads; a first conductive connector contacting the conductive pads of the semiconductor chip, the conductive connector being electrically connected to a second portion of the first wiring structure; and a molding member on the package substrate and covering the sidewalls of the semiconductor chip and the first conductive connector. Attached Figure Description

[0009] The above and other aspects will become clearer based on the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a cross-sectional view of a packaging substrate according to an example embodiment; Figures 2 to 6 This is a cross-sectional view illustrating a method for manufacturing a packaging substrate according to an example embodiment; Figure 7 This is a cross-sectional view of a packaging substrate according to an example embodiment; Figures 8 to 10 This is a cross-sectional view of a packaging substrate according to an example embodiment; Figure 11 This is a cross-sectional view showing a semiconductor package according to an example embodiment; and Figure 12 This is a cross-sectional view showing an electronic device according to an example embodiment. Detailed Implementation

[0010] In the following, exemplary embodiments will be explained in detail with reference to the accompanying drawings. It should be understood that although terms such as “first,” “second,” and / or “third” may be used herein to describe various materials, layers (films), regions, electrodes, pads, patterns, structures, and processes, these materials, layers (films), regions, electrodes, pads, patterns, structures, and processes should not be limited by these terms. These terms are used only to distinguish one material, layer (film), region, electrode, pad, pattern, structure, and process from another. Therefore, the “first” material, layer (film), region, electrode, pad, pattern, structure, and process discussed below may be referred to as a “second” or “third” material, layer (film), region, electrode, pad, pattern, structure, and process, without limiting the layers (films), regions, electrodes, pads, patterns, structures, and / or processes.

[0011] The packaging substrate may include a core, insulating layers on the lower and upper surfaces of the core, and wiring structures within the insulating layers. As mentioned above, as the area of ​​the packaging substrate increases, warping may occur within the packaging substrate, necessitating methods to increase the stiffness of the core.

[0012] In the package substrate according to various example embodiments, recesses can be formed on the surface of the core, thereby increasing the contact area between the bonding layer and the core, and increasing the bonding force between a portion of the bonding layer in the recess and the core. Therefore, delamination between the core and the bonding layer can be reduced, allowing the package to have enhanced structural stability and electrical properties.

[0013] Figure 1 This is a cross-sectional view of a packaging substrate according to an example embodiment.

[0014] Reference Figure 1 The encapsulation substrate 100 may include a core 110 having a first surface 112 and a second surface 114 that are vertically opposite to each other and have recesses 150, a through electrode 130 extending through the core 110 in the vertical direction, a first bonding layer 160 disposed on the first surface 112 and the second surface 114 and filling the recesses 150, an insulating layer structure 300 on the lower surface and the upper surface of the first bonding layer 160, and a first protective layer 222 and a second protective layer 224 on the lower surface and the upper surface of the insulating layer structure 300, and a wiring structure 310 may be disposed between the first bonding layer 160 and each of the first protective layer 222 and the second protective layer 224.

[0015] In an example embodiment, the core 110 may include glass. In an example embodiment, the core 110 may have a thickness of about 400 μm to about 800 μm. Each of the first surface 112 and the second surface 114 may be substantially flat.

[0016] In an example embodiment, a plurality of recesses 150 may be horizontally spaced apart from each other in each of the first surface 112 and the second surface 114 of the core 110. Figure 1 Two recesses 150 are shown in each of the first surface 112 and the second surface 114 of the core 110. However, the exemplary embodiments are not limited to two recesses 150, and in some exemplary embodiments, the number of recesses 150 may be varied. The recesses 150 may be arranged in various layouts in the plan view.

[0017] In the plan view, each recess 150 may have a shape such as circular, elliptical, polygonal, or polygonal with rounded corners. In an example embodiment, the width of each recess 150 in the horizontal direction may be substantially constant in the vertical direction, so the sidewalls of each recess 150 may extend in the vertical direction.

[0018] In an example embodiment, each recess 150 may have a width in the horizontal direction equal to or greater than about 5 μm, and each recess 150 may have a depth in the vertical direction equal to or greater than about 10 μm. In other words, each recess 150 may extend from the first surface 112 or the second surface 114 into the core 110 to a depth equal to or greater than about 10 μm. As described above, the first bonding layer 160 may fill the recesses 150 to a depth equal to or greater than about 10 μm.

[0019] Figure 1 An example is shown in which the recesses 150 on the first surface 112 and the recesses 150 on the second surface 114 of the core 110 have the same layout. However, the example embodiment is not limited thereto, and in some example embodiments, the layout of the recesses 150 on the first surface 112 may be different from the layout of the recesses 150 on the second surface 114.

[0020] Figure 1 An example is shown in which recesses 150 in the first surface 112 and the second surface 114 of the core 110 are arranged symmetrically with respect to a line passing through the center of the core 110 in the vertical direction, and the recesses 150 in the first surface 112 and the second surface 114 of the core 110 overlap each other in the vertical direction. However, the example embodiment is not limited thereto. For example, in some example embodiments, at least one recess 150 in the first surface 112 of the core 110 may not overlap with a recess 150 in the second surface 114 of the core 110.

[0021] In some example embodiments, the recess 150 may be provided only in the first surface 112 of the core 110, or only in the second surface 114 of the core 110. In other words, in some example embodiments, the recess 150 may be omitted from the first surface but provided in the second surface 114, or omitted from the second surface 114 but provided in the first surface 112.

[0022] Multiple through electrodes 130 may be spaced apart from each other in the horizontal direction. Figure 1 An example including four through electrodes 130 is shown. However, the example embodiment is not limited to four through electrodes; in some example embodiments, more or fewer through electrodes may be provided. The through electrodes 130 can be arranged in various layouts in a plan view. In the example embodiment, each through electrode 130 may be spaced apart from the recess 150 in the horizontal direction.

[0023] The through electrode 130 may include a metal, such as copper or aluminum.

[0024] Because the recess 150 is provided in each of the first surface 112 and the second surface 114 of the core 110, the contact area of ​​the first bonding layer 160 with each of the first surface 112 and the second surface 114 of the core 110 can be increased. The upper surface of the first bonding layer 160 on the first surface 112 of the core 110 can be substantially flat, and the lower surface of the first bonding layer 160 on the second surface 114 of the core 110 can be substantially flat.

[0025] In an example embodiment, the first bonding layer 160 may include a polymer, such as an epoxy resin. Alternatively, the first bonding layer 160 may include an insulating material, such as an Ajinomoto structured film (ABF). TM ).

[0026] In an example embodiment, the insulating layer structure 300 may include a first insulating layer 180 and a second insulating layer 200 sequentially stacked in a vertical direction on the lower surface of the first bonding layer 160 or on the upper surface of the first bonding layer 160. However, the example embodiment is not limited thereto, and in some example embodiments, the insulating layer structure 300 may include more than two insulating layers sequentially stacked in a vertical direction.

[0027] Each of the first insulating layer 180 and the second insulating layer 200 may include an insulating material, such as ABF.

[0028] In an example embodiment, the wiring structure 310 may include a first via 170, a second via 190, and a third via 210 stacked vertically, and a first wiring 175, a second wiring 195, and a third wiring 215 stacked vertically on the lower surface of the insulating layer structure 300 or on the upper surface of the insulating layer structure 300. However, the example embodiment is not limited thereto; in some example embodiments, the wiring structure 310 may include more than three vias and / or more than three wirings stacked vertically.

[0029] The first via 170 may contact the upper or lower surface of the through electrode 130 and may be surrounded by the first bonding layer 160. The first wiring 175 may contact the first via 170 and may be disposed on the first bonding layer 160. A portion of the upper or lower surface of the first wiring 175 may be referred to as the first pad.

[0030] The second via 190 can contact the upper or lower surface of the first pad of the first wiring 175 and can be surrounded by the first insulating layer 180. The second wiring 195 can contact the second via 190 and can be disposed on the first insulating layer 180. A portion of the upper or lower surface of the second wiring 195 can be referred to as the second pad.

[0031] The third via 210 may contact the upper or lower surface of the second pad of the second wiring 195 and may be surrounded by the second insulating layer 200. The third wiring 215 may contact the third via 210 and may be disposed on the second insulating layer 200. A portion of the upper or lower surface of the third wiring 215 may be referred to as the third pad.

[0032] Each of the first through-holes 170, 190 and 210 and the first wiring 175, 195 and 215 may include metal, such as copper, aluminum, etc.

[0033] Figure 1 An example is shown in which the first through-holes 170, 190, and 210, and the first wirings 175, 195, and 215, are arranged in the same layout on the first surface 112 and the second surface 114 of the core 110, respectively. However, the example embodiment is not limited to this, and in some example embodiments, the example embodiments may be arranged in different layouts. That is, Figure 1 The illustration shows that the first through-holes 170, 190, and 210, and the first wiring 175, 195, and 215, are arranged symmetrically about a line passing through the center of the core 110 in the vertical direction. However, the example embodiment is not limited thereto.

[0034] The first protective layer 222 and the second protective layer 224 may be disposed on the lower and upper surfaces of the second insulating layer 220, respectively, and may cover the third wiring 215. The second opening 225 may expose the third pad of the third wiring 215 located on the lower or upper surface of the second insulating layer 220. Each of the first protective layer 222 and the second protective layer 224 may include an insulating material, such as solder resist (SR).

[0035] In an example embodiment, the packaging substrate 100 may be, for example, a printed circuit board (PCB).

[0036] As described above, the recesses 150 can be respectively disposed in the first surface 112 and the second surface 114 of the core 110, and the first bonding layer 160 can fill the recesses 150, thereby increasing the total contact area between the first bonding layer 160 and the first surface 112 and the second surface 114 of the core 110. Therefore, compared with the prior art in which the bonding layer is formed on a flat surface of the core without recesses, a portion of the first bonding layer 160 in the recesses 150 can have a greater bonding force on the core 110.

[0037] If the surface of the core, which includes glass, is flat as in the prior art, the bonding layer that contacts the surface of the core and includes a material other than glass may not bond tightly to the core and may detach from the core layer.

[0038] However, in contrast, in the example embodiment, the recess 150 may be disposed in the first surface 112 and the second surface 114 of the core 110 and filled with the first bonding layer 160, thereby increasing the contact area between the first bonding layer 160 and the core 110, and increasing the bonding force between the portion of the first bonding layer 160 in the recess 150 and the core 110. Therefore, even if delamination occurs between a portion of the first bonding layer 160 and the core 110, the total bonding force between the first bonding layer 160 and the core 110 can be increased.

[0039] Figures 2 to 6 This is a cross-sectional view illustrating a method for manufacturing a packaging substrate according to an example embodiment.

[0040] Reference Figure 2 The through-hole 120 can be formed to pass through the core 110, which has a first surface 112 and a second surface 114 that are opposite to each other in the vertical direction.

[0041] In an example embodiment, the core 110 may include glass.

[0042] In the example embodiment, the via 120 can be formed using, for example, laser drilling, and the plurality of vias 120 can be spaced apart from each other in the horizontal direction.

[0043] Reference Figure 3 A first seed layer may be formed on the first surface 112, the second surface 114, and the inner wall of the via 120. For example, an electroplating process or a chemical plating process may be performed to form a through electrode layer on the first seed layer to fill the via 120. A planarization process may be performed on the through electrode layer and the first seed layer until the first surface 112 and the second surface 114 of the core 110 are exposed.

[0044] Therefore, a through electrode 130 can be formed in each through hole 120 that extends vertically through the core 110.

[0045] In an example embodiment, the planarization process may include a chemical mechanical polishing process.

[0046] Reference Figure 4 A first mask 140 can be formed on the first surface 112 and the second surface 114 respectively to cover the upper and lower surfaces of the through electrode 130, and the portion of the core 110 not covered by the first mask 140 can be removed to form a recess 150.

[0047] In an example embodiment, the recess 150 can be formed by an etching process. In some example embodiments, the recess 150 can be formed by a drilling process, such as laser drilling.

[0048] In an example embodiment, the recesses 150 may be formed to be horizontally spaced apart from each other on the upper and / or lower portions of the core 110. In a plan view, each recess 150 may have a shape such as circular, elliptical, polygonal, or polygonal with rounded corners. In an example embodiment, the width of each recess 150 in the horizontal direction may be substantially constant in the vertical direction, so that the sidewalls of each recess 150 may extend in the vertical direction.

[0049] Reference Figure 5 The first mask 140 can be removed to expose the first surface 112 and the second surface 114 of the core 110 and the upper and lower surfaces of the through electrode 130, and a first bonding layer 160 can be formed on the first surface 112 and the second surface 114 of the core 110 and the upper and lower surfaces of the through electrode 130, respectively.

[0050] In an example embodiment, the first bonding layer 160 may be formed by, for example, a lamination process or a coating process.

[0051] Reference Figure 6The first bonding layer 160 can be partially removed to form first openings that expose the upper and lower surfaces of the through electrode 130, respectively. Second seed layers can be formed on the upper and lower surfaces of the through electrode 130 and on the first bonding layer 160, respectively. Second masks with second openings that overlap with the through electrode 130 in the vertical direction can be formed on the second seed layers, respectively. Conductive layers can be formed on the second seed layers by, for example, electroplating or chemical plating, respectively, and the second masks can be removed.

[0052] Therefore, the first via 170 and the first wiring 175 can be formed in each of the second openings to contact the lower or upper surface of the through electrode 130.

[0053] Refer again Figure 1 It can perform operations related to... Figure 6 The processes shown are substantially the same or similar to form the first insulating layer 180 and the second insulating layer 200, the second via 190 and the third via 210, and the second wiring 195 and the third wiring 215.

[0054] The first insulating layer 180 and the second insulating layer 200 stacked in the vertical direction can form an insulating layer structure 300, and the first through-hole to the third through-hole 170, 190 and 210 and the first wiring to the third wiring 175, 195 and 215 can form a wiring structure 310.

[0055] A first protective layer 222 and a second protective layer 224 can be formed on the second insulating layer 200 to cover the third wiring 215, and portions of the first protective layer 222 and the second protective layer 224 can be removed to form a third opening 225 on the surface that exposes portions of the third wiring 215, thereby completing the manufacturing of the packaging substrate 100.

[0056] Figure 7 This is a cross-sectional view of a packaging substrate according to an example embodiment. Figure 7 The packaging substrate shown can be used with Figure 1 The packaging substrates are substantially the same or similar, except that they also include a second bonding layer, so for the sake of brevity, repeated descriptions are omitted here.

[0057] Reference Figure 7 In addition to the first bonding layer 160, the packaging substrate 100 may also include a second bonding layer 165.

[0058] The first bonding layer 160 can contact the flat portions of the first surface 112 and the second surface 114 of the core 110 respectively, and the second bonding layer 165 can be respectively disposed in the recess 150 to contact the upper or lower surface of the core 110 and the first bonding layer 160 respectively.

[0059] In an example embodiment, the second bonding layer 165 may include an organic insulating material that is different from the organic insulating material of the first bonding layer 160. For example, the second bonding layer 165 may include an organic insulating material that has a high bonding strength to the glass used in the core 110 and to the polymer of the first bonding layer 160.

[0060] Figures 8 to 10 This is a cross-sectional view showing a packaging substrate according to an example embodiment. Except for the shape of the recess, Figures 8 to 10 Each package substrate shown can be coupled with Figure 1 The packaging substrates are basically the same or similar, so for the sake of brevity, repeated descriptions are omitted here. Figures 8 to 10 The shape of the recess shown can also be applied to Figure 7 The packaging substrate.

[0061] Reference Figure 8 The width of the recess 150 in the horizontal direction can gradually decrease as the distance from each of the first surface 112 and the second surface 114 of the core 110 increases.

[0062] Therefore, the sidewall of the recess 150 can be inclined relative to the vertical direction.

[0063] Reference Figure 9 The vertical cross-section of the recess 150 may have a semi-circular shape.

[0064] For example, the recess 150 can be formed by an isotropic etching process (e.g., a wet etching process) such that the width of the recess 150 in the horizontal direction can gradually increase and then decrease as the distance from each of the first surface 112 and the second surface 114 of the core 110 increases.

[0065] Reference Figure 10 As the distance from each of the first surface 112 and the second surface 114 of the core 110 increases, the width of the recess 150 in the horizontal direction can be reduced in a stepped manner.

[0066] Therefore, the cross-section of the recess 150 in the vertical direction can have a stepped shape.

[0067] Figure 11 This is a cross-sectional view illustrating a semiconductor package according to an example embodiment. The semiconductor package may include... Figure 1 The packaging substrate is described herein, therefore, for the sake of brevity, repeated descriptions are omitted here. According to some example embodiments... Figure 11 The semiconductor package shown may include Figures 7 to 10 Any of the packaging substrates shown.

[0068] Reference Figure 11The semiconductor package may include a package substrate 100, a semiconductor chip 400 on a first protective layer 222 of the package substrate 100, a first conductive connector 420 between the first protective layer 222 and the semiconductor chip 400, a molding part 500 disposed on the first protective layer 222 and covering the semiconductor chip 400 and the first conductive connector 420, and a second conductive connector 250 on the lower surface of the second protective layer 224 of the package substrate 100.

[0069] Semiconductor chip 400 may be a logic chip including logic devices or a memory chip including memory devices. Conductive pads 410 may be disposed on the surface of semiconductor chip 400, and a first conductive connector 420 may contact the lower surface of conductive pad 410 and the upper surface of the third pad of the third wiring 215 exposed by the third opening 225 in the first protective layer 222. The first conductive connector 420 may be a conductive bump or conductive ball including, for example, solder.

[0070] The molded part 500 may include, for example, an epoxy molding compound (EMC).

[0071] The second conductive connector 250 can contact the lower surface of the third pad of the third wiring 215 exposed by the third opening 225 in the second protective layer 224. The second conductive connector 250 can be a conductive bump or conductive ball including, for example, solder.

[0072] In the example embodiment, the recesses 150 on the first surface 112 and the second surface 114 of the core 110 of the packaging substrate 100 may not overlap with the semiconductor chip 400 in the vertical direction.

[0073] As per the above reference Figure 1 As shown, the bonding force between the core 110 and the first bonding layer 160 can be increased by the recess 150, and thus the semiconductor package including the packaging substrate 100 can have enhanced structural stability and electrical characteristics.

[0074] Figure 12 This is a cross-sectional view illustrating an electronic device according to an example embodiment. The electronic device may include... Figure 1 The packaging substrate is shown; therefore, for the sake of simplicity, repeated descriptions are omitted here. This electronic device may include... Figures 7 to 10 Any of the packaging substrates shown.

[0075] Reference Figure 12 The electronic device 10 includes a packaging substrate 100, an interposer 30, a first semiconductor device 40, and a second semiconductor device 50. The electronic device 10 also includes a first underfill 34, a second underfill 44, and a third underfill 54, a heat sink 60, and a heat sink 62.

[0076] In an example embodiment, the electronic device 10 may be a memory module with a 2.5D package structure, and therefore may include an interposer 30 for electrically connecting the first semiconductor device 40 and the second semiconductor device 50 to each other.

[0077] In an example embodiment, the first semiconductor device 40 may include a logic device, and the second semiconductor device 50 may include a memory device. The logic device may be an application-specific integrated circuit (ASIC) chip, including, for example, a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, a microcontroller, an application processor (AP), a digital signal processing core, etc. The memory device may be a semiconductor package such as an HBM package.

[0078] The interposer 30 can be mounted on the package substrate 100 via the third conductive connector 32. In an example embodiment, the planar area of ​​the interposer 30 may be smaller than the planar area of ​​the package substrate 100. In a plan view, the interposer 30 may be disposed within a region of the package substrate 100.

[0079] Interposer 30 may be a silicon interposer or a redistributed interposer with multiple wirings. The first semiconductor device 40 and the second semiconductor device 50 may be interconnected to each other via wirings in interposer 30 or electrically connected to the package substrate 100 via a third conductive connector 32. The third conductive connector 32 may include, for example, microbumps. The silicon interposer may provide high-density interconnects between the first semiconductor device 40 and the second semiconductor device 50.

[0080] A first semiconductor device 40 may be disposed on an interposer layer 30. The first semiconductor device 40 may be mounted and bonded to the interposer layer 30 using a flip-chip bonding process. In this case, the first semiconductor device 40 may be mounted on the interposer layer 30 such that the active surface on which conductive pads are formed may face downward toward the interposer layer 30. The conductive pads of the first semiconductor device 40 may be electrically connected to the conductive pads of the interposer layer 30 via a fourth conductive connector 42. For example, the fourth conductive connector 42 may include, for example, microbumps.

[0081] In some example embodiments, the first semiconductor device 40 can be mounted on the interposer 30 by a wire bonding process, and in this case, the active surface of the first semiconductor device 40 can face upwards.

[0082] The second semiconductor device 50 may be disposed on the interposer 30 and may be horizontally spaced from the first semiconductor device 40. The second semiconductor device 50 may be mounted on and bonded to the interposer 30 by, for example, a flip-chip bonding process. In this case, the conductive pads of the second semiconductor device 50 may be electrically connected to the conductive pads of the interposer 30 via a fifth conductive connector 52.

[0083] Although a single first semiconductor device 40 and a single second semiconductor device 50 are disposed on the interposer layer 30, the example embodiments are not limited thereto. In some example embodiments, multiple first semiconductor devices 40 and / or multiple second semiconductor devices 50 may be disposed on the interposer layer 30.

[0084] In an example embodiment, the first bottom filler 34 can fill the space between the interposer 30 and the package substrate 100, and the second bottom filler 44 and the third bottom filler 54 can fill the space between the first semiconductor device 40 and the interposer 30 and the space between the second semiconductor device 50 and the interposer 30, respectively.

[0085] The first to third underfillers 34, 44 and 54 may include a material with relatively high flowability to effectively fill the small spaces between the first semiconductor device 40 and the second semiconductor device 50 and the interposer 30, as well as the small spaces between the interposer 30 and the package substrate 100. For example, each of the first and second underfillers 34, 44 and 54 may include an adhesive containing an epoxy material.

[0086] The second semiconductor device 50 may include a buffer die and a plurality of memory dies sequentially stacked on the buffer die. The buffer die and the memory dies are electrically connected to each other via through electrodes (e.g., TSVs), and the through electrodes are electrically connected to each other via conductive bonding pads. Data signals and control signals can be transmitted to the buffer die and the memory dies via the through electrodes.

[0087] In an example embodiment, a heat sink 60 may be formed on a package substrate 100 to thermally contact the first semiconductor device 40 and the second semiconductor device 50. A heat sink 62 may be disposed on the upper surface of each of the first semiconductor device 40 and the second semiconductor device 50, and may include, for example, a thermal interface material (TIM). The heat sink 60 may thermally contact the first semiconductor device 40 and the second semiconductor device 50 via the heat sink 62.

[0088] In an example embodiment, the recesses 150 on the first surface 112 and the second surface 114 of the core 110 in the packaging substrate 100 may not overlap with the first semiconductor device 40 and the second semiconductor device 50 in the vertical direction.

[0089] The electronic device 10 can be mounted on the module substrate via the second conductive connector 250 to form a memory module.

[0090] The above is a description of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined in the claims.

Claims

1. A packaging substrate, comprising: A core having a first surface and a second surface opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat, the core comprising glass and a first recess in the first surface; A first bonding layer contacts the first surface of the core and fills the first recess; A through electrode extends from the first surface through the core along the vertical direction, and the through electrode is spaced apart from the first recess in the planar direction; A first wiring structure is on the first bonding layer and contacts the through electrode; A first insulating layer structure is on the first bonding layer and at least partially covers the first wiring structure; as well as A first protective layer is located on the first insulating layer structure and covers a portion of the upper surface of the first wiring structure.

2. The packaging substrate according to claim 1, wherein, The width of the first recess in the horizontal direction is substantially constant in the vertical direction.

3. The packaging substrate according to claim 1, wherein, The width of the first recess in the horizontal direction gradually decreases as the distance from the first surface of the core in the vertical direction increases.

4. The packaging substrate according to claim 1, wherein, As the distance from the first surface of the core in the vertical direction increases, the width of the first recess in the horizontal direction gradually decreases and then increases again.

5. The packaging substrate according to claim 1, wherein, The first recess has a stepped shape in the vertical cross-section.

6. The packaging substrate according to claim 1 further includes a plurality of first recesses, the plurality of first recesses being spaced apart from each other in the horizontal direction, wherein the first recess is one of the plurality of first recesses.

7. The packaging substrate according to claim 1, wherein, The first bonding layer comprises epoxy resin, and the first insulating layer structure comprises an Ajinomoto structure film.

8. The packaging substrate according to claim 1, wherein, The core also includes a second recess in the second surface of the core.

9. The packaging substrate according to claim 8, wherein, The through electrode extends from the first surface along the vertical direction through the core to the second surface, and The packaging substrate further includes: A second bonding layer contacts the second surface of the core and fills the second recess; A second wiring structure is on the second bonding layer and contacts the through electrode; A second insulating layer structure, which is on the second bonding layer and at least partially covers the second wiring structure; and A second protective layer is on the second insulating layer structure and covers the lower surface of a portion of the second wiring structure.

10. The packaging substrate according to claim 9, wherein, The first recess and the second recess are arranged symmetrically about a line passing through the core in the horizontal direction.

11. A packaging substrate, comprising: A core comprising glass, the core having a first surface and a second surface opposite to the first surface in a vertical direction, and a first recess in the first surface; A first bonding layer is located in a first recess, and the first bonding layer comprises a first organic insulating material; A second bonding layer is in contact with the first surface of the core and the upper surface of the first bonding layer, the second bonding layer comprising a second organic insulating material different from the first organic insulating material; A through electrode extends from the first surface through the core along the vertical direction, and the through electrode is spaced apart from the first recess along the horizontal direction; A first wiring structure is on the first bonding layer and contacts the through electrode; A first insulating layer structure is on the first bonding layer and at least partially covers the first wiring structure; as well as A first protective layer is located on the first insulating layer structure and covers a portion of the upper surface of the first wiring structure.

12. The packaging substrate according to claim 11, wherein, The width of the first recess in the horizontal direction gradually decreases as the distance from the first surface of the core in the vertical direction increases.

13. The packaging substrate according to claim 11, wherein, As the distance from the first surface of the core in the vertical direction increases, the width of the first recess in the horizontal direction gradually decreases and then increases again.

14. The packaging substrate according to claim 11, wherein, The first recess has a stepped shape in the cross-section in the vertical direction.

15. The packaging substrate of claim 11, further comprising a plurality of first recesses spaced apart from each other in the horizontal direction, wherein the first recess is one of the plurality of first recesses.

16. The packaging substrate according to claim 11, wherein, The through electrode extends from the first surface along the vertical direction through the core to the second surface. The core further includes a second recess in the second surface of the core, and The packaging substrate further includes: A third bonding layer contacts the second surface of the core and fills the second recess; A second wiring structure is located on the third bonding layer and contacts the through electrode; A second insulating layer structure, which is on the third bonding layer and at least partially covers the second wiring structure; and A second protective layer is on the second insulating layer structure and covers the lower surface of a portion of the second wiring structure.

17. A semiconductor package, comprising: Packaging substrate, comprising: A core comprising glass and having a first surface and a second surface opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat and the core including a first recess in the first surface; A first bonding layer contacts the first surface of the core and fills the first recess; A through electrode extends from the first surface through the core along the vertical direction, and the through electrode is spaced apart from the first recess in the horizontal direction; A first wiring structure is on the first bonding layer and contacts the through electrode; A first insulating layer structure, which is on the first bonding layer and at least partially covers the first wiring structure; and A first protective layer is located on the first insulating layer structure and covers the upper surface of the first portion of the first wiring structure; A semiconductor chip on the packaging substrate, the semiconductor chip including conductive pads; A first conductive connector contacts the conductive pads of the semiconductor chip, and the conductive connector is electrically connected to a second portion of the first wiring structure; and A molded part, which is on the packaging substrate and covers the semiconductor chip and the sidewall of the first conductive connector.

18. The semiconductor package of claim 17, wherein, The through electrode extends from the first surface along the vertical direction through the core to the second surface. The core of the packaging substrate further includes a second recess in the second surface of the core. The packaging substrate further includes: A second bonding layer contacts the second surface of the core and fills the second recess; A second wiring structure is on the second bonding layer and contacts the through electrode; A second insulating layer structure, which is on the second bonding layer and at least partially covers the second wiring structure; and A second protective layer is formed on the second insulating layer structure and covers the lower surface of the first portion of the second wiring structure. The semiconductor package further includes a second conductive connector that contacts the lower surface of the second portion of the second wiring structure.

19. The semiconductor package of claim 17, wherein, The first recess does not overlap with the semiconductor chip in the vertical direction.

20. The semiconductor package of claim 17, further comprising: An intermediary layer is provided between the packaging substrate and the first conductive connector, and the intermediary layer is electrically connected to the first wiring structure and the first conductive connector. A heat sink that contacts the upper surface of the semiconductor chip; as well as A heat sink that contacts the heat sink component.

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